Lines Matching refs:core_params
78 for (i = 0; i < hsotg->core_params->host_channels; ++i) in dwc2_backup_host_registers()
114 for (i = 0; i < hsotg->core_params->host_channels; ++i) in dwc2_restore_host_registers()
321 if (!hsotg->core_params->hibernation) in dwc2_exit_hibernation()
374 if (!hsotg->core_params->hibernation) in dwc2_enter_hibernation()
443 if (hsotg->core_params->dma_enable <= 0) in dwc2_enable_common_interrupts()
445 if (hsotg->core_params->external_id_pin_ctl <= 0) in dwc2_enable_common_interrupts()
464 hsotg->core_params->ulpi_fs_ls > 0) || in dwc2_init_fs_ls_pclk_sel()
465 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { in dwc2_init_fs_ls_pclk_sel()
577 if (hsotg->core_params->i2c_enable > 0) { in dwc2_fs_phy_init()
613 switch (hsotg->core_params->phy_type) { in dwc2_hs_phy_init()
619 if (hsotg->core_params->phy_ulpi_ddr > 0) in dwc2_hs_phy_init()
626 if (hsotg->core_params->phy_utmi_width == 16) in dwc2_hs_phy_init()
652 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL && in dwc2_phy_init()
653 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { in dwc2_phy_init()
667 hsotg->core_params->ulpi_fs_ls > 0) { in dwc2_phy_init()
694 if (hsotg->core_params->ahbcfg != -1) { in dwc2_gahbcfg_init()
696 ahbcfg |= hsotg->core_params->ahbcfg & in dwc2_gahbcfg_init()
708 hsotg->core_params->dma_enable, in dwc2_gahbcfg_init()
709 hsotg->core_params->dma_desc_enable); in dwc2_gahbcfg_init()
711 if (hsotg->core_params->dma_enable > 0) { in dwc2_gahbcfg_init()
712 if (hsotg->core_params->dma_desc_enable > 0) in dwc2_gahbcfg_init()
718 hsotg->core_params->dma_desc_enable = 0; in dwc2_gahbcfg_init()
721 if (hsotg->core_params->dma_enable > 0) in dwc2_gahbcfg_init()
738 if (hsotg->core_params->otg_cap == in dwc2_gusbcfg_init()
741 if (hsotg->core_params->otg_cap != in dwc2_gusbcfg_init()
749 if (hsotg->core_params->otg_cap != in dwc2_gusbcfg_init()
783 if (hsotg->core_params->phy_ulpi_ext_vbus == in dwc2_core_init()
789 if (hsotg->core_params->ts_dline > 0) in dwc2_core_init()
820 if (hsotg->core_params->otg_ver > 0) in dwc2_core_init()
823 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver); in dwc2_core_init()
894 struct dwc2_core_params *params = hsotg->core_params; in dwc2_calculate_dynamic_fifo()
953 struct dwc2_core_params *params = hsotg->core_params; in dwc2_config_fifos()
994 if (hsotg->core_params->en_multiple_tx_fifo > 0 && in dwc2_config_fifos()
1032 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) { in dwc2_core_host_init()
1043 if (hsotg->core_params->reload_ctl > 0) { in dwc2_core_host_init()
1049 if (hsotg->core_params->dma_desc_enable > 0) { in dwc2_core_host_init()
1060 hsotg->core_params->dma_desc_enable = 0; in dwc2_core_host_init()
1086 if (hsotg->core_params->dma_desc_enable <= 0) { in dwc2_core_host_init()
1091 num_channels = hsotg->core_params->host_channels; in dwc2_core_host_init()
1226 if (hsotg->core_params->dma_desc_enable <= 0) { in dwc2_hc_enable_dma_ints()
1259 if (hsotg->core_params->dma_enable > 0) { in dwc2_hc_enable_ints()
1479 if (hsotg->core_params->dma_desc_enable <= 0) { in dwc2_hc_halt()
1489 if (hsotg->core_params->dma_enable <= 0) { in dwc2_hc_halt()
1705 u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size; in dwc2_hc_start_transfer()
1706 u16 max_hc_pkt_count = hsotg->core_params->max_packet_count; in dwc2_hc_start_transfer()
1715 if (hsotg->core_params->dma_enable <= 0) { in dwc2_hc_start_transfer()
1832 if (hsotg->core_params->dma_enable > 0) { in dwc2_hc_start_transfer()
1884 if (hsotg->core_params->dma_enable <= 0 && in dwc2_hc_start_transfer()
2194 if (hsotg->core_params->dma_desc_enable > 0) { in dwc2_dump_host_registers()
2204 for (i = 0; i < hsotg->core_params->host_channels; i++) { in dwc2_dump_host_registers()
2224 if (hsotg->core_params->dma_desc_enable > 0) { in dwc2_dump_host_registers()
2441 hsotg->core_params->otg_cap = val; in dwc2_set_param_otg_cap()
2462 hsotg->core_params->dma_enable = val; in dwc2_set_param_dma_enable()
2469 if (val > 0 && (hsotg->core_params->dma_enable <= 0 || in dwc2_set_param_dma_desc_enable()
2480 val = (hsotg->core_params->dma_enable > 0 && in dwc2_set_param_dma_desc_enable()
2485 hsotg->core_params->dma_desc_enable = val; in dwc2_set_param_dma_desc_enable()
2503 hsotg->core_params->host_support_fs_ls_low_power = val; in dwc2_set_param_host_support_fs_ls_low_power()
2524 hsotg->core_params->enable_dynamic_fifo = val; in dwc2_set_param_enable_dynamic_fifo()
2543 hsotg->core_params->host_rx_fifo_size = val; in dwc2_set_param_host_rx_fifo_size()
2563 hsotg->core_params->host_nperio_tx_fifo_size = val; in dwc2_set_param_host_nperio_tx_fifo_size()
2583 hsotg->core_params->host_perio_tx_fifo_size = val; in dwc2_set_param_host_perio_tx_fifo_size()
2602 hsotg->core_params->max_transfer_size = val; in dwc2_set_param_max_transfer_size()
2621 hsotg->core_params->max_packet_count = val; in dwc2_set_param_max_packet_count()
2640 hsotg->core_params->host_channels = val; in dwc2_set_param_host_channels()
2688 hsotg->core_params->phy_type = val; in dwc2_set_param_phy_type()
2693 return hsotg->core_params->phy_type; in dwc2_get_param_phy_type()
2722 hsotg->core_params->speed = val; in dwc2_set_param_speed()
2756 hsotg->core_params->host_ls_low_power_phy_clk = val; in dwc2_set_param_host_ls_low_power_phy_clk()
2770 hsotg->core_params->phy_ulpi_ddr = val; in dwc2_set_param_phy_ulpi_ddr()
2786 hsotg->core_params->phy_ulpi_ext_vbus = val; in dwc2_set_param_phy_ulpi_ext_vbus()
2816 hsotg->core_params->phy_utmi_width = val; in dwc2_set_param_phy_utmi_width()
2830 hsotg->core_params->ulpi_fs_ls = val; in dwc2_set_param_ulpi_fs_ls()
2844 hsotg->core_params->ts_dline = val; in dwc2_set_param_ts_dline()
2872 hsotg->core_params->i2c_enable = val; in dwc2_set_param_i2c_enable()
2901 hsotg->core_params->en_multiple_tx_fifo = val; in dwc2_set_param_en_multiple_tx_fifo()
2929 hsotg->core_params->reload_ctl = val; in dwc2_set_param_reload_ctl()
2935 hsotg->core_params->ahbcfg = val; in dwc2_set_param_ahbcfg()
2937 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << in dwc2_set_param_ahbcfg()
2954 hsotg->core_params->otg_ver = val; in dwc2_set_param_otg_ver()
2970 hsotg->core_params->uframe_sched = val; in dwc2_set_param_uframe_sched()
2987 hsotg->core_params->external_id_pin_ctl = val; in dwc2_set_param_external_id_pin_ctl()
3004 hsotg->core_params->hibernation = val; in dwc2_set_param_hibernation()
3239 return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103; in dwc2_get_otg_version()