Lines Matching refs:chip
62 RIVA_HW_INST *chip in nv3Busy() argument
65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv3Busy()
66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01); in nv3Busy()
70 RIVA_HW_INST *chip in nv4Busy() argument
73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv4Busy()
74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); in nv4Busy()
78 RIVA_HW_INST *chip in nv10Busy() argument
81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv10Busy()
82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); in nv10Busy()
87 RIVA_HW_INST *chip, in vgaLockUnlock() argument
92 VGA_WR08(chip->PCIO, 0x3D4, 0x11); in vgaLockUnlock()
93 cr11 = VGA_RD08(chip->PCIO, 0x3D5); in vgaLockUnlock()
96 VGA_WR08(chip->PCIO, 0x3D5, cr11); in vgaLockUnlock()
100 RIVA_HW_INST *chip, in nv3LockUnlock() argument
104 VGA_WR08(chip->PVIO, 0x3C4, 0x06); in nv3LockUnlock()
105 VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57); in nv3LockUnlock()
106 vgaLockUnlock(chip, Lock); in nv3LockUnlock()
110 RIVA_HW_INST *chip, in nv4LockUnlock() argument
114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F); in nv4LockUnlock()
115 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57); in nv4LockUnlock()
116 vgaLockUnlock(chip, Lock); in nv4LockUnlock()
121 RIVA_HW_INST *chip, in ShowHideCursor() argument
126 cursor = chip->CurrentState->cursor1; in ShowHideCursor()
127 chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) | in ShowHideCursor()
129 VGA_WR08(chip->PCIO, 0x3D4, 0x31); in ShowHideCursor()
130 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1); in ShowHideCursor()
614 RIVA_HW_INST *chip in nv3UpdateArbitrationSettings() argument
621 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv3UpdateArbitrationSettings()
623 MClk = (N * chip->CrystalFreqKHz / M) >> P; in nv3UpdateArbitrationSettings()
628 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv3UpdateArbitrationSettings()
803 RIVA_HW_INST *chip in nv4UpdateArbitrationSettings() argument
810 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv4UpdateArbitrationSettings()
812 MClk = (N * chip->CrystalFreqKHz / M) >> P; in nv4UpdateArbitrationSettings()
813 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nv4UpdateArbitrationSettings()
815 NVClk = (N * chip->CrystalFreqKHz / M) >> P; in nv4UpdateArbitrationSettings()
816 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv4UpdateArbitrationSettings()
820 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv4UpdateArbitrationSettings()
1066 RIVA_HW_INST *chip in nv10UpdateArbitrationSettings() argument
1073 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv10UpdateArbitrationSettings()
1075 MClk = (N * chip->CrystalFreqKHz / M) >> P; in nv10UpdateArbitrationSettings()
1076 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nv10UpdateArbitrationSettings()
1078 NVClk = (N * chip->CrystalFreqKHz / M) >> P; in nv10UpdateArbitrationSettings()
1079 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv10UpdateArbitrationSettings()
1083 sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ? in nv10UpdateArbitrationSettings()
1085 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv10UpdateArbitrationSettings()
1111 RIVA_HW_INST *chip in nForceUpdateArbitrationSettings() argument
1128 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nForceUpdateArbitrationSettings()
1130 NVClk = (N * chip->CrystalFreqKHz / M) >> P; in nForceUpdateArbitrationSettings()
1175 RIVA_HW_INST *chip in CalcVClock() argument
1187 if (chip->CrystalFreqKHz == 13500) in CalcVClock()
1190 highM = 13 - (chip->Architecture == NV_ARCH_03); in CalcVClock()
1195 highM = 14 - (chip->Architecture == NV_ARCH_03); in CalcVClock()
1198 highP = 4 - (chip->Architecture == NV_ARCH_03); in CalcVClock()
1202 if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz)) in CalcVClock()
1206 N = (VClk << P) * M / chip->CrystalFreqKHz; in CalcVClock()
1208 Freq = (chip->CrystalFreqKHz * N / M) >> P; in CalcVClock()
1235 RIVA_HW_INST *chip, in CalcStateExt() argument
1258 if (!CalcVClock(dotClock, &VClk, &m, &n, &p, chip)) in CalcStateExt()
1261 switch (chip->Architecture) in CalcStateExt()
1268 chip); in CalcStateExt()
1284 chip); in CalcStateExt()
1296 if((chip->Chipset == NV_CHIP_IGEFORCE2) || in CalcStateExt()
1297 (chip->Chipset == NV_CHIP_0x01F0)) in CalcStateExt()
1303 chip); in CalcStateExt()
1309 chip); in CalcStateExt()
1311 state->cursor0 = 0x80 | (chip->CursorStart >> 17); in CalcStateExt()
1312 state->cursor1 = (chip->CursorStart >> 11) << 2; in CalcStateExt()
1313 state->cursor2 = chip->CursorStart >> 24; in CalcStateExt()
1315 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0); in CalcStateExt()
1323 if((bpp != 8) && (chip->Architecture != NV_ARCH_03)) in CalcStateExt()
1346 chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1]
1349 chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1]
1352 chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1]
1355 chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1]
1358 chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1]
1363 NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1])
1366 NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1])
1369 NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1])
1372 NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1])
1375 NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1])
1379 RIVA_HW_INST *chip in UpdateFifoState() argument
1384 switch (chip->Architecture) in UpdateFifoState()
1388 chip->Tri03 = NULL; in UpdateFifoState()
1389 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); in UpdateFifoState()
1399 chip->Tri03 = NULL; in UpdateFifoState()
1400 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); in UpdateFifoState()
1406 RIVA_HW_INST *chip, in LoadStateExt() argument
1417 switch (chip->Architecture) in LoadStateExt()
1423 NV_WR32(chip->PFB, 0x00000200, state->config); in LoadStateExt()
1433 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1439 chip->Tri03 = NULL; in LoadStateExt()
1445 chip->Tri03 = NULL; in LoadStateExt()
1449 NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03); in LoadStateExt()
1450 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0); in LoadStateExt()
1451 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1); in LoadStateExt()
1452 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2); in LoadStateExt()
1453 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3); in LoadStateExt()
1454 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0); in LoadStateExt()
1455 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1); in LoadStateExt()
1456 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2); in LoadStateExt()
1457 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3); in LoadStateExt()
1463 NV_WR32(chip->PFB, 0x00000200, state->config); in LoadStateExt()
1472 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1477 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1483 chip->Tri03 = NULL; in LoadStateExt()
1489 chip->Tri03 = NULL; in LoadStateExt()
1492 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); in LoadStateExt()
1493 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); in LoadStateExt()
1494 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); in LoadStateExt()
1495 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); in LoadStateExt()
1496 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); in LoadStateExt()
1497 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); in LoadStateExt()
1498 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); in LoadStateExt()
1499 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); in LoadStateExt()
1504 if(chip->twoHeads) { in LoadStateExt()
1505 VGA_WR08(chip->PCIO, 0x03D4, 0x44); in LoadStateExt()
1506 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner); in LoadStateExt()
1507 chip->LockUnlock(chip, 0); in LoadStateExt()
1518 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1523 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1529 chip->Tri03 = NULL; in LoadStateExt()
1535 chip->Tri03 = NULL; in LoadStateExt()
1539 if(chip->Architecture == NV_ARCH_10) { in LoadStateExt()
1540 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); in LoadStateExt()
1541 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); in LoadStateExt()
1542 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); in LoadStateExt()
1543 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); in LoadStateExt()
1544 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); in LoadStateExt()
1545 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); in LoadStateExt()
1546 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); in LoadStateExt()
1547 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); in LoadStateExt()
1548 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3); in LoadStateExt()
1550 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0); in LoadStateExt()
1551 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1); in LoadStateExt()
1552 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2); in LoadStateExt()
1553 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3); in LoadStateExt()
1554 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0); in LoadStateExt()
1555 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1); in LoadStateExt()
1556 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2); in LoadStateExt()
1557 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3); in LoadStateExt()
1558 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3); in LoadStateExt()
1559 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3); in LoadStateExt()
1560 NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200)); in LoadStateExt()
1561 NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204)); in LoadStateExt()
1563 if(chip->twoHeads) { in LoadStateExt()
1564 NV_WR32(chip->PCRTC0, 0x00000860, state->head); in LoadStateExt()
1565 NV_WR32(chip->PCRTC0, 0x00002860, state->head2); in LoadStateExt()
1567 NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25)); in LoadStateExt()
1569 NV_WR32(chip->PMC, 0x00008704, 1); in LoadStateExt()
1570 NV_WR32(chip->PMC, 0x00008140, 0); in LoadStateExt()
1571 NV_WR32(chip->PMC, 0x00008920, 0); in LoadStateExt()
1572 NV_WR32(chip->PMC, 0x00008924, 0); in LoadStateExt()
1573 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); in LoadStateExt()
1574 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); in LoadStateExt()
1575 NV_WR32(chip->PMC, 0x00001588, 0); in LoadStateExt()
1577 NV_WR32(chip->PFB, 0x00000240, 0); in LoadStateExt()
1578 NV_WR32(chip->PFB, 0x00000250, 0); in LoadStateExt()
1579 NV_WR32(chip->PFB, 0x00000260, 0); in LoadStateExt()
1580 NV_WR32(chip->PFB, 0x00000270, 0); in LoadStateExt()
1581 NV_WR32(chip->PFB, 0x00000280, 0); in LoadStateExt()
1582 NV_WR32(chip->PFB, 0x00000290, 0); in LoadStateExt()
1583 NV_WR32(chip->PFB, 0x000002A0, 0); in LoadStateExt()
1584 NV_WR32(chip->PFB, 0x000002B0, 0); in LoadStateExt()
1586 NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240)); in LoadStateExt()
1587 NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244)); in LoadStateExt()
1588 NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248)); in LoadStateExt()
1589 NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C)); in LoadStateExt()
1590 NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250)); in LoadStateExt()
1591 NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254)); in LoadStateExt()
1592 NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258)); in LoadStateExt()
1593 NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C)); in LoadStateExt()
1594 NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260)); in LoadStateExt()
1595 NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264)); in LoadStateExt()
1596 NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268)); in LoadStateExt()
1597 NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C)); in LoadStateExt()
1598 NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270)); in LoadStateExt()
1599 NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274)); in LoadStateExt()
1600 NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278)); in LoadStateExt()
1601 NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C)); in LoadStateExt()
1602 NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280)); in LoadStateExt()
1603 NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284)); in LoadStateExt()
1604 NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288)); in LoadStateExt()
1605 NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C)); in LoadStateExt()
1606 NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290)); in LoadStateExt()
1607 NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294)); in LoadStateExt()
1608 NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298)); in LoadStateExt()
1609 NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C)); in LoadStateExt()
1610 NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0)); in LoadStateExt()
1611 NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4)); in LoadStateExt()
1612 NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8)); in LoadStateExt()
1613 NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC)); in LoadStateExt()
1614 NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0)); in LoadStateExt()
1615 NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4)); in LoadStateExt()
1616 NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8)); in LoadStateExt()
1617 NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC)); in LoadStateExt()
1618 NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000); in LoadStateExt()
1619 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000); in LoadStateExt()
1620 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); in LoadStateExt()
1621 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008); in LoadStateExt()
1622 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200); in LoadStateExt()
1624 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1625 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); in LoadStateExt()
1626 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1627 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800); in LoadStateExt()
1629 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1630 NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000); in LoadStateExt()
1631 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004); in LoadStateExt()
1632 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400); in LoadStateExt()
1634 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1635 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800); in LoadStateExt()
1637 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1638 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00); in LoadStateExt()
1640 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1641 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000); in LoadStateExt()
1643 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1644 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400); in LoadStateExt()
1646 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1647 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800); in LoadStateExt()
1649 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1650 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400); in LoadStateExt()
1652 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1653 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000); in LoadStateExt()
1655 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1656 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); in LoadStateExt()
1658 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1660 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig); in LoadStateExt()
1662 if(chip->flatPanel) { in LoadStateExt()
1663 if((chip->Chipset & 0x0ff0) == 0x0110) { in LoadStateExt()
1664 NV_WR32(chip->PRAMDAC, 0x0528, state->dither); in LoadStateExt()
1666 if((chip->Chipset & 0x0ff0) >= 0x0170) { in LoadStateExt()
1667 NV_WR32(chip->PRAMDAC, 0x083C, state->dither); in LoadStateExt()
1670 VGA_WR08(chip->PCIO, 0x03D4, 0x53); in LoadStateExt()
1671 VGA_WR08(chip->PCIO, 0x03D5, 0); in LoadStateExt()
1672 VGA_WR08(chip->PCIO, 0x03D4, 0x54); in LoadStateExt()
1673 VGA_WR08(chip->PCIO, 0x03D5, 0); in LoadStateExt()
1674 VGA_WR08(chip->PCIO, 0x03D4, 0x21); in LoadStateExt()
1675 VGA_WR08(chip->PCIO, 0x03D5, 0xfa); in LoadStateExt()
1678 VGA_WR08(chip->PCIO, 0x03D4, 0x41); in LoadStateExt()
1679 VGA_WR08(chip->PCIO, 0x03D5, state->extra); in LoadStateExt()
1682 UpdateFifoState(chip); in LoadStateExt()
1686 VGA_WR08(chip->PCIO, 0x03D4, 0x19); in LoadStateExt()
1687 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0); in LoadStateExt()
1688 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); in LoadStateExt()
1689 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1); in LoadStateExt()
1690 VGA_WR08(chip->PCIO, 0x03D4, 0x25); in LoadStateExt()
1691 VGA_WR08(chip->PCIO, 0x03D5, state->screen); in LoadStateExt()
1692 VGA_WR08(chip->PCIO, 0x03D4, 0x28); in LoadStateExt()
1693 VGA_WR08(chip->PCIO, 0x03D5, state->pixel); in LoadStateExt()
1694 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); in LoadStateExt()
1695 VGA_WR08(chip->PCIO, 0x03D5, state->horiz); in LoadStateExt()
1696 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); in LoadStateExt()
1697 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0); in LoadStateExt()
1698 VGA_WR08(chip->PCIO, 0x03D4, 0x20); in LoadStateExt()
1699 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1); in LoadStateExt()
1700 VGA_WR08(chip->PCIO, 0x03D4, 0x30); in LoadStateExt()
1701 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0); in LoadStateExt()
1702 VGA_WR08(chip->PCIO, 0x03D4, 0x31); in LoadStateExt()
1703 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1); in LoadStateExt()
1704 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); in LoadStateExt()
1705 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2); in LoadStateExt()
1706 VGA_WR08(chip->PCIO, 0x03D4, 0x39); in LoadStateExt()
1707 VGA_WR08(chip->PCIO, 0x03D5, state->interlace); in LoadStateExt()
1709 if(!chip->flatPanel) { in LoadStateExt()
1710 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll); in LoadStateExt()
1711 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel); in LoadStateExt()
1712 if(chip->twoHeads) in LoadStateExt()
1713 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2); in LoadStateExt()
1715 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale); in LoadStateExt()
1717 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general); in LoadStateExt()
1722 NV_WR32(chip->PCRTC, 0x00000140, 0); in LoadStateExt()
1723 NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit); in LoadStateExt()
1727 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); in LoadStateExt()
1731 chip->CurrentState = state; in LoadStateExt()
1735 chip->FifoFreeCount = 0; in LoadStateExt()
1737 chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0); in LoadStateExt()
1741 RIVA_HW_INST *chip, in UnloadStateExt() argument
1748 VGA_WR08(chip->PCIO, 0x03D4, 0x19); in UnloadStateExt()
1749 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1750 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); in UnloadStateExt()
1751 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1752 VGA_WR08(chip->PCIO, 0x03D4, 0x25); in UnloadStateExt()
1753 state->screen = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1754 VGA_WR08(chip->PCIO, 0x03D4, 0x28); in UnloadStateExt()
1755 state->pixel = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1756 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); in UnloadStateExt()
1757 state->horiz = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1758 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); in UnloadStateExt()
1759 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1760 VGA_WR08(chip->PCIO, 0x03D4, 0x20); in UnloadStateExt()
1761 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1762 VGA_WR08(chip->PCIO, 0x03D4, 0x30); in UnloadStateExt()
1763 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1764 VGA_WR08(chip->PCIO, 0x03D4, 0x31); in UnloadStateExt()
1765 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1766 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); in UnloadStateExt()
1767 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1768 VGA_WR08(chip->PCIO, 0x03D4, 0x39); in UnloadStateExt()
1769 state->interlace = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1770 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508); in UnloadStateExt()
1771 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520); in UnloadStateExt()
1772 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C); in UnloadStateExt()
1773 state->general = NV_RD32(chip->PRAMDAC, 0x00000600); in UnloadStateExt()
1774 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848); in UnloadStateExt()
1775 state->config = NV_RD32(chip->PFB, 0x00000200); in UnloadStateExt()
1776 switch (chip->Architecture) in UnloadStateExt()
1779 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630); in UnloadStateExt()
1780 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634); in UnloadStateExt()
1781 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638); in UnloadStateExt()
1782 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C); in UnloadStateExt()
1783 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650); in UnloadStateExt()
1784 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654); in UnloadStateExt()
1785 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658); in UnloadStateExt()
1786 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C); in UnloadStateExt()
1789 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); in UnloadStateExt()
1790 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); in UnloadStateExt()
1791 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); in UnloadStateExt()
1792 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); in UnloadStateExt()
1793 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); in UnloadStateExt()
1794 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); in UnloadStateExt()
1795 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); in UnloadStateExt()
1796 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); in UnloadStateExt()
1801 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); in UnloadStateExt()
1802 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); in UnloadStateExt()
1803 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); in UnloadStateExt()
1804 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); in UnloadStateExt()
1805 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); in UnloadStateExt()
1806 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); in UnloadStateExt()
1807 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); in UnloadStateExt()
1808 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); in UnloadStateExt()
1809 if(chip->twoHeads) { in UnloadStateExt()
1810 state->head = NV_RD32(chip->PCRTC0, 0x00000860); in UnloadStateExt()
1811 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860); in UnloadStateExt()
1812 VGA_WR08(chip->PCIO, 0x03D4, 0x44); in UnloadStateExt()
1813 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1815 VGA_WR08(chip->PCIO, 0x03D4, 0x41); in UnloadStateExt()
1816 state->extra = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1817 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810); in UnloadStateExt()
1819 if((chip->Chipset & 0x0ff0) == 0x0110) { in UnloadStateExt()
1820 state->dither = NV_RD32(chip->PRAMDAC, 0x0528); in UnloadStateExt()
1822 if((chip->Chipset & 0x0ff0) >= 0x0170) { in UnloadStateExt()
1823 state->dither = NV_RD32(chip->PRAMDAC, 0x083C); in UnloadStateExt()
1830 RIVA_HW_INST *chip, in SetStartAddress() argument
1834 NV_WR32(chip->PCRTC, 0x800, start); in SetStartAddress()
1839 RIVA_HW_INST *chip, in SetStartAddress3() argument
1850 chip->LockUnlock(chip, 0); in SetStartAddress3()
1854 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset); in SetStartAddress3()
1856 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset); in SetStartAddress3()
1858 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5); in SetStartAddress3()
1859 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F)); in SetStartAddress3()
1860 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5); in SetStartAddress3()
1861 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60)); in SetStartAddress3()
1865 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A); in SetStartAddress3()
1866 VGA_WR08(chip->PCIO, 0x3C0, 0x13); in SetStartAddress3()
1867 VGA_WR08(chip->PCIO, 0x3C0, pan); in SetStartAddress3()
1871 RIVA_HW_INST *chip, in nv3SetSurfaces2D() argument
1877 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv3SetSurfaces2D()
1879 RIVA_FIFO_FREE(*chip,Tri03,5); in nv3SetSurfaces2D()
1880 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); in nv3SetSurfaces2D()
1882 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); in nv3SetSurfaces2D()
1884 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); in nv3SetSurfaces2D()
1888 RIVA_HW_INST *chip, in nv4SetSurfaces2D() argument
1894 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv4SetSurfaces2D()
1896 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); in nv4SetSurfaces2D()
1898 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); in nv4SetSurfaces2D()
1900 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv4SetSurfaces2D()
1904 RIVA_HW_INST *chip, in nv10SetSurfaces2D() argument
1910 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv10SetSurfaces2D()
1912 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); in nv10SetSurfaces2D()
1914 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); in nv10SetSurfaces2D()
1916 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv10SetSurfaces2D()
1920 RIVA_HW_INST *chip, in nv3SetSurfaces3D() argument
1926 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv3SetSurfaces3D()
1928 RIVA_FIFO_FREE(*chip,Tri03,5); in nv3SetSurfaces3D()
1929 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); in nv3SetSurfaces3D()
1931 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); in nv3SetSurfaces3D()
1933 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); in nv3SetSurfaces3D()
1937 RIVA_HW_INST *chip, in nv4SetSurfaces3D() argument
1943 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv4SetSurfaces3D()
1945 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); in nv4SetSurfaces3D()
1947 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); in nv4SetSurfaces3D()
1949 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv4SetSurfaces3D()
1953 RIVA_HW_INST *chip, in nv10SetSurfaces3D() argument
1959 (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]); in nv10SetSurfaces3D()
1961 RIVA_FIFO_FREE(*chip,Tri03,4); in nv10SetSurfaces3D()
1962 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007); in nv10SetSurfaces3D()
1965 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv10SetSurfaces3D()
1976 RIVA_HW_INST *chip in nv3GetConfig() argument
1982 if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020) in nv3GetConfig()
1984 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in nv3GetConfig()
1985 && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02)) in nv3GetConfig()
1990 chip->RamBandwidthKBytesPerSec = 800000; in nv3GetConfig()
1991 switch (NV_RD32(chip->PFB, 0x00000000) & 0x03) in nv3GetConfig()
1994 chip->RamAmountKBytes = 1024 * 4; in nv3GetConfig()
1997 chip->RamAmountKBytes = 1024 * 2; in nv3GetConfig()
2000 chip->RamAmountKBytes = 1024 * 8; in nv3GetConfig()
2006 chip->RamBandwidthKBytesPerSec = 1000000; in nv3GetConfig()
2007 chip->RamAmountKBytes = 1024 * 8; in nv3GetConfig()
2015 chip->RamBandwidthKBytesPerSec = 1000000; in nv3GetConfig()
2016 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) in nv3GetConfig()
2019 chip->RamAmountKBytes = 1024 * 8; in nv3GetConfig()
2022 chip->RamAmountKBytes = 1024 * 4; in nv3GetConfig()
2025 chip->RamAmountKBytes = 1024 * 2; in nv3GetConfig()
2029 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; in nv3GetConfig()
2030 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]); in nv3GetConfig()
2031 chip->VBlankBit = 0x00000100; in nv3GetConfig()
2032 chip->MaxVClockFreqKHz = 256000; in nv3GetConfig()
2036 chip->Busy = nv3Busy; in nv3GetConfig()
2037 chip->ShowHideCursor = ShowHideCursor; in nv3GetConfig()
2038 chip->LoadStateExt = LoadStateExt; in nv3GetConfig()
2039 chip->UnloadStateExt = UnloadStateExt; in nv3GetConfig()
2040 chip->SetStartAddress = SetStartAddress3; in nv3GetConfig()
2041 chip->SetSurfaces2D = nv3SetSurfaces2D; in nv3GetConfig()
2042 chip->SetSurfaces3D = nv3SetSurfaces3D; in nv3GetConfig()
2043 chip->LockUnlock = nv3LockUnlock; in nv3GetConfig()
2047 RIVA_HW_INST *chip in nv4GetConfig() argument
2053 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) in nv4GetConfig()
2055 chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2 in nv4GetConfig()
2060 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) in nv4GetConfig()
2063 chip->RamAmountKBytes = 1024 * 32; in nv4GetConfig()
2066 chip->RamAmountKBytes = 1024 * 4; in nv4GetConfig()
2069 chip->RamAmountKBytes = 1024 * 8; in nv4GetConfig()
2073 chip->RamAmountKBytes = 1024 * 16; in nv4GetConfig()
2077 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) in nv4GetConfig()
2080 chip->RamBandwidthKBytesPerSec = 800000; in nv4GetConfig()
2083 chip->RamBandwidthKBytesPerSec = 1000000; in nv4GetConfig()
2086 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; in nv4GetConfig()
2087 chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]); in nv4GetConfig()
2088 chip->VBlankBit = 0x00000001; in nv4GetConfig()
2089 chip->MaxVClockFreqKHz = 350000; in nv4GetConfig()
2093 chip->Busy = nv4Busy; in nv4GetConfig()
2094 chip->ShowHideCursor = ShowHideCursor; in nv4GetConfig()
2095 chip->LoadStateExt = LoadStateExt; in nv4GetConfig()
2096 chip->UnloadStateExt = UnloadStateExt; in nv4GetConfig()
2097 chip->SetStartAddress = SetStartAddress; in nv4GetConfig()
2098 chip->SetSurfaces2D = nv4SetSurfaces2D; in nv4GetConfig()
2099 chip->SetSurfaces3D = nv4SetSurfaces3D; in nv4GetConfig()
2100 chip->LockUnlock = nv4LockUnlock; in nv4GetConfig()
2104 RIVA_HW_INST *chip, in nv10GetConfig() argument
2113 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001)) in nv10GetConfig()
2114 NV_WR32(chip->PMC, 0x00000004, 0x01000001); in nv10GetConfig()
2124 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; in nv10GetConfig()
2129 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; in nv10GetConfig()
2131 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF) in nv10GetConfig()
2134 chip->RamAmountKBytes = 1024 * 2; in nv10GetConfig()
2137 chip->RamAmountKBytes = 1024 * 4; in nv10GetConfig()
2140 chip->RamAmountKBytes = 1024 * 8; in nv10GetConfig()
2143 chip->RamAmountKBytes = 1024 * 16; in nv10GetConfig()
2146 chip->RamAmountKBytes = 1024 * 32; in nv10GetConfig()
2149 chip->RamAmountKBytes = 1024 * 64; in nv10GetConfig()
2152 chip->RamAmountKBytes = 1024 * 128; in nv10GetConfig()
2155 chip->RamAmountKBytes = 1024 * 16; in nv10GetConfig()
2159 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) in nv10GetConfig()
2162 chip->RamBandwidthKBytesPerSec = 800000; in nv10GetConfig()
2165 chip->RamBandwidthKBytesPerSec = 1000000; in nv10GetConfig()
2168 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ? in nv10GetConfig()
2182 if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22)) in nv10GetConfig()
2183 chip->CrystalFreqKHz = 27000; in nv10GetConfig()
2189 chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024; in nv10GetConfig()
2190 chip->CURSOR = NULL; /* can't set this here */ in nv10GetConfig()
2191 chip->VBlankBit = 0x00000001; in nv10GetConfig()
2192 chip->MaxVClockFreqKHz = 350000; in nv10GetConfig()
2196 chip->Busy = nv10Busy; in nv10GetConfig()
2197 chip->ShowHideCursor = ShowHideCursor; in nv10GetConfig()
2198 chip->LoadStateExt = LoadStateExt; in nv10GetConfig()
2199 chip->UnloadStateExt = UnloadStateExt; in nv10GetConfig()
2200 chip->SetStartAddress = SetStartAddress; in nv10GetConfig()
2201 chip->SetSurfaces2D = nv10SetSurfaces2D; in nv10GetConfig()
2202 chip->SetSurfaces3D = nv10SetSurfaces3D; in nv10GetConfig()
2203 chip->LockUnlock = nv4LockUnlock; in nv10GetConfig()
2217 chip->twoHeads = TRUE; in nv10GetConfig()
2220 chip->twoHeads = FALSE; in nv10GetConfig()
2226 RIVA_HW_INST *chip, in RivaGetConfig() argument
2233 chip->Version = RIVA_SW_VERSION; in RivaGetConfig()
2237 switch (chip->Architecture) in RivaGetConfig()
2240 nv3GetConfig(chip); in RivaGetConfig()
2243 nv4GetConfig(chip); in RivaGetConfig()
2248 nv10GetConfig(chip, chipset); in RivaGetConfig()
2253 chip->Chipset = chipset; in RivaGetConfig()
2257 chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]); in RivaGetConfig()
2258 chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]); in RivaGetConfig()
2259 chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]); in RivaGetConfig()
2260 chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]); in RivaGetConfig()
2261 chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]); in RivaGetConfig()
2262 chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]); in RivaGetConfig()
2263 chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]); in RivaGetConfig()
2264 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in RivaGetConfig()