Lines Matching refs:reg
36 static inline void tegra30_apbif_write(u32 reg, u32 val) in tegra30_apbif_write() argument
38 regmap_write(ahub->regmap_apbif, reg, val); in tegra30_apbif_write()
41 static inline u32 tegra30_apbif_read(u32 reg) in tegra30_apbif_read() argument
44 regmap_read(ahub->regmap_apbif, reg, &val); in tegra30_apbif_read()
48 static inline void tegra30_audio_write(u32 reg, u32 val) in tegra30_audio_write() argument
50 regmap_write(ahub->regmap_ahub, reg, val); in tegra30_audio_write()
102 u32 reg, val; in tegra30_ahub_allocate_rx_fifo() local
119 reg = TEGRA30_AHUB_CHANNEL_CTRL + in tegra30_ahub_allocate_rx_fifo()
121 val = tegra30_apbif_read(reg); in tegra30_ahub_allocate_rx_fifo()
127 tegra30_apbif_write(reg, val); in tegra30_ahub_allocate_rx_fifo()
141 reg = TEGRA30_AHUB_CIF_RX_CTRL + in tegra30_ahub_allocate_rx_fifo()
143 ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); in tegra30_ahub_allocate_rx_fifo()
154 int reg, val; in tegra30_ahub_enable_rx_fifo() local
158 reg = TEGRA30_AHUB_CHANNEL_CTRL + in tegra30_ahub_enable_rx_fifo()
160 val = tegra30_apbif_read(reg); in tegra30_ahub_enable_rx_fifo()
162 tegra30_apbif_write(reg, val); in tegra30_ahub_enable_rx_fifo()
173 int reg, val; in tegra30_ahub_disable_rx_fifo() local
177 reg = TEGRA30_AHUB_CHANNEL_CTRL + in tegra30_ahub_disable_rx_fifo()
179 val = tegra30_apbif_read(reg); in tegra30_ahub_disable_rx_fifo()
181 tegra30_apbif_write(reg, val); in tegra30_ahub_disable_rx_fifo()
204 u32 reg, val; in tegra30_ahub_allocate_tx_fifo() local
221 reg = TEGRA30_AHUB_CHANNEL_CTRL + in tegra30_ahub_allocate_tx_fifo()
223 val = tegra30_apbif_read(reg); in tegra30_ahub_allocate_tx_fifo()
229 tegra30_apbif_write(reg, val); in tegra30_ahub_allocate_tx_fifo()
243 reg = TEGRA30_AHUB_CIF_TX_CTRL + in tegra30_ahub_allocate_tx_fifo()
245 ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); in tegra30_ahub_allocate_tx_fifo()
256 int reg, val; in tegra30_ahub_enable_tx_fifo() local
260 reg = TEGRA30_AHUB_CHANNEL_CTRL + in tegra30_ahub_enable_tx_fifo()
262 val = tegra30_apbif_read(reg); in tegra30_ahub_enable_tx_fifo()
264 tegra30_apbif_write(reg, val); in tegra30_ahub_enable_tx_fifo()
275 int reg, val; in tegra30_ahub_disable_tx_fifo() local
279 reg = TEGRA30_AHUB_CHANNEL_CTRL + in tegra30_ahub_disable_tx_fifo()
281 val = tegra30_apbif_read(reg); in tegra30_ahub_disable_tx_fifo()
283 tegra30_apbif_write(reg, val); in tegra30_ahub_disable_tx_fifo()
305 int reg; in tegra30_ahub_set_rx_cif_source() local
309 reg = TEGRA30_AHUB_AUDIO_RX + in tegra30_ahub_set_rx_cif_source()
311 tegra30_audio_write(reg, 1 << txcif); in tegra30_ahub_set_rx_cif_source()
322 int reg; in tegra30_ahub_unset_rx_cif_source() local
326 reg = TEGRA30_AHUB_AUDIO_RX + in tegra30_ahub_unset_rx_cif_source()
328 tegra30_audio_write(reg, 0); in tegra30_ahub_unset_rx_cif_source()
375 #define REG_IN_ARRAY(reg, name) \ argument
376 ((reg >= TEGRA30_AHUB_##name) && \
377 (reg <= LAST_REG(name) && \
378 (!((reg - TEGRA30_AHUB_##name) % TEGRA30_AHUB_##name##_STRIDE))))
380 static bool tegra30_ahub_apbif_wr_rd_reg(struct device *dev, unsigned int reg) in tegra30_ahub_apbif_wr_rd_reg() argument
382 switch (reg) { in tegra30_ahub_apbif_wr_rd_reg()
409 if (REG_IN_ARRAY(reg, CHANNEL_CTRL) || in tegra30_ahub_apbif_wr_rd_reg()
410 REG_IN_ARRAY(reg, CHANNEL_CLEAR) || in tegra30_ahub_apbif_wr_rd_reg()
411 REG_IN_ARRAY(reg, CHANNEL_STATUS) || in tegra30_ahub_apbif_wr_rd_reg()
412 REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || in tegra30_ahub_apbif_wr_rd_reg()
413 REG_IN_ARRAY(reg, CHANNEL_RXFIFO) || in tegra30_ahub_apbif_wr_rd_reg()
414 REG_IN_ARRAY(reg, CIF_TX_CTRL) || in tegra30_ahub_apbif_wr_rd_reg()
415 REG_IN_ARRAY(reg, CIF_RX_CTRL) || in tegra30_ahub_apbif_wr_rd_reg()
416 REG_IN_ARRAY(reg, DAM_LIVE_STATUS)) in tegra30_ahub_apbif_wr_rd_reg()
423 unsigned int reg) in tegra30_ahub_apbif_volatile_reg() argument
425 switch (reg) { in tegra30_ahub_apbif_volatile_reg()
444 if (REG_IN_ARRAY(reg, CHANNEL_CLEAR) || in tegra30_ahub_apbif_volatile_reg()
445 REG_IN_ARRAY(reg, CHANNEL_STATUS) || in tegra30_ahub_apbif_volatile_reg()
446 REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || in tegra30_ahub_apbif_volatile_reg()
447 REG_IN_ARRAY(reg, CHANNEL_RXFIFO) || in tegra30_ahub_apbif_volatile_reg()
448 REG_IN_ARRAY(reg, DAM_LIVE_STATUS)) in tegra30_ahub_apbif_volatile_reg()
455 unsigned int reg) in tegra30_ahub_apbif_precious_reg() argument
457 if (REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || in tegra30_ahub_apbif_precious_reg()
458 REG_IN_ARRAY(reg, CHANNEL_RXFIFO)) in tegra30_ahub_apbif_precious_reg()
477 static bool tegra30_ahub_ahub_wr_rd_reg(struct device *dev, unsigned int reg) in tegra30_ahub_ahub_wr_rd_reg() argument
479 if (REG_IN_ARRAY(reg, AUDIO_RX)) in tegra30_ahub_ahub_wr_rd_reg()
688 void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg, in tegra30_ahub_set_cif() argument
716 regmap_write(regmap, reg, value); in tegra30_ahub_set_cif()
720 void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg, in tegra124_ahub_set_cif() argument
748 regmap_write(regmap, reg, value); in tegra124_ahub_set_cif()