55 	u32 reg = 0xffffffff;  in handle_mmio_rao_wi()  local
57 	vgic_reg_access(mmio, &reg, offset,  in handle_mmio_rao_wi()
66 	u32 reg = 0;  in handle_mmio_ctlr()  local
73 		reg = GICD_CTLR_ENABLE_SS_G1;  in handle_mmio_ctlr()
74 	reg |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;  in handle_mmio_ctlr()
76 	vgic_reg_access(mmio, &reg, offset,  in handle_mmio_ctlr()
79 		vcpu->kvm->arch.vgic.enabled = !!(reg & GICD_CTLR_ENABLE_SS_G1);  in handle_mmio_ctlr()
96 	u32 reg;  in handle_mmio_typer()  local
98 	reg = (min(vcpu->kvm->arch.vgic.nr_irqs, 1024) >> 5) - 1;  in handle_mmio_typer()
100 	reg |= (INTERRUPT_ID_BITS - 1) << 19;  in handle_mmio_typer()
102 	vgic_reg_access(mmio, &reg, offset,  in handle_mmio_typer()
111 	u32 reg;  in handle_mmio_iidr()  local
113 	reg = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);  in handle_mmio_iidr()
114 	vgic_reg_access(mmio, &reg, offset,  in handle_mmio_iidr()
204 	u32 *reg;  in handle_mmio_priority_reg_dist()  local
212 	reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority,  in handle_mmio_priority_reg_dist()
214 	vgic_reg_access(mmio, reg, offset,  in handle_mmio_priority_reg_dist()
223 	u32 *reg;  in handle_mmio_cfg_reg_dist()  local
231 	reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,  in handle_mmio_cfg_reg_dist()
234 	return vgic_handle_cfg_reg(reg, mmio, offset);  in handle_mmio_cfg_reg_dist()
281 	u32 reg;  in handle_mmio_route_reg()  local
300 	reg = mpidr;  in handle_mmio_route_reg()
302 	vgic_reg_access(mmio, &reg, offset,  in handle_mmio_route_reg()
319 	dist->irq_spi_mpidr[spi] = compress_mpidr(reg);  in handle_mmio_route_reg()
320 	vcpu = kvm_mpidr_to_vcpu(kvm, reg & MPIDR_HWID_BITMASK);  in handle_mmio_route_reg()
353 	u32 reg = 0;  in handle_mmio_idregs()  local
357 		reg = 0x3b;  in handle_mmio_idregs()
361 	vgic_reg_access(mmio, &reg, offset,  in handle_mmio_idregs()
543 	u32 reg;  in handle_mmio_typer_redist()  local
551 		reg = compress_mpidr(mpidr);  in handle_mmio_typer_redist()
553 		vgic_reg_access(mmio, &reg, offset,  in handle_mmio_typer_redist()
558 	reg = redist_vcpu->vcpu_id << 8;  in handle_mmio_typer_redist()
560 		reg |= GICR_TYPER_LAST;  in handle_mmio_typer_redist()
561 	vgic_reg_access(mmio, &reg, offset,  in handle_mmio_typer_redist()
633 	u32 *reg;  in handle_mmio_priority_reg_redist()  local
635 	reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority,  in handle_mmio_priority_reg_redist()
637 	vgic_reg_access(mmio, reg, offset,  in handle_mmio_priority_reg_redist()
648 	u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,  in handle_mmio_cfg_reg_redist()  local
651 	return vgic_handle_cfg_reg(reg, mmio, offset);  in handle_mmio_cfg_reg_redist()
912 #define SGI_AFFINITY_LEVEL(reg, level) \  argument
913 	((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
929 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)  in vgic_v3_dispatch_sgi()  argument
941 	sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;  in vgic_v3_dispatch_sgi()
942 	broadcast = reg & BIT(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);  in vgic_v3_dispatch_sgi()
943 	target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;  in vgic_v3_dispatch_sgi()
944 	mpidr = SGI_AFFINITY_LEVEL(reg, 3);  in vgic_v3_dispatch_sgi()
945 	mpidr |= SGI_AFFINITY_LEVEL(reg, 2);  in vgic_v3_dispatch_sgi()
946 	mpidr |= SGI_AFFINITY_LEVEL(reg, 1);  in vgic_v3_dispatch_sgi()