• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1  /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2   * All Rights Reserved.
3   *
4   * Permission is hereby granted, free of charge, to any person obtaining a
5   * copy of this software and associated documentation files (the
6   * "Software"), to deal in the Software without restriction, including
7   * without limitation the rights to use, copy, modify, merge, publish,
8   * distribute, sub license, and/or sell copies of the Software, and to
9   * permit persons to whom the Software is furnished to do so, subject to
10   * the following conditions:
11   *
12   * The above copyright notice and this permission notice (including the
13   * next paragraph) shall be included in all copies or substantial portions
14   * of the Software.
15   *
16   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17   * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18   * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19   * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20   * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21   * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22   * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23   */
24  
25  #ifndef _I915_REG_H_
26  #define _I915_REG_H_
27  
28  #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29  #define _PLANE(plane, a, b) _PIPE(plane, a, b)
30  #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
31  #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
32  #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
33  			       (pipe) == PIPE_B ? (b) : (c))
34  #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
35  			       (port) == PORT_B ? (b) : (c))
36  
37  #define _MASKED_FIELD(mask, value) ({					   \
38  	if (__builtin_constant_p(mask))					   \
39  		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
40  	if (__builtin_constant_p(value))				   \
41  		BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
42  	if (__builtin_constant_p(mask) && __builtin_constant_p(value))	   \
43  		BUILD_BUG_ON_MSG((value) & ~(mask),			   \
44  				 "Incorrect value for mask");		   \
45  	(mask) << 16 | (value); })
46  #define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
47  #define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
48  
49  
50  
51  /* PCI config space */
52  
53  #define HPLLCC	0xc0 /* 85x only */
54  #define   GC_CLOCK_CONTROL_MASK		(0x7 << 0)
55  #define   GC_CLOCK_133_200		(0 << 0)
56  #define   GC_CLOCK_100_200		(1 << 0)
57  #define   GC_CLOCK_100_133		(2 << 0)
58  #define   GC_CLOCK_133_266		(3 << 0)
59  #define   GC_CLOCK_133_200_2		(4 << 0)
60  #define   GC_CLOCK_133_266_2		(5 << 0)
61  #define   GC_CLOCK_166_266		(6 << 0)
62  #define   GC_CLOCK_166_250		(7 << 0)
63  
64  #define GCFGC2	0xda
65  #define GCFGC	0xf0 /* 915+ only */
66  #define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
67  #define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
68  #define   GC_DISPLAY_CLOCK_333_MHZ	(4 << 4)
69  #define   GC_DISPLAY_CLOCK_267_MHZ_PNV	(0 << 4)
70  #define   GC_DISPLAY_CLOCK_333_MHZ_PNV	(1 << 4)
71  #define   GC_DISPLAY_CLOCK_444_MHZ_PNV	(2 << 4)
72  #define   GC_DISPLAY_CLOCK_200_MHZ_PNV	(5 << 4)
73  #define   GC_DISPLAY_CLOCK_133_MHZ_PNV	(6 << 4)
74  #define   GC_DISPLAY_CLOCK_167_MHZ_PNV	(7 << 4)
75  #define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
76  #define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
77  #define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
78  #define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
79  #define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
80  #define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
81  #define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
82  #define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
83  #define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
84  #define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
85  #define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
86  #define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
87  #define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
88  #define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
89  #define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
90  #define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
91  #define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
92  #define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
93  #define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
94  #define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
95  #define GCDGMBUS 0xcc
96  #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
97  
98  
99  /* Graphics reset regs */
100  #define I915_GDRST 0xc0 /* PCI config register */
101  #define  GRDOM_FULL	(0<<2)
102  #define  GRDOM_RENDER	(1<<2)
103  #define  GRDOM_MEDIA	(3<<2)
104  #define  GRDOM_MASK	(3<<2)
105  #define  GRDOM_RESET_STATUS (1<<1)
106  #define  GRDOM_RESET_ENABLE (1<<0)
107  
108  #define ILK_GDSR (MCHBAR_MIRROR_BASE + 0x2ca4)
109  #define  ILK_GRDOM_FULL		(0<<1)
110  #define  ILK_GRDOM_RENDER	(1<<1)
111  #define  ILK_GRDOM_MEDIA	(3<<1)
112  #define  ILK_GRDOM_MASK		(3<<1)
113  #define  ILK_GRDOM_RESET_ENABLE (1<<0)
114  
115  #define GEN6_MBCUNIT_SNPCR	0x900c /* for LLC config */
116  #define   GEN6_MBC_SNPCR_SHIFT	21
117  #define   GEN6_MBC_SNPCR_MASK	(3<<21)
118  #define   GEN6_MBC_SNPCR_MAX	(0<<21)
119  #define   GEN6_MBC_SNPCR_MED	(1<<21)
120  #define   GEN6_MBC_SNPCR_LOW	(2<<21)
121  #define   GEN6_MBC_SNPCR_MIN	(3<<21) /* only 1/16th of the cache is shared */
122  
123  #define VLV_G3DCTL		0x9024
124  #define VLV_GSCKGCTL		0x9028
125  
126  #define GEN6_MBCTL		0x0907c
127  #define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
128  #define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
129  #define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
130  #define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
131  #define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
132  
133  #define GEN6_GDRST	0x941c
134  #define  GEN6_GRDOM_FULL		(1 << 0)
135  #define  GEN6_GRDOM_RENDER		(1 << 1)
136  #define  GEN6_GRDOM_MEDIA		(1 << 2)
137  #define  GEN6_GRDOM_BLT			(1 << 3)
138  
139  #define RING_PP_DIR_BASE(ring)		((ring)->mmio_base+0x228)
140  #define RING_PP_DIR_BASE_READ(ring)	((ring)->mmio_base+0x518)
141  #define RING_PP_DIR_DCLV(ring)		((ring)->mmio_base+0x220)
142  #define   PP_DIR_DCLV_2G		0xffffffff
143  
144  #define GEN8_RING_PDP_UDW(ring, n)	((ring)->mmio_base+0x270 + ((n) * 8 + 4))
145  #define GEN8_RING_PDP_LDW(ring, n)	((ring)->mmio_base+0x270 + (n) * 8)
146  
147  #define GEN8_R_PWR_CLK_STATE		0x20C8
148  #define   GEN8_RPCS_ENABLE		(1 << 31)
149  #define   GEN8_RPCS_S_CNT_ENABLE	(1 << 18)
150  #define   GEN8_RPCS_S_CNT_SHIFT		15
151  #define   GEN8_RPCS_S_CNT_MASK		(0x7 << GEN8_RPCS_S_CNT_SHIFT)
152  #define   GEN8_RPCS_SS_CNT_ENABLE	(1 << 11)
153  #define   GEN8_RPCS_SS_CNT_SHIFT	8
154  #define   GEN8_RPCS_SS_CNT_MASK		(0x7 << GEN8_RPCS_SS_CNT_SHIFT)
155  #define   GEN8_RPCS_EU_MAX_SHIFT	4
156  #define   GEN8_RPCS_EU_MAX_MASK		(0xf << GEN8_RPCS_EU_MAX_SHIFT)
157  #define   GEN8_RPCS_EU_MIN_SHIFT	0
158  #define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)
159  
160  #define GAM_ECOCHK			0x4090
161  #define   BDW_DISABLE_HDC_INVALIDATION	(1<<25)
162  #define   ECOCHK_SNB_BIT		(1<<10)
163  #define   ECOCHK_DIS_TLB		(1<<8)
164  #define   HSW_ECOCHK_ARB_PRIO_SOL	(1<<6)
165  #define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)
166  #define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)
167  #define   ECOCHK_PPGTT_GFDT_IVB		(0x1<<4)
168  #define   ECOCHK_PPGTT_LLC_IVB		(0x1<<3)
169  #define   ECOCHK_PPGTT_UC_HSW		(0x1<<3)
170  #define   ECOCHK_PPGTT_WT_HSW		(0x2<<3)
171  #define   ECOCHK_PPGTT_WB_HSW		(0x3<<3)
172  
173  #define GEN8_RC6_CTX_INFO		0x8504
174  
175  #define GAC_ECO_BITS			0x14090
176  #define   ECOBITS_SNB_BIT		(1<<13)
177  #define   ECOBITS_PPGTT_CACHE64B	(3<<8)
178  #define   ECOBITS_PPGTT_CACHE4B		(0<<8)
179  
180  #define GAB_CTL				0x24000
181  #define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1<<8)
182  
183  #define GEN6_STOLEN_RESERVED		0x1082C0
184  #define GEN6_STOLEN_RESERVED_ADDR_MASK	(0xFFF << 20)
185  #define GEN7_STOLEN_RESERVED_ADDR_MASK	(0x3FFF << 18)
186  #define GEN6_STOLEN_RESERVED_SIZE_MASK	(3 << 4)
187  #define GEN6_STOLEN_RESERVED_1M		(0 << 4)
188  #define GEN6_STOLEN_RESERVED_512K	(1 << 4)
189  #define GEN6_STOLEN_RESERVED_256K	(2 << 4)
190  #define GEN6_STOLEN_RESERVED_128K	(3 << 4)
191  #define GEN7_STOLEN_RESERVED_SIZE_MASK	(1 << 5)
192  #define GEN7_STOLEN_RESERVED_1M		(0 << 5)
193  #define GEN7_STOLEN_RESERVED_256K	(1 << 5)
194  #define GEN8_STOLEN_RESERVED_SIZE_MASK	(3 << 7)
195  #define GEN8_STOLEN_RESERVED_1M		(0 << 7)
196  #define GEN8_STOLEN_RESERVED_2M		(1 << 7)
197  #define GEN8_STOLEN_RESERVED_4M		(2 << 7)
198  #define GEN8_STOLEN_RESERVED_8M		(3 << 7)
199  
200  /* VGA stuff */
201  
202  #define VGA_ST01_MDA 0x3ba
203  #define VGA_ST01_CGA 0x3da
204  
205  #define VGA_MSR_WRITE 0x3c2
206  #define VGA_MSR_READ 0x3cc
207  #define   VGA_MSR_MEM_EN (1<<1)
208  #define   VGA_MSR_CGA_MODE (1<<0)
209  
210  #define VGA_SR_INDEX 0x3c4
211  #define SR01			1
212  #define VGA_SR_DATA 0x3c5
213  
214  #define VGA_AR_INDEX 0x3c0
215  #define   VGA_AR_VID_EN (1<<5)
216  #define VGA_AR_DATA_WRITE 0x3c0
217  #define VGA_AR_DATA_READ 0x3c1
218  
219  #define VGA_GR_INDEX 0x3ce
220  #define VGA_GR_DATA 0x3cf
221  /* GR05 */
222  #define   VGA_GR_MEM_READ_MODE_SHIFT 3
223  #define     VGA_GR_MEM_READ_MODE_PLANE 1
224  /* GR06 */
225  #define   VGA_GR_MEM_MODE_MASK 0xc
226  #define   VGA_GR_MEM_MODE_SHIFT 2
227  #define   VGA_GR_MEM_A0000_AFFFF 0
228  #define   VGA_GR_MEM_A0000_BFFFF 1
229  #define   VGA_GR_MEM_B0000_B7FFF 2
230  #define   VGA_GR_MEM_B0000_BFFFF 3
231  
232  #define VGA_DACMASK 0x3c6
233  #define VGA_DACRX 0x3c7
234  #define VGA_DACWX 0x3c8
235  #define VGA_DACDATA 0x3c9
236  
237  #define VGA_CR_INDEX_MDA 0x3b4
238  #define VGA_CR_DATA_MDA 0x3b5
239  #define VGA_CR_INDEX_CGA 0x3d4
240  #define VGA_CR_DATA_CGA 0x3d5
241  
242  /*
243   * Instruction field definitions used by the command parser
244   */
245  #define INSTR_CLIENT_SHIFT      29
246  #define INSTR_CLIENT_MASK       0xE0000000
247  #define   INSTR_MI_CLIENT       0x0
248  #define   INSTR_BC_CLIENT       0x2
249  #define   INSTR_RC_CLIENT       0x3
250  #define INSTR_SUBCLIENT_SHIFT   27
251  #define INSTR_SUBCLIENT_MASK    0x18000000
252  #define   INSTR_MEDIA_SUBCLIENT 0x2
253  #define INSTR_26_TO_24_MASK	0x7000000
254  #define   INSTR_26_TO_24_SHIFT	24
255  
256  /*
257   * Memory interface instructions used by the kernel
258   */
259  #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
260  /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
261  #define  MI_GLOBAL_GTT    (1<<22)
262  
263  #define MI_NOOP			MI_INSTR(0, 0)
264  #define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
265  #define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
266  #define   MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)
267  #define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
268  #define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
269  #define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
270  #define MI_FLUSH		MI_INSTR(0x04, 0)
271  #define   MI_READ_FLUSH		(1 << 0)
272  #define   MI_EXE_FLUSH		(1 << 1)
273  #define   MI_NO_WRITE_FLUSH	(1 << 2)
274  #define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
275  #define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
276  #define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */
277  #define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
278  #define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)
279  #define   MI_ARB_ENABLE			(1<<0)
280  #define   MI_ARB_DISABLE		(0<<0)
281  #define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
282  #define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
283  #define   MI_SUSPEND_FLUSH_EN	(1<<0)
284  #define MI_SET_APPID		MI_INSTR(0x0e, 0)
285  #define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)
286  #define   MI_OVERLAY_CONTINUE	(0x0<<21)
287  #define   MI_OVERLAY_ON		(0x1<<21)
288  #define   MI_OVERLAY_OFF	(0x2<<21)
289  #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
290  #define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
291  #define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
292  #define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
293  /* IVB has funny definitions for which plane to flip. */
294  #define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
295  #define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
296  #define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
297  #define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
298  #define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
299  #define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
300  /* SKL ones */
301  #define   MI_DISPLAY_FLIP_SKL_PLANE_1_A	(0 << 8)
302  #define   MI_DISPLAY_FLIP_SKL_PLANE_1_B	(1 << 8)
303  #define   MI_DISPLAY_FLIP_SKL_PLANE_1_C	(2 << 8)
304  #define   MI_DISPLAY_FLIP_SKL_PLANE_2_A	(4 << 8)
305  #define   MI_DISPLAY_FLIP_SKL_PLANE_2_B	(5 << 8)
306  #define   MI_DISPLAY_FLIP_SKL_PLANE_2_C	(6 << 8)
307  #define   MI_DISPLAY_FLIP_SKL_PLANE_3_A	(7 << 8)
308  #define   MI_DISPLAY_FLIP_SKL_PLANE_3_B	(8 << 8)
309  #define   MI_DISPLAY_FLIP_SKL_PLANE_3_C	(9 << 8)
310  #define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6, gen7 */
311  #define   MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
312  #define   MI_SEMAPHORE_UPDATE	    (1<<21)
313  #define   MI_SEMAPHORE_COMPARE	    (1<<20)
314  #define   MI_SEMAPHORE_REGISTER	    (1<<18)
315  #define   MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS  wait for VCS  (RVSYNC) */
316  #define   MI_SEMAPHORE_SYNC_VER	    (1<<16) /* RCS  wait for VECS (RVESYNC) */
317  #define   MI_SEMAPHORE_SYNC_BR	    (2<<16) /* RCS  wait for BCS  (RBSYNC) */
318  #define   MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS  wait for BCS  (VBSYNC) */
319  #define   MI_SEMAPHORE_SYNC_VEV	    (1<<16) /* VCS  wait for VECS (VVESYNC) */
320  #define   MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS  wait for RCS  (VRSYNC) */
321  #define   MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS  wait for RCS  (BRSYNC) */
322  #define   MI_SEMAPHORE_SYNC_VEB	    (1<<16) /* BCS  wait for VECS (BVESYNC) */
323  #define   MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS  wait for VCS  (BVSYNC) */
324  #define   MI_SEMAPHORE_SYNC_BVE	    (0<<16) /* VECS wait for BCS  (VEBSYNC) */
325  #define   MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */
326  #define   MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */
327  #define   MI_SEMAPHORE_SYNC_INVALID (3<<16)
328  #define   MI_SEMAPHORE_SYNC_MASK    (3<<16)
329  #define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
330  #define   MI_MM_SPACE_GTT		(1<<8)
331  #define   MI_MM_SPACE_PHYSICAL		(0<<8)
332  #define   MI_SAVE_EXT_STATE_EN		(1<<3)
333  #define   MI_RESTORE_EXT_STATE_EN	(1<<2)
334  #define   MI_FORCE_RESTORE		(1<<1)
335  #define   MI_RESTORE_INHIBIT		(1<<0)
336  #define   HSW_MI_RS_SAVE_STATE_EN       (1<<3)
337  #define   HSW_MI_RS_RESTORE_STATE_EN    (1<<2)
338  #define MI_SEMAPHORE_SIGNAL	MI_INSTR(0x1b, 0) /* GEN8+ */
339  #define   MI_SEMAPHORE_TARGET(engine)	((engine)<<15)
340  #define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
341  #define   MI_SEMAPHORE_POLL		(1<<15)
342  #define   MI_SEMAPHORE_SAD_GTE_SDD	(1<<12)
343  #define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
344  #define MI_STORE_DWORD_IMM_GEN4	MI_INSTR(0x20, 2)
345  #define   MI_MEM_VIRTUAL	(1 << 22) /* 945,g33,965 */
346  #define   MI_USE_GGTT		(1 << 22) /* g4x+ */
347  #define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
348  #define   MI_STORE_DWORD_INDEX_SHIFT 2
349  /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
350   * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
351   *   simply ignores the register load under certain conditions.
352   * - One can actually load arbitrary many arbitrary registers: Simply issue x
353   *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
354   */
355  #define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*(x)-1)
356  #define   MI_LRI_FORCE_POSTED		(1<<12)
357  #define MI_STORE_REGISTER_MEM        MI_INSTR(0x24, 1)
358  #define MI_STORE_REGISTER_MEM_GEN8   MI_INSTR(0x24, 2)
359  #define   MI_SRM_LRM_GLOBAL_GTT		(1<<22)
360  #define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
361  #define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
362  #define   MI_INVALIDATE_TLB		(1<<18)
363  #define   MI_FLUSH_DW_OP_STOREDW	(1<<14)
364  #define   MI_FLUSH_DW_OP_MASK		(3<<14)
365  #define   MI_FLUSH_DW_NOTIFY		(1<<8)
366  #define   MI_INVALIDATE_BSD		(1<<7)
367  #define   MI_FLUSH_DW_USE_GTT		(1<<2)
368  #define   MI_FLUSH_DW_USE_PPGTT		(0<<2)
369  #define MI_LOAD_REGISTER_MEM	   MI_INSTR(0x29, 1)
370  #define MI_LOAD_REGISTER_MEM_GEN8  MI_INSTR(0x29, 2)
371  #define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
372  #define   MI_BATCH_NON_SECURE		(1)
373  /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
374  #define   MI_BATCH_NON_SECURE_I965	(1<<8)
375  #define   MI_BATCH_PPGTT_HSW		(1<<8)
376  #define   MI_BATCH_NON_SECURE_HSW	(1<<13)
377  #define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
378  #define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */
379  #define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)
380  #define   MI_BATCH_RESOURCE_STREAMER (1<<10)
381  
382  #define MI_PREDICATE_SRC0	(0x2400)
383  #define MI_PREDICATE_SRC1	(0x2408)
384  
385  #define MI_PREDICATE_RESULT_2	(0x2214)
386  #define  LOWER_SLICE_ENABLED	(1<<0)
387  #define  LOWER_SLICE_DISABLED	(0<<0)
388  
389  /*
390   * 3D instructions used by the kernel
391   */
392  #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
393  
394  #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
395  #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
396  #define   SC_UPDATE_SCISSOR       (0x1<<1)
397  #define   SC_ENABLE_MASK          (0x1<<0)
398  #define   SC_ENABLE               (0x1<<0)
399  #define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
400  #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
401  #define   SCI_YMIN_MASK      (0xffff<<16)
402  #define   SCI_XMIN_MASK      (0xffff<<0)
403  #define   SCI_YMAX_MASK      (0xffff<<16)
404  #define   SCI_XMAX_MASK      (0xffff<<0)
405  #define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
406  #define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
407  #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
408  #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
409  #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
410  #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
411  #define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
412  #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
413  #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
414  
415  #define COLOR_BLT_CMD			(2<<29 | 0x40<<22 | (5-2))
416  #define SRC_COPY_BLT_CMD		((2<<29)|(0x43<<22)|4)
417  #define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
418  #define XY_MONO_SRC_COPY_IMM_BLT	((2<<29)|(0x71<<22)|5)
419  #define   BLT_WRITE_A			(2<<20)
420  #define   BLT_WRITE_RGB			(1<<20)
421  #define   BLT_WRITE_RGBA		(BLT_WRITE_RGB | BLT_WRITE_A)
422  #define   BLT_DEPTH_8			(0<<24)
423  #define   BLT_DEPTH_16_565		(1<<24)
424  #define   BLT_DEPTH_16_1555		(2<<24)
425  #define   BLT_DEPTH_32			(3<<24)
426  #define   BLT_ROP_SRC_COPY		(0xcc<<16)
427  #define   BLT_ROP_COLOR_COPY		(0xf0<<16)
428  #define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */
429  #define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */
430  #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
431  #define   ASYNC_FLIP                (1<<22)
432  #define   DISPLAY_PLANE_A           (0<<20)
433  #define   DISPLAY_PLANE_B           (1<<20)
434  #define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
435  #define   PIPE_CONTROL_FLUSH_L3				(1<<27)
436  #define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
437  #define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
438  #define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)
439  #define   PIPE_CONTROL_CS_STALL				(1<<20)
440  #define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
441  #define   PIPE_CONTROL_MEDIA_STATE_CLEAR		(1<<16)
442  #define   PIPE_CONTROL_QW_WRITE				(1<<14)
443  #define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)
444  #define   PIPE_CONTROL_DEPTH_STALL			(1<<13)
445  #define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
446  #define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
447  #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on Ironlake */
448  #define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
449  #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
450  #define   PIPE_CONTROL_NOTIFY				(1<<8)
451  #define   PIPE_CONTROL_FLUSH_ENABLE			(1<<7) /* gen7+ */
452  #define   PIPE_CONTROL_DC_FLUSH_ENABLE			(1<<5)
453  #define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)
454  #define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)
455  #define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)
456  #define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)
457  #define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
458  #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
459  
460  /*
461   * Commands used only by the command parser
462   */
463  #define MI_SET_PREDICATE        MI_INSTR(0x01, 0)
464  #define MI_ARB_CHECK            MI_INSTR(0x05, 0)
465  #define MI_RS_CONTROL           MI_INSTR(0x06, 0)
466  #define MI_URB_ATOMIC_ALLOC     MI_INSTR(0x09, 0)
467  #define MI_PREDICATE            MI_INSTR(0x0C, 0)
468  #define MI_RS_CONTEXT           MI_INSTR(0x0F, 0)
469  #define MI_TOPOLOGY_FILTER      MI_INSTR(0x0D, 0)
470  #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
471  #define MI_URB_CLEAR            MI_INSTR(0x19, 0)
472  #define MI_UPDATE_GTT           MI_INSTR(0x23, 0)
473  #define MI_CLFLUSH              MI_INSTR(0x27, 0)
474  #define MI_REPORT_PERF_COUNT    MI_INSTR(0x28, 0)
475  #define   MI_REPORT_PERF_COUNT_GGTT (1<<0)
476  #define MI_LOAD_REGISTER_REG    MI_INSTR(0x2A, 0)
477  #define MI_RS_STORE_DATA_IMM    MI_INSTR(0x2B, 0)
478  #define MI_LOAD_URB_MEM         MI_INSTR(0x2C, 0)
479  #define MI_STORE_URB_MEM        MI_INSTR(0x2D, 0)
480  #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
481  
482  #define PIPELINE_SELECT                ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
483  #define GFX_OP_3DSTATE_VF_STATISTICS   ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
484  #define MEDIA_VFE_STATE                ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
485  #define  MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
486  #define GPGPU_OBJECT                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
487  #define GPGPU_WALKER                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
488  #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
489  	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
490  #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
491  	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
492  #define GFX_OP_3DSTATE_SO_DECL_LIST \
493  	((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
494  
495  #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
496  	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
497  #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
498  	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
499  #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
500  	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
501  #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
502  	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
503  #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
504  	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
505  
506  #define MFX_WAIT  ((0x3<<29)|(0x1<<27)|(0x0<<16))
507  
508  #define COLOR_BLT     ((0x2<<29)|(0x40<<22))
509  #define SRC_COPY_BLT  ((0x2<<29)|(0x43<<22))
510  
511  /*
512   * Registers used only by the command parser
513   */
514  #define BCS_SWCTRL 0x22200
515  
516  /* There are 16 GPR registers */
517  #define BCS_GPR(n)	(0x22600 + (n) * 8)
518  #define BCS_GPR_UDW(n)	(0x22600 + (n) * 8 + 4)
519  
520  #define GPGPU_THREADS_DISPATCHED        0x2290
521  #define HS_INVOCATION_COUNT             0x2300
522  #define DS_INVOCATION_COUNT             0x2308
523  #define IA_VERTICES_COUNT               0x2310
524  #define IA_PRIMITIVES_COUNT             0x2318
525  #define VS_INVOCATION_COUNT             0x2320
526  #define GS_INVOCATION_COUNT             0x2328
527  #define GS_PRIMITIVES_COUNT             0x2330
528  #define CL_INVOCATION_COUNT             0x2338
529  #define CL_PRIMITIVES_COUNT             0x2340
530  #define PS_INVOCATION_COUNT             0x2348
531  #define PS_DEPTH_COUNT                  0x2350
532  
533  /* There are the 4 64-bit counter registers, one for each stream output */
534  #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
535  
536  #define GEN7_SO_PRIM_STORAGE_NEEDED(n)  (0x5240 + (n) * 8)
537  
538  #define GEN7_3DPRIM_END_OFFSET          0x2420
539  #define GEN7_3DPRIM_START_VERTEX        0x2430
540  #define GEN7_3DPRIM_VERTEX_COUNT        0x2434
541  #define GEN7_3DPRIM_INSTANCE_COUNT      0x2438
542  #define GEN7_3DPRIM_START_INSTANCE      0x243C
543  #define GEN7_3DPRIM_BASE_VERTEX         0x2440
544  
545  #define GEN7_GPGPU_DISPATCHDIMX         0x2500
546  #define GEN7_GPGPU_DISPATCHDIMY         0x2504
547  #define GEN7_GPGPU_DISPATCHDIMZ         0x2508
548  
549  #define OACONTROL 0x2360
550  
551  #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
552  #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
553  #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
554  					 _GEN7_PIPEA_DE_LOAD_SL, \
555  					 _GEN7_PIPEB_DE_LOAD_SL)
556  
557  /*
558   * Reset registers
559   */
560  #define DEBUG_RESET_I830		0x6070
561  #define  DEBUG_RESET_FULL		(1<<7)
562  #define  DEBUG_RESET_RENDER		(1<<8)
563  #define  DEBUG_RESET_DISPLAY		(1<<9)
564  
565  /*
566   * IOSF sideband
567   */
568  #define VLV_IOSF_DOORBELL_REQ			(VLV_DISPLAY_BASE + 0x2100)
569  #define   IOSF_DEVFN_SHIFT			24
570  #define   IOSF_OPCODE_SHIFT			16
571  #define   IOSF_PORT_SHIFT			8
572  #define   IOSF_BYTE_ENABLES_SHIFT		4
573  #define   IOSF_BAR_SHIFT			1
574  #define   IOSF_SB_BUSY				(1<<0)
575  #define   IOSF_PORT_BUNIT			0x3
576  #define   IOSF_PORT_PUNIT			0x4
577  #define   IOSF_PORT_NC				0x11
578  #define   IOSF_PORT_DPIO			0x12
579  #define   IOSF_PORT_DPIO_2			0x1a
580  #define   IOSF_PORT_GPIO_NC			0x13
581  #define   IOSF_PORT_CCK				0x14
582  #define   IOSF_PORT_CCU				0xA9
583  #define   IOSF_PORT_GPS_CORE			0x48
584  #define   IOSF_PORT_FLISDSI			0x1B
585  #define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
586  #define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
587  
588  /* See configdb bunit SB addr map */
589  #define BUNIT_REG_BISOC				0x11
590  
591  #define PUNIT_REG_DSPFREQ			0x36
592  #define   DSPFREQSTAT_SHIFT_CHV			24
593  #define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
594  #define   DSPFREQGUAR_SHIFT_CHV			8
595  #define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
596  #define   DSPFREQSTAT_SHIFT			30
597  #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
598  #define   DSPFREQGUAR_SHIFT			14
599  #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
600  #define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
601  #define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
602  #define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
603  #define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
604  #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
605  #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
606  #define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
607  #define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
608  #define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
609  #define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
610  #define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
611  #define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
612  #define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
613  #define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
614  #define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
615  
616  /* See the PUNIT HAS v0.8 for the below bits */
617  enum punit_power_well {
618  	PUNIT_POWER_WELL_RENDER			= 0,
619  	PUNIT_POWER_WELL_MEDIA			= 1,
620  	PUNIT_POWER_WELL_DISP2D			= 3,
621  	PUNIT_POWER_WELL_DPIO_CMN_BC		= 5,
622  	PUNIT_POWER_WELL_DPIO_TX_B_LANES_01	= 6,
623  	PUNIT_POWER_WELL_DPIO_TX_B_LANES_23	= 7,
624  	PUNIT_POWER_WELL_DPIO_TX_C_LANES_01	= 8,
625  	PUNIT_POWER_WELL_DPIO_TX_C_LANES_23	= 9,
626  	PUNIT_POWER_WELL_DPIO_RX0		= 10,
627  	PUNIT_POWER_WELL_DPIO_RX1		= 11,
628  	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
629  
630  	PUNIT_POWER_WELL_NUM,
631  };
632  
633  enum skl_disp_power_wells {
634  	SKL_DISP_PW_MISC_IO,
635  	SKL_DISP_PW_DDI_A_E,
636  	SKL_DISP_PW_DDI_B,
637  	SKL_DISP_PW_DDI_C,
638  	SKL_DISP_PW_DDI_D,
639  	SKL_DISP_PW_1 = 14,
640  	SKL_DISP_PW_2,
641  };
642  
643  #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
644  #define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1))
645  
646  #define PUNIT_REG_PWRGT_CTRL			0x60
647  #define PUNIT_REG_PWRGT_STATUS			0x61
648  #define   PUNIT_PWRGT_MASK(power_well)		(3 << ((power_well) * 2))
649  #define   PUNIT_PWRGT_PWR_ON(power_well)	(0 << ((power_well) * 2))
650  #define   PUNIT_PWRGT_CLK_GATE(power_well)	(1 << ((power_well) * 2))
651  #define   PUNIT_PWRGT_RESET(power_well)		(2 << ((power_well) * 2))
652  #define   PUNIT_PWRGT_PWR_GATE(power_well)	(3 << ((power_well) * 2))
653  
654  #define PUNIT_REG_GPU_LFM			0xd3
655  #define PUNIT_REG_GPU_FREQ_REQ			0xd4
656  #define PUNIT_REG_GPU_FREQ_STS			0xd8
657  #define   GPLLENABLE				(1<<4)
658  #define   GENFREQSTATUS				(1<<0)
659  #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
660  #define PUNIT_REG_CZ_TIMESTAMP			0xce
661  
662  #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
663  #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
664  
665  #define FB_GFX_FMAX_AT_VMAX_FUSE		0x136
666  #define FB_GFX_FREQ_FUSE_MASK			0xff
667  #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT	24
668  #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT	16
669  #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT	8
670  
671  #define FB_GFX_FMIN_AT_VMIN_FUSE		0x137
672  #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT		8
673  
674  #define PUNIT_REG_DDR_SETUP2			0x139
675  #define   FORCE_DDR_FREQ_REQ_ACK		(1 << 8)
676  #define   FORCE_DDR_LOW_FREQ			(1 << 1)
677  #define   FORCE_DDR_HIGH_FREQ			(1 << 0)
678  
679  #define PUNIT_GPU_STATUS_REG			0xdb
680  #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
681  #define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
682  #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT	8
683  #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff
684  
685  #define PUNIT_GPU_DUTYCYCLE_REG		0xdf
686  #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT	8
687  #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff
688  
689  #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
690  #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
691  #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
692  #define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11
693  #define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
694  #define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
695  #define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
696  #define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
697  #define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
698  #define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
699  
700  #define VLV_TURBO_SOC_OVERRIDE	0x04
701  #define 	VLV_OVERRIDE_EN	1
702  #define 	VLV_SOC_TDP_EN	(1 << 1)
703  #define 	VLV_BIAS_CPU_125_SOC_875 (6 << 2)
704  #define 	CHV_BIAS_CPU_50_SOC_50 (3 << 2)
705  
706  #define VLV_CZ_CLOCK_TO_MILLI_SEC		100000
707  
708  /* vlv2 north clock has */
709  #define CCK_FUSE_REG				0x8
710  #define  CCK_FUSE_HPLL_FREQ_MASK		0x3
711  #define CCK_REG_DSI_PLL_FUSE			0x44
712  #define CCK_REG_DSI_PLL_CONTROL			0x48
713  #define  DSI_PLL_VCO_EN				(1 << 31)
714  #define  DSI_PLL_LDO_GATE			(1 << 30)
715  #define  DSI_PLL_P1_POST_DIV_SHIFT		17
716  #define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)
717  #define  DSI_PLL_P2_MUX_DSI0_DIV2		(1 << 13)
718  #define  DSI_PLL_P3_MUX_DSI1_DIV2		(1 << 12)
719  #define  DSI_PLL_MUX_MASK			(3 << 9)
720  #define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)
721  #define  DSI_PLL_MUX_DSI0_CCK			(1 << 10)
722  #define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)
723  #define  DSI_PLL_MUX_DSI1_CCK			(1 << 9)
724  #define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)
725  #define  DSI_PLL_CLK_GATE_DSI0_DSIPLL		(1 << 8)
726  #define  DSI_PLL_CLK_GATE_DSI1_DSIPLL		(1 << 7)
727  #define  DSI_PLL_CLK_GATE_DSI0_CCK		(1 << 6)
728  #define  DSI_PLL_CLK_GATE_DSI1_CCK		(1 << 5)
729  #define  DSI_PLL_LOCK				(1 << 0)
730  #define CCK_REG_DSI_PLL_DIVIDER			0x4c
731  #define  DSI_PLL_LFSR				(1 << 31)
732  #define  DSI_PLL_FRACTION_EN			(1 << 30)
733  #define  DSI_PLL_FRAC_COUNTER_SHIFT		27
734  #define  DSI_PLL_FRAC_COUNTER_MASK		(7 << 27)
735  #define  DSI_PLL_USYNC_CNT_SHIFT		18
736  #define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)
737  #define  DSI_PLL_N1_DIV_SHIFT			16
738  #define  DSI_PLL_N1_DIV_MASK			(3 << 16)
739  #define  DSI_PLL_M1_DIV_SHIFT			0
740  #define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)
741  #define CCK_CZ_CLOCK_CONTROL			0x62
742  #define CCK_DISPLAY_CLOCK_CONTROL		0x6b
743  #define  CCK_TRUNK_FORCE_ON			(1 << 17)
744  #define  CCK_TRUNK_FORCE_OFF			(1 << 16)
745  #define  CCK_FREQUENCY_STATUS			(0x1f << 8)
746  #define  CCK_FREQUENCY_STATUS_SHIFT		8
747  #define  CCK_FREQUENCY_VALUES			(0x1f << 0)
748  
749  /**
750   * DOC: DPIO
751   *
752   * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
753   * ports. DPIO is the name given to such a display PHY. These PHYs
754   * don't follow the standard programming model using direct MMIO
755   * registers, and instead their registers must be accessed trough IOSF
756   * sideband. VLV has one such PHY for driving ports B and C, and CHV
757   * adds another PHY for driving port D. Each PHY responds to specific
758   * IOSF-SB port.
759   *
760   * Each display PHY is made up of one or two channels. Each channel
761   * houses a common lane part which contains the PLL and other common
762   * logic. CH0 common lane also contains the IOSF-SB logic for the
763   * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
764   * must be running when any DPIO registers are accessed.
765   *
766   * In addition to having their own registers, the PHYs are also
767   * controlled through some dedicated signals from the display
768   * controller. These include PLL reference clock enable, PLL enable,
769   * and CRI clock selection, for example.
770   *
771   * Eeach channel also has two splines (also called data lanes), and
772   * each spline is made up of one Physical Access Coding Sub-Layer
773   * (PCS) block and two TX lanes. So each channel has two PCS blocks
774   * and four TX lanes. The TX lanes are used as DP lanes or TMDS
775   * data/clock pairs depending on the output type.
776   *
777   * Additionally the PHY also contains an AUX lane with AUX blocks
778   * for each channel. This is used for DP AUX communication, but
779   * this fact isn't really relevant for the driver since AUX is
780   * controlled from the display controller side. No DPIO registers
781   * need to be accessed during AUX communication,
782   *
783   * Generally on VLV/CHV the common lane corresponds to the pipe and
784   * the spline (PCS/TX) corresponds to the port.
785   *
786   * For dual channel PHY (VLV/CHV):
787   *
788   *  pipe A == CMN/PLL/REF CH0
789   *
790   *  pipe B == CMN/PLL/REF CH1
791   *
792   *  port B == PCS/TX CH0
793   *
794   *  port C == PCS/TX CH1
795   *
796   * This is especially important when we cross the streams
797   * ie. drive port B with pipe B, or port C with pipe A.
798   *
799   * For single channel PHY (CHV):
800   *
801   *  pipe C == CMN/PLL/REF CH0
802   *
803   *  port D == PCS/TX CH0
804   *
805   * On BXT the entire PHY channel corresponds to the port. That means
806   * the PLL is also now associated with the port rather than the pipe,
807   * and so the clock needs to be routed to the appropriate transcoder.
808   * Port A PLL is directly connected to transcoder EDP and port B/C
809   * PLLs can be routed to any transcoder A/B/C.
810   *
811   * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
812   * digital port D (CHV) or port A (BXT).
813   */
814  /*
815   * Dual channel PHY (VLV/CHV/BXT)
816   * ---------------------------------
817   * |      CH0      |      CH1      |
818   * |  CMN/PLL/REF  |  CMN/PLL/REF  |
819   * |---------------|---------------| Display PHY
820   * | PCS01 | PCS23 | PCS01 | PCS23 |
821   * |-------|-------|-------|-------|
822   * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
823   * ---------------------------------
824   * |     DDI0      |     DDI1      | DP/HDMI ports
825   * ---------------------------------
826   *
827   * Single channel PHY (CHV/BXT)
828   * -----------------
829   * |      CH0      |
830   * |  CMN/PLL/REF  |
831   * |---------------| Display PHY
832   * | PCS01 | PCS23 |
833   * |-------|-------|
834   * |TX0|TX1|TX2|TX3|
835   * -----------------
836   * |     DDI2      | DP/HDMI port
837   * -----------------
838   */
839  #define DPIO_DEVFN			0
840  
841  #define DPIO_CTL			(VLV_DISPLAY_BASE + 0x2110)
842  #define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
843  #define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */
844  #define  DPIO_SFR_BYPASS		(1<<1)
845  #define  DPIO_CMNRST			(1<<0)
846  
847  #define DPIO_PHY(pipe)			((pipe) >> 1)
848  #define DPIO_PHY_IOSF_PORT(phy)		(dev_priv->dpio_phy_iosf_port[phy])
849  
850  /*
851   * Per pipe/PLL DPIO regs
852   */
853  #define _VLV_PLL_DW3_CH0		0x800c
854  #define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
855  #define   DPIO_POST_DIV_DAC		0
856  #define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */
857  #define   DPIO_POST_DIV_LVDS1		2
858  #define   DPIO_POST_DIV_LVDS2		3
859  #define   DPIO_K_SHIFT			(24) /* 4 bits */
860  #define   DPIO_P1_SHIFT			(21) /* 3 bits */
861  #define   DPIO_P2_SHIFT			(16) /* 5 bits */
862  #define   DPIO_N_SHIFT			(12) /* 4 bits */
863  #define   DPIO_ENABLE_CALIBRATION	(1<<11)
864  #define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
865  #define   DPIO_M2DIV_MASK		0xff
866  #define _VLV_PLL_DW3_CH1		0x802c
867  #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
868  
869  #define _VLV_PLL_DW5_CH0		0x8014
870  #define   DPIO_REFSEL_OVERRIDE		27
871  #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
872  #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
873  #define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
874  #define   DPIO_PLL_REFCLK_SEL_MASK	3
875  #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
876  #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
877  #define _VLV_PLL_DW5_CH1		0x8034
878  #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
879  
880  #define _VLV_PLL_DW7_CH0		0x801c
881  #define _VLV_PLL_DW7_CH1		0x803c
882  #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
883  
884  #define _VLV_PLL_DW8_CH0		0x8040
885  #define _VLV_PLL_DW8_CH1		0x8060
886  #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
887  
888  #define VLV_PLL_DW9_BCAST		0xc044
889  #define _VLV_PLL_DW9_CH0		0x8044
890  #define _VLV_PLL_DW9_CH1		0x8064
891  #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
892  
893  #define _VLV_PLL_DW10_CH0		0x8048
894  #define _VLV_PLL_DW10_CH1		0x8068
895  #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
896  
897  #define _VLV_PLL_DW11_CH0		0x804c
898  #define _VLV_PLL_DW11_CH1		0x806c
899  #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
900  
901  /* Spec for ref block start counts at DW10 */
902  #define VLV_REF_DW13			0x80ac
903  
904  #define VLV_CMN_DW0			0x8100
905  
906  /*
907   * Per DDI channel DPIO regs
908   */
909  
910  #define _VLV_PCS_DW0_CH0		0x8200
911  #define _VLV_PCS_DW0_CH1		0x8400
912  #define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
913  #define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
914  #define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1<<4)
915  #define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1<<3)
916  #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
917  
918  #define _VLV_PCS01_DW0_CH0		0x200
919  #define _VLV_PCS23_DW0_CH0		0x400
920  #define _VLV_PCS01_DW0_CH1		0x2600
921  #define _VLV_PCS23_DW0_CH1		0x2800
922  #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
923  #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
924  
925  #define _VLV_PCS_DW1_CH0		0x8204
926  #define _VLV_PCS_DW1_CH1		0x8404
927  #define   CHV_PCS_REQ_SOFTRESET_EN	(1<<23)
928  #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1<<22)
929  #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
930  #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
931  #define   DPIO_PCS_CLK_SOFT_RESET	(1<<5)
932  #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
933  
934  #define _VLV_PCS01_DW1_CH0		0x204
935  #define _VLV_PCS23_DW1_CH0		0x404
936  #define _VLV_PCS01_DW1_CH1		0x2604
937  #define _VLV_PCS23_DW1_CH1		0x2804
938  #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
939  #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
940  
941  #define _VLV_PCS_DW8_CH0		0x8220
942  #define _VLV_PCS_DW8_CH1		0x8420
943  #define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
944  #define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
945  #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
946  
947  #define _VLV_PCS01_DW8_CH0		0x0220
948  #define _VLV_PCS23_DW8_CH0		0x0420
949  #define _VLV_PCS01_DW8_CH1		0x2620
950  #define _VLV_PCS23_DW8_CH1		0x2820
951  #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
952  #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
953  
954  #define _VLV_PCS_DW9_CH0		0x8224
955  #define _VLV_PCS_DW9_CH1		0x8424
956  #define   DPIO_PCS_TX2MARGIN_MASK	(0x7<<13)
957  #define   DPIO_PCS_TX2MARGIN_000	(0<<13)
958  #define   DPIO_PCS_TX2MARGIN_101	(1<<13)
959  #define   DPIO_PCS_TX1MARGIN_MASK	(0x7<<10)
960  #define   DPIO_PCS_TX1MARGIN_000	(0<<10)
961  #define   DPIO_PCS_TX1MARGIN_101	(1<<10)
962  #define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
963  
964  #define _VLV_PCS01_DW9_CH0		0x224
965  #define _VLV_PCS23_DW9_CH0		0x424
966  #define _VLV_PCS01_DW9_CH1		0x2624
967  #define _VLV_PCS23_DW9_CH1		0x2824
968  #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
969  #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
970  
971  #define _CHV_PCS_DW10_CH0		0x8228
972  #define _CHV_PCS_DW10_CH1		0x8428
973  #define   DPIO_PCS_SWING_CALC_TX0_TX2	(1<<30)
974  #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)
975  #define   DPIO_PCS_TX2DEEMP_MASK	(0xf<<24)
976  #define   DPIO_PCS_TX2DEEMP_9P5		(0<<24)
977  #define   DPIO_PCS_TX2DEEMP_6P0		(2<<24)
978  #define   DPIO_PCS_TX1DEEMP_MASK	(0xf<<16)
979  #define   DPIO_PCS_TX1DEEMP_9P5		(0<<16)
980  #define   DPIO_PCS_TX1DEEMP_6P0		(2<<16)
981  #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
982  
983  #define _VLV_PCS01_DW10_CH0		0x0228
984  #define _VLV_PCS23_DW10_CH0		0x0428
985  #define _VLV_PCS01_DW10_CH1		0x2628
986  #define _VLV_PCS23_DW10_CH1		0x2828
987  #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
988  #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
989  
990  #define _VLV_PCS_DW11_CH0		0x822c
991  #define _VLV_PCS_DW11_CH1		0x842c
992  #define   DPIO_TX2_STAGGER_MASK(x)	((x)<<24)
993  #define   DPIO_LANEDESKEW_STRAP_OVRD	(1<<3)
994  #define   DPIO_LEFT_TXFIFO_RST_MASTER	(1<<1)
995  #define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1<<0)
996  #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
997  
998  #define _VLV_PCS01_DW11_CH0		0x022c
999  #define _VLV_PCS23_DW11_CH0		0x042c
1000  #define _VLV_PCS01_DW11_CH1		0x262c
1001  #define _VLV_PCS23_DW11_CH1		0x282c
1002  #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1003  #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1004  
1005  #define _VLV_PCS01_DW12_CH0		0x0230
1006  #define _VLV_PCS23_DW12_CH0		0x0430
1007  #define _VLV_PCS01_DW12_CH1		0x2630
1008  #define _VLV_PCS23_DW12_CH1		0x2830
1009  #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1010  #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1011  
1012  #define _VLV_PCS_DW12_CH0		0x8230
1013  #define _VLV_PCS_DW12_CH1		0x8430
1014  #define   DPIO_TX2_STAGGER_MULT(x)	((x)<<20)
1015  #define   DPIO_TX1_STAGGER_MULT(x)	((x)<<16)
1016  #define   DPIO_TX1_STAGGER_MASK(x)	((x)<<8)
1017  #define   DPIO_LANESTAGGER_STRAP_OVRD	(1<<6)
1018  #define   DPIO_LANESTAGGER_STRAP(x)	((x)<<0)
1019  #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1020  
1021  #define _VLV_PCS_DW14_CH0		0x8238
1022  #define _VLV_PCS_DW14_CH1		0x8438
1023  #define	VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1024  
1025  #define _VLV_PCS_DW23_CH0		0x825c
1026  #define _VLV_PCS_DW23_CH1		0x845c
1027  #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1028  
1029  #define _VLV_TX_DW2_CH0			0x8288
1030  #define _VLV_TX_DW2_CH1			0x8488
1031  #define   DPIO_SWING_MARGIN000_SHIFT	16
1032  #define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
1033  #define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
1034  #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1035  
1036  #define _VLV_TX_DW3_CH0			0x828c
1037  #define _VLV_TX_DW3_CH1			0x848c
1038  /* The following bit for CHV phy */
1039  #define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1<<27)
1040  #define   DPIO_SWING_MARGIN101_SHIFT	16
1041  #define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
1042  #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1043  
1044  #define _VLV_TX_DW4_CH0			0x8290
1045  #define _VLV_TX_DW4_CH1			0x8490
1046  #define   DPIO_SWING_DEEMPH9P5_SHIFT	24
1047  #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1048  #define   DPIO_SWING_DEEMPH6P0_SHIFT	16
1049  #define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1050  #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1051  
1052  #define _VLV_TX3_DW4_CH0		0x690
1053  #define _VLV_TX3_DW4_CH1		0x2a90
1054  #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1055  
1056  #define _VLV_TX_DW5_CH0			0x8294
1057  #define _VLV_TX_DW5_CH1			0x8494
1058  #define   DPIO_TX_OCALINIT_EN		(1<<31)
1059  #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1060  
1061  #define _VLV_TX_DW11_CH0		0x82ac
1062  #define _VLV_TX_DW11_CH1		0x84ac
1063  #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1064  
1065  #define _VLV_TX_DW14_CH0		0x82b8
1066  #define _VLV_TX_DW14_CH1		0x84b8
1067  #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1068  
1069  /* CHV dpPhy registers */
1070  #define _CHV_PLL_DW0_CH0		0x8000
1071  #define _CHV_PLL_DW0_CH1		0x8180
1072  #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1073  
1074  #define _CHV_PLL_DW1_CH0		0x8004
1075  #define _CHV_PLL_DW1_CH1		0x8184
1076  #define   DPIO_CHV_N_DIV_SHIFT		8
1077  #define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
1078  #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1079  
1080  #define _CHV_PLL_DW2_CH0		0x8008
1081  #define _CHV_PLL_DW2_CH1		0x8188
1082  #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1083  
1084  #define _CHV_PLL_DW3_CH0		0x800c
1085  #define _CHV_PLL_DW3_CH1		0x818c
1086  #define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)
1087  #define  DPIO_CHV_FIRST_MOD		(0 << 8)
1088  #define  DPIO_CHV_SECOND_MOD		(1 << 8)
1089  #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
1090  #define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
1091  #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1092  
1093  #define _CHV_PLL_DW6_CH0		0x8018
1094  #define _CHV_PLL_DW6_CH1		0x8198
1095  #define   DPIO_CHV_GAIN_CTRL_SHIFT	16
1096  #define	  DPIO_CHV_INT_COEFF_SHIFT	8
1097  #define   DPIO_CHV_PROP_COEFF_SHIFT	0
1098  #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1099  
1100  #define _CHV_PLL_DW8_CH0		0x8020
1101  #define _CHV_PLL_DW8_CH1		0x81A0
1102  #define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1103  #define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
1104  #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1105  
1106  #define _CHV_PLL_DW9_CH0		0x8024
1107  #define _CHV_PLL_DW9_CH1		0x81A4
1108  #define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
1109  #define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
1110  #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
1111  #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1112  
1113  #define _CHV_CMN_DW0_CH0               0x8100
1114  #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0	19
1115  #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0	18
1116  #define   DPIO_ALLDL_POWERDOWN			(1 << 1)
1117  #define   DPIO_ANYDL_POWERDOWN			(1 << 0)
1118  
1119  #define _CHV_CMN_DW5_CH0               0x8114
1120  #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
1121  #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
1122  #define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
1123  #define   CHV_BUFRIGHTENA1_MASK		(3 << 20)
1124  #define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
1125  #define   CHV_BUFLEFTENA1_NORMAL	(1 << 22)
1126  #define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
1127  #define   CHV_BUFLEFTENA1_MASK		(3 << 22)
1128  
1129  #define _CHV_CMN_DW13_CH0		0x8134
1130  #define _CHV_CMN_DW0_CH1		0x8080
1131  #define   DPIO_CHV_S1_DIV_SHIFT		21
1132  #define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */
1133  #define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */
1134  #define   DPIO_CHV_K_DIV_SHIFT		4
1135  #define   DPIO_PLL_FREQLOCK		(1 << 1)
1136  #define   DPIO_PLL_LOCK			(1 << 0)
1137  #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1138  
1139  #define _CHV_CMN_DW14_CH0		0x8138
1140  #define _CHV_CMN_DW1_CH1		0x8084
1141  #define   DPIO_AFC_RECAL		(1 << 14)
1142  #define   DPIO_DCLKP_EN			(1 << 13)
1143  #define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
1144  #define   CHV_BUFLEFTENA2_NORMAL	(1 << 17) /* CL2 DW1 only */
1145  #define   CHV_BUFLEFTENA2_FORCE		(3 << 17) /* CL2 DW1 only */
1146  #define   CHV_BUFLEFTENA2_MASK		(3 << 17) /* CL2 DW1 only */
1147  #define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
1148  #define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
1149  #define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
1150  #define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
1151  #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1152  
1153  #define _CHV_CMN_DW19_CH0		0x814c
1154  #define _CHV_CMN_DW6_CH1		0x8098
1155  #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1	30 /* CL2 DW6 only */
1156  #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1	29 /* CL2 DW6 only */
1157  #define   DPIO_DYNPWRDOWNEN_CH1		(1 << 28) /* CL2 DW6 only */
1158  #define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
1159  
1160  #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1161  
1162  #define CHV_CMN_DW28			0x8170
1163  #define   DPIO_CL1POWERDOWNEN		(1 << 23)
1164  #define   DPIO_DYNPWRDOWNEN_CH0		(1 << 22)
1165  #define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
1166  #define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
1167  #define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
1168  #define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
1169  
1170  #define CHV_CMN_DW30			0x8178
1171  #define   DPIO_CL2_LDOFUSE_PWRENB	(1 << 6)
1172  #define   DPIO_LRC_BYPASS		(1 << 3)
1173  
1174  #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1175  					(lane) * 0x200 + (offset))
1176  
1177  #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1178  #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1179  #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1180  #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1181  #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1182  #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1183  #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1184  #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1185  #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1186  #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1187  #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1188  #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1189  #define   DPIO_FRC_LATENCY_SHFIT	8
1190  #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1191  #define   DPIO_UPAR_SHIFT		30
1192  
1193  /* BXT PHY registers */
1194  #define _BXT_PHY(phy, a, b)		_PIPE((phy), (a), (b))
1195  
1196  #define BXT_P_CR_GT_DISP_PWRON		0x138090
1197  #define   GT_DISPLAY_POWER_ON(phy)	(1 << (phy))
1198  
1199  #define _PHY_CTL_FAMILY_EDP		0x64C80
1200  #define _PHY_CTL_FAMILY_DDI		0x64C90
1201  #define   COMMON_RESET_DIS		(1 << 31)
1202  #define BXT_PHY_CTL_FAMILY(phy)		_BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \
1203  							_PHY_CTL_FAMILY_EDP)
1204  
1205  /* BXT PHY PLL registers */
1206  #define _PORT_PLL_A			0x46074
1207  #define _PORT_PLL_B			0x46078
1208  #define _PORT_PLL_C			0x4607c
1209  #define   PORT_PLL_ENABLE		(1 << 31)
1210  #define   PORT_PLL_LOCK			(1 << 30)
1211  #define   PORT_PLL_REF_SEL		(1 << 27)
1212  #define BXT_PORT_PLL_ENABLE(port)	_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1213  
1214  #define _PORT_PLL_EBB_0_A		0x162034
1215  #define _PORT_PLL_EBB_0_B		0x6C034
1216  #define _PORT_PLL_EBB_0_C		0x6C340
1217  #define   PORT_PLL_P1_SHIFT		13
1218  #define   PORT_PLL_P1_MASK		(0x07 << PORT_PLL_P1_SHIFT)
1219  #define   PORT_PLL_P1(x)		((x)  << PORT_PLL_P1_SHIFT)
1220  #define   PORT_PLL_P2_SHIFT		8
1221  #define   PORT_PLL_P2_MASK		(0x1f << PORT_PLL_P2_SHIFT)
1222  #define   PORT_PLL_P2(x)		((x)  << PORT_PLL_P2_SHIFT)
1223  #define BXT_PORT_PLL_EBB_0(port)	_PORT3(port, _PORT_PLL_EBB_0_A, \
1224  						_PORT_PLL_EBB_0_B,	\
1225  						_PORT_PLL_EBB_0_C)
1226  
1227  #define _PORT_PLL_EBB_4_A		0x162038
1228  #define _PORT_PLL_EBB_4_B		0x6C038
1229  #define _PORT_PLL_EBB_4_C		0x6C344
1230  #define   PORT_PLL_10BIT_CLK_ENABLE	(1 << 13)
1231  #define   PORT_PLL_RECALIBRATE		(1 << 14)
1232  #define BXT_PORT_PLL_EBB_4(port)	_PORT3(port, _PORT_PLL_EBB_4_A, \
1233  						_PORT_PLL_EBB_4_B,	\
1234  						_PORT_PLL_EBB_4_C)
1235  
1236  #define _PORT_PLL_0_A			0x162100
1237  #define _PORT_PLL_0_B			0x6C100
1238  #define _PORT_PLL_0_C			0x6C380
1239  /* PORT_PLL_0_A */
1240  #define   PORT_PLL_M2_MASK		0xFF
1241  /* PORT_PLL_1_A */
1242  #define   PORT_PLL_N_SHIFT		8
1243  #define   PORT_PLL_N_MASK		(0x0F << PORT_PLL_N_SHIFT)
1244  #define   PORT_PLL_N(x)			((x) << PORT_PLL_N_SHIFT)
1245  /* PORT_PLL_2_A */
1246  #define   PORT_PLL_M2_FRAC_MASK		0x3FFFFF
1247  /* PORT_PLL_3_A */
1248  #define   PORT_PLL_M2_FRAC_ENABLE	(1 << 16)
1249  /* PORT_PLL_6_A */
1250  #define   PORT_PLL_PROP_COEFF_MASK	0xF
1251  #define   PORT_PLL_INT_COEFF_MASK	(0x1F << 8)
1252  #define   PORT_PLL_INT_COEFF(x)		((x)  << 8)
1253  #define   PORT_PLL_GAIN_CTL_MASK	(0x07 << 16)
1254  #define   PORT_PLL_GAIN_CTL(x)		((x)  << 16)
1255  /* PORT_PLL_8_A */
1256  #define   PORT_PLL_TARGET_CNT_MASK	0x3FF
1257  /* PORT_PLL_9_A */
1258  #define  PORT_PLL_LOCK_THRESHOLD_SHIFT	1
1259  #define  PORT_PLL_LOCK_THRESHOLD_MASK	(0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1260  /* PORT_PLL_10_A */
1261  #define  PORT_PLL_DCO_AMP_OVR_EN_H	(1<<27)
1262  #define  PORT_PLL_DCO_AMP_DEFAULT	15
1263  #define  PORT_PLL_DCO_AMP_MASK		0x3c00
1264  #define  PORT_PLL_DCO_AMP(x)		((x)<<10)
1265  #define _PORT_PLL_BASE(port)		_PORT3(port, _PORT_PLL_0_A,	\
1266  						_PORT_PLL_0_B,		\
1267  						_PORT_PLL_0_C)
1268  #define BXT_PORT_PLL(port, idx)		(_PORT_PLL_BASE(port) + (idx) * 4)
1269  
1270  /* BXT PHY common lane registers */
1271  #define _PORT_CL1CM_DW0_A		0x162000
1272  #define _PORT_CL1CM_DW0_BC		0x6C000
1273  #define   PHY_POWER_GOOD		(1 << 16)
1274  #define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
1275  							_PORT_CL1CM_DW0_A)
1276  
1277  #define _PORT_CL1CM_DW9_A		0x162024
1278  #define _PORT_CL1CM_DW9_BC		0x6C024
1279  #define   IREF0RC_OFFSET_SHIFT		8
1280  #define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
1281  #define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \
1282  							_PORT_CL1CM_DW9_A)
1283  
1284  #define _PORT_CL1CM_DW10_A		0x162028
1285  #define _PORT_CL1CM_DW10_BC		0x6C028
1286  #define   IREF1RC_OFFSET_SHIFT		8
1287  #define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
1288  #define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \
1289  							_PORT_CL1CM_DW10_A)
1290  
1291  #define _PORT_CL1CM_DW28_A		0x162070
1292  #define _PORT_CL1CM_DW28_BC		0x6C070
1293  #define   OCL1_POWER_DOWN_EN		(1 << 23)
1294  #define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
1295  #define   SUS_CLK_CONFIG		0x3
1296  #define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \
1297  							_PORT_CL1CM_DW28_A)
1298  
1299  #define _PORT_CL1CM_DW30_A		0x162078
1300  #define _PORT_CL1CM_DW30_BC		0x6C078
1301  #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
1302  #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
1303  							_PORT_CL1CM_DW30_A)
1304  
1305  /* Defined for PHY0 only */
1306  #define BXT_PORT_CL2CM_DW6_BC		0x6C358
1307  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
1308  
1309  /* BXT PHY Ref registers */
1310  #define _PORT_REF_DW3_A			0x16218C
1311  #define _PORT_REF_DW3_BC		0x6C18C
1312  #define   GRC_DONE			(1 << 22)
1313  #define BXT_PORT_REF_DW3(phy)		_BXT_PHY((phy), _PORT_REF_DW3_BC, \
1314  							_PORT_REF_DW3_A)
1315  
1316  #define _PORT_REF_DW6_A			0x162198
1317  #define _PORT_REF_DW6_BC		0x6C198
1318  /*
1319   * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them
1320   * after testing.
1321   */
1322  #define   GRC_CODE_SHIFT		23
1323  #define   GRC_CODE_MASK			(0x1FF << GRC_CODE_SHIFT)
1324  #define   GRC_CODE_FAST_SHIFT		16
1325  #define   GRC_CODE_FAST_MASK		(0x7F << GRC_CODE_FAST_SHIFT)
1326  #define   GRC_CODE_SLOW_SHIFT		8
1327  #define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
1328  #define   GRC_CODE_NOM_MASK		0xFF
1329  #define BXT_PORT_REF_DW6(phy)		_BXT_PHY((phy), _PORT_REF_DW6_BC,	\
1330  						      _PORT_REF_DW6_A)
1331  
1332  #define _PORT_REF_DW8_A			0x1621A0
1333  #define _PORT_REF_DW8_BC		0x6C1A0
1334  #define   GRC_DIS			(1 << 15)
1335  #define   GRC_RDY_OVRD			(1 << 1)
1336  #define BXT_PORT_REF_DW8(phy)		_BXT_PHY((phy), _PORT_REF_DW8_BC,	\
1337  						      _PORT_REF_DW8_A)
1338  
1339  /* BXT PHY PCS registers */
1340  #define _PORT_PCS_DW10_LN01_A		0x162428
1341  #define _PORT_PCS_DW10_LN01_B		0x6C428
1342  #define _PORT_PCS_DW10_LN01_C		0x6C828
1343  #define _PORT_PCS_DW10_GRP_A		0x162C28
1344  #define _PORT_PCS_DW10_GRP_B		0x6CC28
1345  #define _PORT_PCS_DW10_GRP_C		0x6CE28
1346  #define BXT_PORT_PCS_DW10_LN01(port)	_PORT3(port, _PORT_PCS_DW10_LN01_A, \
1347  						     _PORT_PCS_DW10_LN01_B, \
1348  						     _PORT_PCS_DW10_LN01_C)
1349  #define BXT_PORT_PCS_DW10_GRP(port)	_PORT3(port, _PORT_PCS_DW10_GRP_A,  \
1350  						     _PORT_PCS_DW10_GRP_B,  \
1351  						     _PORT_PCS_DW10_GRP_C)
1352  #define   TX2_SWING_CALC_INIT		(1 << 31)
1353  #define   TX1_SWING_CALC_INIT		(1 << 30)
1354  
1355  #define _PORT_PCS_DW12_LN01_A		0x162430
1356  #define _PORT_PCS_DW12_LN01_B		0x6C430
1357  #define _PORT_PCS_DW12_LN01_C		0x6C830
1358  #define _PORT_PCS_DW12_LN23_A		0x162630
1359  #define _PORT_PCS_DW12_LN23_B		0x6C630
1360  #define _PORT_PCS_DW12_LN23_C		0x6CA30
1361  #define _PORT_PCS_DW12_GRP_A		0x162c30
1362  #define _PORT_PCS_DW12_GRP_B		0x6CC30
1363  #define _PORT_PCS_DW12_GRP_C		0x6CE30
1364  #define   LANESTAGGER_STRAP_OVRD	(1 << 6)
1365  #define   LANE_STAGGER_MASK		0x1F
1366  #define BXT_PORT_PCS_DW12_LN01(port)	_PORT3(port, _PORT_PCS_DW12_LN01_A, \
1367  						     _PORT_PCS_DW12_LN01_B, \
1368  						     _PORT_PCS_DW12_LN01_C)
1369  #define BXT_PORT_PCS_DW12_LN23(port)	_PORT3(port, _PORT_PCS_DW12_LN23_A, \
1370  						     _PORT_PCS_DW12_LN23_B, \
1371  						     _PORT_PCS_DW12_LN23_C)
1372  #define BXT_PORT_PCS_DW12_GRP(port)	_PORT3(port, _PORT_PCS_DW12_GRP_A, \
1373  						     _PORT_PCS_DW12_GRP_B, \
1374  						     _PORT_PCS_DW12_GRP_C)
1375  
1376  /* BXT PHY TX registers */
1377  #define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
1378  					  ((lane) & 1) * 0x80)
1379  
1380  #define _PORT_TX_DW2_LN0_A		0x162508
1381  #define _PORT_TX_DW2_LN0_B		0x6C508
1382  #define _PORT_TX_DW2_LN0_C		0x6C908
1383  #define _PORT_TX_DW2_GRP_A		0x162D08
1384  #define _PORT_TX_DW2_GRP_B		0x6CD08
1385  #define _PORT_TX_DW2_GRP_C		0x6CF08
1386  #define BXT_PORT_TX_DW2_GRP(port)	_PORT3(port, _PORT_TX_DW2_GRP_A,  \
1387  						     _PORT_TX_DW2_GRP_B,  \
1388  						     _PORT_TX_DW2_GRP_C)
1389  #define BXT_PORT_TX_DW2_LN0(port)	_PORT3(port, _PORT_TX_DW2_LN0_A,  \
1390  						     _PORT_TX_DW2_LN0_B,  \
1391  						     _PORT_TX_DW2_LN0_C)
1392  #define   MARGIN_000_SHIFT		16
1393  #define   MARGIN_000			(0xFF << MARGIN_000_SHIFT)
1394  #define   UNIQ_TRANS_SCALE_SHIFT	8
1395  #define   UNIQ_TRANS_SCALE		(0xFF << UNIQ_TRANS_SCALE_SHIFT)
1396  
1397  #define _PORT_TX_DW3_LN0_A		0x16250C
1398  #define _PORT_TX_DW3_LN0_B		0x6C50C
1399  #define _PORT_TX_DW3_LN0_C		0x6C90C
1400  #define _PORT_TX_DW3_GRP_A		0x162D0C
1401  #define _PORT_TX_DW3_GRP_B		0x6CD0C
1402  #define _PORT_TX_DW3_GRP_C		0x6CF0C
1403  #define BXT_PORT_TX_DW3_GRP(port)	_PORT3(port, _PORT_TX_DW3_GRP_A,  \
1404  						     _PORT_TX_DW3_GRP_B,  \
1405  						     _PORT_TX_DW3_GRP_C)
1406  #define BXT_PORT_TX_DW3_LN0(port)	_PORT3(port, _PORT_TX_DW3_LN0_A,  \
1407  						     _PORT_TX_DW3_LN0_B,  \
1408  						     _PORT_TX_DW3_LN0_C)
1409  #define   SCALE_DCOMP_METHOD		(1 << 26)
1410  #define   UNIQUE_TRANGE_EN_METHOD	(1 << 27)
1411  
1412  #define _PORT_TX_DW4_LN0_A		0x162510
1413  #define _PORT_TX_DW4_LN0_B		0x6C510
1414  #define _PORT_TX_DW4_LN0_C		0x6C910
1415  #define _PORT_TX_DW4_GRP_A		0x162D10
1416  #define _PORT_TX_DW4_GRP_B		0x6CD10
1417  #define _PORT_TX_DW4_GRP_C		0x6CF10
1418  #define BXT_PORT_TX_DW4_LN0(port)	_PORT3(port, _PORT_TX_DW4_LN0_A,  \
1419  						     _PORT_TX_DW4_LN0_B,  \
1420  						     _PORT_TX_DW4_LN0_C)
1421  #define BXT_PORT_TX_DW4_GRP(port)	_PORT3(port, _PORT_TX_DW4_GRP_A,  \
1422  						     _PORT_TX_DW4_GRP_B,  \
1423  						     _PORT_TX_DW4_GRP_C)
1424  #define   DEEMPH_SHIFT			24
1425  #define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)
1426  
1427  #define _PORT_TX_DW14_LN0_A		0x162538
1428  #define _PORT_TX_DW14_LN0_B		0x6C538
1429  #define _PORT_TX_DW14_LN0_C		0x6C938
1430  #define   LATENCY_OPTIM_SHIFT		30
1431  #define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
1432  #define BXT_PORT_TX_DW14_LN(port, lane)	(_PORT3((port), _PORT_TX_DW14_LN0_A,   \
1433  							_PORT_TX_DW14_LN0_B,   \
1434  							_PORT_TX_DW14_LN0_C) + \
1435  					 _BXT_LANE_OFFSET(lane))
1436  
1437  /* UAIMI scratch pad register 1 */
1438  #define UAIMI_SPR1			0x4F074
1439  /* SKL VccIO mask */
1440  #define SKL_VCCIO_MASK			0x1
1441  /* SKL balance leg register */
1442  #define DISPIO_CR_TX_BMU_CR0		0x6C00C
1443  /* I_boost values */
1444  #define BALANCE_LEG_SHIFT(port)		(8+3*(port))
1445  #define BALANCE_LEG_MASK(port)		(7<<(8+3*(port)))
1446  /* Balance leg disable bits */
1447  #define BALANCE_LEG_DISABLE_SHIFT	23
1448  
1449  /*
1450   * Fence registers
1451   * [0-7]  @ 0x2000 gen2,gen3
1452   * [8-15] @ 0x3000 945,g33,pnv
1453   *
1454   * [0-15] @ 0x3000 gen4,gen5
1455   *
1456   * [0-15] @ 0x100000 gen6,vlv,chv
1457   * [0-31] @ 0x100000 gen7+
1458   */
1459  #define FENCE_REG(i)			(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
1460  #define   I830_FENCE_START_MASK		0x07f80000
1461  #define   I830_FENCE_TILING_Y_SHIFT	12
1462  #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
1463  #define   I830_FENCE_PITCH_SHIFT	4
1464  #define   I830_FENCE_REG_VALID		(1<<0)
1465  #define   I915_FENCE_MAX_PITCH_VAL	4
1466  #define   I830_FENCE_MAX_PITCH_VAL	6
1467  #define   I830_FENCE_MAX_SIZE_VAL	(1<<8)
1468  
1469  #define   I915_FENCE_START_MASK		0x0ff00000
1470  #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
1471  
1472  #define FENCE_REG_965_LO(i)		(0x03000 + (i) * 8)
1473  #define FENCE_REG_965_HI(i)		(0x03000 + (i) * 8 + 4)
1474  #define   I965_FENCE_PITCH_SHIFT	2
1475  #define   I965_FENCE_TILING_Y_SHIFT	1
1476  #define   I965_FENCE_REG_VALID		(1<<0)
1477  #define   I965_FENCE_MAX_PITCH_VAL	0x0400
1478  
1479  #define FENCE_REG_GEN6_LO(i)	(0x100000 + (i) * 8)
1480  #define FENCE_REG_GEN6_HI(i)	(0x100000 + (i) * 8 + 4)
1481  #define   GEN6_FENCE_PITCH_SHIFT	32
1482  #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
1483  
1484  
1485  /* control register for cpu gtt access */
1486  #define TILECTL				0x101000
1487  #define   TILECTL_SWZCTL			(1 << 0)
1488  #define   TILECTL_TLBPF			(1 << 1)
1489  #define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
1490  #define   TILECTL_BACKSNOOP_DIS		(1 << 3)
1491  
1492  /*
1493   * Instruction and interrupt control regs
1494   */
1495  #define PGTBL_CTL	0x02020
1496  #define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */
1497  #define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */
1498  #define PGTBL_ER	0x02024
1499  #define PRB0_BASE (0x2030-0x30)
1500  #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
1501  #define PRB2_BASE (0x2050-0x30) /* gen3 */
1502  #define SRB0_BASE (0x2100-0x30) /* gen2 */
1503  #define SRB1_BASE (0x2110-0x30) /* gen2 */
1504  #define SRB2_BASE (0x2120-0x30) /* 830 */
1505  #define SRB3_BASE (0x2130-0x30) /* 830 */
1506  #define RENDER_RING_BASE	0x02000
1507  #define BSD_RING_BASE		0x04000
1508  #define GEN6_BSD_RING_BASE	0x12000
1509  #define GEN8_BSD2_RING_BASE	0x1c000
1510  #define VEBOX_RING_BASE		0x1a000
1511  #define BLT_RING_BASE		0x22000
1512  #define RING_TAIL(base)		((base)+0x30)
1513  #define RING_HEAD(base)		((base)+0x34)
1514  #define RING_START(base)	((base)+0x38)
1515  #define RING_CTL(base)		((base)+0x3c)
1516  #define RING_SYNC_0(base)	((base)+0x40)
1517  #define RING_SYNC_1(base)	((base)+0x44)
1518  #define RING_SYNC_2(base)	((base)+0x48)
1519  #define GEN6_RVSYNC	(RING_SYNC_0(RENDER_RING_BASE))
1520  #define GEN6_RBSYNC	(RING_SYNC_1(RENDER_RING_BASE))
1521  #define GEN6_RVESYNC	(RING_SYNC_2(RENDER_RING_BASE))
1522  #define GEN6_VBSYNC	(RING_SYNC_0(GEN6_BSD_RING_BASE))
1523  #define GEN6_VRSYNC	(RING_SYNC_1(GEN6_BSD_RING_BASE))
1524  #define GEN6_VVESYNC	(RING_SYNC_2(GEN6_BSD_RING_BASE))
1525  #define GEN6_BRSYNC	(RING_SYNC_0(BLT_RING_BASE))
1526  #define GEN6_BVSYNC	(RING_SYNC_1(BLT_RING_BASE))
1527  #define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))
1528  #define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))
1529  #define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))
1530  #define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))
1531  #define GEN6_NOSYNC 0
1532  #define RING_PSMI_CTL(base)	((base)+0x50)
1533  #define RING_MAX_IDLE(base)	((base)+0x54)
1534  #define RING_HWS_PGA(base)	((base)+0x80)
1535  #define RING_HWS_PGA_GEN6(base)	((base)+0x2080)
1536  #define RING_RESET_CTL(base)	((base)+0xd0)
1537  #define   RESET_CTL_REQUEST_RESET  (1 << 0)
1538  #define   RESET_CTL_READY_TO_RESET (1 << 1)
1539  
1540  #define HSW_GTT_CACHE_EN	0x4024
1541  #define   GTT_CACHE_EN_ALL	0xF0007FFF
1542  #define GEN7_WR_WATERMARK	0x4028
1543  #define GEN7_GFX_PRIO_CTRL	0x402C
1544  #define ARB_MODE		0x4030
1545  #define   ARB_MODE_SWIZZLE_SNB	(1<<4)
1546  #define   ARB_MODE_SWIZZLE_IVB	(1<<5)
1547  #define GEN7_GFX_PEND_TLB0	0x4034
1548  #define GEN7_GFX_PEND_TLB1	0x4038
1549  /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
1550  #define GEN7_LRA_LIMITS(i)	(0x403C + (i) * 4)
1551  #define GEN7_LRA_LIMITS_REG_NUM	13
1552  #define GEN7_MEDIA_MAX_REQ_COUNT	0x4070
1553  #define GEN7_GFX_MAX_REQ_COUNT		0x4074
1554  
1555  #define GAMTARBMODE		0x04a08
1556  #define   ARB_MODE_BWGTLB_DISABLE (1<<9)
1557  #define   ARB_MODE_SWIZZLE_BDW	(1<<1)
1558  #define RENDER_HWS_PGA_GEN7	(0x04080)
1559  #define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
1560  #define   RING_FAULT_GTTSEL_MASK (1<<11)
1561  #define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
1562  #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
1563  #define   RING_FAULT_VALID	(1<<0)
1564  #define DONE_REG		0x40b0
1565  #define GEN8_PRIVATE_PAT_LO	0x40e0
1566  #define GEN8_PRIVATE_PAT_HI	(0x40e0 + 4)
1567  #define BSD_HWS_PGA_GEN7	(0x04180)
1568  #define BLT_HWS_PGA_GEN7	(0x04280)
1569  #define VEBOX_HWS_PGA_GEN7	(0x04380)
1570  #define RING_ACTHD(base)	((base)+0x74)
1571  #define RING_ACTHD_UDW(base)	((base)+0x5c)
1572  #define RING_NOPID(base)	((base)+0x94)
1573  #define RING_IMR(base)		((base)+0xa8)
1574  #define RING_HWSTAM(base)	((base)+0x98)
1575  #define RING_TIMESTAMP(base)	((base)+0x358)
1576  #define RING_TIMESTAMP_UDW(base) ((base) + 0x358 + 4)
1577  #define   TAIL_ADDR		0x001FFFF8
1578  #define   HEAD_WRAP_COUNT	0xFFE00000
1579  #define   HEAD_WRAP_ONE		0x00200000
1580  #define   HEAD_ADDR		0x001FFFFC
1581  #define   RING_NR_PAGES		0x001FF000
1582  #define   RING_REPORT_MASK	0x00000006
1583  #define   RING_REPORT_64K	0x00000002
1584  #define   RING_REPORT_128K	0x00000004
1585  #define   RING_NO_REPORT	0x00000000
1586  #define   RING_VALID_MASK	0x00000001
1587  #define   RING_VALID		0x00000001
1588  #define   RING_INVALID		0x00000000
1589  #define   RING_WAIT_I8XX	(1<<0) /* gen2, PRBx_HEAD */
1590  #define   RING_WAIT		(1<<11) /* gen3+, PRBx_CTL */
1591  #define   RING_WAIT_SEMAPHORE	(1<<10) /* gen6+ */
1592  
1593  #define GEN7_TLB_RD_ADDR	0x4700
1594  
1595  #define GEN8_RTCR	0x4260
1596  #define GEN8_M1TCR	0x4264
1597  #define GEN8_M2TCR	0x4268
1598  #define GEN8_BTCR	0x426c
1599  #define GEN8_VTCR	0x4270
1600  
1601  #if 0
1602  #define PRB0_TAIL	0x02030
1603  #define PRB0_HEAD	0x02034
1604  #define PRB0_START	0x02038
1605  #define PRB0_CTL	0x0203c
1606  #define PRB1_TAIL	0x02040 /* 915+ only */
1607  #define PRB1_HEAD	0x02044 /* 915+ only */
1608  #define PRB1_START	0x02048 /* 915+ only */
1609  #define PRB1_CTL	0x0204c /* 915+ only */
1610  #endif
1611  #define IPEIR_I965	0x02064
1612  #define IPEHR_I965	0x02068
1613  #define GEN7_SC_INSTDONE	0x07100
1614  #define GEN7_SAMPLER_INSTDONE	0x0e160
1615  #define GEN7_ROW_INSTDONE	0x0e164
1616  #define I915_NUM_INSTDONE_REG	4
1617  #define RING_IPEIR(base)	((base)+0x64)
1618  #define RING_IPEHR(base)	((base)+0x68)
1619  /*
1620   * On GEN4, only the render ring INSTDONE exists and has a different
1621   * layout than the GEN7+ version.
1622   * The GEN2 counterpart of this register is GEN2_INSTDONE.
1623   */
1624  #define RING_INSTDONE(base)	((base)+0x6c)
1625  #define RING_INSTPS(base)	((base)+0x70)
1626  #define RING_DMA_FADD(base)	((base)+0x78)
1627  #define RING_DMA_FADD_UDW(base)	((base)+0x60) /* gen8+ */
1628  #define RING_INSTPM(base)	((base)+0xc0)
1629  #define RING_MI_MODE(base)	((base)+0x9c)
1630  #define INSTPS		0x02070 /* 965+ only */
1631  #define GEN4_INSTDONE1	0x0207c /* 965+ only, aka INSTDONE_2 on SNB */
1632  #define ACTHD_I965	0x02074
1633  #define HWS_PGA		0x02080
1634  #define HWS_ADDRESS_MASK	0xfffff000
1635  #define HWS_START_ADDRESS_SHIFT	4
1636  #define PWRCTXA		0x2088 /* 965GM+ only */
1637  #define   PWRCTX_EN	(1<<0)
1638  #define IPEIR		0x02088
1639  #define IPEHR		0x0208c
1640  #define GEN2_INSTDONE	0x02090
1641  #define NOPID		0x02094
1642  #define HWSTAM		0x02098
1643  #define DMA_FADD_I8XX	0x020d0
1644  #define RING_BBSTATE(base)	((base)+0x110)
1645  #define RING_BBADDR(base)	((base)+0x140)
1646  #define RING_BBADDR_UDW(base)	((base)+0x168) /* gen8+ */
1647  
1648  #define ERROR_GEN6	0x040a0
1649  #define GEN7_ERR_INT	0x44040
1650  #define   ERR_INT_POISON		(1<<31)
1651  #define   ERR_INT_MMIO_UNCLAIMED	(1<<13)
1652  #define   ERR_INT_PIPE_CRC_DONE_C	(1<<8)
1653  #define   ERR_INT_FIFO_UNDERRUN_C	(1<<6)
1654  #define   ERR_INT_PIPE_CRC_DONE_B	(1<<5)
1655  #define   ERR_INT_FIFO_UNDERRUN_B	(1<<3)
1656  #define   ERR_INT_PIPE_CRC_DONE_A	(1<<2)
1657  #define   ERR_INT_PIPE_CRC_DONE(pipe)	(1<<(2 + (pipe)*3))
1658  #define   ERR_INT_FIFO_UNDERRUN_A	(1<<0)
1659  #define   ERR_INT_FIFO_UNDERRUN(pipe)	(1<<((pipe)*3))
1660  
1661  #define GEN8_FAULT_TLB_DATA0		0x04b10
1662  #define GEN8_FAULT_TLB_DATA1		0x04b14
1663  
1664  #define FPGA_DBG		0x42300
1665  #define   FPGA_DBG_RM_NOCLAIM	(1<<31)
1666  
1667  #define DERRMR		0x44050
1668  /* Note that HBLANK events are reserved on bdw+ */
1669  #define   DERRMR_PIPEA_SCANLINE		(1<<0)
1670  #define   DERRMR_PIPEA_PRI_FLIP_DONE	(1<<1)
1671  #define   DERRMR_PIPEA_SPR_FLIP_DONE	(1<<2)
1672  #define   DERRMR_PIPEA_VBLANK		(1<<3)
1673  #define   DERRMR_PIPEA_HBLANK		(1<<5)
1674  #define   DERRMR_PIPEB_SCANLINE 	(1<<8)
1675  #define   DERRMR_PIPEB_PRI_FLIP_DONE	(1<<9)
1676  #define   DERRMR_PIPEB_SPR_FLIP_DONE	(1<<10)
1677  #define   DERRMR_PIPEB_VBLANK		(1<<11)
1678  #define   DERRMR_PIPEB_HBLANK		(1<<13)
1679  /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
1680  #define   DERRMR_PIPEC_SCANLINE		(1<<14)
1681  #define   DERRMR_PIPEC_PRI_FLIP_DONE	(1<<15)
1682  #define   DERRMR_PIPEC_SPR_FLIP_DONE	(1<<20)
1683  #define   DERRMR_PIPEC_VBLANK		(1<<21)
1684  #define   DERRMR_PIPEC_HBLANK		(1<<22)
1685  
1686  
1687  /* GM45+ chicken bits -- debug workaround bits that may be required
1688   * for various sorts of correct behavior.  The top 16 bits of each are
1689   * the enables for writing to the corresponding low bit.
1690   */
1691  #define _3D_CHICKEN	0x02084
1692  #define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)
1693  #define _3D_CHICKEN2	0x0208c
1694  /* Disables pipelining of read flushes past the SF-WIZ interface.
1695   * Required on all Ironlake steppings according to the B-Spec, but the
1696   * particular danger of not doing so is not specified.
1697   */
1698  # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
1699  #define _3D_CHICKEN3	0x02090
1700  #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
1701  #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
1702  #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x)<<1) /* gen8+ */
1703  #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH	(1 << 1) /* gen6 */
1704  
1705  #define MI_MODE		0x0209c
1706  # define VS_TIMER_DISPATCH				(1 << 6)
1707  # define MI_FLUSH_ENABLE				(1 << 12)
1708  # define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
1709  # define MODE_IDLE					(1 << 9)
1710  # define STOP_RING					(1 << 8)
1711  
1712  #define GEN6_GT_MODE	0x20d0
1713  #define GEN7_GT_MODE	0x7008
1714  #define   GEN6_WIZ_HASHING(hi, lo)			(((hi) << 9) | ((lo) << 7))
1715  #define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)
1716  #define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)
1717  #define   GEN6_WIZ_HASHING_16x4				GEN6_WIZ_HASHING(1, 0)
1718  #define   GEN6_WIZ_HASHING_MASK				GEN6_WIZ_HASHING(1, 1)
1719  #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)
1720  #define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
1721  #define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))
1722  
1723  #define GFX_MODE	0x02520
1724  #define GFX_MODE_GEN7	0x0229c
1725  #define RING_MODE_GEN7(ring)	((ring)->mmio_base+0x29c)
1726  #define   GFX_RUN_LIST_ENABLE		(1<<15)
1727  #define   GFX_INTERRUPT_STEERING	(1<<14)
1728  #define   GFX_TLB_INVALIDATE_EXPLICIT	(1<<13)
1729  #define   GFX_SURFACE_FAULT_ENABLE	(1<<12)
1730  #define   GFX_REPLAY_MODE		(1<<11)
1731  #define   GFX_PSMI_GRANULARITY		(1<<10)
1732  #define   GFX_PPGTT_ENABLE		(1<<9)
1733  #define   GEN8_GFX_PPGTT_48B		(1<<7)
1734  
1735  #define   GFX_FORWARD_VBLANK_MASK	(3<<5)
1736  #define   GFX_FORWARD_VBLANK_NEVER	(0<<5)
1737  #define   GFX_FORWARD_VBLANK_ALWAYS	(1<<5)
1738  #define   GFX_FORWARD_VBLANK_COND	(2<<5)
1739  
1740  #define VLV_DISPLAY_BASE 0x180000
1741  #define VLV_MIPI_BASE VLV_DISPLAY_BASE
1742  
1743  #define VLV_GU_CTL0	(VLV_DISPLAY_BASE + 0x2030)
1744  #define VLV_GU_CTL1	(VLV_DISPLAY_BASE + 0x2034)
1745  #define SCPD0		0x0209c /* 915+ only */
1746  #define IER		0x020a0
1747  #define IIR		0x020a4
1748  #define IMR		0x020a8
1749  #define ISR		0x020ac
1750  #define VLV_GUNIT_CLOCK_GATE	(VLV_DISPLAY_BASE + 0x2060)
1751  #define   GINT_DIS		(1<<22)
1752  #define   GCFG_DIS		(1<<8)
1753  #define VLV_GUNIT_CLOCK_GATE2	(VLV_DISPLAY_BASE + 0x2064)
1754  #define VLV_IIR_RW	(VLV_DISPLAY_BASE + 0x2084)
1755  #define VLV_IER		(VLV_DISPLAY_BASE + 0x20a0)
1756  #define VLV_IIR		(VLV_DISPLAY_BASE + 0x20a4)
1757  #define VLV_IMR		(VLV_DISPLAY_BASE + 0x20a8)
1758  #define VLV_ISR		(VLV_DISPLAY_BASE + 0x20ac)
1759  #define VLV_PCBR	(VLV_DISPLAY_BASE + 0x2120)
1760  #define VLV_PCBR_ADDR_SHIFT	12
1761  
1762  #define   DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
1763  #define EIR		0x020b0
1764  #define EMR		0x020b4
1765  #define ESR		0x020b8
1766  #define   GM45_ERROR_PAGE_TABLE				(1<<5)
1767  #define   GM45_ERROR_MEM_PRIV				(1<<4)
1768  #define   I915_ERROR_PAGE_TABLE				(1<<4)
1769  #define   GM45_ERROR_CP_PRIV				(1<<3)
1770  #define   I915_ERROR_MEMORY_REFRESH			(1<<1)
1771  #define   I915_ERROR_INSTRUCTION			(1<<0)
1772  #define INSTPM	        0x020c0
1773  #define   INSTPM_SELF_EN (1<<12) /* 915GM only */
1774  #define   INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
1775  					will not assert AGPBUSY# and will only
1776  					be delivered when out of C3. */
1777  #define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */
1778  #define   INSTPM_TLB_INVALIDATE	(1<<9)
1779  #define   INSTPM_SYNC_FLUSH	(1<<5)
1780  #define ACTHD	        0x020c8
1781  #define MEM_MODE	0x020cc
1782  #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
1783  #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
1784  #define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
1785  #define FW_BLC		0x020d8
1786  #define FW_BLC2		0x020dc
1787  #define FW_BLC_SELF	0x020e0 /* 915+ only */
1788  #define   FW_BLC_SELF_EN_MASK      (1<<31)
1789  #define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
1790  #define   FW_BLC_SELF_EN           (1<<15) /* 945 only */
1791  #define MM_BURST_LENGTH     0x00700000
1792  #define MM_FIFO_WATERMARK   0x0001F000
1793  #define LM_BURST_LENGTH     0x00000700
1794  #define LM_FIFO_WATERMARK   0x0000001F
1795  #define MI_ARB_STATE	0x020e4 /* 915+ only */
1796  
1797  /* Make render/texture TLB fetches lower priorty than associated data
1798   *   fetches. This is not turned on by default
1799   */
1800  #define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)
1801  
1802  /* Isoch request wait on GTT enable (Display A/B/C streams).
1803   * Make isoch requests stall on the TLB update. May cause
1804   * display underruns (test mode only)
1805   */
1806  #define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)
1807  
1808  /* Block grant count for isoch requests when block count is
1809   * set to a finite value.
1810   */
1811  #define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)
1812  #define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
1813  #define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */
1814  #define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */
1815  #define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */
1816  
1817  /* Enable render writes to complete in C2/C3/C4 power states.
1818   * If this isn't enabled, render writes are prevented in low
1819   * power states. That seems bad to me.
1820   */
1821  #define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)
1822  
1823  /* This acknowledges an async flip immediately instead
1824   * of waiting for 2TLB fetches.
1825   */
1826  #define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)
1827  
1828  /* Enables non-sequential data reads through arbiter
1829   */
1830  #define   MI_ARB_DUAL_DATA_PHASE_DISABLE	(1 << 9)
1831  
1832  /* Disable FSB snooping of cacheable write cycles from binner/render
1833   * command stream
1834   */
1835  #define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)
1836  
1837  /* Arbiter time slice for non-isoch streams */
1838  #define   MI_ARB_TIME_SLICE_MASK		(7 << 5)
1839  #define   MI_ARB_TIME_SLICE_1			(0 << 5)
1840  #define   MI_ARB_TIME_SLICE_2			(1 << 5)
1841  #define   MI_ARB_TIME_SLICE_4			(2 << 5)
1842  #define   MI_ARB_TIME_SLICE_6			(3 << 5)
1843  #define   MI_ARB_TIME_SLICE_8			(4 << 5)
1844  #define   MI_ARB_TIME_SLICE_10			(5 << 5)
1845  #define   MI_ARB_TIME_SLICE_14			(6 << 5)
1846  #define   MI_ARB_TIME_SLICE_16			(7 << 5)
1847  
1848  /* Low priority grace period page size */
1849  #define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
1850  #define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
1851  
1852  /* Disable display A/B trickle feed */
1853  #define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
1854  
1855  /* Set display plane priority */
1856  #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
1857  #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
1858  
1859  #define MI_STATE	0x020e4 /* gen2 only */
1860  #define   MI_AGPBUSY_INT_EN			(1 << 1) /* 85x only */
1861  #define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
1862  
1863  #define CACHE_MODE_0	0x02120 /* 915+ only */
1864  #define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
1865  #define   CM0_IZ_OPT_DISABLE      (1<<6)
1866  #define   CM0_ZR_OPT_DISABLE      (1<<5)
1867  #define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1<<5)
1868  #define   CM0_DEPTH_EVICT_DISABLE (1<<4)
1869  #define   CM0_COLOR_EVICT_DISABLE (1<<3)
1870  #define   CM0_DEPTH_WRITE_DISABLE (1<<1)
1871  #define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
1872  #define GFX_FLSH_CNTL	0x02170 /* 915+ only */
1873  #define GFX_FLSH_CNTL_GEN6	0x101008
1874  #define   GFX_FLSH_CNTL_EN	(1<<0)
1875  #define ECOSKPD		0x021d0
1876  #define   ECO_GATING_CX_ONLY	(1<<3)
1877  #define   ECO_FLIP_DONE		(1<<0)
1878  
1879  #define CACHE_MODE_0_GEN7	0x7000 /* IVB+ */
1880  #define RC_OP_FLUSH_ENABLE (1<<0)
1881  #define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)
1882  #define CACHE_MODE_1		0x7004 /* IVB+ */
1883  #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1<<6)
1884  #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1<<6)
1885  #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1<<1)
1886  
1887  #define GEN6_BLITTER_ECOSKPD	0x221d0
1888  #define   GEN6_BLITTER_LOCK_SHIFT			16
1889  #define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
1890  
1891  #define GEN6_RC_SLEEP_PSMI_CONTROL	0x2050
1892  #define   GEN6_PSMI_SLEEP_MSG_DISABLE	(1 << 0)
1893  #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
1894  #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1<<10)
1895  
1896  /* Fuse readout registers for GT */
1897  #define CHV_FUSE_GT			(VLV_DISPLAY_BASE + 0x2168)
1898  #define   CHV_FGT_DISABLE_SS0		(1 << 10)
1899  #define   CHV_FGT_DISABLE_SS1		(1 << 11)
1900  #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
1901  #define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
1902  #define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
1903  #define   CHV_FGT_EU_DIS_SS0_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
1904  #define   CHV_FGT_EU_DIS_SS1_R0_SHIFT	24
1905  #define   CHV_FGT_EU_DIS_SS1_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
1906  #define   CHV_FGT_EU_DIS_SS1_R1_SHIFT	28
1907  #define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
1908  
1909  #define GEN8_FUSE2			0x9120
1910  #define   GEN8_F2_SS_DIS_SHIFT		21
1911  #define   GEN8_F2_SS_DIS_MASK		(0x7 << GEN8_F2_SS_DIS_SHIFT)
1912  #define   GEN8_F2_S_ENA_SHIFT		25
1913  #define   GEN8_F2_S_ENA_MASK		(0x7 << GEN8_F2_S_ENA_SHIFT)
1914  
1915  #define   GEN9_F2_SS_DIS_SHIFT		20
1916  #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
1917  
1918  #define GEN8_EU_DISABLE0		0x9134
1919  #define   GEN8_EU_DIS0_S0_MASK		0xffffff
1920  #define   GEN8_EU_DIS0_S1_SHIFT		24
1921  #define   GEN8_EU_DIS0_S1_MASK		(0xff << GEN8_EU_DIS0_S1_SHIFT)
1922  
1923  #define GEN8_EU_DISABLE1		0x9138
1924  #define   GEN8_EU_DIS1_S1_MASK		0xffff
1925  #define   GEN8_EU_DIS1_S2_SHIFT		16
1926  #define   GEN8_EU_DIS1_S2_MASK		(0xffff << GEN8_EU_DIS1_S2_SHIFT)
1927  
1928  #define GEN8_EU_DISABLE2		0x913c
1929  #define   GEN8_EU_DIS2_S2_MASK		0xff
1930  
1931  #define GEN9_EU_DISABLE(slice)		(0x9134 + (slice)*0x4)
1932  
1933  #define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
1934  #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
1935  #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
1936  #define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)
1937  #define   GEN6_BSD_GO_INDICATOR		(1 << 4)
1938  
1939  /* On modern GEN architectures interrupt control consists of two sets
1940   * of registers. The first set pertains to the ring generating the
1941   * interrupt. The second control is for the functional block generating the
1942   * interrupt. These are PM, GT, DE, etc.
1943   *
1944   * Luckily *knocks on wood* all the ring interrupt bits match up with the
1945   * GT interrupt bits, so we don't need to duplicate the defines.
1946   *
1947   * These defines should cover us well from SNB->HSW with minor exceptions
1948   * it can also work on ILK.
1949   */
1950  #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT		(1 << 26)
1951  #define GT_BLT_CS_ERROR_INTERRUPT		(1 << 25)
1952  #define GT_BLT_USER_INTERRUPT			(1 << 22)
1953  #define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)
1954  #define GT_BSD_USER_INTERRUPT			(1 << 12)
1955  #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1	(1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
1956  #define GT_CONTEXT_SWITCH_INTERRUPT		(1 <<  8)
1957  #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT	(1 <<  5) /* !snb */
1958  #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	(1 <<  4)
1959  #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT	(1 <<  3)
1960  #define GT_RENDER_SYNC_STATUS_INTERRUPT		(1 <<  2)
1961  #define GT_RENDER_DEBUG_INTERRUPT		(1 <<  1)
1962  #define GT_RENDER_USER_INTERRUPT		(1 <<  0)
1963  
1964  #define PM_VEBOX_CS_ERROR_INTERRUPT		(1 << 12) /* hsw+ */
1965  #define PM_VEBOX_USER_INTERRUPT			(1 << 10) /* hsw+ */
1966  
1967  #define GT_PARITY_ERROR(dev) \
1968  	(GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
1969  	 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
1970  
1971  /* These are all the "old" interrupts */
1972  #define ILK_BSD_USER_INTERRUPT				(1<<5)
1973  
1974  #define I915_PM_INTERRUPT				(1<<31)
1975  #define I915_ISP_INTERRUPT				(1<<22)
1976  #define I915_LPE_PIPE_B_INTERRUPT			(1<<21)
1977  #define I915_LPE_PIPE_A_INTERRUPT			(1<<20)
1978  #define I915_MIPIC_INTERRUPT				(1<<19)
1979  #define I915_MIPIA_INTERRUPT				(1<<18)
1980  #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
1981  #define I915_DISPLAY_PORT_INTERRUPT			(1<<17)
1982  #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1<<16)
1983  #define I915_MASTER_ERROR_INTERRUPT			(1<<15)
1984  #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
1985  #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1<<14)
1986  #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1<<14) /* p-state */
1987  #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1<<13)
1988  #define I915_HWB_OOM_INTERRUPT				(1<<13)
1989  #define I915_LPE_PIPE_C_INTERRUPT			(1<<12)
1990  #define I915_SYNC_STATUS_INTERRUPT			(1<<12)
1991  #define I915_MISC_INTERRUPT				(1<<11)
1992  #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1<<11)
1993  #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1<<10)
1994  #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1<<10)
1995  #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1<<9)
1996  #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1<<9)
1997  #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1<<8)
1998  #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1<<8)
1999  #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1<<7)
2000  #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
2001  #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
2002  #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
2003  #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1<<3)
2004  #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1<<2)
2005  #define I915_DEBUG_INTERRUPT				(1<<2)
2006  #define I915_WINVALID_INTERRUPT				(1<<1)
2007  #define I915_USER_INTERRUPT				(1<<1)
2008  #define I915_ASLE_INTERRUPT				(1<<0)
2009  #define I915_BSD_USER_INTERRUPT				(1<<25)
2010  
2011  #define GEN6_BSD_RNCID			0x12198
2012  
2013  #define GEN7_FF_THREAD_MODE		0x20a0
2014  #define   GEN7_FF_SCHED_MASK		0x0077070
2015  #define   GEN8_FF_DS_REF_CNT_FFME	(1 << 19)
2016  #define   GEN7_FF_TS_SCHED_HS1		(0x5<<16)
2017  #define   GEN7_FF_TS_SCHED_HS0		(0x3<<16)
2018  #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1<<16)
2019  #define   GEN7_FF_TS_SCHED_HW		(0x0<<16) /* Default */
2020  #define   GEN7_FF_VS_REF_CNT_FFME	(1 << 15)
2021  #define   GEN7_FF_VS_SCHED_HS1		(0x5<<12)
2022  #define   GEN7_FF_VS_SCHED_HS0		(0x3<<12)
2023  #define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1<<12) /* Default */
2024  #define   GEN7_FF_VS_SCHED_HW		(0x0<<12)
2025  #define   GEN7_FF_DS_SCHED_HS1		(0x5<<4)
2026  #define   GEN7_FF_DS_SCHED_HS0		(0x3<<4)
2027  #define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1<<4)  /* Default */
2028  #define   GEN7_FF_DS_SCHED_HW		(0x0<<4)
2029  
2030  /*
2031   * Framebuffer compression (915+ only)
2032   */
2033  
2034  #define FBC_CFB_BASE		0x03200 /* 4k page aligned */
2035  #define FBC_LL_BASE		0x03204 /* 4k page aligned */
2036  #define FBC_CONTROL		0x03208
2037  #define   FBC_CTL_EN		(1<<31)
2038  #define   FBC_CTL_PERIODIC	(1<<30)
2039  #define   FBC_CTL_INTERVAL_SHIFT (16)
2040  #define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
2041  #define   FBC_CTL_C3_IDLE	(1<<13)
2042  #define   FBC_CTL_STRIDE_SHIFT	(5)
2043  #define   FBC_CTL_FENCENO_SHIFT	(0)
2044  #define FBC_COMMAND		0x0320c
2045  #define   FBC_CMD_COMPRESS	(1<<0)
2046  #define FBC_STATUS		0x03210
2047  #define   FBC_STAT_COMPRESSING	(1<<31)
2048  #define   FBC_STAT_COMPRESSED	(1<<30)
2049  #define   FBC_STAT_MODIFIED	(1<<29)
2050  #define   FBC_STAT_CURRENT_LINE_SHIFT	(0)
2051  #define FBC_CONTROL2		0x03214
2052  #define   FBC_CTL_FENCE_DBL	(0<<4)
2053  #define   FBC_CTL_IDLE_IMM	(0<<2)
2054  #define   FBC_CTL_IDLE_FULL	(1<<2)
2055  #define   FBC_CTL_IDLE_LINE	(2<<2)
2056  #define   FBC_CTL_IDLE_DEBUG	(3<<2)
2057  #define   FBC_CTL_CPU_FENCE	(1<<1)
2058  #define   FBC_CTL_PLANE(plane)	((plane)<<0)
2059  #define FBC_FENCE_OFF		0x03218 /* BSpec typo has 321Bh */
2060  #define FBC_TAG(i)		(0x03300 + (i) * 4)
2061  
2062  #define FBC_STATUS2		0x43214
2063  #define  FBC_COMPRESSION_MASK	0x7ff
2064  
2065  #define FBC_LL_SIZE		(1536)
2066  
2067  /* Framebuffer compression for GM45+ */
2068  #define DPFC_CB_BASE		0x3200
2069  #define DPFC_CONTROL		0x3208
2070  #define   DPFC_CTL_EN		(1<<31)
2071  #define   DPFC_CTL_PLANE(plane)	((plane)<<30)
2072  #define   IVB_DPFC_CTL_PLANE(plane)	((plane)<<29)
2073  #define   DPFC_CTL_FENCE_EN	(1<<29)
2074  #define   IVB_DPFC_CTL_FENCE_EN	(1<<28)
2075  #define   DPFC_CTL_PERSISTENT_MODE	(1<<25)
2076  #define   DPFC_SR_EN		(1<<10)
2077  #define   DPFC_CTL_LIMIT_1X	(0<<6)
2078  #define   DPFC_CTL_LIMIT_2X	(1<<6)
2079  #define   DPFC_CTL_LIMIT_4X	(2<<6)
2080  #define DPFC_RECOMP_CTL		0x320c
2081  #define   DPFC_RECOMP_STALL_EN	(1<<27)
2082  #define   DPFC_RECOMP_STALL_WM_SHIFT (16)
2083  #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
2084  #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
2085  #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
2086  #define DPFC_STATUS		0x3210
2087  #define   DPFC_INVAL_SEG_SHIFT  (16)
2088  #define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
2089  #define   DPFC_COMP_SEG_SHIFT	(0)
2090  #define   DPFC_COMP_SEG_MASK	(0x000003ff)
2091  #define DPFC_STATUS2		0x3214
2092  #define DPFC_FENCE_YOFF		0x3218
2093  #define DPFC_CHICKEN		0x3224
2094  #define   DPFC_HT_MODIFY	(1<<31)
2095  
2096  /* Framebuffer compression for Ironlake */
2097  #define ILK_DPFC_CB_BASE	0x43200
2098  #define ILK_DPFC_CONTROL	0x43208
2099  #define   FBC_CTL_FALSE_COLOR	(1<<10)
2100  /* The bit 28-8 is reserved */
2101  #define   DPFC_RESERVED		(0x1FFFFF00)
2102  #define ILK_DPFC_RECOMP_CTL	0x4320c
2103  #define ILK_DPFC_STATUS		0x43210
2104  #define ILK_DPFC_FENCE_YOFF	0x43218
2105  #define ILK_DPFC_CHICKEN	0x43224
2106  #define ILK_FBC_RT_BASE		0x2128
2107  #define   ILK_FBC_RT_VALID	(1<<0)
2108  #define   SNB_FBC_FRONT_BUFFER	(1<<1)
2109  
2110  #define ILK_DISPLAY_CHICKEN1	0x42000
2111  #define   ILK_FBCQ_DIS		(1<<22)
2112  #define	  ILK_PABSTRETCH_DIS	(1<<21)
2113  
2114  
2115  /*
2116   * Framebuffer compression for Sandybridge
2117   *
2118   * The following two registers are of type GTTMMADR
2119   */
2120  #define SNB_DPFC_CTL_SA		0x100100
2121  #define   SNB_CPU_FENCE_ENABLE	(1<<29)
2122  #define DPFC_CPU_FENCE_OFFSET	0x100104
2123  
2124  /* Framebuffer compression for Ivybridge */
2125  #define IVB_FBC_RT_BASE			0x7020
2126  
2127  #define IPS_CTL		0x43408
2128  #define   IPS_ENABLE	(1 << 31)
2129  
2130  #define MSG_FBC_REND_STATE	0x50380
2131  #define   FBC_REND_NUKE		(1<<2)
2132  #define   FBC_REND_CACHE_CLEAN	(1<<1)
2133  
2134  /*
2135   * GPIO regs
2136   */
2137  #define GPIOA			0x5010
2138  #define GPIOB			0x5014
2139  #define GPIOC			0x5018
2140  #define GPIOD			0x501c
2141  #define GPIOE			0x5020
2142  #define GPIOF			0x5024
2143  #define GPIOG			0x5028
2144  #define GPIOH			0x502c
2145  # define GPIO_CLOCK_DIR_MASK		(1 << 0)
2146  # define GPIO_CLOCK_DIR_IN		(0 << 1)
2147  # define GPIO_CLOCK_DIR_OUT		(1 << 1)
2148  # define GPIO_CLOCK_VAL_MASK		(1 << 2)
2149  # define GPIO_CLOCK_VAL_OUT		(1 << 3)
2150  # define GPIO_CLOCK_VAL_IN		(1 << 4)
2151  # define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
2152  # define GPIO_DATA_DIR_MASK		(1 << 8)
2153  # define GPIO_DATA_DIR_IN		(0 << 9)
2154  # define GPIO_DATA_DIR_OUT		(1 << 9)
2155  # define GPIO_DATA_VAL_MASK		(1 << 10)
2156  # define GPIO_DATA_VAL_OUT		(1 << 11)
2157  # define GPIO_DATA_VAL_IN		(1 << 12)
2158  # define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
2159  
2160  #define GMBUS0			(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
2161  #define   GMBUS_RATE_100KHZ	(0<<8)
2162  #define   GMBUS_RATE_50KHZ	(1<<8)
2163  #define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
2164  #define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
2165  #define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
2166  #define   GMBUS_PIN_DISABLED	0
2167  #define   GMBUS_PIN_SSC		1
2168  #define   GMBUS_PIN_VGADDC	2
2169  #define   GMBUS_PIN_PANEL	3
2170  #define   GMBUS_PIN_DPD_CHV	3 /* HDMID_CHV */
2171  #define   GMBUS_PIN_DPC		4 /* HDMIC */
2172  #define   GMBUS_PIN_DPB		5 /* SDVO, HDMIB */
2173  #define   GMBUS_PIN_DPD		6 /* HDMID */
2174  #define   GMBUS_PIN_RESERVED	7 /* 7 reserved */
2175  #define   GMBUS_PIN_1_BXT	1
2176  #define   GMBUS_PIN_2_BXT	2
2177  #define   GMBUS_PIN_3_BXT	3
2178  #define   GMBUS_NUM_PINS	7 /* including 0 */
2179  #define GMBUS1			(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
2180  #define   GMBUS_SW_CLR_INT	(1<<31)
2181  #define   GMBUS_SW_RDY		(1<<30)
2182  #define   GMBUS_ENT		(1<<29) /* enable timeout */
2183  #define   GMBUS_CYCLE_NONE	(0<<25)
2184  #define   GMBUS_CYCLE_WAIT	(1<<25)
2185  #define   GMBUS_CYCLE_INDEX	(2<<25)
2186  #define   GMBUS_CYCLE_STOP	(4<<25)
2187  #define   GMBUS_BYTE_COUNT_SHIFT 16
2188  #define   GMBUS_BYTE_COUNT_MAX   256U
2189  #define   GMBUS_SLAVE_INDEX_SHIFT 8
2190  #define   GMBUS_SLAVE_ADDR_SHIFT 1
2191  #define   GMBUS_SLAVE_READ	(1<<0)
2192  #define   GMBUS_SLAVE_WRITE	(0<<0)
2193  #define GMBUS2			(dev_priv->gpio_mmio_base + 0x5108) /* status */
2194  #define   GMBUS_INUSE		(1<<15)
2195  #define   GMBUS_HW_WAIT_PHASE	(1<<14)
2196  #define   GMBUS_STALL_TIMEOUT	(1<<13)
2197  #define   GMBUS_INT		(1<<12)
2198  #define   GMBUS_HW_RDY		(1<<11)
2199  #define   GMBUS_SATOER		(1<<10)
2200  #define   GMBUS_ACTIVE		(1<<9)
2201  #define GMBUS3			(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
2202  #define GMBUS4			(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
2203  #define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
2204  #define   GMBUS_NAK_EN		(1<<3)
2205  #define   GMBUS_IDLE_EN		(1<<2)
2206  #define   GMBUS_HW_WAIT_EN	(1<<1)
2207  #define   GMBUS_HW_RDY_EN	(1<<0)
2208  #define GMBUS5			(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
2209  #define   GMBUS_2BYTE_INDEX_EN	(1<<31)
2210  
2211  /*
2212   * Clock control & power management
2213   */
2214  #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
2215  #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
2216  #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
2217  #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
2218  
2219  #define VGA0	0x6000
2220  #define VGA1	0x6004
2221  #define VGA_PD	0x6010
2222  #define   VGA0_PD_P2_DIV_4	(1 << 7)
2223  #define   VGA0_PD_P1_DIV_2	(1 << 5)
2224  #define   VGA0_PD_P1_SHIFT	0
2225  #define   VGA0_PD_P1_MASK	(0x1f << 0)
2226  #define   VGA1_PD_P2_DIV_4	(1 << 15)
2227  #define   VGA1_PD_P1_DIV_2	(1 << 13)
2228  #define   VGA1_PD_P1_SHIFT	8
2229  #define   VGA1_PD_P1_MASK	(0x1f << 8)
2230  #define   DPLL_VCO_ENABLE		(1 << 31)
2231  #define   DPLL_SDVO_HIGH_SPEED		(1 << 30)
2232  #define   DPLL_DVO_2X_MODE		(1 << 30)
2233  #define   DPLL_EXT_BUFFER_ENABLE_VLV	(1 << 30)
2234  #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
2235  #define   DPLL_REF_CLK_ENABLE_VLV	(1 << 29)
2236  #define   DPLL_VGA_MODE_DIS		(1 << 28)
2237  #define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
2238  #define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
2239  #define   DPLL_MODE_MASK		(3 << 26)
2240  #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
2241  #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
2242  #define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
2243  #define   DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24) /* i915 */
2244  #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
2245  #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
2246  #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
2247  #define   DPLL_LOCK_VLV			(1<<15)
2248  #define   DPLL_INTEGRATED_CRI_CLK_VLV	(1<<14)
2249  #define   DPLL_INTEGRATED_REF_CLK_VLV	(1<<13)
2250  #define   DPLL_SSC_REF_CLK_CHV		(1<<13)
2251  #define   DPLL_PORTC_READY_MASK		(0xf << 4)
2252  #define   DPLL_PORTB_READY_MASK		(0xf)
2253  
2254  #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
2255  
2256  /* Additional CHV pll/phy registers */
2257  #define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE + 0x6240)
2258  #define   DPLL_PORTD_READY_MASK		(0xf)
2259  #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
2260  #define   PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)	(1 << (2*(phy)+(ch)+27))
2261  #define   PHY_LDO_DELAY_0NS			0x0
2262  #define   PHY_LDO_DELAY_200NS			0x1
2263  #define   PHY_LDO_DELAY_600NS			0x2
2264  #define   PHY_LDO_SEQ_DELAY(delay, phy)		((delay) << (2*(phy)+23))
2265  #define   PHY_CH_POWER_DOWN_OVRD(mask, phy, ch)	((mask) << (8*(phy)+4*(ch)+11))
2266  #define   PHY_CH_SU_PSR				0x1
2267  #define   PHY_CH_DEEP_PSR			0x7
2268  #define   PHY_CH_POWER_MODE(mode, phy, ch)	((mode) << (6*(phy)+3*(ch)+2))
2269  #define   PHY_COM_LANE_RESET_DEASSERT(phy)	(1 << (phy))
2270  #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
2271  #define   PHY_POWERGOOD(phy)	(((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
2272  #define   PHY_STATUS_CMN_LDO(phy, ch)                   (1 << (6-(6*(phy)+3*(ch))))
2273  #define   PHY_STATUS_SPLINE_LDO(phy, ch, spline)        (1 << (8-(6*(phy)+3*(ch)+(spline))))
2274  
2275  /*
2276   * The i830 generation, in LVDS mode, defines P1 as the bit number set within
2277   * this field (only one bit may be set).
2278   */
2279  #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
2280  #define   DPLL_FPA01_P1_POST_DIV_SHIFT	16
2281  #define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
2282  /* i830, required in DVO non-gang */
2283  #define   PLL_P2_DIVIDE_BY_4		(1 << 23)
2284  #define   PLL_P1_DIVIDE_BY_TWO		(1 << 21) /* i830 */
2285  #define   PLL_REF_INPUT_DREFCLK		(0 << 13)
2286  #define   PLL_REF_INPUT_TVCLKINA	(1 << 13) /* i830 */
2287  #define   PLL_REF_INPUT_TVCLKINBC	(2 << 13) /* SDVO TVCLKIN */
2288  #define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
2289  #define   PLL_REF_INPUT_MASK		(3 << 13)
2290  #define   PLL_LOAD_PULSE_PHASE_SHIFT		9
2291  /* Ironlake */
2292  # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
2293  # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
2294  # define PLL_REF_SDVO_HDMI_MULTIPLIER(x)	(((x)-1) << 9)
2295  # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
2296  # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
2297  
2298  /*
2299   * Parallel to Serial Load Pulse phase selection.
2300   * Selects the phase for the 10X DPLL clock for the PCIe
2301   * digital display port. The range is 4 to 13; 10 or more
2302   * is just a flip delay. The default is 6
2303   */
2304  #define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
2305  #define   DISPLAY_RATE_SELECT_FPA1		(1 << 8)
2306  /*
2307   * SDVO multiplier for 945G/GM. Not used on 965.
2308   */
2309  #define   SDVO_MULTIPLIER_MASK			0x000000ff
2310  #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
2311  #define   SDVO_MULTIPLIER_SHIFT_VGA		0
2312  
2313  #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
2314  #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
2315  #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
2316  #define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
2317  
2318  /*
2319   * UDI pixel divider, controlling how many pixels are stuffed into a packet.
2320   *
2321   * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
2322   */
2323  #define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
2324  #define   DPLL_MD_UDI_DIVIDER_SHIFT		24
2325  /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
2326  #define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
2327  #define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
2328  /*
2329   * SDVO/UDI pixel multiplier.
2330   *
2331   * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
2332   * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
2333   * modes, the bus rate would be below the limits, so SDVO allows for stuffing
2334   * dummy bytes in the datastream at an increased clock rate, with both sides of
2335   * the link knowing how many bytes are fill.
2336   *
2337   * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
2338   * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
2339   * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
2340   * through an SDVO command.
2341   *
2342   * This register field has values of multiplication factor minus 1, with
2343   * a maximum multiplier of 5 for SDVO.
2344   */
2345  #define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
2346  #define   DPLL_MD_UDI_MULTIPLIER_SHIFT		8
2347  /*
2348   * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
2349   * This best be set to the default value (3) or the CRT won't work. No,
2350   * I don't entirely understand what this does...
2351   */
2352  #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
2353  #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
2354  
2355  #define _FPA0	0x06040
2356  #define _FPA1	0x06044
2357  #define _FPB0	0x06048
2358  #define _FPB1	0x0604c
2359  #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
2360  #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
2361  #define   FP_N_DIV_MASK		0x003f0000
2362  #define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
2363  #define   FP_N_DIV_SHIFT		16
2364  #define   FP_M1_DIV_MASK	0x00003f00
2365  #define   FP_M1_DIV_SHIFT		 8
2366  #define   FP_M2_DIV_MASK	0x0000003f
2367  #define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
2368  #define   FP_M2_DIV_SHIFT		 0
2369  #define DPLL_TEST	0x606c
2370  #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
2371  #define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
2372  #define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
2373  #define   DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
2374  #define   DPLLB_TEST_N_BYPASS		(1 << 19)
2375  #define   DPLLB_TEST_M_BYPASS		(1 << 18)
2376  #define   DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
2377  #define   DPLLA_TEST_N_BYPASS		(1 << 3)
2378  #define   DPLLA_TEST_M_BYPASS		(1 << 2)
2379  #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
2380  #define D_STATE		0x6104
2381  #define  DSTATE_GFX_RESET_I830			(1<<6)
2382  #define  DSTATE_PLL_D3_OFF			(1<<3)
2383  #define  DSTATE_GFX_CLOCK_GATING		(1<<1)
2384  #define  DSTATE_DOT_CLOCK_GATING		(1<<0)
2385  #define DSPCLK_GATE_D	(dev_priv->info.display_mmio_offset + 0x6200)
2386  # define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
2387  # define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
2388  # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
2389  # define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
2390  # define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
2391  # define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
2392  # define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
2393  # define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
2394  # define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
2395  # define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
2396  # define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
2397  # define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
2398  # define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
2399  # define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
2400  # define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
2401  # define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
2402  # define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
2403  # define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
2404  # define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
2405  # define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
2406  # define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
2407  # define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
2408  # define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
2409  # define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
2410  # define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
2411  # define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
2412  # define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
2413  # define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
2414  /*
2415   * This bit must be set on the 830 to prevent hangs when turning off the
2416   * overlay scaler.
2417   */
2418  # define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
2419  # define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
2420  # define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
2421  # define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
2422  # define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
2423  
2424  #define RENCLK_GATE_D1		0x6204
2425  # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
2426  # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
2427  # define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
2428  # define PC_BE_CLOCK_GATE_DISABLE		(1 << 10)
2429  # define WINDOWER_CLOCK_GATE_DISABLE		(1 << 9)
2430  # define INTERPOLATOR_CLOCK_GATE_DISABLE	(1 << 8)
2431  # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE	(1 << 7)
2432  # define MOTION_COMP_CLOCK_GATE_DISABLE		(1 << 6)
2433  # define MAG_CLOCK_GATE_DISABLE			(1 << 5)
2434  /* This bit must be unset on 855,865 */
2435  # define MECI_CLOCK_GATE_DISABLE		(1 << 4)
2436  # define DCMP_CLOCK_GATE_DISABLE		(1 << 3)
2437  # define MEC_CLOCK_GATE_DISABLE			(1 << 2)
2438  # define MECO_CLOCK_GATE_DISABLE		(1 << 1)
2439  /* This bit must be set on 855,865. */
2440  # define SV_CLOCK_GATE_DISABLE			(1 << 0)
2441  # define I915_MPEG_CLOCK_GATE_DISABLE		(1 << 16)
2442  # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE	(1 << 15)
2443  # define I915_MOTION_COMP_CLOCK_GATE_DISABLE	(1 << 14)
2444  # define I915_BD_BF_CLOCK_GATE_DISABLE		(1 << 13)
2445  # define I915_SF_SE_CLOCK_GATE_DISABLE		(1 << 12)
2446  # define I915_WM_CLOCK_GATE_DISABLE		(1 << 11)
2447  # define I915_IZ_CLOCK_GATE_DISABLE		(1 << 10)
2448  # define I915_PI_CLOCK_GATE_DISABLE		(1 << 9)
2449  # define I915_DI_CLOCK_GATE_DISABLE		(1 << 8)
2450  # define I915_SH_SV_CLOCK_GATE_DISABLE		(1 << 7)
2451  # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE	(1 << 6)
2452  # define I915_SC_CLOCK_GATE_DISABLE		(1 << 5)
2453  # define I915_FL_CLOCK_GATE_DISABLE		(1 << 4)
2454  # define I915_DM_CLOCK_GATE_DISABLE		(1 << 3)
2455  # define I915_PS_CLOCK_GATE_DISABLE		(1 << 2)
2456  # define I915_CC_CLOCK_GATE_DISABLE		(1 << 1)
2457  # define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
2458  
2459  # define I965_RCZ_CLOCK_GATE_DISABLE		(1 << 30)
2460  /* This bit must always be set on 965G/965GM */
2461  # define I965_RCC_CLOCK_GATE_DISABLE		(1 << 29)
2462  # define I965_RCPB_CLOCK_GATE_DISABLE		(1 << 28)
2463  # define I965_DAP_CLOCK_GATE_DISABLE		(1 << 27)
2464  # define I965_ROC_CLOCK_GATE_DISABLE		(1 << 26)
2465  # define I965_GW_CLOCK_GATE_DISABLE		(1 << 25)
2466  # define I965_TD_CLOCK_GATE_DISABLE		(1 << 24)
2467  /* This bit must always be set on 965G */
2468  # define I965_ISC_CLOCK_GATE_DISABLE		(1 << 23)
2469  # define I965_IC_CLOCK_GATE_DISABLE		(1 << 22)
2470  # define I965_EU_CLOCK_GATE_DISABLE		(1 << 21)
2471  # define I965_IF_CLOCK_GATE_DISABLE		(1 << 20)
2472  # define I965_TC_CLOCK_GATE_DISABLE		(1 << 19)
2473  # define I965_SO_CLOCK_GATE_DISABLE		(1 << 17)
2474  # define I965_FBC_CLOCK_GATE_DISABLE		(1 << 16)
2475  # define I965_MARI_CLOCK_GATE_DISABLE		(1 << 15)
2476  # define I965_MASF_CLOCK_GATE_DISABLE		(1 << 14)
2477  # define I965_MAWB_CLOCK_GATE_DISABLE		(1 << 13)
2478  # define I965_EM_CLOCK_GATE_DISABLE		(1 << 12)
2479  # define I965_UC_CLOCK_GATE_DISABLE		(1 << 11)
2480  # define I965_SI_CLOCK_GATE_DISABLE		(1 << 6)
2481  # define I965_MT_CLOCK_GATE_DISABLE		(1 << 5)
2482  # define I965_PL_CLOCK_GATE_DISABLE		(1 << 4)
2483  # define I965_DG_CLOCK_GATE_DISABLE		(1 << 3)
2484  # define I965_QC_CLOCK_GATE_DISABLE		(1 << 2)
2485  # define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
2486  # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
2487  
2488  #define RENCLK_GATE_D2		0x6208
2489  #define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
2490  #define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
2491  #define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
2492  
2493  #define VDECCLK_GATE_D		0x620C		/* g4x only */
2494  #define  VCP_UNIT_CLOCK_GATE_DISABLE		(1 << 4)
2495  
2496  #define RAMCLK_GATE_D		0x6210		/* CRL only */
2497  #define DEUC			0x6214          /* CRL only */
2498  
2499  #define FW_BLC_SELF_VLV		(VLV_DISPLAY_BASE + 0x6500)
2500  #define  FW_CSPWRDWNEN		(1<<15)
2501  
2502  #define MI_ARB_VLV		(VLV_DISPLAY_BASE + 0x6504)
2503  
2504  #define CZCLK_CDCLK_FREQ_RATIO	(VLV_DISPLAY_BASE + 0x6508)
2505  #define   CDCLK_FREQ_SHIFT	4
2506  #define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
2507  #define   CZCLK_FREQ_MASK	0xf
2508  
2509  #define GCI_CONTROL		(VLV_DISPLAY_BASE + 0x650C)
2510  #define   PFI_CREDIT_63		(9 << 28)		/* chv only */
2511  #define   PFI_CREDIT_31		(8 << 28)		/* chv only */
2512  #define   PFI_CREDIT(x)		(((x) - 8) << 28)	/* 8-15 */
2513  #define   PFI_CREDIT_RESEND	(1 << 27)
2514  #define   VGA_FAST_MODE_DISABLE	(1 << 14)
2515  
2516  #define GMBUSFREQ_VLV		(VLV_DISPLAY_BASE + 0x6510)
2517  
2518  /*
2519   * Palette regs
2520   */
2521  #define PALETTE_A_OFFSET 0xa000
2522  #define PALETTE_B_OFFSET 0xa800
2523  #define CHV_PALETTE_C_OFFSET 0xc000
2524  #define PALETTE(pipe, i) (dev_priv->info.palette_offsets[pipe] + \
2525  			  dev_priv->info.display_mmio_offset + (i) * 4)
2526  
2527  /* MCH MMIO space */
2528  
2529  /*
2530   * MCHBAR mirror.
2531   *
2532   * This mirrors the MCHBAR MMIO space whose location is determined by
2533   * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
2534   * every way.  It is not accessible from the CP register read instructions.
2535   *
2536   * Starting from Haswell, you can't write registers using the MCHBAR mirror,
2537   * just read.
2538   */
2539  #define MCHBAR_MIRROR_BASE	0x10000
2540  
2541  #define MCHBAR_MIRROR_BASE_SNB	0x140000
2542  
2543  #define CTG_STOLEN_RESERVED		(MCHBAR_MIRROR_BASE + 0x34)
2544  #define ELK_STOLEN_RESERVED		(MCHBAR_MIRROR_BASE + 0x48)
2545  #define G4X_STOLEN_RESERVED_ADDR1_MASK	(0xFFFF << 16)
2546  #define G4X_STOLEN_RESERVED_ADDR2_MASK	(0xFFF << 4)
2547  
2548  /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
2549  #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
2550  
2551  /* 915-945 and GM965 MCH register controlling DRAM channel access */
2552  #define DCC			0x10200
2553  #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
2554  #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
2555  #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
2556  #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
2557  #define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
2558  #define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
2559  #define DCC2			0x10204
2560  #define DCC2_MODIFIED_ENHANCED_DISABLE			(1 << 20)
2561  
2562  /* Pineview MCH register contains DDR3 setting */
2563  #define CSHRDDR3CTL            0x101a8
2564  #define CSHRDDR3CTL_DDR3       (1 << 2)
2565  
2566  /* 965 MCH register controlling DRAM channel configuration */
2567  #define C0DRB3			0x10206
2568  #define C1DRB3			0x10606
2569  
2570  /* snb MCH registers for reading the DRAM channel configuration */
2571  #define MAD_DIMM_C0			(MCHBAR_MIRROR_BASE_SNB + 0x5004)
2572  #define MAD_DIMM_C1			(MCHBAR_MIRROR_BASE_SNB + 0x5008)
2573  #define MAD_DIMM_C2			(MCHBAR_MIRROR_BASE_SNB + 0x500C)
2574  #define   MAD_DIMM_ECC_MASK		(0x3 << 24)
2575  #define   MAD_DIMM_ECC_OFF		(0x0 << 24)
2576  #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
2577  #define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON	(0x2 << 24)
2578  #define   MAD_DIMM_ECC_ON		(0x3 << 24)
2579  #define   MAD_DIMM_ENH_INTERLEAVE	(0x1 << 22)
2580  #define   MAD_DIMM_RANK_INTERLEAVE	(0x1 << 21)
2581  #define   MAD_DIMM_B_WIDTH_X16		(0x1 << 20) /* X8 chips if unset */
2582  #define   MAD_DIMM_A_WIDTH_X16		(0x1 << 19) /* X8 chips if unset */
2583  #define   MAD_DIMM_B_DUAL_RANK		(0x1 << 18)
2584  #define   MAD_DIMM_A_DUAL_RANK		(0x1 << 17)
2585  #define   MAD_DIMM_A_SELECT		(0x1 << 16)
2586  /* DIMM sizes are in multiples of 256mb. */
2587  #define   MAD_DIMM_B_SIZE_SHIFT		8
2588  #define   MAD_DIMM_B_SIZE_MASK		(0xff << MAD_DIMM_B_SIZE_SHIFT)
2589  #define   MAD_DIMM_A_SIZE_SHIFT		0
2590  #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
2591  
2592  /* snb MCH registers for priority tuning */
2593  #define MCH_SSKPD			(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
2594  #define   MCH_SSKPD_WM0_MASK		0x3f
2595  #define   MCH_SSKPD_WM0_VAL		0xc
2596  
2597  #define MCH_SECP_NRG_STTS		(MCHBAR_MIRROR_BASE_SNB + 0x592c)
2598  
2599  /* Clocking configuration register */
2600  #define CLKCFG			0x10c00
2601  #define CLKCFG_FSB_400					(5 << 0)	/* hrawclk 100 */
2602  #define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
2603  #define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
2604  #define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */
2605  #define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */
2606  #define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */
2607  /* Note, below two are guess */
2608  #define CLKCFG_FSB_1600					(4 << 0)	/* hrawclk 400 */
2609  #define CLKCFG_FSB_1600_ALT				(0 << 0)	/* hrawclk 400 */
2610  #define CLKCFG_FSB_MASK					(7 << 0)
2611  #define CLKCFG_MEM_533					(1 << 4)
2612  #define CLKCFG_MEM_667					(2 << 4)
2613  #define CLKCFG_MEM_800					(3 << 4)
2614  #define CLKCFG_MEM_MASK					(7 << 4)
2615  
2616  #define HPLLVCO                 (MCHBAR_MIRROR_BASE + 0xc38)
2617  #define HPLLVCO_MOBILE          (MCHBAR_MIRROR_BASE + 0xc0f)
2618  
2619  #define TSC1			0x11001
2620  #define   TSE			(1<<0)
2621  #define TR1			0x11006
2622  #define TSFS			0x11020
2623  #define   TSFS_SLOPE_MASK	0x0000ff00
2624  #define   TSFS_SLOPE_SHIFT	8
2625  #define   TSFS_INTR_MASK	0x000000ff
2626  
2627  #define CRSTANDVID		0x11100
2628  #define PXVFREQ(i)		(0x11110 + (i) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
2629  #define   PXVFREQ_PX_MASK	0x7f000000
2630  #define   PXVFREQ_PX_SHIFT	24
2631  #define VIDFREQ_BASE		0x11110
2632  #define VIDFREQ1		0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
2633  #define VIDFREQ2		0x11114
2634  #define VIDFREQ3		0x11118
2635  #define VIDFREQ4		0x1111c
2636  #define   VIDFREQ_P0_MASK	0x1f000000
2637  #define   VIDFREQ_P0_SHIFT	24
2638  #define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
2639  #define   VIDFREQ_P0_CSCLK_SHIFT 20
2640  #define   VIDFREQ_P0_CRCLK_MASK	0x000f0000
2641  #define   VIDFREQ_P0_CRCLK_SHIFT 16
2642  #define   VIDFREQ_P1_MASK	0x00001f00
2643  #define   VIDFREQ_P1_SHIFT	8
2644  #define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
2645  #define   VIDFREQ_P1_CSCLK_SHIFT 4
2646  #define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
2647  #define INTTOEXT_BASE_ILK	0x11300
2648  #define INTTOEXT_BASE		0x11120 /* INTTOEXT1-8 (0x1113c) */
2649  #define   INTTOEXT_MAP3_SHIFT	24
2650  #define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
2651  #define   INTTOEXT_MAP2_SHIFT	16
2652  #define   INTTOEXT_MAP2_MASK	(0x1f << INTTOEXT_MAP2_SHIFT)
2653  #define   INTTOEXT_MAP1_SHIFT	8
2654  #define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
2655  #define   INTTOEXT_MAP0_SHIFT	0
2656  #define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
2657  #define MEMSWCTL		0x11170 /* Ironlake only */
2658  #define   MEMCTL_CMD_MASK	0xe000
2659  #define   MEMCTL_CMD_SHIFT	13
2660  #define   MEMCTL_CMD_RCLK_OFF	0
2661  #define   MEMCTL_CMD_RCLK_ON	1
2662  #define   MEMCTL_CMD_CHFREQ	2
2663  #define   MEMCTL_CMD_CHVID	3
2664  #define   MEMCTL_CMD_VMMOFF	4
2665  #define   MEMCTL_CMD_VMMON	5
2666  #define   MEMCTL_CMD_STS	(1<<12) /* write 1 triggers command, clears
2667  					   when command complete */
2668  #define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
2669  #define   MEMCTL_FREQ_SHIFT	8
2670  #define   MEMCTL_SFCAVM		(1<<7)
2671  #define   MEMCTL_TGT_VID_MASK	0x007f
2672  #define MEMIHYST		0x1117c
2673  #define MEMINTREN		0x11180 /* 16 bits */
2674  #define   MEMINT_RSEXIT_EN	(1<<8)
2675  #define   MEMINT_CX_SUPR_EN	(1<<7)
2676  #define   MEMINT_CONT_BUSY_EN	(1<<6)
2677  #define   MEMINT_AVG_BUSY_EN	(1<<5)
2678  #define   MEMINT_EVAL_CHG_EN	(1<<4)
2679  #define   MEMINT_MON_IDLE_EN	(1<<3)
2680  #define   MEMINT_UP_EVAL_EN	(1<<2)
2681  #define   MEMINT_DOWN_EVAL_EN	(1<<1)
2682  #define   MEMINT_SW_CMD_EN	(1<<0)
2683  #define MEMINTRSTR		0x11182 /* 16 bits */
2684  #define   MEM_RSEXIT_MASK	0xc000
2685  #define   MEM_RSEXIT_SHIFT	14
2686  #define   MEM_CONT_BUSY_MASK	0x3000
2687  #define   MEM_CONT_BUSY_SHIFT	12
2688  #define   MEM_AVG_BUSY_MASK	0x0c00
2689  #define   MEM_AVG_BUSY_SHIFT	10
2690  #define   MEM_EVAL_CHG_MASK	0x0300
2691  #define   MEM_EVAL_BUSY_SHIFT	8
2692  #define   MEM_MON_IDLE_MASK	0x00c0
2693  #define   MEM_MON_IDLE_SHIFT	6
2694  #define   MEM_UP_EVAL_MASK	0x0030
2695  #define   MEM_UP_EVAL_SHIFT	4
2696  #define   MEM_DOWN_EVAL_MASK	0x000c
2697  #define   MEM_DOWN_EVAL_SHIFT	2
2698  #define   MEM_SW_CMD_MASK	0x0003
2699  #define   MEM_INT_STEER_GFX	0
2700  #define   MEM_INT_STEER_CMR	1
2701  #define   MEM_INT_STEER_SMI	2
2702  #define   MEM_INT_STEER_SCI	3
2703  #define MEMINTRSTS		0x11184
2704  #define   MEMINT_RSEXIT		(1<<7)
2705  #define   MEMINT_CONT_BUSY	(1<<6)
2706  #define   MEMINT_AVG_BUSY	(1<<5)
2707  #define   MEMINT_EVAL_CHG	(1<<4)
2708  #define   MEMINT_MON_IDLE	(1<<3)
2709  #define   MEMINT_UP_EVAL	(1<<2)
2710  #define   MEMINT_DOWN_EVAL	(1<<1)
2711  #define   MEMINT_SW_CMD		(1<<0)
2712  #define MEMMODECTL		0x11190
2713  #define   MEMMODE_BOOST_EN	(1<<31)
2714  #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
2715  #define   MEMMODE_BOOST_FREQ_SHIFT 24
2716  #define   MEMMODE_IDLE_MODE_MASK 0x00030000
2717  #define   MEMMODE_IDLE_MODE_SHIFT 16
2718  #define   MEMMODE_IDLE_MODE_EVAL 0
2719  #define   MEMMODE_IDLE_MODE_CONT 1
2720  #define   MEMMODE_HWIDLE_EN	(1<<15)
2721  #define   MEMMODE_SWMODE_EN	(1<<14)
2722  #define   MEMMODE_RCLK_GATE	(1<<13)
2723  #define   MEMMODE_HW_UPDATE	(1<<12)
2724  #define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
2725  #define   MEMMODE_FSTART_SHIFT	8
2726  #define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
2727  #define   MEMMODE_FMAX_SHIFT	4
2728  #define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
2729  #define RCBMAXAVG		0x1119c
2730  #define MEMSWCTL2		0x1119e /* Cantiga only */
2731  #define   SWMEMCMD_RENDER_OFF	(0 << 13)
2732  #define   SWMEMCMD_RENDER_ON	(1 << 13)
2733  #define   SWMEMCMD_SWFREQ	(2 << 13)
2734  #define   SWMEMCMD_TARVID	(3 << 13)
2735  #define   SWMEMCMD_VRM_OFF	(4 << 13)
2736  #define   SWMEMCMD_VRM_ON	(5 << 13)
2737  #define   CMDSTS		(1<<12)
2738  #define   SFCAVM		(1<<11)
2739  #define   SWFREQ_MASK		0x0380 /* P0-7 */
2740  #define   SWFREQ_SHIFT		7
2741  #define   TARVID_MASK		0x001f
2742  #define MEMSTAT_CTG		0x111a0
2743  #define RCBMINAVG		0x111a0
2744  #define RCUPEI			0x111b0
2745  #define RCDNEI			0x111b4
2746  #define RSTDBYCTL		0x111b8
2747  #define   RS1EN			(1<<31)
2748  #define   RS2EN			(1<<30)
2749  #define   RS3EN			(1<<29)
2750  #define   D3RS3EN		(1<<28) /* Display D3 imlies RS3 */
2751  #define   SWPROMORSX		(1<<27) /* RSx promotion timers ignored */
2752  #define   RCWAKERW		(1<<26) /* Resetwarn from PCH causes wakeup */
2753  #define   DPRSLPVREN		(1<<25) /* Fast voltage ramp enable */
2754  #define   GFXTGHYST		(1<<24) /* Hysteresis to allow trunk gating */
2755  #define   RCX_SW_EXIT		(1<<23) /* Leave RSx and prevent re-entry */
2756  #define   RSX_STATUS_MASK	(7<<20)
2757  #define   RSX_STATUS_ON		(0<<20)
2758  #define   RSX_STATUS_RC1	(1<<20)
2759  #define   RSX_STATUS_RC1E	(2<<20)
2760  #define   RSX_STATUS_RS1	(3<<20)
2761  #define   RSX_STATUS_RS2	(4<<20) /* aka rc6 */
2762  #define   RSX_STATUS_RSVD	(5<<20) /* deep rc6 unsupported on ilk */
2763  #define   RSX_STATUS_RS3	(6<<20) /* rs3 unsupported on ilk */
2764  #define   RSX_STATUS_RSVD2	(7<<20)
2765  #define   UWRCRSXE		(1<<19) /* wake counter limit prevents rsx */
2766  #define   RSCRP			(1<<18) /* rs requests control on rs1/2 reqs */
2767  #define   JRSC			(1<<17) /* rsx coupled to cpu c-state */
2768  #define   RS2INC0		(1<<16) /* allow rs2 in cpu c0 */
2769  #define   RS1CONTSAV_MASK	(3<<14)
2770  #define   RS1CONTSAV_NO_RS1	(0<<14) /* rs1 doesn't save/restore context */
2771  #define   RS1CONTSAV_RSVD	(1<<14)
2772  #define   RS1CONTSAV_SAVE_RS1	(2<<14) /* rs1 saves context */
2773  #define   RS1CONTSAV_FULL_RS1	(3<<14) /* rs1 saves and restores context */
2774  #define   NORMSLEXLAT_MASK	(3<<12)
2775  #define   SLOW_RS123		(0<<12)
2776  #define   SLOW_RS23		(1<<12)
2777  #define   SLOW_RS3		(2<<12)
2778  #define   NORMAL_RS123		(3<<12)
2779  #define   RCMODE_TIMEOUT	(1<<11) /* 0 is eval interval method */
2780  #define   IMPROMOEN		(1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
2781  #define   RCENTSYNC		(1<<9) /* rs coupled to cpu c-state (3/6/7) */
2782  #define   STATELOCK		(1<<7) /* locked to rs_cstate if 0 */
2783  #define   RS_CSTATE_MASK	(3<<4)
2784  #define   RS_CSTATE_C367_RS1	(0<<4)
2785  #define   RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
2786  #define   RS_CSTATE_RSVD	(2<<4)
2787  #define   RS_CSTATE_C367_RS2	(3<<4)
2788  #define   REDSAVES		(1<<3) /* no context save if was idle during rs0 */
2789  #define   REDRESTORES		(1<<2) /* no restore if was idle during rs0 */
2790  #define VIDCTL			0x111c0
2791  #define VIDSTS			0x111c8
2792  #define VIDSTART		0x111cc /* 8 bits */
2793  #define MEMSTAT_ILK			0x111f8
2794  #define   MEMSTAT_VID_MASK	0x7f00
2795  #define   MEMSTAT_VID_SHIFT	8
2796  #define   MEMSTAT_PSTATE_MASK	0x00f8
2797  #define   MEMSTAT_PSTATE_SHIFT  3
2798  #define   MEMSTAT_MON_ACTV	(1<<2)
2799  #define   MEMSTAT_SRC_CTL_MASK	0x0003
2800  #define   MEMSTAT_SRC_CTL_CORE	0
2801  #define   MEMSTAT_SRC_CTL_TRB	1
2802  #define   MEMSTAT_SRC_CTL_THM	2
2803  #define   MEMSTAT_SRC_CTL_STDBY 3
2804  #define RCPREVBSYTUPAVG		0x113b8
2805  #define RCPREVBSYTDNAVG		0x113bc
2806  #define PMMISC			0x11214
2807  #define   MCPPCE_EN		(1<<0) /* enable PM_MSG from PCH->MPC */
2808  #define SDEW			0x1124c
2809  #define CSIEW0			0x11250
2810  #define CSIEW1			0x11254
2811  #define CSIEW2			0x11258
2812  #define PEW(i)			(0x1125c + (i) * 4) /* 5 registers */
2813  #define DEW(i)			(0x11270 + (i) * 4) /* 3 registers */
2814  #define MCHAFE			0x112c0
2815  #define CSIEC			0x112e0
2816  #define DMIEC			0x112e4
2817  #define DDREC			0x112e8
2818  #define PEG0EC			0x112ec
2819  #define PEG1EC			0x112f0
2820  #define GFXEC			0x112f4
2821  #define RPPREVBSYTUPAVG		0x113b8
2822  #define RPPREVBSYTDNAVG		0x113bc
2823  #define ECR			0x11600
2824  #define   ECR_GPFE		(1<<31)
2825  #define   ECR_IMONE		(1<<30)
2826  #define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
2827  #define OGW0			0x11608
2828  #define OGW1			0x1160c
2829  #define EG0			0x11610
2830  #define EG1			0x11614
2831  #define EG2			0x11618
2832  #define EG3			0x1161c
2833  #define EG4			0x11620
2834  #define EG5			0x11624
2835  #define EG6			0x11628
2836  #define EG7			0x1162c
2837  #define PXW(i)			(0x11664 + (i) * 4) /* 4 registers */
2838  #define PXWL(i)			(0x11680 + (i) * 4) /* 8 registers */
2839  #define LCFUSE02		0x116c0
2840  #define   LCFUSE_HIV_MASK	0x000000ff
2841  #define CSIPLL0			0x12c10
2842  #define DDRMPLL1		0X12c20
2843  #define PEG_BAND_GAP_DATA	0x14d68
2844  
2845  #define GEN6_GT_THREAD_STATUS_REG 0x13805c
2846  #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
2847  
2848  #define GEN6_GT_PERF_STATUS	(MCHBAR_MIRROR_BASE_SNB + 0x5948)
2849  #define BXT_GT_PERF_STATUS      (MCHBAR_MIRROR_BASE_SNB + 0x7070)
2850  #define GEN6_RP_STATE_LIMITS	(MCHBAR_MIRROR_BASE_SNB + 0x5994)
2851  #define GEN6_RP_STATE_CAP	(MCHBAR_MIRROR_BASE_SNB + 0x5998)
2852  #define BXT_RP_STATE_CAP        0x138170
2853  
2854  /*
2855   * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
2856   * 8300) freezing up around GPU hangs. Looks as if even
2857   * scheduling/timer interrupts start misbehaving if the RPS
2858   * EI/thresholds are "bad", leading to a very sluggish or even
2859   * frozen machine.
2860   */
2861  #define INTERVAL_1_28_US(us)	roundup(((us) * 100) >> 7, 25)
2862  #define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
2863  #define INTERVAL_0_833_US(us)	(((us) * 6) / 5)
2864  #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
2865  				(IS_BROXTON(dev_priv) ? \
2866  				INTERVAL_0_833_US(us) : \
2867  				INTERVAL_1_33_US(us)) : \
2868  				INTERVAL_1_28_US(us))
2869  
2870  /*
2871   * Logical Context regs
2872   */
2873  #define CCID			0x2180
2874  #define   CCID_EN		(1<<0)
2875  /*
2876   * Notes on SNB/IVB/VLV context size:
2877   * - Power context is saved elsewhere (LLC or stolen)
2878   * - Ring/execlist context is saved on SNB, not on IVB
2879   * - Extended context size already includes render context size
2880   * - We always need to follow the extended context size.
2881   *   SNB BSpec has comments indicating that we should use the
2882   *   render context size instead if execlists are disabled, but
2883   *   based on empirical testing that's just nonsense.
2884   * - Pipelined/VF state is saved on SNB/IVB respectively
2885   * - GT1 size just indicates how much of render context
2886   *   doesn't need saving on GT1
2887   */
2888  #define CXT_SIZE		0x21a0
2889  #define GEN6_CXT_POWER_SIZE(cxt_reg)	(((cxt_reg) >> 24) & 0x3f)
2890  #define GEN6_CXT_RING_SIZE(cxt_reg)	(((cxt_reg) >> 18) & 0x3f)
2891  #define GEN6_CXT_RENDER_SIZE(cxt_reg)	(((cxt_reg) >> 12) & 0x3f)
2892  #define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	(((cxt_reg) >> 6) & 0x3f)
2893  #define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	(((cxt_reg) >> 0) & 0x3f)
2894  #define GEN6_CXT_TOTAL_SIZE(cxt_reg)	(GEN6_CXT_RING_SIZE(cxt_reg) + \
2895  					GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
2896  					GEN6_CXT_PIPELINE_SIZE(cxt_reg))
2897  #define GEN7_CXT_SIZE		0x21a8
2898  #define GEN7_CXT_POWER_SIZE(ctx_reg)	(((ctx_reg) >> 25) & 0x7f)
2899  #define GEN7_CXT_RING_SIZE(ctx_reg)	(((ctx_reg) >> 22) & 0x7)
2900  #define GEN7_CXT_RENDER_SIZE(ctx_reg)	(((ctx_reg) >> 16) & 0x3f)
2901  #define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	(((ctx_reg) >> 9) & 0x7f)
2902  #define GEN7_CXT_GT1_SIZE(ctx_reg)	(((ctx_reg) >> 6) & 0x7)
2903  #define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	(((ctx_reg) >> 0) & 0x3f)
2904  #define GEN7_CXT_TOTAL_SIZE(ctx_reg)	(GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
2905  					 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
2906  /* Haswell does have the CXT_SIZE register however it does not appear to be
2907   * valid. Now, docs explain in dwords what is in the context object. The full
2908   * size is 70720 bytes, however, the power context and execlist context will
2909   * never be saved (power context is stored elsewhere, and execlists don't work
2910   * on HSW) - so the final size, including the extra state required for the
2911   * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
2912   */
2913  #define HSW_CXT_TOTAL_SIZE		(17 * PAGE_SIZE)
2914  /* Same as Haswell, but 72064 bytes now. */
2915  #define GEN8_CXT_TOTAL_SIZE		(18 * PAGE_SIZE)
2916  
2917  #define CHV_CLK_CTL1			0x101100
2918  #define VLV_CLK_CTL2			0x101104
2919  #define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28
2920  
2921  /*
2922   * Overlay regs
2923   */
2924  
2925  #define OVADD			0x30000
2926  #define DOVSTA			0x30008
2927  #define OC_BUF			(0x3<<20)
2928  #define OGAMC5			0x30010
2929  #define OGAMC4			0x30014
2930  #define OGAMC3			0x30018
2931  #define OGAMC2			0x3001c
2932  #define OGAMC1			0x30020
2933  #define OGAMC0			0x30024
2934  
2935  /*
2936   * Display engine regs
2937   */
2938  
2939  /* Pipe A CRC regs */
2940  #define _PIPE_CRC_CTL_A			0x60050
2941  #define   PIPE_CRC_ENABLE		(1 << 31)
2942  /* ivb+ source selection */
2943  #define   PIPE_CRC_SOURCE_PRIMARY_IVB	(0 << 29)
2944  #define   PIPE_CRC_SOURCE_SPRITE_IVB	(1 << 29)
2945  #define   PIPE_CRC_SOURCE_PF_IVB	(2 << 29)
2946  /* ilk+ source selection */
2947  #define   PIPE_CRC_SOURCE_PRIMARY_ILK	(0 << 28)
2948  #define   PIPE_CRC_SOURCE_SPRITE_ILK	(1 << 28)
2949  #define   PIPE_CRC_SOURCE_PIPE_ILK	(2 << 28)
2950  /* embedded DP port on the north display block, reserved on ivb */
2951  #define   PIPE_CRC_SOURCE_PORT_A_ILK	(4 << 28)
2952  #define   PIPE_CRC_SOURCE_FDI_ILK	(5 << 28) /* reserved on ivb */
2953  /* vlv source selection */
2954  #define   PIPE_CRC_SOURCE_PIPE_VLV	(0 << 27)
2955  #define   PIPE_CRC_SOURCE_HDMIB_VLV	(1 << 27)
2956  #define   PIPE_CRC_SOURCE_HDMIC_VLV	(2 << 27)
2957  /* with DP port the pipe source is invalid */
2958  #define   PIPE_CRC_SOURCE_DP_D_VLV	(3 << 27)
2959  #define   PIPE_CRC_SOURCE_DP_B_VLV	(6 << 27)
2960  #define   PIPE_CRC_SOURCE_DP_C_VLV	(7 << 27)
2961  /* gen3+ source selection */
2962  #define   PIPE_CRC_SOURCE_PIPE_I9XX	(0 << 28)
2963  #define   PIPE_CRC_SOURCE_SDVOB_I9XX	(1 << 28)
2964  #define   PIPE_CRC_SOURCE_SDVOC_I9XX	(2 << 28)
2965  /* with DP/TV port the pipe source is invalid */
2966  #define   PIPE_CRC_SOURCE_DP_D_G4X	(3 << 28)
2967  #define   PIPE_CRC_SOURCE_TV_PRE	(4 << 28)
2968  #define   PIPE_CRC_SOURCE_TV_POST	(5 << 28)
2969  #define   PIPE_CRC_SOURCE_DP_B_G4X	(6 << 28)
2970  #define   PIPE_CRC_SOURCE_DP_C_G4X	(7 << 28)
2971  /* gen2 doesn't have source selection bits */
2972  #define   PIPE_CRC_INCLUDE_BORDER_I8XX	(1 << 30)
2973  
2974  #define _PIPE_CRC_RES_1_A_IVB		0x60064
2975  #define _PIPE_CRC_RES_2_A_IVB		0x60068
2976  #define _PIPE_CRC_RES_3_A_IVB		0x6006c
2977  #define _PIPE_CRC_RES_4_A_IVB		0x60070
2978  #define _PIPE_CRC_RES_5_A_IVB		0x60074
2979  
2980  #define _PIPE_CRC_RES_RED_A		0x60060
2981  #define _PIPE_CRC_RES_GREEN_A		0x60064
2982  #define _PIPE_CRC_RES_BLUE_A		0x60068
2983  #define _PIPE_CRC_RES_RES1_A_I915	0x6006c
2984  #define _PIPE_CRC_RES_RES2_A_G4X	0x60080
2985  
2986  /* Pipe B CRC regs */
2987  #define _PIPE_CRC_RES_1_B_IVB		0x61064
2988  #define _PIPE_CRC_RES_2_B_IVB		0x61068
2989  #define _PIPE_CRC_RES_3_B_IVB		0x6106c
2990  #define _PIPE_CRC_RES_4_B_IVB		0x61070
2991  #define _PIPE_CRC_RES_5_B_IVB		0x61074
2992  
2993  #define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
2994  #define PIPE_CRC_RES_1_IVB(pipe)	\
2995  	_TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
2996  #define PIPE_CRC_RES_2_IVB(pipe)	\
2997  	_TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
2998  #define PIPE_CRC_RES_3_IVB(pipe)	\
2999  	_TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
3000  #define PIPE_CRC_RES_4_IVB(pipe)	\
3001  	_TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
3002  #define PIPE_CRC_RES_5_IVB(pipe)	\
3003  	_TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
3004  
3005  #define PIPE_CRC_RES_RED(pipe) \
3006  	_TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
3007  #define PIPE_CRC_RES_GREEN(pipe) \
3008  	_TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
3009  #define PIPE_CRC_RES_BLUE(pipe) \
3010  	_TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
3011  #define PIPE_CRC_RES_RES1_I915(pipe) \
3012  	_TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
3013  #define PIPE_CRC_RES_RES2_G4X(pipe) \
3014  	_TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
3015  
3016  /* Pipe A timing regs */
3017  #define _HTOTAL_A	0x60000
3018  #define _HBLANK_A	0x60004
3019  #define _HSYNC_A	0x60008
3020  #define _VTOTAL_A	0x6000c
3021  #define _VBLANK_A	0x60010
3022  #define _VSYNC_A	0x60014
3023  #define _PIPEASRC	0x6001c
3024  #define _BCLRPAT_A	0x60020
3025  #define _VSYNCSHIFT_A	0x60028
3026  #define _PIPE_MULT_A	0x6002c
3027  
3028  /* Pipe B timing regs */
3029  #define _HTOTAL_B	0x61000
3030  #define _HBLANK_B	0x61004
3031  #define _HSYNC_B	0x61008
3032  #define _VTOTAL_B	0x6100c
3033  #define _VBLANK_B	0x61010
3034  #define _VSYNC_B	0x61014
3035  #define _PIPEBSRC	0x6101c
3036  #define _BCLRPAT_B	0x61020
3037  #define _VSYNCSHIFT_B	0x61028
3038  #define _PIPE_MULT_B	0x6102c
3039  
3040  #define TRANSCODER_A_OFFSET 0x60000
3041  #define TRANSCODER_B_OFFSET 0x61000
3042  #define TRANSCODER_C_OFFSET 0x62000
3043  #define CHV_TRANSCODER_C_OFFSET 0x63000
3044  #define TRANSCODER_EDP_OFFSET 0x6f000
3045  
3046  #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
3047  	dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
3048  	dev_priv->info.display_mmio_offset)
3049  
3050  #define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
3051  #define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
3052  #define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
3053  #define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
3054  #define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
3055  #define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
3056  #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
3057  #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
3058  #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
3059  #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A)
3060  
3061  /* VLV eDP PSR registers */
3062  #define _PSRCTLA				(VLV_DISPLAY_BASE + 0x60090)
3063  #define _PSRCTLB				(VLV_DISPLAY_BASE + 0x61090)
3064  #define  VLV_EDP_PSR_ENABLE			(1<<0)
3065  #define  VLV_EDP_PSR_RESET			(1<<1)
3066  #define  VLV_EDP_PSR_MODE_MASK			(7<<2)
3067  #define  VLV_EDP_PSR_MODE_HW_TIMER		(1<<3)
3068  #define  VLV_EDP_PSR_MODE_SW_TIMER		(1<<2)
3069  #define  VLV_EDP_PSR_SINGLE_FRAME_UPDATE	(1<<7)
3070  #define  VLV_EDP_PSR_ACTIVE_ENTRY		(1<<8)
3071  #define  VLV_EDP_PSR_SRC_TRANSMITTER_STATE	(1<<9)
3072  #define  VLV_EDP_PSR_DBL_FRAME			(1<<10)
3073  #define  VLV_EDP_PSR_FRAME_COUNT_MASK		(0xff<<16)
3074  #define  VLV_EDP_PSR_IDLE_FRAME_SHIFT		16
3075  #define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB)
3076  
3077  #define _VSCSDPA			(VLV_DISPLAY_BASE + 0x600a0)
3078  #define _VSCSDPB			(VLV_DISPLAY_BASE + 0x610a0)
3079  #define  VLV_EDP_PSR_SDP_FREQ_MASK	(3<<30)
3080  #define  VLV_EDP_PSR_SDP_FREQ_ONCE	(1<<31)
3081  #define  VLV_EDP_PSR_SDP_FREQ_EVFRAME	(1<<30)
3082  #define VLV_VSCSDP(pipe)	_PIPE(pipe, _VSCSDPA, _VSCSDPB)
3083  
3084  #define _PSRSTATA			(VLV_DISPLAY_BASE + 0x60094)
3085  #define _PSRSTATB			(VLV_DISPLAY_BASE + 0x61094)
3086  #define  VLV_EDP_PSR_LAST_STATE_MASK	(7<<3)
3087  #define  VLV_EDP_PSR_CURR_STATE_MASK	7
3088  #define  VLV_EDP_PSR_DISABLED		(0<<0)
3089  #define  VLV_EDP_PSR_INACTIVE		(1<<0)
3090  #define  VLV_EDP_PSR_IN_TRANS_TO_ACTIVE	(2<<0)
3091  #define  VLV_EDP_PSR_ACTIVE_NORFB_UP	(3<<0)
3092  #define  VLV_EDP_PSR_ACTIVE_SF_UPDATE	(4<<0)
3093  #define  VLV_EDP_PSR_EXIT		(5<<0)
3094  #define  VLV_EDP_PSR_IN_TRANS		(1<<7)
3095  #define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
3096  
3097  /* HSW+ eDP PSR registers */
3098  #define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
3099  #define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
3100  #define   EDP_PSR_ENABLE			(1<<31)
3101  #define   BDW_PSR_SINGLE_FRAME			(1<<30)
3102  #define   EDP_PSR_LINK_STANDBY			(1<<27)
3103  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK	(3<<25)
3104  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES	(0<<25)
3105  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES	(1<<25)
3106  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES	(2<<25)
3107  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES	(3<<25)
3108  #define   EDP_PSR_MAX_SLEEP_TIME_SHIFT		20
3109  #define   EDP_PSR_SKIP_AUX_EXIT			(1<<12)
3110  #define   EDP_PSR_TP1_TP2_SEL			(0<<11)
3111  #define   EDP_PSR_TP1_TP3_SEL			(1<<11)
3112  #define   EDP_PSR_TP2_TP3_TIME_500us		(0<<8)
3113  #define   EDP_PSR_TP2_TP3_TIME_100us		(1<<8)
3114  #define   EDP_PSR_TP2_TP3_TIME_2500us		(2<<8)
3115  #define   EDP_PSR_TP2_TP3_TIME_0us		(3<<8)
3116  #define   EDP_PSR_TP1_TIME_500us		(0<<4)
3117  #define   EDP_PSR_TP1_TIME_100us		(1<<4)
3118  #define   EDP_PSR_TP1_TIME_2500us		(2<<4)
3119  #define   EDP_PSR_TP1_TIME_0us			(3<<4)
3120  #define   EDP_PSR_IDLE_FRAME_SHIFT		0
3121  
3122  #define EDP_PSR_AUX_CTL(dev)			(EDP_PSR_BASE(dev) + 0x10)
3123  #define EDP_PSR_AUX_DATA1(dev)			(EDP_PSR_BASE(dev) + 0x14)
3124  #define EDP_PSR_AUX_DATA2(dev)			(EDP_PSR_BASE(dev) + 0x18)
3125  #define EDP_PSR_AUX_DATA3(dev)			(EDP_PSR_BASE(dev) + 0x1c)
3126  #define EDP_PSR_AUX_DATA4(dev)			(EDP_PSR_BASE(dev) + 0x20)
3127  #define EDP_PSR_AUX_DATA5(dev)			(EDP_PSR_BASE(dev) + 0x24)
3128  
3129  #define EDP_PSR_STATUS_CTL(dev)			(EDP_PSR_BASE(dev) + 0x40)
3130  #define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
3131  #define   EDP_PSR_STATUS_STATE_IDLE		(0<<29)
3132  #define   EDP_PSR_STATUS_STATE_SRDONACK		(1<<29)
3133  #define   EDP_PSR_STATUS_STATE_SRDENT		(2<<29)
3134  #define   EDP_PSR_STATUS_STATE_BUFOFF		(3<<29)
3135  #define   EDP_PSR_STATUS_STATE_BUFON		(4<<29)
3136  #define   EDP_PSR_STATUS_STATE_AUXACK		(5<<29)
3137  #define   EDP_PSR_STATUS_STATE_SRDOFFACK	(6<<29)
3138  #define   EDP_PSR_STATUS_LINK_MASK		(3<<26)
3139  #define   EDP_PSR_STATUS_LINK_FULL_OFF		(0<<26)
3140  #define   EDP_PSR_STATUS_LINK_FULL_ON		(1<<26)
3141  #define   EDP_PSR_STATUS_LINK_STANDBY		(2<<26)
3142  #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT	20
3143  #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK	0x1f
3144  #define   EDP_PSR_STATUS_COUNT_SHIFT		16
3145  #define   EDP_PSR_STATUS_COUNT_MASK		0xf
3146  #define   EDP_PSR_STATUS_AUX_ERROR		(1<<15)
3147  #define   EDP_PSR_STATUS_AUX_SENDING		(1<<12)
3148  #define   EDP_PSR_STATUS_SENDING_IDLE		(1<<9)
3149  #define   EDP_PSR_STATUS_SENDING_TP2_TP3	(1<<8)
3150  #define   EDP_PSR_STATUS_SENDING_TP1		(1<<4)
3151  #define   EDP_PSR_STATUS_IDLE_MASK		0xf
3152  
3153  #define EDP_PSR_PERF_CNT(dev)		(EDP_PSR_BASE(dev) + 0x44)
3154  #define   EDP_PSR_PERF_CNT_MASK		0xffffff
3155  
3156  #define EDP_PSR_DEBUG_CTL(dev)		(EDP_PSR_BASE(dev) + 0x60)
3157  #define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
3158  #define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
3159  #define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
3160  
3161  #define EDP_PSR2_CTL			0x6f900
3162  #define   EDP_PSR2_ENABLE		(1<<31)
3163  #define   EDP_SU_TRACK_ENABLE		(1<<30)
3164  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
3165  #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
3166  #define   EDP_PSR2_TP2_TIME_500		(0<<8)
3167  #define   EDP_PSR2_TP2_TIME_100		(1<<8)
3168  #define   EDP_PSR2_TP2_TIME_2500	(2<<8)
3169  #define   EDP_PSR2_TP2_TIME_50		(3<<8)
3170  #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
3171  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
3172  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
3173  #define   EDP_PSR2_IDLE_MASK		0xf
3174  
3175  /* VGA port control */
3176  #define ADPA			0x61100
3177  #define PCH_ADPA                0xe1100
3178  #define VLV_ADPA		(VLV_DISPLAY_BASE + ADPA)
3179  
3180  #define   ADPA_DAC_ENABLE	(1<<31)
3181  #define   ADPA_DAC_DISABLE	0
3182  #define   ADPA_PIPE_SELECT_MASK	(1<<30)
3183  #define   ADPA_PIPE_A_SELECT	0
3184  #define   ADPA_PIPE_B_SELECT	(1<<30)
3185  #define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
3186  /* CPT uses bits 29:30 for pch transcoder select */
3187  #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
3188  #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
3189  #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
3190  #define   ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3191  #define   ADPA_CRT_HOTPLUG_MONITOR_MONO  (2<<24)
3192  #define   ADPA_CRT_HOTPLUG_ENABLE        (1<<23)
3193  #define   ADPA_CRT_HOTPLUG_PERIOD_64     (0<<22)
3194  #define   ADPA_CRT_HOTPLUG_PERIOD_128    (1<<22)
3195  #define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0<<21)
3196  #define   ADPA_CRT_HOTPLUG_WARMUP_10MS   (1<<21)
3197  #define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0<<20)
3198  #define   ADPA_CRT_HOTPLUG_SAMPLE_4S     (1<<20)
3199  #define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0<<18)
3200  #define   ADPA_CRT_HOTPLUG_VOLTAGE_50    (1<<18)
3201  #define   ADPA_CRT_HOTPLUG_VOLTAGE_60    (2<<18)
3202  #define   ADPA_CRT_HOTPLUG_VOLTAGE_70    (3<<18)
3203  #define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0<<17)
3204  #define   ADPA_CRT_HOTPLUG_VOLREF_475MV  (1<<17)
3205  #define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3206  #define   ADPA_USE_VGA_HVPOLARITY (1<<15)
3207  #define   ADPA_SETS_HVPOLARITY	0
3208  #define   ADPA_VSYNC_CNTL_DISABLE (1<<10)
3209  #define   ADPA_VSYNC_CNTL_ENABLE 0
3210  #define   ADPA_HSYNC_CNTL_DISABLE (1<<11)
3211  #define   ADPA_HSYNC_CNTL_ENABLE 0
3212  #define   ADPA_VSYNC_ACTIVE_HIGH (1<<4)
3213  #define   ADPA_VSYNC_ACTIVE_LOW	0
3214  #define   ADPA_HSYNC_ACTIVE_HIGH (1<<3)
3215  #define   ADPA_HSYNC_ACTIVE_LOW	0
3216  #define   ADPA_DPMS_MASK	(~(3<<10))
3217  #define   ADPA_DPMS_ON		(0<<10)
3218  #define   ADPA_DPMS_SUSPEND	(1<<10)
3219  #define   ADPA_DPMS_STANDBY	(2<<10)
3220  #define   ADPA_DPMS_OFF		(3<<10)
3221  
3222  
3223  /* Hotplug control (945+ only) */
3224  #define PORT_HOTPLUG_EN		(dev_priv->info.display_mmio_offset + 0x61110)
3225  #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
3226  #define   PORTC_HOTPLUG_INT_EN			(1 << 28)
3227  #define   PORTD_HOTPLUG_INT_EN			(1 << 27)
3228  #define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
3229  #define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
3230  #define   TV_HOTPLUG_INT_EN			(1 << 18)
3231  #define   CRT_HOTPLUG_INT_EN			(1 << 9)
3232  #define HOTPLUG_INT_EN_MASK			(PORTB_HOTPLUG_INT_EN | \
3233  						 PORTC_HOTPLUG_INT_EN | \
3234  						 PORTD_HOTPLUG_INT_EN | \
3235  						 SDVOC_HOTPLUG_INT_EN | \
3236  						 SDVOB_HOTPLUG_INT_EN | \
3237  						 CRT_HOTPLUG_INT_EN)
3238  #define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
3239  #define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
3240  /* must use period 64 on GM45 according to docs */
3241  #define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
3242  #define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
3243  #define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
3244  #define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
3245  #define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
3246  #define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
3247  #define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
3248  #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
3249  #define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
3250  #define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
3251  #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
3252  #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
3253  
3254  #define PORT_HOTPLUG_STAT	(dev_priv->info.display_mmio_offset + 0x61114)
3255  /*
3256   * HDMI/DP bits are g4x+
3257   *
3258   * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
3259   * Please check the detailed lore in the commit message for for experimental
3260   * evidence.
3261   */
3262  /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
3263  #define   PORTD_HOTPLUG_LIVE_STATUS_GM45	(1 << 29)
3264  #define   PORTC_HOTPLUG_LIVE_STATUS_GM45	(1 << 28)
3265  #define   PORTB_HOTPLUG_LIVE_STATUS_GM45	(1 << 27)
3266  /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
3267  #define   PORTD_HOTPLUG_LIVE_STATUS_G4X		(1 << 27)
3268  #define   PORTC_HOTPLUG_LIVE_STATUS_G4X		(1 << 28)
3269  #define   PORTB_HOTPLUG_LIVE_STATUS_G4X		(1 << 29)
3270  #define   PORTD_HOTPLUG_INT_STATUS		(3 << 21)
3271  #define   PORTD_HOTPLUG_INT_LONG_PULSE		(2 << 21)
3272  #define   PORTD_HOTPLUG_INT_SHORT_PULSE		(1 << 21)
3273  #define   PORTC_HOTPLUG_INT_STATUS		(3 << 19)
3274  #define   PORTC_HOTPLUG_INT_LONG_PULSE		(2 << 19)
3275  #define   PORTC_HOTPLUG_INT_SHORT_PULSE		(1 << 19)
3276  #define   PORTB_HOTPLUG_INT_STATUS		(3 << 17)
3277  #define   PORTB_HOTPLUG_INT_LONG_PULSE		(2 << 17)
3278  #define   PORTB_HOTPLUG_INT_SHORT_PLUSE		(1 << 17)
3279  /* CRT/TV common between gen3+ */
3280  #define   CRT_HOTPLUG_INT_STATUS		(1 << 11)
3281  #define   TV_HOTPLUG_INT_STATUS			(1 << 10)
3282  #define   CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
3283  #define   CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
3284  #define   CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
3285  #define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
3286  #define   DP_AUX_CHANNEL_D_INT_STATUS_G4X	(1 << 6)
3287  #define   DP_AUX_CHANNEL_C_INT_STATUS_G4X	(1 << 5)
3288  #define   DP_AUX_CHANNEL_B_INT_STATUS_G4X	(1 << 4)
3289  #define   DP_AUX_CHANNEL_MASK_INT_STATUS_G4X	(7 << 4)
3290  
3291  /* SDVO is different across gen3/4 */
3292  #define   SDVOC_HOTPLUG_INT_STATUS_G4X		(1 << 3)
3293  #define   SDVOB_HOTPLUG_INT_STATUS_G4X		(1 << 2)
3294  /*
3295   * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
3296   * since reality corrobates that they're the same as on gen3. But keep these
3297   * bits here (and the comment!) to help any other lost wanderers back onto the
3298   * right tracks.
3299   */
3300  #define   SDVOC_HOTPLUG_INT_STATUS_I965		(3 << 4)
3301  #define   SDVOB_HOTPLUG_INT_STATUS_I965		(3 << 2)
3302  #define   SDVOC_HOTPLUG_INT_STATUS_I915		(1 << 7)
3303  #define   SDVOB_HOTPLUG_INT_STATUS_I915		(1 << 6)
3304  #define   HOTPLUG_INT_STATUS_G4X		(CRT_HOTPLUG_INT_STATUS | \
3305  						 SDVOB_HOTPLUG_INT_STATUS_G4X | \
3306  						 SDVOC_HOTPLUG_INT_STATUS_G4X | \
3307  						 PORTB_HOTPLUG_INT_STATUS | \
3308  						 PORTC_HOTPLUG_INT_STATUS | \
3309  						 PORTD_HOTPLUG_INT_STATUS)
3310  
3311  #define HOTPLUG_INT_STATUS_I915			(CRT_HOTPLUG_INT_STATUS | \
3312  						 SDVOB_HOTPLUG_INT_STATUS_I915 | \
3313  						 SDVOC_HOTPLUG_INT_STATUS_I915 | \
3314  						 PORTB_HOTPLUG_INT_STATUS | \
3315  						 PORTC_HOTPLUG_INT_STATUS | \
3316  						 PORTD_HOTPLUG_INT_STATUS)
3317  
3318  /* SDVO and HDMI port control.
3319   * The same register may be used for SDVO or HDMI */
3320  #define GEN3_SDVOB	0x61140
3321  #define GEN3_SDVOC	0x61160
3322  #define GEN4_HDMIB	GEN3_SDVOB
3323  #define GEN4_HDMIC	GEN3_SDVOC
3324  #define VLV_HDMIB	(VLV_DISPLAY_BASE + GEN4_HDMIB)
3325  #define VLV_HDMIC	(VLV_DISPLAY_BASE + GEN4_HDMIC)
3326  #define CHV_HDMID	(VLV_DISPLAY_BASE + 0x6116C)
3327  #define PCH_SDVOB	0xe1140
3328  #define PCH_HDMIB	PCH_SDVOB
3329  #define PCH_HDMIC	0xe1150
3330  #define PCH_HDMID	0xe1160
3331  
3332  #define PORT_DFT_I9XX				0x61150
3333  #define   DC_BALANCE_RESET			(1 << 25)
3334  #define PORT_DFT2_G4X		(dev_priv->info.display_mmio_offset + 0x61154)
3335  #define   DC_BALANCE_RESET_VLV			(1 << 31)
3336  #define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
3337  #define   PIPE_C_SCRAMBLE_RESET			(1 << 14) /* chv */
3338  #define   PIPE_B_SCRAMBLE_RESET			(1 << 1)
3339  #define   PIPE_A_SCRAMBLE_RESET			(1 << 0)
3340  
3341  /* Gen 3 SDVO bits: */
3342  #define   SDVO_ENABLE				(1 << 31)
3343  #define   SDVO_PIPE_SEL(pipe)			((pipe) << 30)
3344  #define   SDVO_PIPE_SEL_MASK			(1 << 30)
3345  #define   SDVO_PIPE_B_SELECT			(1 << 30)
3346  #define   SDVO_STALL_SELECT			(1 << 29)
3347  #define   SDVO_INTERRUPT_ENABLE			(1 << 26)
3348  /*
3349   * 915G/GM SDVO pixel multiplier.
3350   * Programmed value is multiplier - 1, up to 5x.
3351   * \sa DPLL_MD_UDI_MULTIPLIER_MASK
3352   */
3353  #define   SDVO_PORT_MULTIPLY_MASK		(7 << 23)
3354  #define   SDVO_PORT_MULTIPLY_SHIFT		23
3355  #define   SDVO_PHASE_SELECT_MASK		(15 << 19)
3356  #define   SDVO_PHASE_SELECT_DEFAULT		(6 << 19)
3357  #define   SDVO_CLOCK_OUTPUT_INVERT		(1 << 18)
3358  #define   SDVOC_GANG_MODE			(1 << 16) /* Port C only */
3359  #define   SDVO_BORDER_ENABLE			(1 << 7) /* SDVO only */
3360  #define   SDVOB_PCIE_CONCURRENCY		(1 << 3) /* Port B only */
3361  #define   SDVO_DETECTED				(1 << 2)
3362  /* Bits to be preserved when writing */
3363  #define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
3364  			       SDVO_INTERRUPT_ENABLE)
3365  #define   SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
3366  
3367  /* Gen 4 SDVO/HDMI bits: */
3368  #define   SDVO_COLOR_FORMAT_8bpc		(0 << 26)
3369  #define   SDVO_COLOR_FORMAT_MASK		(7 << 26)
3370  #define   SDVO_ENCODING_SDVO			(0 << 10)
3371  #define   SDVO_ENCODING_HDMI			(2 << 10)
3372  #define   HDMI_MODE_SELECT_HDMI			(1 << 9) /* HDMI only */
3373  #define   HDMI_MODE_SELECT_DVI			(0 << 9) /* HDMI only */
3374  #define   HDMI_COLOR_RANGE_16_235		(1 << 8) /* HDMI only */
3375  #define   SDVO_AUDIO_ENABLE			(1 << 6)
3376  /* VSYNC/HSYNC bits new with 965, default is to be set */
3377  #define   SDVO_VSYNC_ACTIVE_HIGH		(1 << 4)
3378  #define   SDVO_HSYNC_ACTIVE_HIGH		(1 << 3)
3379  
3380  /* Gen 5 (IBX) SDVO/HDMI bits: */
3381  #define   HDMI_COLOR_FORMAT_12bpc		(3 << 26) /* HDMI only */
3382  #define   SDVOB_HOTPLUG_ENABLE			(1 << 23) /* SDVO only */
3383  
3384  /* Gen 6 (CPT) SDVO/HDMI bits: */
3385  #define   SDVO_PIPE_SEL_CPT(pipe)		((pipe) << 29)
3386  #define   SDVO_PIPE_SEL_MASK_CPT		(3 << 29)
3387  
3388  /* CHV SDVO/HDMI bits: */
3389  #define   SDVO_PIPE_SEL_CHV(pipe)		((pipe) << 24)
3390  #define   SDVO_PIPE_SEL_MASK_CHV		(3 << 24)
3391  
3392  
3393  /* DVO port control */
3394  #define DVOA			0x61120
3395  #define DVOB			0x61140
3396  #define DVOC			0x61160
3397  #define   DVO_ENABLE			(1 << 31)
3398  #define   DVO_PIPE_B_SELECT		(1 << 30)
3399  #define   DVO_PIPE_STALL_UNUSED		(0 << 28)
3400  #define   DVO_PIPE_STALL		(1 << 28)
3401  #define   DVO_PIPE_STALL_TV		(2 << 28)
3402  #define   DVO_PIPE_STALL_MASK		(3 << 28)
3403  #define   DVO_USE_VGA_SYNC		(1 << 15)
3404  #define   DVO_DATA_ORDER_I740		(0 << 14)
3405  #define   DVO_DATA_ORDER_FP		(1 << 14)
3406  #define   DVO_VSYNC_DISABLE		(1 << 11)
3407  #define   DVO_HSYNC_DISABLE		(1 << 10)
3408  #define   DVO_VSYNC_TRISTATE		(1 << 9)
3409  #define   DVO_HSYNC_TRISTATE		(1 << 8)
3410  #define   DVO_BORDER_ENABLE		(1 << 7)
3411  #define   DVO_DATA_ORDER_GBRG		(1 << 6)
3412  #define   DVO_DATA_ORDER_RGGB		(0 << 6)
3413  #define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
3414  #define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
3415  #define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
3416  #define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
3417  #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
3418  #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
3419  #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
3420  #define   DVO_PRESERVE_MASK		(0x7<<24)
3421  #define DVOA_SRCDIM		0x61124
3422  #define DVOB_SRCDIM		0x61144
3423  #define DVOC_SRCDIM		0x61164
3424  #define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
3425  #define   DVO_SRCDIM_VERTICAL_SHIFT	0
3426  
3427  /* LVDS port control */
3428  #define LVDS			0x61180
3429  /*
3430   * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
3431   * the DPLL semantics change when the LVDS is assigned to that pipe.
3432   */
3433  #define   LVDS_PORT_EN			(1 << 31)
3434  /* Selects pipe B for LVDS data.  Must be set on pre-965. */
3435  #define   LVDS_PIPEB_SELECT		(1 << 30)
3436  #define   LVDS_PIPE_MASK		(1 << 30)
3437  #define   LVDS_PIPE(pipe)		((pipe) << 30)
3438  /* LVDS dithering flag on 965/g4x platform */
3439  #define   LVDS_ENABLE_DITHER		(1 << 25)
3440  /* LVDS sync polarity flags. Set to invert (i.e. negative) */
3441  #define   LVDS_VSYNC_POLARITY		(1 << 21)
3442  #define   LVDS_HSYNC_POLARITY		(1 << 20)
3443  
3444  /* Enable border for unscaled (or aspect-scaled) display */
3445  #define   LVDS_BORDER_ENABLE		(1 << 15)
3446  /*
3447   * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
3448   * pixel.
3449   */
3450  #define   LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
3451  #define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
3452  #define   LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
3453  /*
3454   * Controls the A3 data pair, which contains the additional LSBs for 24 bit
3455   * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
3456   * on.
3457   */
3458  #define   LVDS_A3_POWER_MASK		(3 << 6)
3459  #define   LVDS_A3_POWER_DOWN		(0 << 6)
3460  #define   LVDS_A3_POWER_UP		(3 << 6)
3461  /*
3462   * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
3463   * is set.
3464   */
3465  #define   LVDS_CLKB_POWER_MASK		(3 << 4)
3466  #define   LVDS_CLKB_POWER_DOWN		(0 << 4)
3467  #define   LVDS_CLKB_POWER_UP		(3 << 4)
3468  /*
3469   * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
3470   * setting for whether we are in dual-channel mode.  The B3 pair will
3471   * additionally only be powered up when LVDS_A3_POWER_UP is set.
3472   */
3473  #define   LVDS_B0B3_POWER_MASK		(3 << 2)
3474  #define   LVDS_B0B3_POWER_DOWN		(0 << 2)
3475  #define   LVDS_B0B3_POWER_UP		(3 << 2)
3476  
3477  /* Video Data Island Packet control */
3478  #define VIDEO_DIP_DATA		0x61178
3479  /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
3480   * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
3481   * of the infoframe structure specified by CEA-861. */
3482  #define   VIDEO_DIP_DATA_SIZE	32
3483  #define   VIDEO_DIP_VSC_DATA_SIZE	36
3484  #define VIDEO_DIP_CTL		0x61170
3485  /* Pre HSW: */
3486  #define   VIDEO_DIP_ENABLE		(1 << 31)
3487  #define   VIDEO_DIP_PORT(port)		((port) << 29)
3488  #define   VIDEO_DIP_PORT_MASK		(3 << 29)
3489  #define   VIDEO_DIP_ENABLE_GCP		(1 << 25)
3490  #define   VIDEO_DIP_ENABLE_AVI		(1 << 21)
3491  #define   VIDEO_DIP_ENABLE_VENDOR	(2 << 21)
3492  #define   VIDEO_DIP_ENABLE_GAMUT	(4 << 21)
3493  #define   VIDEO_DIP_ENABLE_SPD		(8 << 21)
3494  #define   VIDEO_DIP_SELECT_AVI		(0 << 19)
3495  #define   VIDEO_DIP_SELECT_VENDOR	(1 << 19)
3496  #define   VIDEO_DIP_SELECT_SPD		(3 << 19)
3497  #define   VIDEO_DIP_SELECT_MASK		(3 << 19)
3498  #define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
3499  #define   VIDEO_DIP_FREQ_VSYNC		(1 << 16)
3500  #define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)
3501  #define   VIDEO_DIP_FREQ_MASK		(3 << 16)
3502  /* HSW and later: */
3503  #define   VIDEO_DIP_ENABLE_VSC_HSW	(1 << 20)
3504  #define   VIDEO_DIP_ENABLE_GCP_HSW	(1 << 16)
3505  #define   VIDEO_DIP_ENABLE_AVI_HSW	(1 << 12)
3506  #define   VIDEO_DIP_ENABLE_VS_HSW	(1 << 8)
3507  #define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)
3508  #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
3509  
3510  /* Panel power sequencing */
3511  #define PP_STATUS	0x61200
3512  #define   PP_ON		(1 << 31)
3513  /*
3514   * Indicates that all dependencies of the panel are on:
3515   *
3516   * - PLL enabled
3517   * - pipe enabled
3518   * - LVDS/DVOB/DVOC on
3519   */
3520  #define   PP_READY		(1 << 30)
3521  #define   PP_SEQUENCE_NONE	(0 << 28)
3522  #define   PP_SEQUENCE_POWER_UP	(1 << 28)
3523  #define   PP_SEQUENCE_POWER_DOWN (2 << 28)
3524  #define   PP_SEQUENCE_MASK	(3 << 28)
3525  #define   PP_SEQUENCE_SHIFT	28
3526  #define   PP_CYCLE_DELAY_ACTIVE	(1 << 27)
3527  #define   PP_SEQUENCE_STATE_MASK 0x0000000f
3528  #define   PP_SEQUENCE_STATE_OFF_IDLE	(0x0 << 0)
3529  #define   PP_SEQUENCE_STATE_OFF_S0_1	(0x1 << 0)
3530  #define   PP_SEQUENCE_STATE_OFF_S0_2	(0x2 << 0)
3531  #define   PP_SEQUENCE_STATE_OFF_S0_3	(0x3 << 0)
3532  #define   PP_SEQUENCE_STATE_ON_IDLE	(0x8 << 0)
3533  #define   PP_SEQUENCE_STATE_ON_S1_0	(0x9 << 0)
3534  #define   PP_SEQUENCE_STATE_ON_S1_2	(0xa << 0)
3535  #define   PP_SEQUENCE_STATE_ON_S1_3	(0xb << 0)
3536  #define   PP_SEQUENCE_STATE_RESET	(0xf << 0)
3537  #define PP_CONTROL	0x61204
3538  #define   POWER_TARGET_ON	(1 << 0)
3539  #define PP_ON_DELAYS	0x61208
3540  #define PP_OFF_DELAYS	0x6120c
3541  #define PP_DIVISOR	0x61210
3542  
3543  /* Panel fitting */
3544  #define PFIT_CONTROL	(dev_priv->info.display_mmio_offset + 0x61230)
3545  #define   PFIT_ENABLE		(1 << 31)
3546  #define   PFIT_PIPE_MASK	(3 << 29)
3547  #define   PFIT_PIPE_SHIFT	29
3548  #define   VERT_INTERP_DISABLE	(0 << 10)
3549  #define   VERT_INTERP_BILINEAR	(1 << 10)
3550  #define   VERT_INTERP_MASK	(3 << 10)
3551  #define   VERT_AUTO_SCALE	(1 << 9)
3552  #define   HORIZ_INTERP_DISABLE	(0 << 6)
3553  #define   HORIZ_INTERP_BILINEAR	(1 << 6)
3554  #define   HORIZ_INTERP_MASK	(3 << 6)
3555  #define   HORIZ_AUTO_SCALE	(1 << 5)
3556  #define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
3557  #define   PFIT_FILTER_FUZZY	(0 << 24)
3558  #define   PFIT_SCALING_AUTO	(0 << 26)
3559  #define   PFIT_SCALING_PROGRAMMED (1 << 26)
3560  #define   PFIT_SCALING_PILLAR	(2 << 26)
3561  #define   PFIT_SCALING_LETTER	(3 << 26)
3562  #define PFIT_PGM_RATIOS	(dev_priv->info.display_mmio_offset + 0x61234)
3563  /* Pre-965 */
3564  #define		PFIT_VERT_SCALE_SHIFT		20
3565  #define		PFIT_VERT_SCALE_MASK		0xfff00000
3566  #define		PFIT_HORIZ_SCALE_SHIFT		4
3567  #define		PFIT_HORIZ_SCALE_MASK		0x0000fff0
3568  /* 965+ */
3569  #define		PFIT_VERT_SCALE_SHIFT_965	16
3570  #define		PFIT_VERT_SCALE_MASK_965	0x1fff0000
3571  #define		PFIT_HORIZ_SCALE_SHIFT_965	0
3572  #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
3573  
3574  #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
3575  
3576  #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
3577  #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
3578  #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
3579  				     _VLV_BLC_PWM_CTL2_B)
3580  
3581  #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
3582  #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
3583  #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
3584  				    _VLV_BLC_PWM_CTL_B)
3585  
3586  #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3587  #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
3588  #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
3589  				     _VLV_BLC_HIST_CTL_B)
3590  
3591  /* Backlight control */
3592  #define BLC_PWM_CTL2	(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
3593  #define   BLM_PWM_ENABLE		(1 << 31)
3594  #define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
3595  #define   BLM_PIPE_SELECT		(1 << 29)
3596  #define   BLM_PIPE_SELECT_IVB		(3 << 29)
3597  #define   BLM_PIPE_A			(0 << 29)
3598  #define   BLM_PIPE_B			(1 << 29)
3599  #define   BLM_PIPE_C			(2 << 29) /* ivb + */
3600  #define   BLM_TRANSCODER_A		BLM_PIPE_A /* hsw */
3601  #define   BLM_TRANSCODER_B		BLM_PIPE_B
3602  #define   BLM_TRANSCODER_C		BLM_PIPE_C
3603  #define   BLM_TRANSCODER_EDP		(3 << 29)
3604  #define   BLM_PIPE(pipe)		((pipe) << 29)
3605  #define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
3606  #define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
3607  #define   BLM_PHASE_IN_ENABLE		(1 << 25)
3608  #define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
3609  #define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
3610  #define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
3611  #define   BLM_PHASE_IN_COUNT_SHIFT	(8)
3612  #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
3613  #define   BLM_PHASE_IN_INCR_SHIFT	(0)
3614  #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
3615  #define BLC_PWM_CTL	(dev_priv->info.display_mmio_offset + 0x61254)
3616  /*
3617   * This is the most significant 15 bits of the number of backlight cycles in a
3618   * complete cycle of the modulated backlight control.
3619   *
3620   * The actual value is this field multiplied by two.
3621   */
3622  #define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
3623  #define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
3624  #define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
3625  /*
3626   * This is the number of cycles out of the backlight modulation cycle for which
3627   * the backlight is on.
3628   *
3629   * This field must be no greater than the number of cycles in the complete
3630   * backlight modulation cycle.
3631   */
3632  #define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
3633  #define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
3634  #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
3635  #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
3636  
3637  #define BLC_HIST_CTL	(dev_priv->info.display_mmio_offset + 0x61260)
3638  #define  BLM_HISTOGRAM_ENABLE			(1 << 31)
3639  
3640  /* New registers for PCH-split platforms. Safe where new bits show up, the
3641   * register layout machtes with gen4 BLC_PWM_CTL[12]. */
3642  #define BLC_PWM_CPU_CTL2	0x48250
3643  #define BLC_PWM_CPU_CTL		0x48254
3644  
3645  #define HSW_BLC_PWM2_CTL	0x48350
3646  
3647  /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
3648   * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
3649  #define BLC_PWM_PCH_CTL1	0xc8250
3650  #define   BLM_PCH_PWM_ENABLE			(1 << 31)
3651  #define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
3652  #define   BLM_PCH_POLARITY			(1 << 29)
3653  #define BLC_PWM_PCH_CTL2	0xc8254
3654  
3655  #define UTIL_PIN_CTL		0x48400
3656  #define   UTIL_PIN_ENABLE	(1 << 31)
3657  
3658  #define   UTIL_PIN_PIPE(x)     ((x) << 29)
3659  #define   UTIL_PIN_PIPE_MASK   (3 << 29)
3660  #define   UTIL_PIN_MODE_PWM    (1 << 24)
3661  #define   UTIL_PIN_MODE_MASK   (0xf << 24)
3662  #define   UTIL_PIN_POLARITY    (1 << 22)
3663  
3664  /* BXT backlight register definition. */
3665  #define _BXT_BLC_PWM_CTL1			0xC8250
3666  #define   BXT_BLC_PWM_ENABLE			(1 << 31)
3667  #define   BXT_BLC_PWM_POLARITY			(1 << 29)
3668  #define _BXT_BLC_PWM_FREQ1			0xC8254
3669  #define _BXT_BLC_PWM_DUTY1			0xC8258
3670  
3671  #define _BXT_BLC_PWM_CTL2			0xC8350
3672  #define _BXT_BLC_PWM_FREQ2			0xC8354
3673  #define _BXT_BLC_PWM_DUTY2			0xC8358
3674  
3675  #define BXT_BLC_PWM_CTL(controller)    _PIPE(controller, \
3676  					_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
3677  #define BXT_BLC_PWM_FREQ(controller)   _PIPE(controller, \
3678  					_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
3679  #define BXT_BLC_PWM_DUTY(controller)   _PIPE(controller, \
3680  					_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
3681  
3682  #define PCH_GTC_CTL		0xe7000
3683  #define   PCH_GTC_ENABLE	(1 << 31)
3684  
3685  /* TV port control */
3686  #define TV_CTL			0x68000
3687  /* Enables the TV encoder */
3688  # define TV_ENC_ENABLE			(1 << 31)
3689  /* Sources the TV encoder input from pipe B instead of A. */
3690  # define TV_ENC_PIPEB_SELECT		(1 << 30)
3691  /* Outputs composite video (DAC A only) */
3692  # define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
3693  /* Outputs SVideo video (DAC B/C) */
3694  # define TV_ENC_OUTPUT_SVIDEO		(1 << 28)
3695  /* Outputs Component video (DAC A/B/C) */
3696  # define TV_ENC_OUTPUT_COMPONENT	(2 << 28)
3697  /* Outputs Composite and SVideo (DAC A/B/C) */
3698  # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE	(3 << 28)
3699  # define TV_TRILEVEL_SYNC		(1 << 21)
3700  /* Enables slow sync generation (945GM only) */
3701  # define TV_SLOW_SYNC			(1 << 20)
3702  /* Selects 4x oversampling for 480i and 576p */
3703  # define TV_OVERSAMPLE_4X		(0 << 18)
3704  /* Selects 2x oversampling for 720p and 1080i */
3705  # define TV_OVERSAMPLE_2X		(1 << 18)
3706  /* Selects no oversampling for 1080p */
3707  # define TV_OVERSAMPLE_NONE		(2 << 18)
3708  /* Selects 8x oversampling */
3709  # define TV_OVERSAMPLE_8X		(3 << 18)
3710  /* Selects progressive mode rather than interlaced */
3711  # define TV_PROGRESSIVE			(1 << 17)
3712  /* Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
3713  # define TV_PAL_BURST			(1 << 16)
3714  /* Field for setting delay of Y compared to C */
3715  # define TV_YC_SKEW_MASK		(7 << 12)
3716  /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
3717  # define TV_ENC_SDP_FIX			(1 << 11)
3718  /*
3719   * Enables a fix for the 915GM only.
3720   *
3721   * Not sure what it does.
3722   */
3723  # define TV_ENC_C0_FIX			(1 << 10)
3724  /* Bits that must be preserved by software */
3725  # define TV_CTL_SAVE			((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
3726  # define TV_FUSE_STATE_MASK		(3 << 4)
3727  /* Read-only state that reports all features enabled */
3728  # define TV_FUSE_STATE_ENABLED		(0 << 4)
3729  /* Read-only state that reports that Macrovision is disabled in hardware*/
3730  # define TV_FUSE_STATE_NO_MACROVISION	(1 << 4)
3731  /* Read-only state that reports that TV-out is disabled in hardware. */
3732  # define TV_FUSE_STATE_DISABLED		(2 << 4)
3733  /* Normal operation */
3734  # define TV_TEST_MODE_NORMAL		(0 << 0)
3735  /* Encoder test pattern 1 - combo pattern */
3736  # define TV_TEST_MODE_PATTERN_1		(1 << 0)
3737  /* Encoder test pattern 2 - full screen vertical 75% color bars */
3738  # define TV_TEST_MODE_PATTERN_2		(2 << 0)
3739  /* Encoder test pattern 3 - full screen horizontal 75% color bars */
3740  # define TV_TEST_MODE_PATTERN_3		(3 << 0)
3741  /* Encoder test pattern 4 - random noise */
3742  # define TV_TEST_MODE_PATTERN_4		(4 << 0)
3743  /* Encoder test pattern 5 - linear color ramps */
3744  # define TV_TEST_MODE_PATTERN_5		(5 << 0)
3745  /*
3746   * This test mode forces the DACs to 50% of full output.
3747   *
3748   * This is used for load detection in combination with TVDAC_SENSE_MASK
3749   */
3750  # define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
3751  # define TV_TEST_MODE_MASK		(7 << 0)
3752  
3753  #define TV_DAC			0x68004
3754  # define TV_DAC_SAVE		0x00ffff00
3755  /*
3756   * Reports that DAC state change logic has reported change (RO).
3757   *
3758   * This gets cleared when TV_DAC_STATE_EN is cleared
3759  */
3760  # define TVDAC_STATE_CHG		(1 << 31)
3761  # define TVDAC_SENSE_MASK		(7 << 28)
3762  /* Reports that DAC A voltage is above the detect threshold */
3763  # define TVDAC_A_SENSE			(1 << 30)
3764  /* Reports that DAC B voltage is above the detect threshold */
3765  # define TVDAC_B_SENSE			(1 << 29)
3766  /* Reports that DAC C voltage is above the detect threshold */
3767  # define TVDAC_C_SENSE			(1 << 28)
3768  /*
3769   * Enables DAC state detection logic, for load-based TV detection.
3770   *
3771   * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
3772   * to off, for load detection to work.
3773   */
3774  # define TVDAC_STATE_CHG_EN		(1 << 27)
3775  /* Sets the DAC A sense value to high */
3776  # define TVDAC_A_SENSE_CTL		(1 << 26)
3777  /* Sets the DAC B sense value to high */
3778  # define TVDAC_B_SENSE_CTL		(1 << 25)
3779  /* Sets the DAC C sense value to high */
3780  # define TVDAC_C_SENSE_CTL		(1 << 24)
3781  /* Overrides the ENC_ENABLE and DAC voltage levels */
3782  # define DAC_CTL_OVERRIDE		(1 << 7)
3783  /* Sets the slew rate.  Must be preserved in software */
3784  # define ENC_TVDAC_SLEW_FAST		(1 << 6)
3785  # define DAC_A_1_3_V			(0 << 4)
3786  # define DAC_A_1_1_V			(1 << 4)
3787  # define DAC_A_0_7_V			(2 << 4)
3788  # define DAC_A_MASK			(3 << 4)
3789  # define DAC_B_1_3_V			(0 << 2)
3790  # define DAC_B_1_1_V			(1 << 2)
3791  # define DAC_B_0_7_V			(2 << 2)
3792  # define DAC_B_MASK			(3 << 2)
3793  # define DAC_C_1_3_V			(0 << 0)
3794  # define DAC_C_1_1_V			(1 << 0)
3795  # define DAC_C_0_7_V			(2 << 0)
3796  # define DAC_C_MASK			(3 << 0)
3797  
3798  /*
3799   * CSC coefficients are stored in a floating point format with 9 bits of
3800   * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
3801   * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
3802   * -1 (0x3) being the only legal negative value.
3803   */
3804  #define TV_CSC_Y		0x68010
3805  # define TV_RY_MASK			0x07ff0000
3806  # define TV_RY_SHIFT			16
3807  # define TV_GY_MASK			0x00000fff
3808  # define TV_GY_SHIFT			0
3809  
3810  #define TV_CSC_Y2		0x68014
3811  # define TV_BY_MASK			0x07ff0000
3812  # define TV_BY_SHIFT			16
3813  /*
3814   * Y attenuation for component video.
3815   *
3816   * Stored in 1.9 fixed point.
3817   */
3818  # define TV_AY_MASK			0x000003ff
3819  # define TV_AY_SHIFT			0
3820  
3821  #define TV_CSC_U		0x68018
3822  # define TV_RU_MASK			0x07ff0000
3823  # define TV_RU_SHIFT			16
3824  # define TV_GU_MASK			0x000007ff
3825  # define TV_GU_SHIFT			0
3826  
3827  #define TV_CSC_U2		0x6801c
3828  # define TV_BU_MASK			0x07ff0000
3829  # define TV_BU_SHIFT			16
3830  /*
3831   * U attenuation for component video.
3832   *
3833   * Stored in 1.9 fixed point.
3834   */
3835  # define TV_AU_MASK			0x000003ff
3836  # define TV_AU_SHIFT			0
3837  
3838  #define TV_CSC_V		0x68020
3839  # define TV_RV_MASK			0x0fff0000
3840  # define TV_RV_SHIFT			16
3841  # define TV_GV_MASK			0x000007ff
3842  # define TV_GV_SHIFT			0
3843  
3844  #define TV_CSC_V2		0x68024
3845  # define TV_BV_MASK			0x07ff0000
3846  # define TV_BV_SHIFT			16
3847  /*
3848   * V attenuation for component video.
3849   *
3850   * Stored in 1.9 fixed point.
3851   */
3852  # define TV_AV_MASK			0x000007ff
3853  # define TV_AV_SHIFT			0
3854  
3855  #define TV_CLR_KNOBS		0x68028
3856  /* 2s-complement brightness adjustment */
3857  # define TV_BRIGHTNESS_MASK		0xff000000
3858  # define TV_BRIGHTNESS_SHIFT		24
3859  /* Contrast adjustment, as a 2.6 unsigned floating point number */
3860  # define TV_CONTRAST_MASK		0x00ff0000
3861  # define TV_CONTRAST_SHIFT		16
3862  /* Saturation adjustment, as a 2.6 unsigned floating point number */
3863  # define TV_SATURATION_MASK		0x0000ff00
3864  # define TV_SATURATION_SHIFT		8
3865  /* Hue adjustment, as an integer phase angle in degrees */
3866  # define TV_HUE_MASK			0x000000ff
3867  # define TV_HUE_SHIFT			0
3868  
3869  #define TV_CLR_LEVEL		0x6802c
3870  /* Controls the DAC level for black */
3871  # define TV_BLACK_LEVEL_MASK		0x01ff0000
3872  # define TV_BLACK_LEVEL_SHIFT		16
3873  /* Controls the DAC level for blanking */
3874  # define TV_BLANK_LEVEL_MASK		0x000001ff
3875  # define TV_BLANK_LEVEL_SHIFT		0
3876  
3877  #define TV_H_CTL_1		0x68030
3878  /* Number of pixels in the hsync. */
3879  # define TV_HSYNC_END_MASK		0x1fff0000
3880  # define TV_HSYNC_END_SHIFT		16
3881  /* Total number of pixels minus one in the line (display and blanking). */
3882  # define TV_HTOTAL_MASK			0x00001fff
3883  # define TV_HTOTAL_SHIFT		0
3884  
3885  #define TV_H_CTL_2		0x68034
3886  /* Enables the colorburst (needed for non-component color) */
3887  # define TV_BURST_ENA			(1 << 31)
3888  /* Offset of the colorburst from the start of hsync, in pixels minus one. */
3889  # define TV_HBURST_START_SHIFT		16
3890  # define TV_HBURST_START_MASK		0x1fff0000
3891  /* Length of the colorburst */
3892  # define TV_HBURST_LEN_SHIFT		0
3893  # define TV_HBURST_LEN_MASK		0x0001fff
3894  
3895  #define TV_H_CTL_3		0x68038
3896  /* End of hblank, measured in pixels minus one from start of hsync */
3897  # define TV_HBLANK_END_SHIFT		16
3898  # define TV_HBLANK_END_MASK		0x1fff0000
3899  /* Start of hblank, measured in pixels minus one from start of hsync */
3900  # define TV_HBLANK_START_SHIFT		0
3901  # define TV_HBLANK_START_MASK		0x0001fff
3902  
3903  #define TV_V_CTL_1		0x6803c
3904  /* XXX */
3905  # define TV_NBR_END_SHIFT		16
3906  # define TV_NBR_END_MASK		0x07ff0000
3907  /* XXX */
3908  # define TV_VI_END_F1_SHIFT		8
3909  # define TV_VI_END_F1_MASK		0x00003f00
3910  /* XXX */
3911  # define TV_VI_END_F2_SHIFT		0
3912  # define TV_VI_END_F2_MASK		0x0000003f
3913  
3914  #define TV_V_CTL_2		0x68040
3915  /* Length of vsync, in half lines */
3916  # define TV_VSYNC_LEN_MASK		0x07ff0000
3917  # define TV_VSYNC_LEN_SHIFT		16
3918  /* Offset of the start of vsync in field 1, measured in one less than the
3919   * number of half lines.
3920   */
3921  # define TV_VSYNC_START_F1_MASK		0x00007f00
3922  # define TV_VSYNC_START_F1_SHIFT	8
3923  /*
3924   * Offset of the start of vsync in field 2, measured in one less than the
3925   * number of half lines.
3926   */
3927  # define TV_VSYNC_START_F2_MASK		0x0000007f
3928  # define TV_VSYNC_START_F2_SHIFT	0
3929  
3930  #define TV_V_CTL_3		0x68044
3931  /* Enables generation of the equalization signal */
3932  # define TV_EQUAL_ENA			(1 << 31)
3933  /* Length of vsync, in half lines */
3934  # define TV_VEQ_LEN_MASK		0x007f0000
3935  # define TV_VEQ_LEN_SHIFT		16
3936  /* Offset of the start of equalization in field 1, measured in one less than
3937   * the number of half lines.
3938   */
3939  # define TV_VEQ_START_F1_MASK		0x0007f00
3940  # define TV_VEQ_START_F1_SHIFT		8
3941  /*
3942   * Offset of the start of equalization in field 2, measured in one less than
3943   * the number of half lines.
3944   */
3945  # define TV_VEQ_START_F2_MASK		0x000007f
3946  # define TV_VEQ_START_F2_SHIFT		0
3947  
3948  #define TV_V_CTL_4		0x68048
3949  /*
3950   * Offset to start of vertical colorburst, measured in one less than the
3951   * number of lines from vertical start.
3952   */
3953  # define TV_VBURST_START_F1_MASK	0x003f0000
3954  # define TV_VBURST_START_F1_SHIFT	16
3955  /*
3956   * Offset to the end of vertical colorburst, measured in one less than the
3957   * number of lines from the start of NBR.
3958   */
3959  # define TV_VBURST_END_F1_MASK		0x000000ff
3960  # define TV_VBURST_END_F1_SHIFT		0
3961  
3962  #define TV_V_CTL_5		0x6804c
3963  /*
3964   * Offset to start of vertical colorburst, measured in one less than the
3965   * number of lines from vertical start.
3966   */
3967  # define TV_VBURST_START_F2_MASK	0x003f0000
3968  # define TV_VBURST_START_F2_SHIFT	16
3969  /*
3970   * Offset to the end of vertical colorburst, measured in one less than the
3971   * number of lines from the start of NBR.
3972   */
3973  # define TV_VBURST_END_F2_MASK		0x000000ff
3974  # define TV_VBURST_END_F2_SHIFT		0
3975  
3976  #define TV_V_CTL_6		0x68050
3977  /*
3978   * Offset to start of vertical colorburst, measured in one less than the
3979   * number of lines from vertical start.
3980   */
3981  # define TV_VBURST_START_F3_MASK	0x003f0000
3982  # define TV_VBURST_START_F3_SHIFT	16
3983  /*
3984   * Offset to the end of vertical colorburst, measured in one less than the
3985   * number of lines from the start of NBR.
3986   */
3987  # define TV_VBURST_END_F3_MASK		0x000000ff
3988  # define TV_VBURST_END_F3_SHIFT		0
3989  
3990  #define TV_V_CTL_7		0x68054
3991  /*
3992   * Offset to start of vertical colorburst, measured in one less than the
3993   * number of lines from vertical start.
3994   */
3995  # define TV_VBURST_START_F4_MASK	0x003f0000
3996  # define TV_VBURST_START_F4_SHIFT	16
3997  /*
3998   * Offset to the end of vertical colorburst, measured in one less than the
3999   * number of lines from the start of NBR.
4000   */
4001  # define TV_VBURST_END_F4_MASK		0x000000ff
4002  # define TV_VBURST_END_F4_SHIFT		0
4003  
4004  #define TV_SC_CTL_1		0x68060
4005  /* Turns on the first subcarrier phase generation DDA */
4006  # define TV_SC_DDA1_EN			(1 << 31)
4007  /* Turns on the first subcarrier phase generation DDA */
4008  # define TV_SC_DDA2_EN			(1 << 30)
4009  /* Turns on the first subcarrier phase generation DDA */
4010  # define TV_SC_DDA3_EN			(1 << 29)
4011  /* Sets the subcarrier DDA to reset frequency every other field */
4012  # define TV_SC_RESET_EVERY_2		(0 << 24)
4013  /* Sets the subcarrier DDA to reset frequency every fourth field */
4014  # define TV_SC_RESET_EVERY_4		(1 << 24)
4015  /* Sets the subcarrier DDA to reset frequency every eighth field */
4016  # define TV_SC_RESET_EVERY_8		(2 << 24)
4017  /* Sets the subcarrier DDA to never reset the frequency */
4018  # define TV_SC_RESET_NEVER		(3 << 24)
4019  /* Sets the peak amplitude of the colorburst.*/
4020  # define TV_BURST_LEVEL_MASK		0x00ff0000
4021  # define TV_BURST_LEVEL_SHIFT		16
4022  /* Sets the increment of the first subcarrier phase generation DDA */
4023  # define TV_SCDDA1_INC_MASK		0x00000fff
4024  # define TV_SCDDA1_INC_SHIFT		0
4025  
4026  #define TV_SC_CTL_2		0x68064
4027  /* Sets the rollover for the second subcarrier phase generation DDA */
4028  # define TV_SCDDA2_SIZE_MASK		0x7fff0000
4029  # define TV_SCDDA2_SIZE_SHIFT		16
4030  /* Sets the increent of the second subcarrier phase generation DDA */
4031  # define TV_SCDDA2_INC_MASK		0x00007fff
4032  # define TV_SCDDA2_INC_SHIFT		0
4033  
4034  #define TV_SC_CTL_3		0x68068
4035  /* Sets the rollover for the third subcarrier phase generation DDA */
4036  # define TV_SCDDA3_SIZE_MASK		0x7fff0000
4037  # define TV_SCDDA3_SIZE_SHIFT		16
4038  /* Sets the increent of the third subcarrier phase generation DDA */
4039  # define TV_SCDDA3_INC_MASK		0x00007fff
4040  # define TV_SCDDA3_INC_SHIFT		0
4041  
4042  #define TV_WIN_POS		0x68070
4043  /* X coordinate of the display from the start of horizontal active */
4044  # define TV_XPOS_MASK			0x1fff0000
4045  # define TV_XPOS_SHIFT			16
4046  /* Y coordinate of the display from the start of vertical active (NBR) */
4047  # define TV_YPOS_MASK			0x00000fff
4048  # define TV_YPOS_SHIFT			0
4049  
4050  #define TV_WIN_SIZE		0x68074
4051  /* Horizontal size of the display window, measured in pixels*/
4052  # define TV_XSIZE_MASK			0x1fff0000
4053  # define TV_XSIZE_SHIFT			16
4054  /*
4055   * Vertical size of the display window, measured in pixels.
4056   *
4057   * Must be even for interlaced modes.
4058   */
4059  # define TV_YSIZE_MASK			0x00000fff
4060  # define TV_YSIZE_SHIFT			0
4061  
4062  #define TV_FILTER_CTL_1		0x68080
4063  /*
4064   * Enables automatic scaling calculation.
4065   *
4066   * If set, the rest of the registers are ignored, and the calculated values can
4067   * be read back from the register.
4068   */
4069  # define TV_AUTO_SCALE			(1 << 31)
4070  /*
4071   * Disables the vertical filter.
4072   *
4073   * This is required on modes more than 1024 pixels wide */
4074  # define TV_V_FILTER_BYPASS		(1 << 29)
4075  /* Enables adaptive vertical filtering */
4076  # define TV_VADAPT			(1 << 28)
4077  # define TV_VADAPT_MODE_MASK		(3 << 26)
4078  /* Selects the least adaptive vertical filtering mode */
4079  # define TV_VADAPT_MODE_LEAST		(0 << 26)
4080  /* Selects the moderately adaptive vertical filtering mode */
4081  # define TV_VADAPT_MODE_MODERATE	(1 << 26)
4082  /* Selects the most adaptive vertical filtering mode */
4083  # define TV_VADAPT_MODE_MOST		(3 << 26)
4084  /*
4085   * Sets the horizontal scaling factor.
4086   *
4087   * This should be the fractional part of the horizontal scaling factor divided
4088   * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
4089   *
4090   * (src width - 1) / ((oversample * dest width) - 1)
4091   */
4092  # define TV_HSCALE_FRAC_MASK		0x00003fff
4093  # define TV_HSCALE_FRAC_SHIFT		0
4094  
4095  #define TV_FILTER_CTL_2		0x68084
4096  /*
4097   * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
4098   *
4099   * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
4100   */
4101  # define TV_VSCALE_INT_MASK		0x00038000
4102  # define TV_VSCALE_INT_SHIFT		15
4103  /*
4104   * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
4105   *
4106   * \sa TV_VSCALE_INT_MASK
4107   */
4108  # define TV_VSCALE_FRAC_MASK		0x00007fff
4109  # define TV_VSCALE_FRAC_SHIFT		0
4110  
4111  #define TV_FILTER_CTL_3		0x68088
4112  /*
4113   * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
4114   *
4115   * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
4116   *
4117   * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4118   */
4119  # define TV_VSCALE_IP_INT_MASK		0x00038000
4120  # define TV_VSCALE_IP_INT_SHIFT		15
4121  /*
4122   * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
4123   *
4124   * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4125   *
4126   * \sa TV_VSCALE_IP_INT_MASK
4127   */
4128  # define TV_VSCALE_IP_FRAC_MASK		0x00007fff
4129  # define TV_VSCALE_IP_FRAC_SHIFT		0
4130  
4131  #define TV_CC_CONTROL		0x68090
4132  # define TV_CC_ENABLE			(1 << 31)
4133  /*
4134   * Specifies which field to send the CC data in.
4135   *
4136   * CC data is usually sent in field 0.
4137   */
4138  # define TV_CC_FID_MASK			(1 << 27)
4139  # define TV_CC_FID_SHIFT		27
4140  /* Sets the horizontal position of the CC data.  Usually 135. */
4141  # define TV_CC_HOFF_MASK		0x03ff0000
4142  # define TV_CC_HOFF_SHIFT		16
4143  /* Sets the vertical position of the CC data.  Usually 21 */
4144  # define TV_CC_LINE_MASK		0x0000003f
4145  # define TV_CC_LINE_SHIFT		0
4146  
4147  #define TV_CC_DATA		0x68094
4148  # define TV_CC_RDY			(1 << 31)
4149  /* Second word of CC data to be transmitted. */
4150  # define TV_CC_DATA_2_MASK		0x007f0000
4151  # define TV_CC_DATA_2_SHIFT		16
4152  /* First word of CC data to be transmitted. */
4153  # define TV_CC_DATA_1_MASK		0x0000007f
4154  # define TV_CC_DATA_1_SHIFT		0
4155  
4156  #define TV_H_LUMA(i)		(0x68100 + (i) * 4) /* 60 registers */
4157  #define TV_H_CHROMA(i)		(0x68200 + (i) * 4) /* 60 registers */
4158  #define TV_V_LUMA(i)		(0x68300 + (i) * 4) /* 43 registers */
4159  #define TV_V_CHROMA(i)		(0x68400 + (i) * 4) /* 43 registers */
4160  
4161  /* Display Port */
4162  #define DP_A				0x64000 /* eDP */
4163  #define DP_B				0x64100
4164  #define DP_C				0x64200
4165  #define DP_D				0x64300
4166  
4167  #define VLV_DP_B			(VLV_DISPLAY_BASE + DP_B)
4168  #define VLV_DP_C			(VLV_DISPLAY_BASE + DP_C)
4169  #define CHV_DP_D			(VLV_DISPLAY_BASE + DP_D)
4170  
4171  #define   DP_PORT_EN			(1 << 31)
4172  #define   DP_PIPEB_SELECT		(1 << 30)
4173  #define   DP_PIPE_MASK			(1 << 30)
4174  #define   DP_PIPE_SELECT_CHV(pipe)	((pipe) << 16)
4175  #define   DP_PIPE_MASK_CHV		(3 << 16)
4176  
4177  /* Link training mode - select a suitable mode for each stage */
4178  #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
4179  #define   DP_LINK_TRAIN_PAT_2		(1 << 28)
4180  #define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)
4181  #define   DP_LINK_TRAIN_OFF		(3 << 28)
4182  #define   DP_LINK_TRAIN_MASK		(3 << 28)
4183  #define   DP_LINK_TRAIN_SHIFT		28
4184  #define   DP_LINK_TRAIN_PAT_3_CHV	(1 << 14)
4185  #define   DP_LINK_TRAIN_MASK_CHV	((3 << 28)|(1<<14))
4186  
4187  /* CPT Link training mode */
4188  #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
4189  #define   DP_LINK_TRAIN_PAT_2_CPT	(1 << 8)
4190  #define   DP_LINK_TRAIN_PAT_IDLE_CPT	(2 << 8)
4191  #define   DP_LINK_TRAIN_OFF_CPT		(3 << 8)
4192  #define   DP_LINK_TRAIN_MASK_CPT	(7 << 8)
4193  #define   DP_LINK_TRAIN_SHIFT_CPT	8
4194  
4195  /* Signal voltages. These are mostly controlled by the other end */
4196  #define   DP_VOLTAGE_0_4		(0 << 25)
4197  #define   DP_VOLTAGE_0_6		(1 << 25)
4198  #define   DP_VOLTAGE_0_8		(2 << 25)
4199  #define   DP_VOLTAGE_1_2		(3 << 25)
4200  #define   DP_VOLTAGE_MASK		(7 << 25)
4201  #define   DP_VOLTAGE_SHIFT		25
4202  
4203  /* Signal pre-emphasis levels, like voltages, the other end tells us what
4204   * they want
4205   */
4206  #define   DP_PRE_EMPHASIS_0		(0 << 22)
4207  #define   DP_PRE_EMPHASIS_3_5		(1 << 22)
4208  #define   DP_PRE_EMPHASIS_6		(2 << 22)
4209  #define   DP_PRE_EMPHASIS_9_5		(3 << 22)
4210  #define   DP_PRE_EMPHASIS_MASK		(7 << 22)
4211  #define   DP_PRE_EMPHASIS_SHIFT		22
4212  
4213  /* How many wires to use. I guess 3 was too hard */
4214  #define   DP_PORT_WIDTH(width)		(((width) - 1) << 19)
4215  #define   DP_PORT_WIDTH_MASK		(7 << 19)
4216  #define   DP_PORT_WIDTH_SHIFT		19
4217  
4218  /* Mystic DPCD version 1.1 special mode */
4219  #define   DP_ENHANCED_FRAMING		(1 << 18)
4220  
4221  /* eDP */
4222  #define   DP_PLL_FREQ_270MHZ		(0 << 16)
4223  #define   DP_PLL_FREQ_160MHZ		(1 << 16)
4224  #define   DP_PLL_FREQ_MASK		(3 << 16)
4225  
4226  /* locked once port is enabled */
4227  #define   DP_PORT_REVERSAL		(1 << 15)
4228  
4229  /* eDP */
4230  #define   DP_PLL_ENABLE			(1 << 14)
4231  
4232  /* sends the clock on lane 15 of the PEG for debug */
4233  #define   DP_CLOCK_OUTPUT_ENABLE	(1 << 13)
4234  
4235  #define   DP_SCRAMBLING_DISABLE		(1 << 12)
4236  #define   DP_SCRAMBLING_DISABLE_IRONLAKE	(1 << 7)
4237  
4238  /* limit RGB values to avoid confusing TVs */
4239  #define   DP_COLOR_RANGE_16_235		(1 << 8)
4240  
4241  /* Turn on the audio link */
4242  #define   DP_AUDIO_OUTPUT_ENABLE	(1 << 6)
4243  
4244  /* vs and hs sync polarity */
4245  #define   DP_SYNC_VS_HIGH		(1 << 4)
4246  #define   DP_SYNC_HS_HIGH		(1 << 3)
4247  
4248  /* A fantasy */
4249  #define   DP_DETECTED			(1 << 2)
4250  
4251  /* The aux channel provides a way to talk to the
4252   * signal sink for DDC etc. Max packet size supported
4253   * is 20 bytes in each direction, hence the 5 fixed
4254   * data registers
4255   */
4256  #define DPA_AUX_CH_CTL			0x64010
4257  #define DPA_AUX_CH_DATA1		0x64014
4258  #define DPA_AUX_CH_DATA2		0x64018
4259  #define DPA_AUX_CH_DATA3		0x6401c
4260  #define DPA_AUX_CH_DATA4		0x64020
4261  #define DPA_AUX_CH_DATA5		0x64024
4262  
4263  #define DPB_AUX_CH_CTL			0x64110
4264  #define DPB_AUX_CH_DATA1		0x64114
4265  #define DPB_AUX_CH_DATA2		0x64118
4266  #define DPB_AUX_CH_DATA3		0x6411c
4267  #define DPB_AUX_CH_DATA4		0x64120
4268  #define DPB_AUX_CH_DATA5		0x64124
4269  
4270  #define DPC_AUX_CH_CTL			0x64210
4271  #define DPC_AUX_CH_DATA1		0x64214
4272  #define DPC_AUX_CH_DATA2		0x64218
4273  #define DPC_AUX_CH_DATA3		0x6421c
4274  #define DPC_AUX_CH_DATA4		0x64220
4275  #define DPC_AUX_CH_DATA5		0x64224
4276  
4277  #define DPD_AUX_CH_CTL			0x64310
4278  #define DPD_AUX_CH_DATA1		0x64314
4279  #define DPD_AUX_CH_DATA2		0x64318
4280  #define DPD_AUX_CH_DATA3		0x6431c
4281  #define DPD_AUX_CH_DATA4		0x64320
4282  #define DPD_AUX_CH_DATA5		0x64324
4283  
4284  #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
4285  #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
4286  #define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)
4287  #define   DP_AUX_CH_CTL_TIME_OUT_ERROR	    (1 << 28)
4288  #define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
4289  #define   DP_AUX_CH_CTL_TIME_OUT_600us	    (1 << 26)
4290  #define   DP_AUX_CH_CTL_TIME_OUT_800us	    (2 << 26)
4291  #define   DP_AUX_CH_CTL_TIME_OUT_1600us	    (3 << 26)
4292  #define   DP_AUX_CH_CTL_TIME_OUT_MASK	    (3 << 26)
4293  #define   DP_AUX_CH_CTL_RECEIVE_ERROR	    (1 << 25)
4294  #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
4295  #define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
4296  #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
4297  #define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
4298  #define   DP_AUX_CH_CTL_AUX_AKSV_SELECT	    (1 << 15)
4299  #define   DP_AUX_CH_CTL_MANCHESTER_TEST	    (1 << 14)
4300  #define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
4301  #define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
4302  #define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
4303  #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
4304  #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
4305  #define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL	(1 << 14)
4306  #define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL	(1 << 13)
4307  #define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL	(1 << 12)
4308  #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
4309  #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
4310  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
4311  
4312  /*
4313   * Computing GMCH M and N values for the Display Port link
4314   *
4315   * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
4316   *
4317   * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
4318   *
4319   * The GMCH value is used internally
4320   *
4321   * bytes_per_pixel is the number of bytes coming out of the plane,
4322   * which is after the LUTs, so we want the bytes for our color format.
4323   * For our current usage, this is always 3, one byte for R, G and B.
4324   */
4325  #define _PIPEA_DATA_M_G4X	0x70050
4326  #define _PIPEB_DATA_M_G4X	0x71050
4327  
4328  /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
4329  #define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */
4330  #define  TU_SIZE_SHIFT		25
4331  #define  TU_SIZE_MASK           (0x3f << 25)
4332  
4333  #define  DATA_LINK_M_N_MASK	(0xffffff)
4334  #define  DATA_LINK_N_MAX	(0x800000)
4335  
4336  #define _PIPEA_DATA_N_G4X	0x70054
4337  #define _PIPEB_DATA_N_G4X	0x71054
4338  #define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
4339  
4340  /*
4341   * Computing Link M and N values for the Display Port link
4342   *
4343   * Link M / N = pixel_clock / ls_clk
4344   *
4345   * (the DP spec calls pixel_clock the 'strm_clk')
4346   *
4347   * The Link value is transmitted in the Main Stream
4348   * Attributes and VB-ID.
4349   */
4350  
4351  #define _PIPEA_LINK_M_G4X	0x70060
4352  #define _PIPEB_LINK_M_G4X	0x71060
4353  #define   PIPEA_DP_LINK_M_MASK			(0xffffff)
4354  
4355  #define _PIPEA_LINK_N_G4X	0x70064
4356  #define _PIPEB_LINK_N_G4X	0x71064
4357  #define   PIPEA_DP_LINK_N_MASK			(0xffffff)
4358  
4359  #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
4360  #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
4361  #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
4362  #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
4363  
4364  /* Display & cursor control */
4365  
4366  /* Pipe A */
4367  #define _PIPEADSL		0x70000
4368  #define   DSL_LINEMASK_GEN2	0x00000fff
4369  #define   DSL_LINEMASK_GEN3	0x00001fff
4370  #define _PIPEACONF		0x70008
4371  #define   PIPECONF_ENABLE	(1<<31)
4372  #define   PIPECONF_DISABLE	0
4373  #define   PIPECONF_DOUBLE_WIDE	(1<<30)
4374  #define   I965_PIPECONF_ACTIVE	(1<<30)
4375  #define   PIPECONF_DSI_PLL_LOCKED	(1<<29) /* vlv & pipe A only */
4376  #define   PIPECONF_FRAME_START_DELAY_MASK (3<<27)
4377  #define   PIPECONF_SINGLE_WIDE	0
4378  #define   PIPECONF_PIPE_UNLOCKED 0
4379  #define   PIPECONF_PIPE_LOCKED	(1<<25)
4380  #define   PIPECONF_PALETTE	0
4381  #define   PIPECONF_GAMMA		(1<<24)
4382  #define   PIPECONF_FORCE_BORDER	(1<<25)
4383  #define   PIPECONF_INTERLACE_MASK	(7 << 21)
4384  #define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
4385  /* Note that pre-gen3 does not support interlaced display directly. Panel
4386   * fitting must be disabled on pre-ilk for interlaced. */
4387  #define   PIPECONF_PROGRESSIVE			(0 << 21)
4388  #define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
4389  #define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
4390  #define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
4391  #define   PIPECONF_INTERLACE_FIELD_0_ONLY	(7 << 21) /* gen3 only */
4392  /* Ironlake and later have a complete new set of values for interlaced. PFIT
4393   * means panel fitter required, PF means progressive fetch, DBL means power
4394   * saving pixel doubling. */
4395  #define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
4396  #define   PIPECONF_INTERLACED_ILK		(3 << 21)
4397  #define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
4398  #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
4399  #define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)
4400  #define   PIPECONF_EDP_RR_MODE_SWITCH		(1 << 20)
4401  #define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)
4402  #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
4403  #define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
4404  #define   PIPECONF_BPC_MASK	(0x7 << 5)
4405  #define   PIPECONF_8BPC		(0<<5)
4406  #define   PIPECONF_10BPC	(1<<5)
4407  #define   PIPECONF_6BPC		(2<<5)
4408  #define   PIPECONF_12BPC	(3<<5)
4409  #define   PIPECONF_DITHER_EN	(1<<4)
4410  #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
4411  #define   PIPECONF_DITHER_TYPE_SP (0<<2)
4412  #define   PIPECONF_DITHER_TYPE_ST1 (1<<2)
4413  #define   PIPECONF_DITHER_TYPE_ST2 (2<<2)
4414  #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
4415  #define _PIPEASTAT		0x70024
4416  #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
4417  #define   SPRITE1_FLIP_DONE_INT_EN_VLV		(1UL<<30)
4418  #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
4419  #define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
4420  #define   PERF_COUNTER2_INTERRUPT_EN		(1UL<<27)
4421  #define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
4422  #define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL<<26)
4423  #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
4424  #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
4425  #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
4426  #define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
4427  #define   SPRITE0_FLIP_DONE_INT_EN_VLV		(1UL<<22)
4428  #define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
4429  #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
4430  #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
4431  #define   PIPE_B_PSR_INTERRUPT_ENABLE_VLV	(1UL<<19)
4432  #define   PERF_COUNTER_INTERRUPT_EN		(1UL<<19)
4433  #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
4434  #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
4435  #define   PIPE_FRAMESTART_INTERRUPT_ENABLE	(1UL<<17)
4436  #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
4437  #define   PIPEA_HBLANK_INT_EN_VLV		(1UL<<16)
4438  #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
4439  #define   SPRITE1_FLIP_DONE_INT_STATUS_VLV	(1UL<<15)
4440  #define   SPRITE0_FLIP_DONE_INT_STATUS_VLV	(1UL<<14)
4441  #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
4442  #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
4443  #define   PERF_COUNTER2_INTERRUPT_STATUS	(1UL<<11)
4444  #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
4445  #define   PLANE_FLIP_DONE_INT_STATUS_VLV	(1UL<<10)
4446  #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
4447  #define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
4448  #define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
4449  #define   PIPE_DPST_EVENT_STATUS		(1UL<<7)
4450  #define   PIPE_A_PSR_STATUS_VLV			(1UL<<6)
4451  #define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
4452  #define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL<<5)
4453  #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
4454  #define   PIPE_B_PSR_STATUS_VLV			(1UL<<3)
4455  #define   PERF_COUNTER_INTERRUPT_STATUS		(1UL<<3)
4456  #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL<<2) /* pre-965 */
4457  #define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or later */
4458  #define   PIPE_FRAMESTART_INTERRUPT_STATUS	(1UL<<1)
4459  #define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)
4460  #define   PIPE_HBLANK_INT_STATUS		(1UL<<0)
4461  #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)
4462  
4463  #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
4464  #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
4465  
4466  #define PIPE_A_OFFSET		0x70000
4467  #define PIPE_B_OFFSET		0x71000
4468  #define PIPE_C_OFFSET		0x72000
4469  #define CHV_PIPE_C_OFFSET	0x74000
4470  /*
4471   * There's actually no pipe EDP. Some pipe registers have
4472   * simply shifted from the pipe to the transcoder, while
4473   * keeping their original offset. Thus we need PIPE_EDP_OFFSET
4474   * to access such registers in transcoder EDP.
4475   */
4476  #define PIPE_EDP_OFFSET	0x7f000
4477  
4478  #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
4479  	dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
4480  	dev_priv->info.display_mmio_offset)
4481  
4482  #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
4483  #define PIPEDSL(pipe)  _PIPE2(pipe, _PIPEADSL)
4484  #define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
4485  #define PIPEFRAMEPIXEL(pipe)  _PIPE2(pipe, _PIPEAFRAMEPIXEL)
4486  #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
4487  
4488  #define _PIPE_MISC_A			0x70030
4489  #define _PIPE_MISC_B			0x71030
4490  #define   PIPEMISC_DITHER_BPC_MASK	(7<<5)
4491  #define   PIPEMISC_DITHER_8_BPC		(0<<5)
4492  #define   PIPEMISC_DITHER_10_BPC	(1<<5)
4493  #define   PIPEMISC_DITHER_6_BPC		(2<<5)
4494  #define   PIPEMISC_DITHER_12_BPC	(3<<5)
4495  #define   PIPEMISC_DITHER_ENABLE	(1<<4)
4496  #define   PIPEMISC_DITHER_TYPE_MASK	(3<<2)
4497  #define   PIPEMISC_DITHER_TYPE_SP	(0<<2)
4498  #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
4499  
4500  #define VLV_DPFLIPSTAT				(VLV_DISPLAY_BASE + 0x70028)
4501  #define   PIPEB_LINE_COMPARE_INT_EN		(1<<29)
4502  #define   PIPEB_HLINE_INT_EN			(1<<28)
4503  #define   PIPEB_VBLANK_INT_EN			(1<<27)
4504  #define   SPRITED_FLIP_DONE_INT_EN		(1<<26)
4505  #define   SPRITEC_FLIP_DONE_INT_EN		(1<<25)
4506  #define   PLANEB_FLIP_DONE_INT_EN		(1<<24)
4507  #define   PIPE_PSR_INT_EN			(1<<22)
4508  #define   PIPEA_LINE_COMPARE_INT_EN		(1<<21)
4509  #define   PIPEA_HLINE_INT_EN			(1<<20)
4510  #define   PIPEA_VBLANK_INT_EN			(1<<19)
4511  #define   SPRITEB_FLIP_DONE_INT_EN		(1<<18)
4512  #define   SPRITEA_FLIP_DONE_INT_EN		(1<<17)
4513  #define   PLANEA_FLIPDONE_INT_EN		(1<<16)
4514  #define   PIPEC_LINE_COMPARE_INT_EN		(1<<13)
4515  #define   PIPEC_HLINE_INT_EN			(1<<12)
4516  #define   PIPEC_VBLANK_INT_EN			(1<<11)
4517  #define   SPRITEF_FLIPDONE_INT_EN		(1<<10)
4518  #define   SPRITEE_FLIPDONE_INT_EN		(1<<9)
4519  #define   PLANEC_FLIPDONE_INT_EN		(1<<8)
4520  
4521  #define DPINVGTT				(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
4522  #define   SPRITEF_INVALID_GTT_INT_EN		(1<<27)
4523  #define   SPRITEE_INVALID_GTT_INT_EN		(1<<26)
4524  #define   PLANEC_INVALID_GTT_INT_EN		(1<<25)
4525  #define   CURSORC_INVALID_GTT_INT_EN		(1<<24)
4526  #define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
4527  #define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
4528  #define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
4529  #define   SPRITEC_INVALID_GTT_INT_EN		(1<<20)
4530  #define   PLANEB_INVALID_GTT_INT_EN		(1<<19)
4531  #define   SPRITEB_INVALID_GTT_INT_EN		(1<<18)
4532  #define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
4533  #define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
4534  #define   DPINVGTT_EN_MASK			0xff0000
4535  #define   DPINVGTT_EN_MASK_CHV			0xfff0000
4536  #define   SPRITEF_INVALID_GTT_STATUS		(1<<11)
4537  #define   SPRITEE_INVALID_GTT_STATUS		(1<<10)
4538  #define   PLANEC_INVALID_GTT_STATUS		(1<<9)
4539  #define   CURSORC_INVALID_GTT_STATUS		(1<<8)
4540  #define   CURSORB_INVALID_GTT_STATUS		(1<<7)
4541  #define   CURSORA_INVALID_GTT_STATUS		(1<<6)
4542  #define   SPRITED_INVALID_GTT_STATUS		(1<<5)
4543  #define   SPRITEC_INVALID_GTT_STATUS		(1<<4)
4544  #define   PLANEB_INVALID_GTT_STATUS		(1<<3)
4545  #define   SPRITEB_INVALID_GTT_STATUS		(1<<2)
4546  #define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
4547  #define   PLANEA_INVALID_GTT_STATUS		(1<<0)
4548  #define   DPINVGTT_STATUS_MASK			0xff
4549  #define   DPINVGTT_STATUS_MASK_CHV		0xfff
4550  
4551  #define DSPARB			(dev_priv->info.display_mmio_offset + 0x70030)
4552  #define   DSPARB_CSTART_MASK	(0x7f << 7)
4553  #define   DSPARB_CSTART_SHIFT	7
4554  #define   DSPARB_BSTART_MASK	(0x7f)
4555  #define   DSPARB_BSTART_SHIFT	0
4556  #define   DSPARB_BEND_SHIFT	9 /* on 855 */
4557  #define   DSPARB_AEND_SHIFT	0
4558  #define   DSPARB_SPRITEA_SHIFT_VLV	0
4559  #define   DSPARB_SPRITEA_MASK_VLV	(0xff << 0)
4560  #define   DSPARB_SPRITEB_SHIFT_VLV	8
4561  #define   DSPARB_SPRITEB_MASK_VLV	(0xff << 8)
4562  #define   DSPARB_SPRITEC_SHIFT_VLV	16
4563  #define   DSPARB_SPRITEC_MASK_VLV	(0xff << 16)
4564  #define   DSPARB_SPRITED_SHIFT_VLV	24
4565  #define   DSPARB_SPRITED_MASK_VLV	(0xff << 24)
4566  #define DSPARB2			(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
4567  #define   DSPARB_SPRITEA_HI_SHIFT_VLV	0
4568  #define   DSPARB_SPRITEA_HI_MASK_VLV	(0x1 << 0)
4569  #define   DSPARB_SPRITEB_HI_SHIFT_VLV	4
4570  #define   DSPARB_SPRITEB_HI_MASK_VLV	(0x1 << 4)
4571  #define   DSPARB_SPRITEC_HI_SHIFT_VLV	8
4572  #define   DSPARB_SPRITEC_HI_MASK_VLV	(0x1 << 8)
4573  #define   DSPARB_SPRITED_HI_SHIFT_VLV	12
4574  #define   DSPARB_SPRITED_HI_MASK_VLV	(0x1 << 12)
4575  #define   DSPARB_SPRITEE_HI_SHIFT_VLV	16
4576  #define   DSPARB_SPRITEE_HI_MASK_VLV	(0x1 << 16)
4577  #define   DSPARB_SPRITEF_HI_SHIFT_VLV	20
4578  #define   DSPARB_SPRITEF_HI_MASK_VLV	(0x1 << 20)
4579  #define DSPARB3			(VLV_DISPLAY_BASE + 0x7006c) /* chv */
4580  #define   DSPARB_SPRITEE_SHIFT_VLV	0
4581  #define   DSPARB_SPRITEE_MASK_VLV	(0xff << 0)
4582  #define   DSPARB_SPRITEF_SHIFT_VLV	8
4583  #define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
4584  
4585  /* pnv/gen4/g4x/vlv/chv */
4586  #define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
4587  #define   DSPFW_SR_SHIFT		23
4588  #define   DSPFW_SR_MASK			(0x1ff<<23)
4589  #define   DSPFW_CURSORB_SHIFT		16
4590  #define   DSPFW_CURSORB_MASK		(0x3f<<16)
4591  #define   DSPFW_PLANEB_SHIFT		8
4592  #define   DSPFW_PLANEB_MASK		(0x7f<<8)
4593  #define   DSPFW_PLANEB_MASK_VLV		(0xff<<8) /* vlv/chv */
4594  #define   DSPFW_PLANEA_SHIFT		0
4595  #define   DSPFW_PLANEA_MASK		(0x7f<<0)
4596  #define   DSPFW_PLANEA_MASK_VLV		(0xff<<0) /* vlv/chv */
4597  #define DSPFW2			(dev_priv->info.display_mmio_offset + 0x70038)
4598  #define   DSPFW_FBC_SR_EN		(1<<31)	  /* g4x */
4599  #define   DSPFW_FBC_SR_SHIFT		28
4600  #define   DSPFW_FBC_SR_MASK		(0x7<<28) /* g4x */
4601  #define   DSPFW_FBC_HPLL_SR_SHIFT	24
4602  #define   DSPFW_FBC_HPLL_SR_MASK	(0xf<<24) /* g4x */
4603  #define   DSPFW_SPRITEB_SHIFT		(16)
4604  #define   DSPFW_SPRITEB_MASK		(0x7f<<16) /* g4x */
4605  #define   DSPFW_SPRITEB_MASK_VLV	(0xff<<16) /* vlv/chv */
4606  #define   DSPFW_CURSORA_SHIFT		8
4607  #define   DSPFW_CURSORA_MASK		(0x3f<<8)
4608  #define   DSPFW_PLANEC_OLD_SHIFT	0
4609  #define   DSPFW_PLANEC_OLD_MASK		(0x7f<<0) /* pre-gen4 sprite C */
4610  #define   DSPFW_SPRITEA_SHIFT		0
4611  #define   DSPFW_SPRITEA_MASK		(0x7f<<0) /* g4x */
4612  #define   DSPFW_SPRITEA_MASK_VLV	(0xff<<0) /* vlv/chv */
4613  #define DSPFW3			(dev_priv->info.display_mmio_offset + 0x7003c)
4614  #define   DSPFW_HPLL_SR_EN		(1<<31)
4615  #define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
4616  #define   DSPFW_CURSOR_SR_SHIFT		24
4617  #define   DSPFW_CURSOR_SR_MASK		(0x3f<<24)
4618  #define   DSPFW_HPLL_CURSOR_SHIFT	16
4619  #define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
4620  #define   DSPFW_HPLL_SR_SHIFT		0
4621  #define   DSPFW_HPLL_SR_MASK		(0x1ff<<0)
4622  
4623  /* vlv/chv */
4624  #define DSPFW4			(VLV_DISPLAY_BASE + 0x70070)
4625  #define   DSPFW_SPRITEB_WM1_SHIFT	16
4626  #define   DSPFW_SPRITEB_WM1_MASK	(0xff<<16)
4627  #define   DSPFW_CURSORA_WM1_SHIFT	8
4628  #define   DSPFW_CURSORA_WM1_MASK	(0x3f<<8)
4629  #define   DSPFW_SPRITEA_WM1_SHIFT	0
4630  #define   DSPFW_SPRITEA_WM1_MASK	(0xff<<0)
4631  #define DSPFW5			(VLV_DISPLAY_BASE + 0x70074)
4632  #define   DSPFW_PLANEB_WM1_SHIFT	24
4633  #define   DSPFW_PLANEB_WM1_MASK		(0xff<<24)
4634  #define   DSPFW_PLANEA_WM1_SHIFT	16
4635  #define   DSPFW_PLANEA_WM1_MASK		(0xff<<16)
4636  #define   DSPFW_CURSORB_WM1_SHIFT	8
4637  #define   DSPFW_CURSORB_WM1_MASK	(0x3f<<8)
4638  #define   DSPFW_CURSOR_SR_WM1_SHIFT	0
4639  #define   DSPFW_CURSOR_SR_WM1_MASK	(0x3f<<0)
4640  #define DSPFW6			(VLV_DISPLAY_BASE + 0x70078)
4641  #define   DSPFW_SR_WM1_SHIFT		0
4642  #define   DSPFW_SR_WM1_MASK		(0x1ff<<0)
4643  #define DSPFW7			(VLV_DISPLAY_BASE + 0x7007c)
4644  #define DSPFW7_CHV		(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
4645  #define   DSPFW_SPRITED_WM1_SHIFT	24
4646  #define   DSPFW_SPRITED_WM1_MASK	(0xff<<24)
4647  #define   DSPFW_SPRITED_SHIFT		16
4648  #define   DSPFW_SPRITED_MASK_VLV	(0xff<<16)
4649  #define   DSPFW_SPRITEC_WM1_SHIFT	8
4650  #define   DSPFW_SPRITEC_WM1_MASK	(0xff<<8)
4651  #define   DSPFW_SPRITEC_SHIFT		0
4652  #define   DSPFW_SPRITEC_MASK_VLV	(0xff<<0)
4653  #define DSPFW8_CHV		(VLV_DISPLAY_BASE + 0x700b8)
4654  #define   DSPFW_SPRITEF_WM1_SHIFT	24
4655  #define   DSPFW_SPRITEF_WM1_MASK	(0xff<<24)
4656  #define   DSPFW_SPRITEF_SHIFT		16
4657  #define   DSPFW_SPRITEF_MASK_VLV	(0xff<<16)
4658  #define   DSPFW_SPRITEE_WM1_SHIFT	8
4659  #define   DSPFW_SPRITEE_WM1_MASK	(0xff<<8)
4660  #define   DSPFW_SPRITEE_SHIFT		0
4661  #define   DSPFW_SPRITEE_MASK_VLV	(0xff<<0)
4662  #define DSPFW9_CHV		(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
4663  #define   DSPFW_PLANEC_WM1_SHIFT	24
4664  #define   DSPFW_PLANEC_WM1_MASK		(0xff<<24)
4665  #define   DSPFW_PLANEC_SHIFT		16
4666  #define   DSPFW_PLANEC_MASK_VLV		(0xff<<16)
4667  #define   DSPFW_CURSORC_WM1_SHIFT	8
4668  #define   DSPFW_CURSORC_WM1_MASK	(0x3f<<16)
4669  #define   DSPFW_CURSORC_SHIFT		0
4670  #define   DSPFW_CURSORC_MASK		(0x3f<<0)
4671  
4672  /* vlv/chv high order bits */
4673  #define DSPHOWM			(VLV_DISPLAY_BASE + 0x70064)
4674  #define   DSPFW_SR_HI_SHIFT		24
4675  #define   DSPFW_SR_HI_MASK		(3<<24) /* 2 bits for chv, 1 for vlv */
4676  #define   DSPFW_SPRITEF_HI_SHIFT	23
4677  #define   DSPFW_SPRITEF_HI_MASK		(1<<23)
4678  #define   DSPFW_SPRITEE_HI_SHIFT	22
4679  #define   DSPFW_SPRITEE_HI_MASK		(1<<22)
4680  #define   DSPFW_PLANEC_HI_SHIFT		21
4681  #define   DSPFW_PLANEC_HI_MASK		(1<<21)
4682  #define   DSPFW_SPRITED_HI_SHIFT	20
4683  #define   DSPFW_SPRITED_HI_MASK		(1<<20)
4684  #define   DSPFW_SPRITEC_HI_SHIFT	16
4685  #define   DSPFW_SPRITEC_HI_MASK		(1<<16)
4686  #define   DSPFW_PLANEB_HI_SHIFT		12
4687  #define   DSPFW_PLANEB_HI_MASK		(1<<12)
4688  #define   DSPFW_SPRITEB_HI_SHIFT	8
4689  #define   DSPFW_SPRITEB_HI_MASK		(1<<8)
4690  #define   DSPFW_SPRITEA_HI_SHIFT	4
4691  #define   DSPFW_SPRITEA_HI_MASK		(1<<4)
4692  #define   DSPFW_PLANEA_HI_SHIFT		0
4693  #define   DSPFW_PLANEA_HI_MASK		(1<<0)
4694  #define DSPHOWM1		(VLV_DISPLAY_BASE + 0x70068)
4695  #define   DSPFW_SR_WM1_HI_SHIFT		24
4696  #define   DSPFW_SR_WM1_HI_MASK		(3<<24) /* 2 bits for chv, 1 for vlv */
4697  #define   DSPFW_SPRITEF_WM1_HI_SHIFT	23
4698  #define   DSPFW_SPRITEF_WM1_HI_MASK	(1<<23)
4699  #define   DSPFW_SPRITEE_WM1_HI_SHIFT	22
4700  #define   DSPFW_SPRITEE_WM1_HI_MASK	(1<<22)
4701  #define   DSPFW_PLANEC_WM1_HI_SHIFT	21
4702  #define   DSPFW_PLANEC_WM1_HI_MASK	(1<<21)
4703  #define   DSPFW_SPRITED_WM1_HI_SHIFT	20
4704  #define   DSPFW_SPRITED_WM1_HI_MASK	(1<<20)
4705  #define   DSPFW_SPRITEC_WM1_HI_SHIFT	16
4706  #define   DSPFW_SPRITEC_WM1_HI_MASK	(1<<16)
4707  #define   DSPFW_PLANEB_WM1_HI_SHIFT	12
4708  #define   DSPFW_PLANEB_WM1_HI_MASK	(1<<12)
4709  #define   DSPFW_SPRITEB_WM1_HI_SHIFT	8
4710  #define   DSPFW_SPRITEB_WM1_HI_MASK	(1<<8)
4711  #define   DSPFW_SPRITEA_WM1_HI_SHIFT	4
4712  #define   DSPFW_SPRITEA_WM1_HI_MASK	(1<<4)
4713  #define   DSPFW_PLANEA_WM1_HI_SHIFT	0
4714  #define   DSPFW_PLANEA_WM1_HI_MASK	(1<<0)
4715  
4716  /* drain latency register values*/
4717  #define VLV_DDL(pipe)			(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
4718  #define DDL_CURSOR_SHIFT		24
4719  #define DDL_SPRITE_SHIFT(sprite)	(8+8*(sprite))
4720  #define DDL_PLANE_SHIFT			0
4721  #define DDL_PRECISION_HIGH		(1<<7)
4722  #define DDL_PRECISION_LOW		(0<<7)
4723  #define DRAIN_LATENCY_MASK		0x7f
4724  
4725  #define CBR1_VLV			(VLV_DISPLAY_BASE + 0x70400)
4726  #define  CBR_PND_DEADLINE_DISABLE	(1<<31)
4727  #define  CBR_PWM_CLOCK_MUX_SELECT	(1<<30)
4728  
4729  /* FIFO watermark sizes etc */
4730  #define G4X_FIFO_LINE_SIZE	64
4731  #define I915_FIFO_LINE_SIZE	64
4732  #define I830_FIFO_LINE_SIZE	32
4733  
4734  #define VALLEYVIEW_FIFO_SIZE	255
4735  #define G4X_FIFO_SIZE		127
4736  #define I965_FIFO_SIZE		512
4737  #define I945_FIFO_SIZE		127
4738  #define I915_FIFO_SIZE		95
4739  #define I855GM_FIFO_SIZE	127 /* In cachelines */
4740  #define I830_FIFO_SIZE		95
4741  
4742  #define VALLEYVIEW_MAX_WM	0xff
4743  #define G4X_MAX_WM		0x3f
4744  #define I915_MAX_WM		0x3f
4745  
4746  #define PINEVIEW_DISPLAY_FIFO	512 /* in 64byte unit */
4747  #define PINEVIEW_FIFO_LINE_SIZE	64
4748  #define PINEVIEW_MAX_WM		0x1ff
4749  #define PINEVIEW_DFT_WM		0x3f
4750  #define PINEVIEW_DFT_HPLLOFF_WM	0
4751  #define PINEVIEW_GUARD_WM		10
4752  #define PINEVIEW_CURSOR_FIFO		64
4753  #define PINEVIEW_CURSOR_MAX_WM	0x3f
4754  #define PINEVIEW_CURSOR_DFT_WM	0
4755  #define PINEVIEW_CURSOR_GUARD_WM	5
4756  
4757  #define VALLEYVIEW_CURSOR_MAX_WM 64
4758  #define I965_CURSOR_FIFO	64
4759  #define I965_CURSOR_MAX_WM	32
4760  #define I965_CURSOR_DFT_WM	8
4761  
4762  /* Watermark register definitions for SKL */
4763  #define CUR_WM_A_0		0x70140
4764  #define CUR_WM_B_0		0x71140
4765  #define PLANE_WM_1_A_0		0x70240
4766  #define PLANE_WM_1_B_0		0x71240
4767  #define PLANE_WM_2_A_0		0x70340
4768  #define PLANE_WM_2_B_0		0x71340
4769  #define PLANE_WM_TRANS_1_A_0	0x70268
4770  #define PLANE_WM_TRANS_1_B_0	0x71268
4771  #define PLANE_WM_TRANS_2_A_0	0x70368
4772  #define PLANE_WM_TRANS_2_B_0	0x71368
4773  #define CUR_WM_TRANS_A_0	0x70168
4774  #define CUR_WM_TRANS_B_0	0x71168
4775  #define   PLANE_WM_EN		(1 << 31)
4776  #define   PLANE_WM_LINES_SHIFT	14
4777  #define   PLANE_WM_LINES_MASK	0x1f
4778  #define   PLANE_WM_BLOCKS_MASK	0x3ff
4779  
4780  #define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0)
4781  #define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level)))
4782  #define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0)
4783  
4784  #define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0)
4785  #define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0)
4786  #define _PLANE_WM_BASE(pipe, plane)	\
4787  			_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
4788  #define PLANE_WM(pipe, plane, level)	\
4789  			(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
4790  #define _PLANE_WM_TRANS_1(pipe)	\
4791  			_PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0)
4792  #define _PLANE_WM_TRANS_2(pipe)	\
4793  			_PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0)
4794  #define PLANE_WM_TRANS(pipe, plane)	\
4795  		_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))
4796  
4797  /* define the Watermark register on Ironlake */
4798  #define WM0_PIPEA_ILK		0x45100
4799  #define  WM0_PIPE_PLANE_MASK	(0xffff<<16)
4800  #define  WM0_PIPE_PLANE_SHIFT	16
4801  #define  WM0_PIPE_SPRITE_MASK	(0xff<<8)
4802  #define  WM0_PIPE_SPRITE_SHIFT	8
4803  #define  WM0_PIPE_CURSOR_MASK	(0xff)
4804  
4805  #define WM0_PIPEB_ILK		0x45104
4806  #define WM0_PIPEC_IVB		0x45200
4807  #define WM1_LP_ILK		0x45108
4808  #define  WM1_LP_SR_EN		(1<<31)
4809  #define  WM1_LP_LATENCY_SHIFT	24
4810  #define  WM1_LP_LATENCY_MASK	(0x7f<<24)
4811  #define  WM1_LP_FBC_MASK	(0xf<<20)
4812  #define  WM1_LP_FBC_SHIFT	20
4813  #define  WM1_LP_FBC_SHIFT_BDW	19
4814  #define  WM1_LP_SR_MASK		(0x7ff<<8)
4815  #define  WM1_LP_SR_SHIFT	8
4816  #define  WM1_LP_CURSOR_MASK	(0xff)
4817  #define WM2_LP_ILK		0x4510c
4818  #define  WM2_LP_EN		(1<<31)
4819  #define WM3_LP_ILK		0x45110
4820  #define  WM3_LP_EN		(1<<31)
4821  #define WM1S_LP_ILK		0x45120
4822  #define WM2S_LP_IVB		0x45124
4823  #define WM3S_LP_IVB		0x45128
4824  #define  WM1S_LP_EN		(1<<31)
4825  
4826  #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
4827  	(WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
4828  	 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
4829  
4830  /* Memory latency timer register */
4831  #define MLTR_ILK		0x11222
4832  #define  MLTR_WM1_SHIFT		0
4833  #define  MLTR_WM2_SHIFT		8
4834  /* the unit of memory self-refresh latency time is 0.5us */
4835  #define  ILK_SRLT_MASK		0x3f
4836  
4837  
4838  /* the address where we get all kinds of latency value */
4839  #define SSKPD			0x5d10
4840  #define SSKPD_WM_MASK		0x3f
4841  #define SSKPD_WM0_SHIFT		0
4842  #define SSKPD_WM1_SHIFT		8
4843  #define SSKPD_WM2_SHIFT		16
4844  #define SSKPD_WM3_SHIFT		24
4845  
4846  /*
4847   * The two pipe frame counter registers are not synchronized, so
4848   * reading a stable value is somewhat tricky. The following code
4849   * should work:
4850   *
4851   *  do {
4852   *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4853   *             PIPE_FRAME_HIGH_SHIFT;
4854   *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
4855   *             PIPE_FRAME_LOW_SHIFT);
4856   *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4857   *             PIPE_FRAME_HIGH_SHIFT);
4858   *  } while (high1 != high2);
4859   *  frame = (high1 << 8) | low1;
4860   */
4861  #define _PIPEAFRAMEHIGH          0x70040
4862  #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
4863  #define   PIPE_FRAME_HIGH_SHIFT   0
4864  #define _PIPEAFRAMEPIXEL         0x70044
4865  #define   PIPE_FRAME_LOW_MASK     0xff000000
4866  #define   PIPE_FRAME_LOW_SHIFT    24
4867  #define   PIPE_PIXEL_MASK         0x00ffffff
4868  #define   PIPE_PIXEL_SHIFT        0
4869  /* GM45+ just has to be different */
4870  #define _PIPEA_FRMCOUNT_G4X	0x70040
4871  #define _PIPEA_FLIPCOUNT_G4X	0x70044
4872  #define PIPE_FRMCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
4873  #define PIPE_FLIPCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
4874  
4875  /* Cursor A & B regs */
4876  #define _CURACNTR		0x70080
4877  /* Old style CUR*CNTR flags (desktop 8xx) */
4878  #define   CURSOR_ENABLE		0x80000000
4879  #define   CURSOR_GAMMA_ENABLE	0x40000000
4880  #define   CURSOR_STRIDE_SHIFT	28
4881  #define   CURSOR_STRIDE(x)	((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
4882  #define   CURSOR_PIPE_CSC_ENABLE (1<<24)
4883  #define   CURSOR_FORMAT_SHIFT	24
4884  #define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
4885  #define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
4886  #define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
4887  #define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)
4888  #define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
4889  #define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
4890  /* New style CUR*CNTR flags */
4891  #define   CURSOR_MODE		0x27
4892  #define   CURSOR_MODE_DISABLE   0x00
4893  #define   CURSOR_MODE_128_32B_AX 0x02
4894  #define   CURSOR_MODE_256_32B_AX 0x03
4895  #define   CURSOR_MODE_64_32B_AX 0x07
4896  #define   CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
4897  #define   CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
4898  #define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
4899  #define   MCURSOR_PIPE_SELECT	(1 << 28)
4900  #define   MCURSOR_PIPE_A	0x00
4901  #define   MCURSOR_PIPE_B	(1 << 28)
4902  #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
4903  #define   CURSOR_ROTATE_180	(1<<15)
4904  #define   CURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
4905  #define _CURABASE		0x70084
4906  #define _CURAPOS		0x70088
4907  #define   CURSOR_POS_MASK       0x007FF
4908  #define   CURSOR_POS_SIGN       0x8000
4909  #define   CURSOR_X_SHIFT        0
4910  #define   CURSOR_Y_SHIFT        16
4911  #define CURSIZE			0x700a0
4912  #define _CURBCNTR		0x700c0
4913  #define _CURBBASE		0x700c4
4914  #define _CURBPOS		0x700c8
4915  
4916  #define _CURBCNTR_IVB		0x71080
4917  #define _CURBBASE_IVB		0x71084
4918  #define _CURBPOS_IVB		0x71088
4919  
4920  #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
4921  	dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
4922  	dev_priv->info.display_mmio_offset)
4923  
4924  #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
4925  #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
4926  #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
4927  
4928  #define CURSOR_A_OFFSET 0x70080
4929  #define CURSOR_B_OFFSET 0x700c0
4930  #define CHV_CURSOR_C_OFFSET 0x700e0
4931  #define IVB_CURSOR_B_OFFSET 0x71080
4932  #define IVB_CURSOR_C_OFFSET 0x72080
4933  
4934  /* Display A control */
4935  #define _DSPACNTR				0x70180
4936  #define   DISPLAY_PLANE_ENABLE			(1<<31)
4937  #define   DISPLAY_PLANE_DISABLE			0
4938  #define   DISPPLANE_GAMMA_ENABLE		(1<<30)
4939  #define   DISPPLANE_GAMMA_DISABLE		0
4940  #define   DISPPLANE_PIXFORMAT_MASK		(0xf<<26)
4941  #define   DISPPLANE_YUV422			(0x0<<26)
4942  #define   DISPPLANE_8BPP			(0x2<<26)
4943  #define   DISPPLANE_BGRA555			(0x3<<26)
4944  #define   DISPPLANE_BGRX555			(0x4<<26)
4945  #define   DISPPLANE_BGRX565			(0x5<<26)
4946  #define   DISPPLANE_BGRX888			(0x6<<26)
4947  #define   DISPPLANE_BGRA888			(0x7<<26)
4948  #define   DISPPLANE_RGBX101010			(0x8<<26)
4949  #define   DISPPLANE_RGBA101010			(0x9<<26)
4950  #define   DISPPLANE_BGRX101010			(0xa<<26)
4951  #define   DISPPLANE_RGBX161616			(0xc<<26)
4952  #define   DISPPLANE_RGBX888			(0xe<<26)
4953  #define   DISPPLANE_RGBA888			(0xf<<26)
4954  #define   DISPPLANE_STEREO_ENABLE		(1<<25)
4955  #define   DISPPLANE_STEREO_DISABLE		0
4956  #define   DISPPLANE_PIPE_CSC_ENABLE		(1<<24)
4957  #define   DISPPLANE_SEL_PIPE_SHIFT		24
4958  #define   DISPPLANE_SEL_PIPE_MASK		(3<<DISPPLANE_SEL_PIPE_SHIFT)
4959  #define   DISPPLANE_SEL_PIPE_A			0
4960  #define   DISPPLANE_SEL_PIPE_B			(1<<DISPPLANE_SEL_PIPE_SHIFT)
4961  #define   DISPPLANE_SRC_KEY_ENABLE		(1<<22)
4962  #define   DISPPLANE_SRC_KEY_DISABLE		0
4963  #define   DISPPLANE_LINE_DOUBLE			(1<<20)
4964  #define   DISPPLANE_NO_LINE_DOUBLE		0
4965  #define   DISPPLANE_STEREO_POLARITY_FIRST	0
4966  #define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
4967  #define   DISPPLANE_ALPHA_PREMULTIPLY		(1<<16) /* CHV pipe B */
4968  #define   DISPPLANE_ROTATE_180			(1<<15)
4969  #define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* Ironlake */
4970  #define   DISPPLANE_TILED			(1<<10)
4971  #define   DISPPLANE_MIRROR			(1<<8) /* CHV pipe B */
4972  #define _DSPAADDR				0x70184
4973  #define _DSPASTRIDE				0x70188
4974  #define _DSPAPOS				0x7018C /* reserved */
4975  #define _DSPASIZE				0x70190
4976  #define _DSPASURF				0x7019C /* 965+ only */
4977  #define _DSPATILEOFF				0x701A4 /* 965+ only */
4978  #define _DSPAOFFSET				0x701A4 /* HSW */
4979  #define _DSPASURFLIVE				0x701AC
4980  
4981  #define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
4982  #define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
4983  #define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
4984  #define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
4985  #define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
4986  #define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
4987  #define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
4988  #define DSPLINOFF(plane) DSPADDR(plane)
4989  #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
4990  #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
4991  
4992  /* CHV pipe B blender and primary plane */
4993  #define _CHV_BLEND_A		0x60a00
4994  #define   CHV_BLEND_LEGACY		(0<<30)
4995  #define   CHV_BLEND_ANDROID		(1<<30)
4996  #define   CHV_BLEND_MPO			(2<<30)
4997  #define   CHV_BLEND_MASK		(3<<30)
4998  #define _CHV_CANVAS_A		0x60a04
4999  #define _PRIMPOS_A		0x60a08
5000  #define _PRIMSIZE_A		0x60a0c
5001  #define _PRIMCNSTALPHA_A	0x60a10
5002  #define   PRIM_CONST_ALPHA_ENABLE	(1<<31)
5003  
5004  #define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
5005  #define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
5006  #define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
5007  #define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
5008  #define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
5009  
5010  /* Display/Sprite base address macros */
5011  #define DISP_BASEADDR_MASK	(0xfffff000)
5012  #define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)
5013  #define I915_HI_DISPBASE(val)	(val & DISP_BASEADDR_MASK)
5014  
5015  /*
5016   * VBIOS flags
5017   * gen2:
5018   * [00:06] alm,mgm
5019   * [10:16] all
5020   * [30:32] alm,mgm
5021   * gen3+:
5022   * [00:0f] all
5023   * [10:1f] all
5024   * [30:32] all
5025   */
5026  #define SWF0(i)	(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
5027  #define SWF1(i)	(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
5028  #define SWF3(i)	(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
5029  
5030  /* Pipe B */
5031  #define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
5032  #define _PIPEBCONF		(dev_priv->info.display_mmio_offset + 0x71008)
5033  #define _PIPEBSTAT		(dev_priv->info.display_mmio_offset + 0x71024)
5034  #define _PIPEBFRAMEHIGH		0x71040
5035  #define _PIPEBFRAMEPIXEL	0x71044
5036  #define _PIPEB_FRMCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71040)
5037  #define _PIPEB_FLIPCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71044)
5038  
5039  
5040  /* Display B control */
5041  #define _DSPBCNTR		(dev_priv->info.display_mmio_offset + 0x71180)
5042  #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
5043  #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
5044  #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
5045  #define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
5046  #define _DSPBADDR		(dev_priv->info.display_mmio_offset + 0x71184)
5047  #define _DSPBSTRIDE		(dev_priv->info.display_mmio_offset + 0x71188)
5048  #define _DSPBPOS		(dev_priv->info.display_mmio_offset + 0x7118C)
5049  #define _DSPBSIZE		(dev_priv->info.display_mmio_offset + 0x71190)
5050  #define _DSPBSURF		(dev_priv->info.display_mmio_offset + 0x7119C)
5051  #define _DSPBTILEOFF		(dev_priv->info.display_mmio_offset + 0x711A4)
5052  #define _DSPBOFFSET		(dev_priv->info.display_mmio_offset + 0x711A4)
5053  #define _DSPBSURFLIVE		(dev_priv->info.display_mmio_offset + 0x711AC)
5054  
5055  /* Sprite A control */
5056  #define _DVSACNTR		0x72180
5057  #define   DVS_ENABLE		(1<<31)
5058  #define   DVS_GAMMA_ENABLE	(1<<30)
5059  #define   DVS_PIXFORMAT_MASK	(3<<25)
5060  #define   DVS_FORMAT_YUV422	(0<<25)
5061  #define   DVS_FORMAT_RGBX101010	(1<<25)
5062  #define   DVS_FORMAT_RGBX888	(2<<25)
5063  #define   DVS_FORMAT_RGBX161616	(3<<25)
5064  #define   DVS_PIPE_CSC_ENABLE   (1<<24)
5065  #define   DVS_SOURCE_KEY	(1<<22)
5066  #define   DVS_RGB_ORDER_XBGR	(1<<20)
5067  #define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
5068  #define   DVS_YUV_ORDER_YUYV	(0<<16)
5069  #define   DVS_YUV_ORDER_UYVY	(1<<16)
5070  #define   DVS_YUV_ORDER_YVYU	(2<<16)
5071  #define   DVS_YUV_ORDER_VYUY	(3<<16)
5072  #define   DVS_ROTATE_180	(1<<15)
5073  #define   DVS_DEST_KEY		(1<<2)
5074  #define   DVS_TRICKLE_FEED_DISABLE (1<<14)
5075  #define   DVS_TILED		(1<<10)
5076  #define _DVSALINOFF		0x72184
5077  #define _DVSASTRIDE		0x72188
5078  #define _DVSAPOS		0x7218c
5079  #define _DVSASIZE		0x72190
5080  #define _DVSAKEYVAL		0x72194
5081  #define _DVSAKEYMSK		0x72198
5082  #define _DVSASURF		0x7219c
5083  #define _DVSAKEYMAXVAL		0x721a0
5084  #define _DVSATILEOFF		0x721a4
5085  #define _DVSASURFLIVE		0x721ac
5086  #define _DVSASCALE		0x72204
5087  #define   DVS_SCALE_ENABLE	(1<<31)
5088  #define   DVS_FILTER_MASK	(3<<29)
5089  #define   DVS_FILTER_MEDIUM	(0<<29)
5090  #define   DVS_FILTER_ENHANCING	(1<<29)
5091  #define   DVS_FILTER_SOFTENING	(2<<29)
5092  #define   DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
5093  #define   DVS_VERTICAL_OFFSET_ENABLE (1<<27)
5094  #define _DVSAGAMC		0x72300
5095  
5096  #define _DVSBCNTR		0x73180
5097  #define _DVSBLINOFF		0x73184
5098  #define _DVSBSTRIDE		0x73188
5099  #define _DVSBPOS		0x7318c
5100  #define _DVSBSIZE		0x73190
5101  #define _DVSBKEYVAL		0x73194
5102  #define _DVSBKEYMSK		0x73198
5103  #define _DVSBSURF		0x7319c
5104  #define _DVSBKEYMAXVAL		0x731a0
5105  #define _DVSBTILEOFF		0x731a4
5106  #define _DVSBSURFLIVE		0x731ac
5107  #define _DVSBSCALE		0x73204
5108  #define _DVSBGAMC		0x73300
5109  
5110  #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
5111  #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
5112  #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
5113  #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
5114  #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
5115  #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
5116  #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
5117  #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
5118  #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
5119  #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
5120  #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
5121  #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
5122  
5123  #define _SPRA_CTL		0x70280
5124  #define   SPRITE_ENABLE			(1<<31)
5125  #define   SPRITE_GAMMA_ENABLE		(1<<30)
5126  #define   SPRITE_PIXFORMAT_MASK		(7<<25)
5127  #define   SPRITE_FORMAT_YUV422		(0<<25)
5128  #define   SPRITE_FORMAT_RGBX101010	(1<<25)
5129  #define   SPRITE_FORMAT_RGBX888		(2<<25)
5130  #define   SPRITE_FORMAT_RGBX161616	(3<<25)
5131  #define   SPRITE_FORMAT_YUV444		(4<<25)
5132  #define   SPRITE_FORMAT_XR_BGR101010	(5<<25) /* Extended range */
5133  #define   SPRITE_PIPE_CSC_ENABLE	(1<<24)
5134  #define   SPRITE_SOURCE_KEY		(1<<22)
5135  #define   SPRITE_RGB_ORDER_RGBX		(1<<20) /* only for 888 and 161616 */
5136  #define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1<<19)
5137  #define   SPRITE_YUV_CSC_FORMAT_BT709	(1<<18) /* 0 is BT601 */
5138  #define   SPRITE_YUV_BYTE_ORDER_MASK	(3<<16)
5139  #define   SPRITE_YUV_ORDER_YUYV		(0<<16)
5140  #define   SPRITE_YUV_ORDER_UYVY		(1<<16)
5141  #define   SPRITE_YUV_ORDER_YVYU		(2<<16)
5142  #define   SPRITE_YUV_ORDER_VYUY		(3<<16)
5143  #define   SPRITE_ROTATE_180		(1<<15)
5144  #define   SPRITE_TRICKLE_FEED_DISABLE	(1<<14)
5145  #define   SPRITE_INT_GAMMA_ENABLE	(1<<13)
5146  #define   SPRITE_TILED			(1<<10)
5147  #define   SPRITE_DEST_KEY		(1<<2)
5148  #define _SPRA_LINOFF		0x70284
5149  #define _SPRA_STRIDE		0x70288
5150  #define _SPRA_POS		0x7028c
5151  #define _SPRA_SIZE		0x70290
5152  #define _SPRA_KEYVAL		0x70294
5153  #define _SPRA_KEYMSK		0x70298
5154  #define _SPRA_SURF		0x7029c
5155  #define _SPRA_KEYMAX		0x702a0
5156  #define _SPRA_TILEOFF		0x702a4
5157  #define _SPRA_OFFSET		0x702a4
5158  #define _SPRA_SURFLIVE		0x702ac
5159  #define _SPRA_SCALE		0x70304
5160  #define   SPRITE_SCALE_ENABLE	(1<<31)
5161  #define   SPRITE_FILTER_MASK	(3<<29)
5162  #define   SPRITE_FILTER_MEDIUM	(0<<29)
5163  #define   SPRITE_FILTER_ENHANCING	(1<<29)
5164  #define   SPRITE_FILTER_SOFTENING	(2<<29)
5165  #define   SPRITE_VERTICAL_OFFSET_HALF	(1<<28) /* must be enabled below */
5166  #define   SPRITE_VERTICAL_OFFSET_ENABLE	(1<<27)
5167  #define _SPRA_GAMC		0x70400
5168  
5169  #define _SPRB_CTL		0x71280
5170  #define _SPRB_LINOFF		0x71284
5171  #define _SPRB_STRIDE		0x71288
5172  #define _SPRB_POS		0x7128c
5173  #define _SPRB_SIZE		0x71290
5174  #define _SPRB_KEYVAL		0x71294
5175  #define _SPRB_KEYMSK		0x71298
5176  #define _SPRB_SURF		0x7129c
5177  #define _SPRB_KEYMAX		0x712a0
5178  #define _SPRB_TILEOFF		0x712a4
5179  #define _SPRB_OFFSET		0x712a4
5180  #define _SPRB_SURFLIVE		0x712ac
5181  #define _SPRB_SCALE		0x71304
5182  #define _SPRB_GAMC		0x71400
5183  
5184  #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
5185  #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
5186  #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
5187  #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
5188  #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
5189  #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
5190  #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
5191  #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
5192  #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
5193  #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
5194  #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
5195  #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
5196  #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
5197  #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
5198  
5199  #define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
5200  #define   SP_ENABLE			(1<<31)
5201  #define   SP_GAMMA_ENABLE		(1<<30)
5202  #define   SP_PIXFORMAT_MASK		(0xf<<26)
5203  #define   SP_FORMAT_YUV422		(0<<26)
5204  #define   SP_FORMAT_BGR565		(5<<26)
5205  #define   SP_FORMAT_BGRX8888		(6<<26)
5206  #define   SP_FORMAT_BGRA8888		(7<<26)
5207  #define   SP_FORMAT_RGBX1010102		(8<<26)
5208  #define   SP_FORMAT_RGBA1010102		(9<<26)
5209  #define   SP_FORMAT_RGBX8888		(0xe<<26)
5210  #define   SP_FORMAT_RGBA8888		(0xf<<26)
5211  #define   SP_ALPHA_PREMULTIPLY		(1<<23) /* CHV pipe B */
5212  #define   SP_SOURCE_KEY			(1<<22)
5213  #define   SP_YUV_BYTE_ORDER_MASK	(3<<16)
5214  #define   SP_YUV_ORDER_YUYV		(0<<16)
5215  #define   SP_YUV_ORDER_UYVY		(1<<16)
5216  #define   SP_YUV_ORDER_YVYU		(2<<16)
5217  #define   SP_YUV_ORDER_VYUY		(3<<16)
5218  #define   SP_ROTATE_180			(1<<15)
5219  #define   SP_TILED			(1<<10)
5220  #define   SP_MIRROR			(1<<8) /* CHV pipe B */
5221  #define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
5222  #define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
5223  #define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
5224  #define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
5225  #define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
5226  #define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
5227  #define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
5228  #define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
5229  #define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
5230  #define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
5231  #define   SP_CONST_ALPHA_ENABLE		(1<<31)
5232  #define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721f4)
5233  
5234  #define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
5235  #define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
5236  #define _SPBSTRIDE		(VLV_DISPLAY_BASE + 0x72288)
5237  #define _SPBPOS			(VLV_DISPLAY_BASE + 0x7228c)
5238  #define _SPBSIZE		(VLV_DISPLAY_BASE + 0x72290)
5239  #define _SPBKEYMINVAL		(VLV_DISPLAY_BASE + 0x72294)
5240  #define _SPBKEYMSK		(VLV_DISPLAY_BASE + 0x72298)
5241  #define _SPBSURF		(VLV_DISPLAY_BASE + 0x7229c)
5242  #define _SPBKEYMAXVAL		(VLV_DISPLAY_BASE + 0x722a0)
5243  #define _SPBTILEOFF		(VLV_DISPLAY_BASE + 0x722a4)
5244  #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
5245  #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
5246  
5247  #define SPCNTR(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
5248  #define SPLINOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
5249  #define SPSTRIDE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
5250  #define SPPOS(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
5251  #define SPSIZE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
5252  #define SPKEYMINVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
5253  #define SPKEYMSK(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
5254  #define SPSURF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
5255  #define SPKEYMAXVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
5256  #define SPTILEOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
5257  #define SPCONSTALPHA(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
5258  #define SPGAMC(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
5259  
5260  /*
5261   * CHV pipe B sprite CSC
5262   *
5263   * |cr|   |c0 c1 c2|   |cr + cr_ioff|   |cr_ooff|
5264   * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
5265   * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
5266   */
5267  #define SPCSCYGOFF(sprite)	(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
5268  #define SPCSCCBOFF(sprite)	(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
5269  #define SPCSCCROFF(sprite)	(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
5270  #define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11 */
5271  #define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
5272  
5273  #define SPCSCC01(sprite)	(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
5274  #define SPCSCC23(sprite)	(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
5275  #define SPCSCC45(sprite)	(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
5276  #define SPCSCC67(sprite)	(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
5277  #define SPCSCC8(sprite)		(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
5278  #define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12 */
5279  #define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12 */
5280  
5281  #define SPCSCYGICLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
5282  #define SPCSCCBICLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
5283  #define SPCSCCRICLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
5284  #define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11 */
5285  #define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
5286  
5287  #define SPCSCYGOCLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
5288  #define SPCSCCBOCLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
5289  #define SPCSCCROCLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
5290  #define  SPCSC_OMAX(x)		((x) << 16) /* u10 */
5291  #define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
5292  
5293  /* Skylake plane registers */
5294  
5295  #define _PLANE_CTL_1_A				0x70180
5296  #define _PLANE_CTL_2_A				0x70280
5297  #define _PLANE_CTL_3_A				0x70380
5298  #define   PLANE_CTL_ENABLE			(1 << 31)
5299  #define   PLANE_CTL_PIPE_GAMMA_ENABLE		(1 << 30)
5300  #define   PLANE_CTL_FORMAT_MASK			(0xf << 24)
5301  #define   PLANE_CTL_FORMAT_YUV422		(  0 << 24)
5302  #define   PLANE_CTL_FORMAT_NV12			(  1 << 24)
5303  #define   PLANE_CTL_FORMAT_XRGB_2101010		(  2 << 24)
5304  #define   PLANE_CTL_FORMAT_XRGB_8888		(  4 << 24)
5305  #define   PLANE_CTL_FORMAT_XRGB_16161616F	(  6 << 24)
5306  #define   PLANE_CTL_FORMAT_AYUV			(  8 << 24)
5307  #define   PLANE_CTL_FORMAT_INDEXED		( 12 << 24)
5308  #define   PLANE_CTL_FORMAT_RGB_565		( 14 << 24)
5309  #define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23)
5310  #define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
5311  #define   PLANE_CTL_KEY_ENABLE_SOURCE		(  1 << 21)
5312  #define   PLANE_CTL_KEY_ENABLE_DESTINATION	(  2 << 21)
5313  #define   PLANE_CTL_ORDER_BGRX			(0 << 20)
5314  #define   PLANE_CTL_ORDER_RGBX			(1 << 20)
5315  #define   PLANE_CTL_YUV422_ORDER_MASK		(0x3 << 16)
5316  #define   PLANE_CTL_YUV422_YUYV			(  0 << 16)
5317  #define   PLANE_CTL_YUV422_UYVY			(  1 << 16)
5318  #define   PLANE_CTL_YUV422_YVYU			(  2 << 16)
5319  #define   PLANE_CTL_YUV422_VYUY			(  3 << 16)
5320  #define   PLANE_CTL_DECOMPRESSION_ENABLE	(1 << 15)
5321  #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
5322  #define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13)
5323  #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
5324  #define   PLANE_CTL_TILED_LINEAR		(  0 << 10)
5325  #define   PLANE_CTL_TILED_X			(  1 << 10)
5326  #define   PLANE_CTL_TILED_Y			(  4 << 10)
5327  #define   PLANE_CTL_TILED_YF			(  5 << 10)
5328  #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4)
5329  #define   PLANE_CTL_ALPHA_DISABLE		(  0 << 4)
5330  #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(  2 << 4)
5331  #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY	(  3 << 4)
5332  #define   PLANE_CTL_ROTATE_MASK			0x3
5333  #define   PLANE_CTL_ROTATE_0			0x0
5334  #define   PLANE_CTL_ROTATE_90			0x1
5335  #define   PLANE_CTL_ROTATE_180			0x2
5336  #define   PLANE_CTL_ROTATE_270			0x3
5337  #define _PLANE_STRIDE_1_A			0x70188
5338  #define _PLANE_STRIDE_2_A			0x70288
5339  #define _PLANE_STRIDE_3_A			0x70388
5340  #define _PLANE_POS_1_A				0x7018c
5341  #define _PLANE_POS_2_A				0x7028c
5342  #define _PLANE_POS_3_A				0x7038c
5343  #define _PLANE_SIZE_1_A				0x70190
5344  #define _PLANE_SIZE_2_A				0x70290
5345  #define _PLANE_SIZE_3_A				0x70390
5346  #define _PLANE_SURF_1_A				0x7019c
5347  #define _PLANE_SURF_2_A				0x7029c
5348  #define _PLANE_SURF_3_A				0x7039c
5349  #define _PLANE_OFFSET_1_A			0x701a4
5350  #define _PLANE_OFFSET_2_A			0x702a4
5351  #define _PLANE_OFFSET_3_A			0x703a4
5352  #define _PLANE_KEYVAL_1_A			0x70194
5353  #define _PLANE_KEYVAL_2_A			0x70294
5354  #define _PLANE_KEYMSK_1_A			0x70198
5355  #define _PLANE_KEYMSK_2_A			0x70298
5356  #define _PLANE_KEYMAX_1_A			0x701a0
5357  #define _PLANE_KEYMAX_2_A			0x702a0
5358  #define _PLANE_BUF_CFG_1_A			0x7027c
5359  #define _PLANE_BUF_CFG_2_A			0x7037c
5360  #define _PLANE_NV12_BUF_CFG_1_A		0x70278
5361  #define _PLANE_NV12_BUF_CFG_2_A		0x70378
5362  
5363  #define _PLANE_CTL_1_B				0x71180
5364  #define _PLANE_CTL_2_B				0x71280
5365  #define _PLANE_CTL_3_B				0x71380
5366  #define _PLANE_CTL_1(pipe)	_PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
5367  #define _PLANE_CTL_2(pipe)	_PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
5368  #define _PLANE_CTL_3(pipe)	_PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
5369  #define PLANE_CTL(pipe, plane)	\
5370  	_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
5371  
5372  #define _PLANE_STRIDE_1_B			0x71188
5373  #define _PLANE_STRIDE_2_B			0x71288
5374  #define _PLANE_STRIDE_3_B			0x71388
5375  #define _PLANE_STRIDE_1(pipe)	\
5376  	_PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
5377  #define _PLANE_STRIDE_2(pipe)	\
5378  	_PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
5379  #define _PLANE_STRIDE_3(pipe)	\
5380  	_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
5381  #define PLANE_STRIDE(pipe, plane)	\
5382  	_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
5383  
5384  #define _PLANE_POS_1_B				0x7118c
5385  #define _PLANE_POS_2_B				0x7128c
5386  #define _PLANE_POS_3_B				0x7138c
5387  #define _PLANE_POS_1(pipe)	_PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
5388  #define _PLANE_POS_2(pipe)	_PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
5389  #define _PLANE_POS_3(pipe)	_PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
5390  #define PLANE_POS(pipe, plane)	\
5391  	_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
5392  
5393  #define _PLANE_SIZE_1_B				0x71190
5394  #define _PLANE_SIZE_2_B				0x71290
5395  #define _PLANE_SIZE_3_B				0x71390
5396  #define _PLANE_SIZE_1(pipe)	_PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
5397  #define _PLANE_SIZE_2(pipe)	_PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
5398  #define _PLANE_SIZE_3(pipe)	_PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
5399  #define PLANE_SIZE(pipe, plane)	\
5400  	_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
5401  
5402  #define _PLANE_SURF_1_B				0x7119c
5403  #define _PLANE_SURF_2_B				0x7129c
5404  #define _PLANE_SURF_3_B				0x7139c
5405  #define _PLANE_SURF_1(pipe)	_PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
5406  #define _PLANE_SURF_2(pipe)	_PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
5407  #define _PLANE_SURF_3(pipe)	_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
5408  #define PLANE_SURF(pipe, plane)	\
5409  	_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
5410  
5411  #define _PLANE_OFFSET_1_B			0x711a4
5412  #define _PLANE_OFFSET_2_B			0x712a4
5413  #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
5414  #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
5415  #define PLANE_OFFSET(pipe, plane)	\
5416  	_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
5417  
5418  #define _PLANE_KEYVAL_1_B			0x71194
5419  #define _PLANE_KEYVAL_2_B			0x71294
5420  #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
5421  #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
5422  #define PLANE_KEYVAL(pipe, plane)	\
5423  	_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
5424  
5425  #define _PLANE_KEYMSK_1_B			0x71198
5426  #define _PLANE_KEYMSK_2_B			0x71298
5427  #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
5428  #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
5429  #define PLANE_KEYMSK(pipe, plane)	\
5430  	_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
5431  
5432  #define _PLANE_KEYMAX_1_B			0x711a0
5433  #define _PLANE_KEYMAX_2_B			0x712a0
5434  #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
5435  #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
5436  #define PLANE_KEYMAX(pipe, plane)	\
5437  	_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
5438  
5439  #define _PLANE_BUF_CFG_1_B			0x7127c
5440  #define _PLANE_BUF_CFG_2_B			0x7137c
5441  #define _PLANE_BUF_CFG_1(pipe)	\
5442  	_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
5443  #define _PLANE_BUF_CFG_2(pipe)	\
5444  	_PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
5445  #define PLANE_BUF_CFG(pipe, plane)	\
5446  	_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
5447  
5448  #define _PLANE_NV12_BUF_CFG_1_B		0x71278
5449  #define _PLANE_NV12_BUF_CFG_2_B		0x71378
5450  #define _PLANE_NV12_BUF_CFG_1(pipe)	\
5451  	_PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
5452  #define _PLANE_NV12_BUF_CFG_2(pipe)	\
5453  	_PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
5454  #define PLANE_NV12_BUF_CFG(pipe, plane)	\
5455  	_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
5456  
5457  /* SKL new cursor registers */
5458  #define _CUR_BUF_CFG_A				0x7017c
5459  #define _CUR_BUF_CFG_B				0x7117c
5460  #define CUR_BUF_CFG(pipe)	_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
5461  
5462  /* VBIOS regs */
5463  #define VGACNTRL		0x71400
5464  # define VGA_DISP_DISABLE			(1 << 31)
5465  # define VGA_2X_MODE				(1 << 30)
5466  # define VGA_PIPE_B_SELECT			(1 << 29)
5467  
5468  #define VLV_VGACNTRL		(VLV_DISPLAY_BASE + 0x71400)
5469  
5470  /* Ironlake */
5471  
5472  #define CPU_VGACNTRL	0x41000
5473  
5474  #define DIGITAL_PORT_HOTPLUG_CNTRL	0x44030
5475  #define  DIGITAL_PORTA_HOTPLUG_ENABLE		(1 << 4)
5476  #define  DIGITAL_PORTA_PULSE_DURATION_2ms	(0 << 2) /* pre-HSW */
5477  #define  DIGITAL_PORTA_PULSE_DURATION_4_5ms	(1 << 2) /* pre-HSW */
5478  #define  DIGITAL_PORTA_PULSE_DURATION_6ms	(2 << 2) /* pre-HSW */
5479  #define  DIGITAL_PORTA_PULSE_DURATION_100ms	(3 << 2) /* pre-HSW */
5480  #define  DIGITAL_PORTA_PULSE_DURATION_MASK	(3 << 2) /* pre-HSW */
5481  #define  DIGITAL_PORTA_HOTPLUG_STATUS_MASK	(3 << 0)
5482  #define  DIGITAL_PORTA_HOTPLUG_NO_DETECT	(0 << 0)
5483  #define  DIGITAL_PORTA_HOTPLUG_SHORT_DETECT	(1 << 0)
5484  #define  DIGITAL_PORTA_HOTPLUG_LONG_DETECT	(2 << 0)
5485  
5486  /* refresh rate hardware control */
5487  #define RR_HW_CTL       0x45300
5488  #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
5489  #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
5490  
5491  #define FDI_PLL_BIOS_0  0x46000
5492  #define  FDI_PLL_FB_CLOCK_MASK  0xff
5493  #define FDI_PLL_BIOS_1  0x46004
5494  #define FDI_PLL_BIOS_2  0x46008
5495  #define DISPLAY_PORT_PLL_BIOS_0         0x4600c
5496  #define DISPLAY_PORT_PLL_BIOS_1         0x46010
5497  #define DISPLAY_PORT_PLL_BIOS_2         0x46014
5498  
5499  #define PCH_3DCGDIS0		0x46020
5500  # define MARIUNIT_CLOCK_GATE_DISABLE		(1 << 18)
5501  # define SVSMUNIT_CLOCK_GATE_DISABLE		(1 << 1)
5502  
5503  #define PCH_3DCGDIS1		0x46024
5504  # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
5505  
5506  #define FDI_PLL_FREQ_CTL        0x46030
5507  #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1<<24)
5508  #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
5509  #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
5510  
5511  
5512  #define _PIPEA_DATA_M1		0x60030
5513  #define  PIPE_DATA_M1_OFFSET    0
5514  #define _PIPEA_DATA_N1		0x60034
5515  #define  PIPE_DATA_N1_OFFSET    0
5516  
5517  #define _PIPEA_DATA_M2		0x60038
5518  #define  PIPE_DATA_M2_OFFSET    0
5519  #define _PIPEA_DATA_N2		0x6003c
5520  #define  PIPE_DATA_N2_OFFSET    0
5521  
5522  #define _PIPEA_LINK_M1		0x60040
5523  #define  PIPE_LINK_M1_OFFSET    0
5524  #define _PIPEA_LINK_N1		0x60044
5525  #define  PIPE_LINK_N1_OFFSET    0
5526  
5527  #define _PIPEA_LINK_M2		0x60048
5528  #define  PIPE_LINK_M2_OFFSET    0
5529  #define _PIPEA_LINK_N2		0x6004c
5530  #define  PIPE_LINK_N2_OFFSET    0
5531  
5532  /* PIPEB timing regs are same start from 0x61000 */
5533  
5534  #define _PIPEB_DATA_M1		0x61030
5535  #define _PIPEB_DATA_N1		0x61034
5536  #define _PIPEB_DATA_M2		0x61038
5537  #define _PIPEB_DATA_N2		0x6103c
5538  #define _PIPEB_LINK_M1		0x61040
5539  #define _PIPEB_LINK_N1		0x61044
5540  #define _PIPEB_LINK_M2		0x61048
5541  #define _PIPEB_LINK_N2		0x6104c
5542  
5543  #define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
5544  #define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
5545  #define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
5546  #define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
5547  #define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
5548  #define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
5549  #define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
5550  #define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
5551  
5552  /* CPU panel fitter */
5553  /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
5554  #define _PFA_CTL_1               0x68080
5555  #define _PFB_CTL_1               0x68880
5556  #define  PF_ENABLE              (1<<31)
5557  #define  PF_PIPE_SEL_MASK_IVB	(3<<29)
5558  #define  PF_PIPE_SEL_IVB(pipe)	((pipe)<<29)
5559  #define  PF_FILTER_MASK		(3<<23)
5560  #define  PF_FILTER_PROGRAMMED	(0<<23)
5561  #define  PF_FILTER_MED_3x3	(1<<23)
5562  #define  PF_FILTER_EDGE_ENHANCE	(2<<23)
5563  #define  PF_FILTER_EDGE_SOFTEN	(3<<23)
5564  #define _PFA_WIN_SZ		0x68074
5565  #define _PFB_WIN_SZ		0x68874
5566  #define _PFA_WIN_POS		0x68070
5567  #define _PFB_WIN_POS		0x68870
5568  #define _PFA_VSCALE		0x68084
5569  #define _PFB_VSCALE		0x68884
5570  #define _PFA_HSCALE		0x68090
5571  #define _PFB_HSCALE		0x68890
5572  
5573  #define PF_CTL(pipe)		_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
5574  #define PF_WIN_SZ(pipe)		_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
5575  #define PF_WIN_POS(pipe)	_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
5576  #define PF_VSCALE(pipe)		_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
5577  #define PF_HSCALE(pipe)		_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
5578  
5579  #define _PSA_CTL		0x68180
5580  #define _PSB_CTL		0x68980
5581  #define PS_ENABLE		(1<<31)
5582  #define _PSA_WIN_SZ		0x68174
5583  #define _PSB_WIN_SZ		0x68974
5584  #define _PSA_WIN_POS		0x68170
5585  #define _PSB_WIN_POS		0x68970
5586  
5587  #define PS_CTL(pipe)		_PIPE(pipe, _PSA_CTL, _PSB_CTL)
5588  #define PS_WIN_SZ(pipe)		_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
5589  #define PS_WIN_POS(pipe)	_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
5590  
5591  /*
5592   * Skylake scalers
5593   */
5594  #define _PS_1A_CTRL      0x68180
5595  #define _PS_2A_CTRL      0x68280
5596  #define _PS_1B_CTRL      0x68980
5597  #define _PS_2B_CTRL      0x68A80
5598  #define _PS_1C_CTRL      0x69180
5599  #define PS_SCALER_EN        (1 << 31)
5600  #define PS_SCALER_MODE_MASK (3 << 28)
5601  #define PS_SCALER_MODE_DYN  (0 << 28)
5602  #define PS_SCALER_MODE_HQ  (1 << 28)
5603  #define PS_PLANE_SEL_MASK  (7 << 25)
5604  #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
5605  #define PS_FILTER_MASK         (3 << 23)
5606  #define PS_FILTER_MEDIUM       (0 << 23)
5607  #define PS_FILTER_EDGE_ENHANCE (2 << 23)
5608  #define PS_FILTER_BILINEAR     (3 << 23)
5609  #define PS_VERT3TAP            (1 << 21)
5610  #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
5611  #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
5612  #define PS_PWRUP_PROGRESS         (1 << 17)
5613  #define PS_V_FILTER_BYPASS        (1 << 8)
5614  #define PS_VADAPT_EN              (1 << 7)
5615  #define PS_VADAPT_MODE_MASK        (3 << 5)
5616  #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
5617  #define PS_VADAPT_MODE_MOD_ADAPT   (1 << 5)
5618  #define PS_VADAPT_MODE_MOST_ADAPT  (3 << 5)
5619  
5620  #define _PS_PWR_GATE_1A     0x68160
5621  #define _PS_PWR_GATE_2A     0x68260
5622  #define _PS_PWR_GATE_1B     0x68960
5623  #define _PS_PWR_GATE_2B     0x68A60
5624  #define _PS_PWR_GATE_1C     0x69160
5625  #define PS_PWR_GATE_DIS_OVERRIDE       (1 << 31)
5626  #define PS_PWR_GATE_SETTLING_TIME_32   (0 << 3)
5627  #define PS_PWR_GATE_SETTLING_TIME_64   (1 << 3)
5628  #define PS_PWR_GATE_SETTLING_TIME_96   (2 << 3)
5629  #define PS_PWR_GATE_SETTLING_TIME_128  (3 << 3)
5630  #define PS_PWR_GATE_SLPEN_8             0
5631  #define PS_PWR_GATE_SLPEN_16            1
5632  #define PS_PWR_GATE_SLPEN_24            2
5633  #define PS_PWR_GATE_SLPEN_32            3
5634  
5635  #define _PS_WIN_POS_1A      0x68170
5636  #define _PS_WIN_POS_2A      0x68270
5637  #define _PS_WIN_POS_1B      0x68970
5638  #define _PS_WIN_POS_2B      0x68A70
5639  #define _PS_WIN_POS_1C      0x69170
5640  
5641  #define _PS_WIN_SZ_1A       0x68174
5642  #define _PS_WIN_SZ_2A       0x68274
5643  #define _PS_WIN_SZ_1B       0x68974
5644  #define _PS_WIN_SZ_2B       0x68A74
5645  #define _PS_WIN_SZ_1C       0x69174
5646  
5647  #define _PS_VSCALE_1A       0x68184
5648  #define _PS_VSCALE_2A       0x68284
5649  #define _PS_VSCALE_1B       0x68984
5650  #define _PS_VSCALE_2B       0x68A84
5651  #define _PS_VSCALE_1C       0x69184
5652  
5653  #define _PS_HSCALE_1A       0x68190
5654  #define _PS_HSCALE_2A       0x68290
5655  #define _PS_HSCALE_1B       0x68990
5656  #define _PS_HSCALE_2B       0x68A90
5657  #define _PS_HSCALE_1C       0x69190
5658  
5659  #define _PS_VPHASE_1A       0x68188
5660  #define _PS_VPHASE_2A       0x68288
5661  #define _PS_VPHASE_1B       0x68988
5662  #define _PS_VPHASE_2B       0x68A88
5663  #define _PS_VPHASE_1C       0x69188
5664  
5665  #define _PS_HPHASE_1A       0x68194
5666  #define _PS_HPHASE_2A       0x68294
5667  #define _PS_HPHASE_1B       0x68994
5668  #define _PS_HPHASE_2B       0x68A94
5669  #define _PS_HPHASE_1C       0x69194
5670  
5671  #define _PS_ECC_STAT_1A     0x681D0
5672  #define _PS_ECC_STAT_2A     0x682D0
5673  #define _PS_ECC_STAT_1B     0x689D0
5674  #define _PS_ECC_STAT_2B     0x68AD0
5675  #define _PS_ECC_STAT_1C     0x691D0
5676  
5677  #define _ID(id, a, b) ((a) + (id)*((b)-(a)))
5678  #define SKL_PS_CTRL(pipe, id) _PIPE(pipe,        \
5679  			_ID(id, _PS_1A_CTRL, _PS_2A_CTRL),       \
5680  			_ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
5681  #define SKL_PS_PWR_GATE(pipe, id) _PIPE(pipe,    \
5682  			_ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
5683  			_ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
5684  #define SKL_PS_WIN_POS(pipe, id) _PIPE(pipe,     \
5685  			_ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
5686  			_ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
5687  #define SKL_PS_WIN_SZ(pipe, id)  _PIPE(pipe,     \
5688  			_ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A),   \
5689  			_ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
5690  #define SKL_PS_VSCALE(pipe, id)  _PIPE(pipe,     \
5691  			_ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A),   \
5692  			_ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
5693  #define SKL_PS_HSCALE(pipe, id)  _PIPE(pipe,     \
5694  			_ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A),   \
5695  			_ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
5696  #define SKL_PS_VPHASE(pipe, id)  _PIPE(pipe,     \
5697  			_ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A),   \
5698  			_ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
5699  #define SKL_PS_HPHASE(pipe, id)  _PIPE(pipe,     \
5700  			_ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A),   \
5701  			_ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
5702  #define SKL_PS_ECC_STAT(pipe, id)  _PIPE(pipe,     \
5703  			_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
5704  			_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
5705  
5706  /* legacy palette */
5707  #define _LGC_PALETTE_A           0x4a000
5708  #define _LGC_PALETTE_B           0x4a800
5709  #define LGC_PALETTE(pipe, i) (_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
5710  
5711  #define _GAMMA_MODE_A		0x4a480
5712  #define _GAMMA_MODE_B		0x4ac80
5713  #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
5714  #define GAMMA_MODE_MODE_MASK	(3 << 0)
5715  #define GAMMA_MODE_MODE_8BIT	(0 << 0)
5716  #define GAMMA_MODE_MODE_10BIT	(1 << 0)
5717  #define GAMMA_MODE_MODE_12BIT	(2 << 0)
5718  #define GAMMA_MODE_MODE_SPLIT	(3 << 0)
5719  
5720  /* Display Internal Timeout Register */
5721  #define RM_TIMEOUT		0x42060
5722  #define  MMIO_TIMEOUT_US(us)	((us) << 0)
5723  
5724  /* interrupts */
5725  #define DE_MASTER_IRQ_CONTROL   (1 << 31)
5726  #define DE_SPRITEB_FLIP_DONE    (1 << 29)
5727  #define DE_SPRITEA_FLIP_DONE    (1 << 28)
5728  #define DE_PLANEB_FLIP_DONE     (1 << 27)
5729  #define DE_PLANEA_FLIP_DONE     (1 << 26)
5730  #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
5731  #define DE_PCU_EVENT            (1 << 25)
5732  #define DE_GTT_FAULT            (1 << 24)
5733  #define DE_POISON               (1 << 23)
5734  #define DE_PERFORM_COUNTER      (1 << 22)
5735  #define DE_PCH_EVENT            (1 << 21)
5736  #define DE_AUX_CHANNEL_A        (1 << 20)
5737  #define DE_DP_A_HOTPLUG         (1 << 19)
5738  #define DE_GSE                  (1 << 18)
5739  #define DE_PIPEB_VBLANK         (1 << 15)
5740  #define DE_PIPEB_EVEN_FIELD     (1 << 14)
5741  #define DE_PIPEB_ODD_FIELD      (1 << 13)
5742  #define DE_PIPEB_LINE_COMPARE   (1 << 12)
5743  #define DE_PIPEB_VSYNC          (1 << 11)
5744  #define DE_PIPEB_CRC_DONE	(1 << 10)
5745  #define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
5746  #define DE_PIPEA_VBLANK         (1 << 7)
5747  #define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8*(pipe)))
5748  #define DE_PIPEA_EVEN_FIELD     (1 << 6)
5749  #define DE_PIPEA_ODD_FIELD      (1 << 5)
5750  #define DE_PIPEA_LINE_COMPARE   (1 << 4)
5751  #define DE_PIPEA_VSYNC          (1 << 3)
5752  #define DE_PIPEA_CRC_DONE	(1 << 2)
5753  #define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8*(pipe)))
5754  #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
5755  #define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8*(pipe)))
5756  
5757  /* More Ivybridge lolz */
5758  #define DE_ERR_INT_IVB			(1<<30)
5759  #define DE_GSE_IVB			(1<<29)
5760  #define DE_PCH_EVENT_IVB		(1<<28)
5761  #define DE_DP_A_HOTPLUG_IVB		(1<<27)
5762  #define DE_AUX_CHANNEL_A_IVB		(1<<26)
5763  #define DE_SPRITEC_FLIP_DONE_IVB	(1<<14)
5764  #define DE_PLANEC_FLIP_DONE_IVB		(1<<13)
5765  #define DE_PIPEC_VBLANK_IVB		(1<<10)
5766  #define DE_SPRITEB_FLIP_DONE_IVB	(1<<9)
5767  #define DE_PLANEB_FLIP_DONE_IVB		(1<<8)
5768  #define DE_PIPEB_VBLANK_IVB		(1<<5)
5769  #define DE_SPRITEA_FLIP_DONE_IVB	(1<<4)
5770  #define DE_PLANEA_FLIP_DONE_IVB		(1<<3)
5771  #define DE_PLANE_FLIP_DONE_IVB(plane)	(1<< (3 + 5*(plane)))
5772  #define DE_PIPEA_VBLANK_IVB		(1<<0)
5773  #define DE_PIPE_VBLANK_IVB(pipe)	(1 << ((pipe) * 5))
5774  
5775  #define VLV_MASTER_IER			0x4400c /* Gunit master IER */
5776  #define   MASTER_INTERRUPT_ENABLE	(1<<31)
5777  
5778  #define DEISR   0x44000
5779  #define DEIMR   0x44004
5780  #define DEIIR   0x44008
5781  #define DEIER   0x4400c
5782  
5783  #define GTISR   0x44010
5784  #define GTIMR   0x44014
5785  #define GTIIR   0x44018
5786  #define GTIER   0x4401c
5787  
5788  #define GEN8_MASTER_IRQ			0x44200
5789  #define  GEN8_MASTER_IRQ_CONTROL	(1<<31)
5790  #define  GEN8_PCU_IRQ			(1<<30)
5791  #define  GEN8_DE_PCH_IRQ		(1<<23)
5792  #define  GEN8_DE_MISC_IRQ		(1<<22)
5793  #define  GEN8_DE_PORT_IRQ		(1<<20)
5794  #define  GEN8_DE_PIPE_C_IRQ		(1<<18)
5795  #define  GEN8_DE_PIPE_B_IRQ		(1<<17)
5796  #define  GEN8_DE_PIPE_A_IRQ		(1<<16)
5797  #define  GEN8_DE_PIPE_IRQ(pipe)		(1<<(16+(pipe)))
5798  #define  GEN8_GT_VECS_IRQ		(1<<6)
5799  #define  GEN8_GT_PM_IRQ			(1<<4)
5800  #define  GEN8_GT_VCS2_IRQ		(1<<3)
5801  #define  GEN8_GT_VCS1_IRQ		(1<<2)
5802  #define  GEN8_GT_BCS_IRQ		(1<<1)
5803  #define  GEN8_GT_RCS_IRQ		(1<<0)
5804  
5805  #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
5806  #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
5807  #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
5808  #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
5809  
5810  #define GEN8_RCS_IRQ_SHIFT 0
5811  #define GEN8_BCS_IRQ_SHIFT 16
5812  #define GEN8_VCS1_IRQ_SHIFT 0
5813  #define GEN8_VCS2_IRQ_SHIFT 16
5814  #define GEN8_VECS_IRQ_SHIFT 0
5815  #define GEN8_WD_IRQ_SHIFT 16
5816  
5817  #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
5818  #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
5819  #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
5820  #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
5821  #define  GEN8_PIPE_FIFO_UNDERRUN	(1 << 31)
5822  #define  GEN8_PIPE_CDCLK_CRC_ERROR	(1 << 29)
5823  #define  GEN8_PIPE_CDCLK_CRC_DONE	(1 << 28)
5824  #define  GEN8_PIPE_CURSOR_FAULT		(1 << 10)
5825  #define  GEN8_PIPE_SPRITE_FAULT		(1 << 9)
5826  #define  GEN8_PIPE_PRIMARY_FAULT	(1 << 8)
5827  #define  GEN8_PIPE_SPRITE_FLIP_DONE	(1 << 5)
5828  #define  GEN8_PIPE_PRIMARY_FLIP_DONE	(1 << 4)
5829  #define  GEN8_PIPE_SCAN_LINE_EVENT	(1 << 2)
5830  #define  GEN8_PIPE_VSYNC		(1 << 1)
5831  #define  GEN8_PIPE_VBLANK		(1 << 0)
5832  #define  GEN9_PIPE_CURSOR_FAULT		(1 << 11)
5833  #define  GEN9_PIPE_PLANE4_FAULT		(1 << 10)
5834  #define  GEN9_PIPE_PLANE3_FAULT		(1 << 9)
5835  #define  GEN9_PIPE_PLANE2_FAULT		(1 << 8)
5836  #define  GEN9_PIPE_PLANE1_FAULT		(1 << 7)
5837  #define  GEN9_PIPE_PLANE4_FLIP_DONE	(1 << 6)
5838  #define  GEN9_PIPE_PLANE3_FLIP_DONE	(1 << 5)
5839  #define  GEN9_PIPE_PLANE2_FLIP_DONE	(1 << 4)
5840  #define  GEN9_PIPE_PLANE1_FLIP_DONE	(1 << 3)
5841  #define  GEN9_PIPE_PLANE_FLIP_DONE(p)	(1 << (3 + (p)))
5842  #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
5843  	(GEN8_PIPE_CURSOR_FAULT | \
5844  	 GEN8_PIPE_SPRITE_FAULT | \
5845  	 GEN8_PIPE_PRIMARY_FAULT)
5846  #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
5847  	(GEN9_PIPE_CURSOR_FAULT | \
5848  	 GEN9_PIPE_PLANE4_FAULT | \
5849  	 GEN9_PIPE_PLANE3_FAULT | \
5850  	 GEN9_PIPE_PLANE2_FAULT | \
5851  	 GEN9_PIPE_PLANE1_FAULT)
5852  
5853  #define GEN8_DE_PORT_ISR 0x44440
5854  #define GEN8_DE_PORT_IMR 0x44444
5855  #define GEN8_DE_PORT_IIR 0x44448
5856  #define GEN8_DE_PORT_IER 0x4444c
5857  #define  GEN9_AUX_CHANNEL_D		(1 << 27)
5858  #define  GEN9_AUX_CHANNEL_C		(1 << 26)
5859  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
5860  #define  BXT_DE_PORT_HP_DDIC		(1 << 5)
5861  #define  BXT_DE_PORT_HP_DDIB		(1 << 4)
5862  #define  BXT_DE_PORT_HP_DDIA		(1 << 3)
5863  #define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDIA | \
5864  					 BXT_DE_PORT_HP_DDIB | \
5865  					 BXT_DE_PORT_HP_DDIC)
5866  #define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
5867  #define  BXT_DE_PORT_GMBUS		(1 << 1)
5868  #define  GEN8_AUX_CHANNEL_A		(1 << 0)
5869  
5870  #define GEN8_DE_MISC_ISR 0x44460
5871  #define GEN8_DE_MISC_IMR 0x44464
5872  #define GEN8_DE_MISC_IIR 0x44468
5873  #define GEN8_DE_MISC_IER 0x4446c
5874  #define  GEN8_DE_MISC_GSE		(1 << 27)
5875  
5876  #define GEN8_PCU_ISR 0x444e0
5877  #define GEN8_PCU_IMR 0x444e4
5878  #define GEN8_PCU_IIR 0x444e8
5879  #define GEN8_PCU_IER 0x444ec
5880  
5881  #define ILK_DISPLAY_CHICKEN2	0x42004
5882  /* Required on all Ironlake and Sandybridge according to the B-Spec. */
5883  #define  ILK_ELPIN_409_SELECT	(1 << 25)
5884  #define  ILK_DPARB_GATE	(1<<22)
5885  #define  ILK_VSDPFD_FULL	(1<<21)
5886  #define FUSE_STRAP			0x42014
5887  #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)
5888  #define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)
5889  #define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)
5890  #define  ILK_HDCP_DISABLE		(1 << 25)
5891  #define  ILK_eDP_A_DISABLE		(1 << 24)
5892  #define  HSW_CDCLK_LIMIT		(1 << 24)
5893  #define  ILK_DESKTOP			(1 << 23)
5894  
5895  #define ILK_DSPCLK_GATE_D			0x42020
5896  #define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	(1 << 28)
5897  #define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE	(1 << 9)
5898  #define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE	(1 << 8)
5899  #define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE	(1 << 7)
5900  #define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE	(1 << 5)
5901  
5902  #define IVB_CHICKEN3	0x4200c
5903  # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)
5904  # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
5905  
5906  #define CHICKEN_PAR1_1		0x42080
5907  #define  DPA_MASK_VBLANK_SRD	(1 << 15)
5908  #define  FORCE_ARB_IDLE_PLANES	(1 << 14)
5909  
5910  #define _CHICKEN_PIPESL_1_A	0x420b0
5911  #define _CHICKEN_PIPESL_1_B	0x420b4
5912  #define  HSW_FBCQ_DIS			(1 << 22)
5913  #define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)
5914  #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
5915  
5916  #define DISP_ARB_CTL	0x45000
5917  #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
5918  #define  DISP_FBC_WM_DIS		(1<<15)
5919  #define DISP_ARB_CTL2	0x45004
5920  #define  DISP_DATA_PARTITION_5_6	(1<<6)
5921  #define DBUF_CTL	0x45008
5922  #define  DBUF_POWER_REQUEST		(1<<31)
5923  #define  DBUF_POWER_STATE		(1<<30)
5924  #define GEN7_MSG_CTL	0x45010
5925  #define  WAIT_FOR_PCH_RESET_ACK		(1<<1)
5926  #define  WAIT_FOR_PCH_FLR_ACK		(1<<0)
5927  #define HSW_NDE_RSTWRN_OPT	0x46408
5928  #define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)
5929  
5930  #define SKL_DFSM			0x51000
5931  #define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
5932  #define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
5933  #define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
5934  #define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
5935  #define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
5936  
5937  #define FF_SLICE_CS_CHICKEN2			0x20e4
5938  #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
5939  
5940  /* GEN7 chicken */
5941  #define GEN7_COMMON_SLICE_CHICKEN1		0x7010
5942  # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
5943  # define GEN9_RHWO_OPTIMIZATION_DISABLE		(1<<14)
5944  #define COMMON_SLICE_CHICKEN2			0x7014
5945  # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
5946  
5947  #define HIZ_CHICKEN					0x7018
5948  # define CHV_HZ_8X8_MODE_IN_1X				(1<<15)
5949  # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	(1<<3)
5950  
5951  #define GEN9_SLICE_COMMON_ECO_CHICKEN0		0x7308
5952  #define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
5953  
5954  #define GEN7_L3SQCREG1				0xB010
5955  #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
5956  
5957  #define GEN8_L3SQCREG1				0xB100
5958  #define  BDW_WA_L3SQCREG1_DEFAULT		0x784000
5959  
5960  #define GEN7_L3CNTLREG1				0xB01C
5961  #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
5962  #define  GEN7_L3AGDIS				(1<<19)
5963  #define GEN7_L3CNTLREG2				0xB020
5964  #define GEN7_L3CNTLREG3				0xB024
5965  
5966  #define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
5967  #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
5968  
5969  #define GEN7_L3SQCREG4				0xb034
5970  #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
5971  
5972  #define GEN8_L3SQCREG4				0xb118
5973  #define  GEN8_LQSC_RO_PERF_DIS			(1<<27)
5974  #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1<<21)
5975  
5976  /* GEN8 chicken */
5977  #define HDC_CHICKEN0				0x7300
5978  #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)
5979  #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
5980  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
5981  #define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1<<5)
5982  #define  HDC_FORCE_NON_COHERENT			(1<<4)
5983  #define  HDC_BARRIER_PERFORMANCE_DISABLE	(1<<10)
5984  
5985  /* GEN9 chicken */
5986  #define SLICE_ECO_CHICKEN0			0x7308
5987  #define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
5988  
5989  /* WaCatErrorRejectionIssue */
5990  #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
5991  #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
5992  
5993  #define HSW_SCRATCH1				0xb038
5994  #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1<<27)
5995  
5996  #define BDW_SCRATCH1					0xb11c
5997  #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1<<2)
5998  
5999  /* PCH */
6000  
6001  /* south display engine interrupt: IBX */
6002  #define SDE_AUDIO_POWER_D	(1 << 27)
6003  #define SDE_AUDIO_POWER_C	(1 << 26)
6004  #define SDE_AUDIO_POWER_B	(1 << 25)
6005  #define SDE_AUDIO_POWER_SHIFT	(25)
6006  #define SDE_AUDIO_POWER_MASK	(7 << SDE_AUDIO_POWER_SHIFT)
6007  #define SDE_GMBUS		(1 << 24)
6008  #define SDE_AUDIO_HDCP_TRANSB	(1 << 23)
6009  #define SDE_AUDIO_HDCP_TRANSA	(1 << 22)
6010  #define SDE_AUDIO_HDCP_MASK	(3 << 22)
6011  #define SDE_AUDIO_TRANSB	(1 << 21)
6012  #define SDE_AUDIO_TRANSA	(1 << 20)
6013  #define SDE_AUDIO_TRANS_MASK	(3 << 20)
6014  #define SDE_POISON		(1 << 19)
6015  /* 18 reserved */
6016  #define SDE_FDI_RXB		(1 << 17)
6017  #define SDE_FDI_RXA		(1 << 16)
6018  #define SDE_FDI_MASK		(3 << 16)
6019  #define SDE_AUXD		(1 << 15)
6020  #define SDE_AUXC		(1 << 14)
6021  #define SDE_AUXB		(1 << 13)
6022  #define SDE_AUX_MASK		(7 << 13)
6023  /* 12 reserved */
6024  #define SDE_CRT_HOTPLUG         (1 << 11)
6025  #define SDE_PORTD_HOTPLUG       (1 << 10)
6026  #define SDE_PORTC_HOTPLUG       (1 << 9)
6027  #define SDE_PORTB_HOTPLUG       (1 << 8)
6028  #define SDE_SDVOB_HOTPLUG       (1 << 6)
6029  #define SDE_HOTPLUG_MASK        (SDE_CRT_HOTPLUG | \
6030  				 SDE_SDVOB_HOTPLUG |	\
6031  				 SDE_PORTB_HOTPLUG |	\
6032  				 SDE_PORTC_HOTPLUG |	\
6033  				 SDE_PORTD_HOTPLUG)
6034  #define SDE_TRANSB_CRC_DONE	(1 << 5)
6035  #define SDE_TRANSB_CRC_ERR	(1 << 4)
6036  #define SDE_TRANSB_FIFO_UNDER	(1 << 3)
6037  #define SDE_TRANSA_CRC_DONE	(1 << 2)
6038  #define SDE_TRANSA_CRC_ERR	(1 << 1)
6039  #define SDE_TRANSA_FIFO_UNDER	(1 << 0)
6040  #define SDE_TRANS_MASK		(0x3f)
6041  
6042  /* south display engine interrupt: CPT/PPT */
6043  #define SDE_AUDIO_POWER_D_CPT	(1 << 31)
6044  #define SDE_AUDIO_POWER_C_CPT	(1 << 30)
6045  #define SDE_AUDIO_POWER_B_CPT	(1 << 29)
6046  #define SDE_AUDIO_POWER_SHIFT_CPT   29
6047  #define SDE_AUDIO_POWER_MASK_CPT    (7 << 29)
6048  #define SDE_AUXD_CPT		(1 << 27)
6049  #define SDE_AUXC_CPT		(1 << 26)
6050  #define SDE_AUXB_CPT		(1 << 25)
6051  #define SDE_AUX_MASK_CPT	(7 << 25)
6052  #define SDE_PORTE_HOTPLUG_SPT	(1 << 25)
6053  #define SDE_PORTA_HOTPLUG_SPT	(1 << 24)
6054  #define SDE_PORTD_HOTPLUG_CPT	(1 << 23)
6055  #define SDE_PORTC_HOTPLUG_CPT	(1 << 22)
6056  #define SDE_PORTB_HOTPLUG_CPT	(1 << 21)
6057  #define SDE_CRT_HOTPLUG_CPT	(1 << 19)
6058  #define SDE_SDVOB_HOTPLUG_CPT	(1 << 18)
6059  #define SDE_HOTPLUG_MASK_CPT	(SDE_CRT_HOTPLUG_CPT |		\
6060  				 SDE_SDVOB_HOTPLUG_CPT |	\
6061  				 SDE_PORTD_HOTPLUG_CPT |	\
6062  				 SDE_PORTC_HOTPLUG_CPT |	\
6063  				 SDE_PORTB_HOTPLUG_CPT)
6064  #define SDE_HOTPLUG_MASK_SPT	(SDE_PORTE_HOTPLUG_SPT |	\
6065  				 SDE_PORTD_HOTPLUG_CPT |	\
6066  				 SDE_PORTC_HOTPLUG_CPT |	\
6067  				 SDE_PORTB_HOTPLUG_CPT |	\
6068  				 SDE_PORTA_HOTPLUG_SPT)
6069  #define SDE_GMBUS_CPT		(1 << 17)
6070  #define SDE_ERROR_CPT		(1 << 16)
6071  #define SDE_AUDIO_CP_REQ_C_CPT	(1 << 10)
6072  #define SDE_AUDIO_CP_CHG_C_CPT	(1 << 9)
6073  #define SDE_FDI_RXC_CPT		(1 << 8)
6074  #define SDE_AUDIO_CP_REQ_B_CPT	(1 << 6)
6075  #define SDE_AUDIO_CP_CHG_B_CPT	(1 << 5)
6076  #define SDE_FDI_RXB_CPT		(1 << 4)
6077  #define SDE_AUDIO_CP_REQ_A_CPT	(1 << 2)
6078  #define SDE_AUDIO_CP_CHG_A_CPT	(1 << 1)
6079  #define SDE_FDI_RXA_CPT		(1 << 0)
6080  #define SDE_AUDIO_CP_REQ_CPT	(SDE_AUDIO_CP_REQ_C_CPT | \
6081  				 SDE_AUDIO_CP_REQ_B_CPT | \
6082  				 SDE_AUDIO_CP_REQ_A_CPT)
6083  #define SDE_AUDIO_CP_CHG_CPT	(SDE_AUDIO_CP_CHG_C_CPT | \
6084  				 SDE_AUDIO_CP_CHG_B_CPT | \
6085  				 SDE_AUDIO_CP_CHG_A_CPT)
6086  #define SDE_FDI_MASK_CPT	(SDE_FDI_RXC_CPT | \
6087  				 SDE_FDI_RXB_CPT | \
6088  				 SDE_FDI_RXA_CPT)
6089  
6090  #define SDEISR  0xc4000
6091  #define SDEIMR  0xc4004
6092  #define SDEIIR  0xc4008
6093  #define SDEIER  0xc400c
6094  
6095  #define SERR_INT			0xc4040
6096  #define  SERR_INT_POISON		(1<<31)
6097  #define  SERR_INT_TRANS_C_FIFO_UNDERRUN	(1<<6)
6098  #define  SERR_INT_TRANS_B_FIFO_UNDERRUN	(1<<3)
6099  #define  SERR_INT_TRANS_A_FIFO_UNDERRUN	(1<<0)
6100  #define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)	(1<<((pipe)*3))
6101  
6102  /* digital port hotplug */
6103  #define PCH_PORT_HOTPLUG		0xc4030	/* SHOTPLUG_CTL */
6104  #define  PORTA_HOTPLUG_ENABLE		(1 << 28) /* LPT:LP+ & BXT */
6105  #define  PORTA_HOTPLUG_STATUS_MASK	(3 << 24) /* SPT+ & BXT */
6106  #define  PORTA_HOTPLUG_NO_DETECT	(0 << 24) /* SPT+ & BXT */
6107  #define  PORTA_HOTPLUG_SHORT_DETECT	(1 << 24) /* SPT+ & BXT */
6108  #define  PORTA_HOTPLUG_LONG_DETECT	(2 << 24) /* SPT+ & BXT */
6109  #define  PORTD_HOTPLUG_ENABLE		(1 << 20)
6110  #define  PORTD_PULSE_DURATION_2ms	(0 << 18) /* pre-LPT */
6111  #define  PORTD_PULSE_DURATION_4_5ms	(1 << 18) /* pre-LPT */
6112  #define  PORTD_PULSE_DURATION_6ms	(2 << 18) /* pre-LPT */
6113  #define  PORTD_PULSE_DURATION_100ms	(3 << 18) /* pre-LPT */
6114  #define  PORTD_PULSE_DURATION_MASK	(3 << 18) /* pre-LPT */
6115  #define  PORTD_HOTPLUG_STATUS_MASK	(3 << 16)
6116  #define  PORTD_HOTPLUG_NO_DETECT	(0 << 16)
6117  #define  PORTD_HOTPLUG_SHORT_DETECT	(1 << 16)
6118  #define  PORTD_HOTPLUG_LONG_DETECT	(2 << 16)
6119  #define  PORTC_HOTPLUG_ENABLE		(1 << 12)
6120  #define  PORTC_PULSE_DURATION_2ms	(0 << 10) /* pre-LPT */
6121  #define  PORTC_PULSE_DURATION_4_5ms	(1 << 10) /* pre-LPT */
6122  #define  PORTC_PULSE_DURATION_6ms	(2 << 10) /* pre-LPT */
6123  #define  PORTC_PULSE_DURATION_100ms	(3 << 10) /* pre-LPT */
6124  #define  PORTC_PULSE_DURATION_MASK	(3 << 10) /* pre-LPT */
6125  #define  PORTC_HOTPLUG_STATUS_MASK	(3 << 8)
6126  #define  PORTC_HOTPLUG_NO_DETECT	(0 << 8)
6127  #define  PORTC_HOTPLUG_SHORT_DETECT	(1 << 8)
6128  #define  PORTC_HOTPLUG_LONG_DETECT	(2 << 8)
6129  #define  PORTB_HOTPLUG_ENABLE		(1 << 4)
6130  #define  PORTB_PULSE_DURATION_2ms	(0 << 2) /* pre-LPT */
6131  #define  PORTB_PULSE_DURATION_4_5ms	(1 << 2) /* pre-LPT */
6132  #define  PORTB_PULSE_DURATION_6ms	(2 << 2) /* pre-LPT */
6133  #define  PORTB_PULSE_DURATION_100ms	(3 << 2) /* pre-LPT */
6134  #define  PORTB_PULSE_DURATION_MASK	(3 << 2) /* pre-LPT */
6135  #define  PORTB_HOTPLUG_STATUS_MASK	(3 << 0)
6136  #define  PORTB_HOTPLUG_NO_DETECT	(0 << 0)
6137  #define  PORTB_HOTPLUG_SHORT_DETECT	(1 << 0)
6138  #define  PORTB_HOTPLUG_LONG_DETECT	(2 << 0)
6139  
6140  #define PCH_PORT_HOTPLUG2		0xc403C	/* SHOTPLUG_CTL2 SPT+ */
6141  #define  PORTE_HOTPLUG_ENABLE		(1 << 4)
6142  #define  PORTE_HOTPLUG_STATUS_MASK	(3 << 0)
6143  #define  PORTE_HOTPLUG_NO_DETECT	(0 << 0)
6144  #define  PORTE_HOTPLUG_SHORT_DETECT	(1 << 0)
6145  #define  PORTE_HOTPLUG_LONG_DETECT	(2 << 0)
6146  
6147  #define PCH_GPIOA               0xc5010
6148  #define PCH_GPIOB               0xc5014
6149  #define PCH_GPIOC               0xc5018
6150  #define PCH_GPIOD               0xc501c
6151  #define PCH_GPIOE               0xc5020
6152  #define PCH_GPIOF               0xc5024
6153  
6154  #define PCH_GMBUS0		0xc5100
6155  #define PCH_GMBUS1		0xc5104
6156  #define PCH_GMBUS2		0xc5108
6157  #define PCH_GMBUS3		0xc510c
6158  #define PCH_GMBUS4		0xc5110
6159  #define PCH_GMBUS5		0xc5120
6160  
6161  #define _PCH_DPLL_A              0xc6014
6162  #define _PCH_DPLL_B              0xc6018
6163  #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
6164  
6165  #define _PCH_FPA0                0xc6040
6166  #define  FP_CB_TUNE		(0x3<<22)
6167  #define _PCH_FPA1                0xc6044
6168  #define _PCH_FPB0                0xc6048
6169  #define _PCH_FPB1                0xc604c
6170  #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
6171  #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
6172  
6173  #define PCH_DPLL_TEST           0xc606c
6174  
6175  #define PCH_DREF_CONTROL        0xC6200
6176  #define  DREF_CONTROL_MASK      0x7fc3
6177  #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
6178  #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
6179  #define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3<<13)
6180  #define  DREF_CPU_SOURCE_OUTPUT_MASK		(3<<13)
6181  #define  DREF_SSC_SOURCE_DISABLE                (0<<11)
6182  #define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
6183  #define  DREF_SSC_SOURCE_MASK			(3<<11)
6184  #define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
6185  #define  DREF_NONSPREAD_CK505_ENABLE		(1<<9)
6186  #define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
6187  #define  DREF_NONSPREAD_SOURCE_MASK		(3<<9)
6188  #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
6189  #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
6190  #define  DREF_SUPERSPREAD_SOURCE_MASK		(3<<7)
6191  #define  DREF_SSC4_DOWNSPREAD                   (0<<6)
6192  #define  DREF_SSC4_CENTERSPREAD                 (1<<6)
6193  #define  DREF_SSC1_DISABLE                      (0<<1)
6194  #define  DREF_SSC1_ENABLE                       (1<<1)
6195  #define  DREF_SSC4_DISABLE                      (0)
6196  #define  DREF_SSC4_ENABLE                       (1)
6197  
6198  #define PCH_RAWCLK_FREQ         0xc6204
6199  #define  FDL_TP1_TIMER_SHIFT    12
6200  #define  FDL_TP1_TIMER_MASK     (3<<12)
6201  #define  FDL_TP2_TIMER_SHIFT    10
6202  #define  FDL_TP2_TIMER_MASK     (3<<10)
6203  #define  RAWCLK_FREQ_MASK       0x3ff
6204  
6205  #define PCH_DPLL_TMR_CFG        0xc6208
6206  
6207  #define PCH_SSC4_PARMS          0xc6210
6208  #define PCH_SSC4_AUX_PARMS      0xc6214
6209  
6210  #define PCH_DPLL_SEL		0xc7000
6211  #define	 TRANS_DPLLB_SEL(pipe)		(1 << ((pipe) * 4))
6212  #define	 TRANS_DPLLA_SEL(pipe)		0
6213  #define  TRANS_DPLL_ENABLE(pipe)	(1 << ((pipe) * 4 + 3))
6214  
6215  /* transcoder */
6216  
6217  #define _PCH_TRANS_HTOTAL_A		0xe0000
6218  #define  TRANS_HTOTAL_SHIFT		16
6219  #define  TRANS_HACTIVE_SHIFT		0
6220  #define _PCH_TRANS_HBLANK_A		0xe0004
6221  #define  TRANS_HBLANK_END_SHIFT		16
6222  #define  TRANS_HBLANK_START_SHIFT	0
6223  #define _PCH_TRANS_HSYNC_A		0xe0008
6224  #define  TRANS_HSYNC_END_SHIFT		16
6225  #define  TRANS_HSYNC_START_SHIFT	0
6226  #define _PCH_TRANS_VTOTAL_A		0xe000c
6227  #define  TRANS_VTOTAL_SHIFT		16
6228  #define  TRANS_VACTIVE_SHIFT		0
6229  #define _PCH_TRANS_VBLANK_A		0xe0010
6230  #define  TRANS_VBLANK_END_SHIFT		16
6231  #define  TRANS_VBLANK_START_SHIFT	0
6232  #define _PCH_TRANS_VSYNC_A		0xe0014
6233  #define  TRANS_VSYNC_END_SHIFT	 	16
6234  #define  TRANS_VSYNC_START_SHIFT	0
6235  #define _PCH_TRANS_VSYNCSHIFT_A		0xe0028
6236  
6237  #define _PCH_TRANSA_DATA_M1	0xe0030
6238  #define _PCH_TRANSA_DATA_N1	0xe0034
6239  #define _PCH_TRANSA_DATA_M2	0xe0038
6240  #define _PCH_TRANSA_DATA_N2	0xe003c
6241  #define _PCH_TRANSA_LINK_M1	0xe0040
6242  #define _PCH_TRANSA_LINK_N1	0xe0044
6243  #define _PCH_TRANSA_LINK_M2	0xe0048
6244  #define _PCH_TRANSA_LINK_N2	0xe004c
6245  
6246  /* Per-transcoder DIP controls (PCH) */
6247  #define _VIDEO_DIP_CTL_A         0xe0200
6248  #define _VIDEO_DIP_DATA_A        0xe0208
6249  #define _VIDEO_DIP_GCP_A         0xe0210
6250  #define  GCP_COLOR_INDICATION		(1 << 2)
6251  #define  GCP_DEFAULT_PHASE_ENABLE	(1 << 1)
6252  #define  GCP_AV_MUTE			(1 << 0)
6253  
6254  #define _VIDEO_DIP_CTL_B         0xe1200
6255  #define _VIDEO_DIP_DATA_B        0xe1208
6256  #define _VIDEO_DIP_GCP_B         0xe1210
6257  
6258  #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
6259  #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
6260  #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
6261  
6262  /* Per-transcoder DIP controls (VLV) */
6263  #define VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
6264  #define VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
6265  #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
6266  
6267  #define VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
6268  #define VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
6269  #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
6270  
6271  #define CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
6272  #define CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
6273  #define CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
6274  
6275  #define VLV_TVIDEO_DIP_CTL(pipe) \
6276  	_PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \
6277  	       VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C)
6278  #define VLV_TVIDEO_DIP_DATA(pipe) \
6279  	_PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \
6280  	       VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C)
6281  #define VLV_TVIDEO_DIP_GCP(pipe) \
6282  	_PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
6283  		VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
6284  
6285  /* Haswell DIP controls */
6286  #define HSW_VIDEO_DIP_CTL_A		0x60200
6287  #define HSW_VIDEO_DIP_AVI_DATA_A	0x60220
6288  #define HSW_VIDEO_DIP_VS_DATA_A		0x60260
6289  #define HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
6290  #define HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
6291  #define HSW_VIDEO_DIP_VSC_DATA_A	0x60320
6292  #define HSW_VIDEO_DIP_AVI_ECC_A		0x60240
6293  #define HSW_VIDEO_DIP_VS_ECC_A		0x60280
6294  #define HSW_VIDEO_DIP_SPD_ECC_A		0x602C0
6295  #define HSW_VIDEO_DIP_GMP_ECC_A		0x60300
6296  #define HSW_VIDEO_DIP_VSC_ECC_A		0x60344
6297  #define HSW_VIDEO_DIP_GCP_A		0x60210
6298  
6299  #define HSW_VIDEO_DIP_CTL_B		0x61200
6300  #define HSW_VIDEO_DIP_AVI_DATA_B	0x61220
6301  #define HSW_VIDEO_DIP_VS_DATA_B		0x61260
6302  #define HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
6303  #define HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
6304  #define HSW_VIDEO_DIP_VSC_DATA_B	0x61320
6305  #define HSW_VIDEO_DIP_BVI_ECC_B		0x61240
6306  #define HSW_VIDEO_DIP_VS_ECC_B		0x61280
6307  #define HSW_VIDEO_DIP_SPD_ECC_B		0x612C0
6308  #define HSW_VIDEO_DIP_GMP_ECC_B		0x61300
6309  #define HSW_VIDEO_DIP_VSC_ECC_B		0x61344
6310  #define HSW_VIDEO_DIP_GCP_B		0x61210
6311  
6312  #define HSW_TVIDEO_DIP_CTL(trans) \
6313  	 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
6314  #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) \
6315  	(_TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) + (i) * 4)
6316  #define HSW_TVIDEO_DIP_VS_DATA(trans, i) \
6317  	(_TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) + (i) * 4)
6318  #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) \
6319  	(_TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) + (i) * 4)
6320  #define HSW_TVIDEO_DIP_GCP(trans) \
6321  	_TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
6322  #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) \
6323  	(_TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) + (i) * 4)
6324  
6325  #define HSW_STEREO_3D_CTL_A	0x70020
6326  #define   S3D_ENABLE		(1<<31)
6327  #define HSW_STEREO_3D_CTL_B	0x71020
6328  
6329  #define HSW_STEREO_3D_CTL(trans) \
6330  	_PIPE2(trans, HSW_STEREO_3D_CTL_A)
6331  
6332  #define _PCH_TRANS_HTOTAL_B          0xe1000
6333  #define _PCH_TRANS_HBLANK_B          0xe1004
6334  #define _PCH_TRANS_HSYNC_B           0xe1008
6335  #define _PCH_TRANS_VTOTAL_B          0xe100c
6336  #define _PCH_TRANS_VBLANK_B          0xe1010
6337  #define _PCH_TRANS_VSYNC_B           0xe1014
6338  #define _PCH_TRANS_VSYNCSHIFT_B	 0xe1028
6339  
6340  #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
6341  #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
6342  #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
6343  #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
6344  #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
6345  #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
6346  #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
6347  					 _PCH_TRANS_VSYNCSHIFT_B)
6348  
6349  #define _PCH_TRANSB_DATA_M1	0xe1030
6350  #define _PCH_TRANSB_DATA_N1	0xe1034
6351  #define _PCH_TRANSB_DATA_M2	0xe1038
6352  #define _PCH_TRANSB_DATA_N2	0xe103c
6353  #define _PCH_TRANSB_LINK_M1	0xe1040
6354  #define _PCH_TRANSB_LINK_N1	0xe1044
6355  #define _PCH_TRANSB_LINK_M2	0xe1048
6356  #define _PCH_TRANSB_LINK_N2	0xe104c
6357  
6358  #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
6359  #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
6360  #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
6361  #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
6362  #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
6363  #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
6364  #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
6365  #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
6366  
6367  #define _PCH_TRANSACONF              0xf0008
6368  #define _PCH_TRANSBCONF              0xf1008
6369  #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
6370  #define LPT_TRANSCONF		_PCH_TRANSACONF /* lpt has only one transcoder */
6371  #define  TRANS_DISABLE          (0<<31)
6372  #define  TRANS_ENABLE           (1<<31)
6373  #define  TRANS_STATE_MASK       (1<<30)
6374  #define  TRANS_STATE_DISABLE    (0<<30)
6375  #define  TRANS_STATE_ENABLE     (1<<30)
6376  #define  TRANS_FSYNC_DELAY_HB1  (0<<27)
6377  #define  TRANS_FSYNC_DELAY_HB2  (1<<27)
6378  #define  TRANS_FSYNC_DELAY_HB3  (2<<27)
6379  #define  TRANS_FSYNC_DELAY_HB4  (3<<27)
6380  #define  TRANS_INTERLACE_MASK   (7<<21)
6381  #define  TRANS_PROGRESSIVE      (0<<21)
6382  #define  TRANS_INTERLACED       (3<<21)
6383  #define  TRANS_LEGACY_INTERLACED_ILK (2<<21)
6384  #define  TRANS_8BPC             (0<<5)
6385  #define  TRANS_10BPC            (1<<5)
6386  #define  TRANS_6BPC             (2<<5)
6387  #define  TRANS_12BPC            (3<<5)
6388  
6389  #define _TRANSA_CHICKEN1	 0xf0060
6390  #define _TRANSB_CHICKEN1	 0xf1060
6391  #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
6392  #define  TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	(1<<10)
6393  #define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	(1<<4)
6394  #define _TRANSA_CHICKEN2	 0xf0064
6395  #define _TRANSB_CHICKEN2	 0xf1064
6396  #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
6397  #define  TRANS_CHICKEN2_TIMING_OVERRIDE			(1<<31)
6398  #define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED		(1<<29)
6399  #define  TRANS_CHICKEN2_FRAME_START_DELAY_MASK		(3<<27)
6400  #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	(1<<26)
6401  #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	(1<<25)
6402  
6403  #define SOUTH_CHICKEN1		0xc2000
6404  #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
6405  #define  FDIA_PHASE_SYNC_SHIFT_EN	18
6406  #define  FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
6407  #define  FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
6408  #define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
6409  #define  SPT_PWM_GRANULARITY		(1<<0)
6410  #define SOUTH_CHICKEN2		0xc2004
6411  #define  FDI_MPHY_IOSFSB_RESET_STATUS	(1<<13)
6412  #define  FDI_MPHY_IOSFSB_RESET_CTL	(1<<12)
6413  #define  LPT_PWM_GRANULARITY		(1<<5)
6414  #define  DPLS_EDP_PPS_FIX_DIS		(1<<0)
6415  
6416  #define _FDI_RXA_CHICKEN         0xc200c
6417  #define _FDI_RXB_CHICKEN         0xc2010
6418  #define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1<<1)
6419  #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1<<0)
6420  #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
6421  
6422  #define SOUTH_DSPCLK_GATE_D	0xc2020
6423  #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
6424  #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
6425  #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
6426  #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
6427  
6428  /* CPU: FDI_TX */
6429  #define _FDI_TXA_CTL             0x60100
6430  #define _FDI_TXB_CTL             0x61100
6431  #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
6432  #define  FDI_TX_DISABLE         (0<<31)
6433  #define  FDI_TX_ENABLE          (1<<31)
6434  #define  FDI_LINK_TRAIN_PATTERN_1       (0<<28)
6435  #define  FDI_LINK_TRAIN_PATTERN_2       (1<<28)
6436  #define  FDI_LINK_TRAIN_PATTERN_IDLE    (2<<28)
6437  #define  FDI_LINK_TRAIN_NONE            (3<<28)
6438  #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0<<25)
6439  #define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1<<25)
6440  #define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2<<25)
6441  #define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3<<25)
6442  #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
6443  #define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
6444  #define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2<<22)
6445  #define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3<<22)
6446  /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
6447     SNB has different settings. */
6448  /* SNB A-stepping */
6449  #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
6450  #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
6451  #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
6452  #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
6453  /* SNB B-stepping */
6454  #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0<<22)
6455  #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a<<22)
6456  #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39<<22)
6457  #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38<<22)
6458  #define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f<<22)
6459  #define  FDI_DP_PORT_WIDTH_SHIFT		19
6460  #define  FDI_DP_PORT_WIDTH_MASK			(7 << FDI_DP_PORT_WIDTH_SHIFT)
6461  #define  FDI_DP_PORT_WIDTH(width)           (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
6462  #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1<<18)
6463  /* Ironlake: hardwired to 1 */
6464  #define  FDI_TX_PLL_ENABLE              (1<<14)
6465  
6466  /* Ivybridge has different bits for lolz */
6467  #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0<<8)
6468  #define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1<<8)
6469  #define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2<<8)
6470  #define  FDI_LINK_TRAIN_NONE_IVB            (3<<8)
6471  
6472  /* both Tx and Rx */
6473  #define  FDI_COMPOSITE_SYNC		(1<<11)
6474  #define  FDI_LINK_TRAIN_AUTO		(1<<10)
6475  #define  FDI_SCRAMBLING_ENABLE          (0<<7)
6476  #define  FDI_SCRAMBLING_DISABLE         (1<<7)
6477  
6478  /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
6479  #define _FDI_RXA_CTL             0xf000c
6480  #define _FDI_RXB_CTL             0xf100c
6481  #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
6482  #define  FDI_RX_ENABLE          (1<<31)
6483  /* train, dp width same as FDI_TX */
6484  #define  FDI_FS_ERRC_ENABLE		(1<<27)
6485  #define  FDI_FE_ERRC_ENABLE		(1<<26)
6486  #define  FDI_RX_POLARITY_REVERSED_LPT	(1<<16)
6487  #define  FDI_8BPC                       (0<<16)
6488  #define  FDI_10BPC                      (1<<16)
6489  #define  FDI_6BPC                       (2<<16)
6490  #define  FDI_12BPC                      (3<<16)
6491  #define  FDI_RX_LINK_REVERSAL_OVERRIDE  (1<<15)
6492  #define  FDI_DMI_LINK_REVERSE_MASK      (1<<14)
6493  #define  FDI_RX_PLL_ENABLE              (1<<13)
6494  #define  FDI_FS_ERR_CORRECT_ENABLE      (1<<11)
6495  #define  FDI_FE_ERR_CORRECT_ENABLE      (1<<10)
6496  #define  FDI_FS_ERR_REPORT_ENABLE       (1<<9)
6497  #define  FDI_FE_ERR_REPORT_ENABLE       (1<<8)
6498  #define  FDI_RX_ENHANCE_FRAME_ENABLE    (1<<6)
6499  #define  FDI_PCDCLK	                (1<<4)
6500  /* CPT */
6501  #define  FDI_AUTO_TRAINING			(1<<10)
6502  #define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0<<8)
6503  #define  FDI_LINK_TRAIN_PATTERN_2_CPT		(1<<8)
6504  #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2<<8)
6505  #define  FDI_LINK_TRAIN_NORMAL_CPT		(3<<8)
6506  #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3<<8)
6507  
6508  #define _FDI_RXA_MISC			0xf0010
6509  #define _FDI_RXB_MISC			0xf1010
6510  #define  FDI_RX_PWRDN_LANE1_MASK	(3<<26)
6511  #define  FDI_RX_PWRDN_LANE1_VAL(x)	((x)<<26)
6512  #define  FDI_RX_PWRDN_LANE0_MASK	(3<<24)
6513  #define  FDI_RX_PWRDN_LANE0_VAL(x)	((x)<<24)
6514  #define  FDI_RX_TP1_TO_TP2_48		(2<<20)
6515  #define  FDI_RX_TP1_TO_TP2_64		(3<<20)
6516  #define  FDI_RX_FDI_DELAY_90		(0x90<<0)
6517  #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
6518  
6519  #define _FDI_RXA_TUSIZE1         0xf0030
6520  #define _FDI_RXA_TUSIZE2         0xf0038
6521  #define _FDI_RXB_TUSIZE1         0xf1030
6522  #define _FDI_RXB_TUSIZE2         0xf1038
6523  #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
6524  #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
6525  
6526  /* FDI_RX interrupt register format */
6527  #define FDI_RX_INTER_LANE_ALIGN         (1<<10)
6528  #define FDI_RX_SYMBOL_LOCK              (1<<9) /* train 2 */
6529  #define FDI_RX_BIT_LOCK                 (1<<8) /* train 1 */
6530  #define FDI_RX_TRAIN_PATTERN_2_FAIL     (1<<7)
6531  #define FDI_RX_FS_CODE_ERR              (1<<6)
6532  #define FDI_RX_FE_CODE_ERR              (1<<5)
6533  #define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1<<4)
6534  #define FDI_RX_HDCP_LINK_FAIL           (1<<3)
6535  #define FDI_RX_PIXEL_FIFO_OVERFLOW      (1<<2)
6536  #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1<<1)
6537  #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1<<0)
6538  
6539  #define _FDI_RXA_IIR             0xf0014
6540  #define _FDI_RXA_IMR             0xf0018
6541  #define _FDI_RXB_IIR             0xf1014
6542  #define _FDI_RXB_IMR             0xf1018
6543  #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
6544  #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
6545  
6546  #define FDI_PLL_CTL_1           0xfe000
6547  #define FDI_PLL_CTL_2           0xfe004
6548  
6549  #define PCH_LVDS	0xe1180
6550  #define  LVDS_DETECTED	(1 << 1)
6551  
6552  /* vlv has 2 sets of panel control regs. */
6553  #define PIPEA_PP_STATUS         (VLV_DISPLAY_BASE + 0x61200)
6554  #define PIPEA_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61204)
6555  #define PIPEA_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61208)
6556  #define  PANEL_PORT_SELECT_VLV(port)	((port) << 30)
6557  #define PIPEA_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6120c)
6558  #define PIPEA_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61210)
6559  
6560  #define PIPEB_PP_STATUS         (VLV_DISPLAY_BASE + 0x61300)
6561  #define PIPEB_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61304)
6562  #define PIPEB_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61308)
6563  #define PIPEB_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6130c)
6564  #define PIPEB_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61310)
6565  
6566  #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
6567  #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
6568  #define VLV_PIPE_PP_ON_DELAYS(pipe) \
6569  		_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
6570  #define VLV_PIPE_PP_OFF_DELAYS(pipe) \
6571  		_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
6572  #define VLV_PIPE_PP_DIVISOR(pipe) \
6573  		_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
6574  
6575  #define PCH_PP_STATUS		0xc7200
6576  #define PCH_PP_CONTROL		0xc7204
6577  #define  PANEL_UNLOCK_REGS	(0xabcd << 16)
6578  #define  PANEL_UNLOCK_MASK	(0xffff << 16)
6579  #define  BXT_POWER_CYCLE_DELAY_MASK	(0x1f0)
6580  #define  BXT_POWER_CYCLE_DELAY_SHIFT	4
6581  #define  EDP_FORCE_VDD		(1 << 3)
6582  #define  EDP_BLC_ENABLE		(1 << 2)
6583  #define  PANEL_POWER_RESET	(1 << 1)
6584  #define  PANEL_POWER_OFF	(0 << 0)
6585  #define  PANEL_POWER_ON		(1 << 0)
6586  #define PCH_PP_ON_DELAYS	0xc7208
6587  #define  PANEL_PORT_SELECT_MASK	(3 << 30)
6588  #define  PANEL_PORT_SELECT_LVDS	(0 << 30)
6589  #define  PANEL_PORT_SELECT_DPA	(1 << 30)
6590  #define  PANEL_PORT_SELECT_DPC	(2 << 30)
6591  #define  PANEL_PORT_SELECT_DPD	(3 << 30)
6592  #define  PANEL_POWER_UP_DELAY_MASK	(0x1fff0000)
6593  #define  PANEL_POWER_UP_DELAY_SHIFT	16
6594  #define  PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)
6595  #define  PANEL_LIGHT_ON_DELAY_SHIFT	0
6596  
6597  #define PCH_PP_OFF_DELAYS	0xc720c
6598  #define  PANEL_POWER_DOWN_DELAY_MASK	(0x1fff0000)
6599  #define  PANEL_POWER_DOWN_DELAY_SHIFT	16
6600  #define  PANEL_LIGHT_OFF_DELAY_MASK	(0x1fff)
6601  #define  PANEL_LIGHT_OFF_DELAY_SHIFT	0
6602  
6603  #define PCH_PP_DIVISOR		0xc7210
6604  #define  PP_REFERENCE_DIVIDER_MASK	(0xffffff00)
6605  #define  PP_REFERENCE_DIVIDER_SHIFT	8
6606  #define  PANEL_POWER_CYCLE_DELAY_MASK	(0x1f)
6607  #define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
6608  
6609  /* BXT PPS changes - 2nd set of PPS registers */
6610  #define _BXT_PP_STATUS2 	0xc7300
6611  #define _BXT_PP_CONTROL2 	0xc7304
6612  #define _BXT_PP_ON_DELAYS2	0xc7308
6613  #define _BXT_PP_OFF_DELAYS2	0xc730c
6614  
6615  #define BXT_PP_STATUS(n)	_PIPE(n, PCH_PP_STATUS, _BXT_PP_STATUS2)
6616  #define BXT_PP_CONTROL(n)	_PIPE(n, PCH_PP_CONTROL, _BXT_PP_CONTROL2)
6617  #define BXT_PP_ON_DELAYS(n)	_PIPE(n, PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2)
6618  #define BXT_PP_OFF_DELAYS(n)	_PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
6619  
6620  #define PCH_DP_B		0xe4100
6621  #define PCH_DPB_AUX_CH_CTL	0xe4110
6622  #define PCH_DPB_AUX_CH_DATA1	0xe4114
6623  #define PCH_DPB_AUX_CH_DATA2	0xe4118
6624  #define PCH_DPB_AUX_CH_DATA3	0xe411c
6625  #define PCH_DPB_AUX_CH_DATA4	0xe4120
6626  #define PCH_DPB_AUX_CH_DATA5	0xe4124
6627  
6628  #define PCH_DP_C		0xe4200
6629  #define PCH_DPC_AUX_CH_CTL	0xe4210
6630  #define PCH_DPC_AUX_CH_DATA1	0xe4214
6631  #define PCH_DPC_AUX_CH_DATA2	0xe4218
6632  #define PCH_DPC_AUX_CH_DATA3	0xe421c
6633  #define PCH_DPC_AUX_CH_DATA4	0xe4220
6634  #define PCH_DPC_AUX_CH_DATA5	0xe4224
6635  
6636  #define PCH_DP_D		0xe4300
6637  #define PCH_DPD_AUX_CH_CTL	0xe4310
6638  #define PCH_DPD_AUX_CH_DATA1	0xe4314
6639  #define PCH_DPD_AUX_CH_DATA2	0xe4318
6640  #define PCH_DPD_AUX_CH_DATA3	0xe431c
6641  #define PCH_DPD_AUX_CH_DATA4	0xe4320
6642  #define PCH_DPD_AUX_CH_DATA5	0xe4324
6643  
6644  /* CPT */
6645  #define  PORT_TRANS_A_SEL_CPT	0
6646  #define  PORT_TRANS_B_SEL_CPT	(1<<29)
6647  #define  PORT_TRANS_C_SEL_CPT	(2<<29)
6648  #define  PORT_TRANS_SEL_MASK	(3<<29)
6649  #define  PORT_TRANS_SEL_CPT(pipe)	((pipe) << 29)
6650  #define  PORT_TO_PIPE(val)	(((val) & (1<<30)) >> 30)
6651  #define  PORT_TO_PIPE_CPT(val)	(((val) & PORT_TRANS_SEL_MASK) >> 29)
6652  #define  SDVO_PORT_TO_PIPE_CHV(val)	(((val) & (3<<24)) >> 24)
6653  #define  DP_PORT_TO_PIPE_CHV(val)	(((val) & (3<<16)) >> 16)
6654  
6655  #define TRANS_DP_CTL_A		0xe0300
6656  #define TRANS_DP_CTL_B		0xe1300
6657  #define TRANS_DP_CTL_C		0xe2300
6658  #define TRANS_DP_CTL(pipe)	_PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
6659  #define  TRANS_DP_OUTPUT_ENABLE	(1<<31)
6660  #define  TRANS_DP_PORT_SEL_B	(0<<29)
6661  #define  TRANS_DP_PORT_SEL_C	(1<<29)
6662  #define  TRANS_DP_PORT_SEL_D	(2<<29)
6663  #define  TRANS_DP_PORT_SEL_NONE	(3<<29)
6664  #define  TRANS_DP_PORT_SEL_MASK	(3<<29)
6665  #define  TRANS_DP_PIPE_TO_PORT(val)	((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
6666  #define  TRANS_DP_AUDIO_ONLY	(1<<26)
6667  #define  TRANS_DP_ENH_FRAMING	(1<<18)
6668  #define  TRANS_DP_8BPC		(0<<9)
6669  #define  TRANS_DP_10BPC		(1<<9)
6670  #define  TRANS_DP_6BPC		(2<<9)
6671  #define  TRANS_DP_12BPC		(3<<9)
6672  #define  TRANS_DP_BPC_MASK	(3<<9)
6673  #define  TRANS_DP_VSYNC_ACTIVE_HIGH	(1<<4)
6674  #define  TRANS_DP_VSYNC_ACTIVE_LOW	0
6675  #define  TRANS_DP_HSYNC_ACTIVE_HIGH	(1<<3)
6676  #define  TRANS_DP_HSYNC_ACTIVE_LOW	0
6677  #define  TRANS_DP_SYNC_MASK	(3<<3)
6678  
6679  /* SNB eDP training params */
6680  /* SNB A-stepping */
6681  #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
6682  #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
6683  #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
6684  #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
6685  /* SNB B-stepping */
6686  #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0<<22)
6687  #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1<<22)
6688  #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a<<22)
6689  #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39<<22)
6690  #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38<<22)
6691  #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f<<22)
6692  
6693  /* IVB */
6694  #define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 <<22)
6695  #define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a <<22)
6696  #define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f <<22)
6697  #define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 <<22)
6698  #define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 <<22)
6699  #define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 <<22)
6700  #define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x3e <<22)
6701  
6702  /* legacy values */
6703  #define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 <<22)
6704  #define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 <<22)
6705  #define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 <<22)
6706  #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 <<22)
6707  #define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 <<22)
6708  
6709  #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f<<22)
6710  
6711  #define  VLV_PMWGICZ				0x1300a4
6712  
6713  #define  FORCEWAKE				0xA18C
6714  #define  FORCEWAKE_VLV				0x1300b0
6715  #define  FORCEWAKE_ACK_VLV			0x1300b4
6716  #define  FORCEWAKE_MEDIA_VLV			0x1300b8
6717  #define  FORCEWAKE_ACK_MEDIA_VLV		0x1300bc
6718  #define  FORCEWAKE_ACK_HSW			0x130044
6719  #define  FORCEWAKE_ACK				0x130090
6720  #define  VLV_GTLC_WAKE_CTRL			0x130090
6721  #define   VLV_GTLC_RENDER_CTX_EXISTS		(1 << 25)
6722  #define   VLV_GTLC_MEDIA_CTX_EXISTS		(1 << 24)
6723  #define   VLV_GTLC_ALLOWWAKEREQ			(1 << 0)
6724  
6725  #define  VLV_GTLC_PW_STATUS			0x130094
6726  #define   VLV_GTLC_ALLOWWAKEACK			(1 << 0)
6727  #define   VLV_GTLC_ALLOWWAKEERR			(1 << 1)
6728  #define   VLV_GTLC_PW_MEDIA_STATUS_MASK		(1 << 5)
6729  #define   VLV_GTLC_PW_RENDER_STATUS_MASK	(1 << 7)
6730  #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
6731  #define  FORCEWAKE_MEDIA_GEN9			0xa270
6732  #define  FORCEWAKE_RENDER_GEN9			0xa278
6733  #define  FORCEWAKE_BLITTER_GEN9			0xa188
6734  #define  FORCEWAKE_ACK_MEDIA_GEN9		0x0D88
6735  #define  FORCEWAKE_ACK_RENDER_GEN9		0x0D84
6736  #define  FORCEWAKE_ACK_BLITTER_GEN9		0x130044
6737  #define   FORCEWAKE_KERNEL			0x1
6738  #define   FORCEWAKE_USER			0x2
6739  #define  FORCEWAKE_MT_ACK			0x130040
6740  #define  ECOBUS					0xa180
6741  #define    FORCEWAKE_MT_ENABLE			(1<<5)
6742  #define  VLV_SPAREG2H				0xA194
6743  
6744  #define  GTFIFODBG				0x120000
6745  #define    GT_FIFO_SBDROPERR			(1<<6)
6746  #define    GT_FIFO_BLOBDROPERR			(1<<5)
6747  #define    GT_FIFO_SB_READ_ABORTERR		(1<<4)
6748  #define    GT_FIFO_DROPERR			(1<<3)
6749  #define    GT_FIFO_OVFERR			(1<<2)
6750  #define    GT_FIFO_IAWRERR			(1<<1)
6751  #define    GT_FIFO_IARDERR			(1<<0)
6752  
6753  #define  GTFIFOCTL				0x120008
6754  #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
6755  #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
6756  #define    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
6757  #define    GT_FIFO_CTL_RC6_POLICY_STALL		(1 << 11)
6758  
6759  #define  HSW_IDICR				0x9008
6760  #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
6761  #define  HSW_EDRAM_PRESENT			0x120010
6762  #define    EDRAM_ENABLED			0x1
6763  
6764  #define GEN6_UCGCTL1				0x9400
6765  # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
6766  # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
6767  # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
6768  
6769  #define GEN6_UCGCTL2				0x9404
6770  # define GEN6_VFUNIT_CLOCK_GATE_DISABLE			(1 << 31)
6771  # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
6772  # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
6773  # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
6774  # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
6775  # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
6776  
6777  #define GEN6_UCGCTL3				0x9408
6778  
6779  #define GEN7_UCGCTL4				0x940c
6780  #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1<<25)
6781  
6782  #define GEN6_RCGCTL1				0x9410
6783  #define GEN6_RCGCTL2				0x9414
6784  #define GEN6_RSTCTL				0x9420
6785  
6786  #define GEN8_UCGCTL6				0x9430
6787  #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)
6788  #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
6789  #define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
6790  
6791  #define GEN6_GFXPAUSE				0xA000
6792  #define GEN6_RPNSWREQ				0xA008
6793  #define   GEN6_TURBO_DISABLE			(1<<31)
6794  #define   GEN6_FREQUENCY(x)			((x)<<25)
6795  #define   HSW_FREQUENCY(x)			((x)<<24)
6796  #define   GEN9_FREQUENCY(x)			((x)<<23)
6797  #define   GEN6_OFFSET(x)			((x)<<19)
6798  #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
6799  #define GEN6_RC_VIDEO_FREQ			0xA00C
6800  #define GEN6_RC_CONTROL				0xA090
6801  #define   GEN6_RC_CTL_RC6pp_ENABLE		(1<<16)
6802  #define   GEN6_RC_CTL_RC6p_ENABLE		(1<<17)
6803  #define   GEN6_RC_CTL_RC6_ENABLE		(1<<18)
6804  #define   GEN6_RC_CTL_RC1e_ENABLE		(1<<20)
6805  #define   GEN6_RC_CTL_RC7_ENABLE		(1<<22)
6806  #define   VLV_RC_CTL_CTX_RST_PARALLEL		(1<<24)
6807  #define   GEN7_RC_CTL_TO_MODE			(1<<28)
6808  #define   GEN6_RC_CTL_EI_MODE(x)		((x)<<27)
6809  #define   GEN6_RC_CTL_HW_ENABLE			(1<<31)
6810  #define GEN6_RP_DOWN_TIMEOUT			0xA010
6811  #define GEN6_RP_INTERRUPT_LIMITS		0xA014
6812  #define GEN6_RPSTAT1				0xA01C
6813  #define   GEN6_CAGF_SHIFT			8
6814  #define   HSW_CAGF_SHIFT			7
6815  #define   GEN9_CAGF_SHIFT			23
6816  #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
6817  #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
6818  #define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
6819  #define GEN6_RP_CONTROL				0xA024
6820  #define   GEN6_RP_MEDIA_TURBO			(1<<11)
6821  #define   GEN6_RP_MEDIA_MODE_MASK		(3<<9)
6822  #define   GEN6_RP_MEDIA_HW_TURBO_MODE		(3<<9)
6823  #define   GEN6_RP_MEDIA_HW_NORMAL_MODE		(2<<9)
6824  #define   GEN6_RP_MEDIA_HW_MODE			(1<<9)
6825  #define   GEN6_RP_MEDIA_SW_MODE			(0<<9)
6826  #define   GEN6_RP_MEDIA_IS_GFX			(1<<8)
6827  #define   GEN6_RP_ENABLE			(1<<7)
6828  #define   GEN6_RP_UP_IDLE_MIN			(0x1<<3)
6829  #define   GEN6_RP_UP_BUSY_AVG			(0x2<<3)
6830  #define   GEN6_RP_UP_BUSY_CONT			(0x4<<3)
6831  #define   GEN6_RP_DOWN_IDLE_AVG			(0x2<<0)
6832  #define   GEN6_RP_DOWN_IDLE_CONT		(0x1<<0)
6833  #define GEN6_RP_UP_THRESHOLD			0xA02C
6834  #define GEN6_RP_DOWN_THRESHOLD			0xA030
6835  #define GEN6_RP_CUR_UP_EI			0xA050
6836  #define   GEN6_CURICONT_MASK			0xffffff
6837  #define GEN6_RP_CUR_UP				0xA054
6838  #define   GEN6_CURBSYTAVG_MASK			0xffffff
6839  #define GEN6_RP_PREV_UP				0xA058
6840  #define GEN6_RP_CUR_DOWN_EI			0xA05C
6841  #define   GEN6_CURIAVG_MASK			0xffffff
6842  #define GEN6_RP_CUR_DOWN			0xA060
6843  #define GEN6_RP_PREV_DOWN			0xA064
6844  #define GEN6_RP_UP_EI				0xA068
6845  #define GEN6_RP_DOWN_EI				0xA06C
6846  #define GEN6_RP_IDLE_HYSTERSIS			0xA070
6847  #define GEN6_RPDEUHWTC				0xA080
6848  #define GEN6_RPDEUC				0xA084
6849  #define GEN6_RPDEUCSW				0xA088
6850  #define GEN6_RC_STATE				0xA094
6851  #define GEN6_RC1_WAKE_RATE_LIMIT		0xA098
6852  #define GEN6_RC6_WAKE_RATE_LIMIT		0xA09C
6853  #define GEN6_RC6pp_WAKE_RATE_LIMIT		0xA0A0
6854  #define GEN6_RC_EVALUATION_INTERVAL		0xA0A8
6855  #define GEN6_RC_IDLE_HYSTERSIS			0xA0AC
6856  #define GEN6_RC_SLEEP				0xA0B0
6857  #define GEN6_RCUBMABDTMR			0xA0B0
6858  #define GEN6_RC1e_THRESHOLD			0xA0B4
6859  #define GEN6_RC6_THRESHOLD			0xA0B8
6860  #define GEN6_RC6p_THRESHOLD			0xA0BC
6861  #define VLV_RCEDATA				0xA0BC
6862  #define GEN6_RC6pp_THRESHOLD			0xA0C0
6863  #define GEN6_PMINTRMSK				0xA168
6864  #define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
6865  #define VLV_PWRDWNUPCTL				0xA294
6866  #define GEN9_MEDIA_PG_IDLE_HYSTERESIS		0xA0C4
6867  #define GEN9_RENDER_PG_IDLE_HYSTERESIS		0xA0C8
6868  #define GEN9_PG_ENABLE				0xA210
6869  #define GEN9_RENDER_PG_ENABLE			(1<<0)
6870  #define GEN9_MEDIA_PG_ENABLE			(1<<1)
6871  
6872  #define VLV_CHICKEN_3				(VLV_DISPLAY_BASE + 0x7040C)
6873  #define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
6874  #define  PIXEL_OVERLAP_CNT_SHIFT		30
6875  
6876  #define GEN6_PMISR				0x44020
6877  #define GEN6_PMIMR				0x44024 /* rps_lock */
6878  #define GEN6_PMIIR				0x44028
6879  #define GEN6_PMIER				0x4402C
6880  #define  GEN6_PM_MBOX_EVENT			(1<<25)
6881  #define  GEN6_PM_THERMAL_EVENT			(1<<24)
6882  #define  GEN6_PM_RP_DOWN_TIMEOUT		(1<<6)
6883  #define  GEN6_PM_RP_UP_THRESHOLD		(1<<5)
6884  #define  GEN6_PM_RP_DOWN_THRESHOLD		(1<<4)
6885  #define  GEN6_PM_RP_UP_EI_EXPIRED		(1<<2)
6886  #define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1<<1)
6887  #define  GEN6_PM_RPS_EVENTS			(GEN6_PM_RP_UP_THRESHOLD | \
6888  						 GEN6_PM_RP_DOWN_THRESHOLD | \
6889  						 GEN6_PM_RP_DOWN_TIMEOUT)
6890  
6891  #define GEN7_GT_SCRATCH(i)			(0x4F100 + (i) * 4)
6892  #define GEN7_GT_SCRATCH_REG_NUM			8
6893  
6894  #define VLV_GTLC_SURVIVABILITY_REG              0x130098
6895  #define VLV_GFX_CLK_STATUS_BIT			(1<<3)
6896  #define VLV_GFX_CLK_FORCE_ON_BIT		(1<<2)
6897  
6898  #define GEN6_GT_GFX_RC6_LOCKED			0x138104
6899  #define VLV_COUNTER_CONTROL			0x138104
6900  #define   VLV_COUNT_RANGE_HIGH			(1<<15)
6901  #define   VLV_MEDIA_RC0_COUNT_EN		(1<<5)
6902  #define   VLV_RENDER_RC0_COUNT_EN		(1<<4)
6903  #define   VLV_MEDIA_RC6_COUNT_EN		(1<<1)
6904  #define   VLV_RENDER_RC6_COUNT_EN		(1<<0)
6905  #define GEN6_GT_GFX_RC6				0x138108
6906  #define VLV_GT_RENDER_RC6			0x138108
6907  #define VLV_GT_MEDIA_RC6			0x13810C
6908  
6909  #define GEN6_GT_GFX_RC6p			0x13810C
6910  #define GEN6_GT_GFX_RC6pp			0x138110
6911  #define VLV_RENDER_C0_COUNT			0x138118
6912  #define VLV_MEDIA_C0_COUNT			0x13811C
6913  
6914  #define GEN6_PCODE_MAILBOX			0x138124
6915  #define   GEN6_PCODE_READY			(1<<31)
6916  #define	  GEN6_PCODE_WRITE_RC6VIDS		0x4
6917  #define	  GEN6_PCODE_READ_RC6VIDS		0x5
6918  #define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
6919  #define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
6920  #define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
6921  #define   GEN9_PCODE_READ_MEM_LATENCY		0x6
6922  #define     GEN9_MEM_LATENCY_LEVEL_MASK		0xFF
6923  #define     GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT	8
6924  #define     GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT	16
6925  #define     GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT	24
6926  #define   SKL_PCODE_CDCLK_CONTROL		0x7
6927  #define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
6928  #define     SKL_CDCLK_READY_FOR_CHANGE		0x1
6929  #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
6930  #define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
6931  #define   GEN6_READ_OC_PARAMS			0xc
6932  #define   GEN6_PCODE_READ_D_COMP		0x10
6933  #define   GEN6_PCODE_WRITE_D_COMP		0x11
6934  #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
6935  #define   DISPLAY_IPS_CONTROL			0x19
6936  #define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
6937  #define GEN6_PCODE_DATA				0x138128
6938  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
6939  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
6940  #define GEN6_PCODE_DATA1			0x13812C
6941  
6942  #define GEN6_GT_CORE_STATUS		0x138060
6943  #define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
6944  #define   GEN6_RCn_MASK			7
6945  #define   GEN6_RC0			0
6946  #define   GEN6_RC3			2
6947  #define   GEN6_RC6			3
6948  #define   GEN6_RC7			4
6949  
6950  #define GEN8_GT_SLICE_INFO		0x138064
6951  #define   GEN8_LSLICESTAT_MASK		0x7
6952  
6953  #define CHV_POWER_SS0_SIG1		0xa720
6954  #define CHV_POWER_SS1_SIG1		0xa728
6955  #define   CHV_SS_PG_ENABLE		(1<<1)
6956  #define   CHV_EU08_PG_ENABLE		(1<<9)
6957  #define   CHV_EU19_PG_ENABLE		(1<<17)
6958  #define   CHV_EU210_PG_ENABLE		(1<<25)
6959  
6960  #define CHV_POWER_SS0_SIG2		0xa724
6961  #define CHV_POWER_SS1_SIG2		0xa72c
6962  #define   CHV_EU311_PG_ENABLE		(1<<1)
6963  
6964  #define GEN9_SLICE_PGCTL_ACK(slice)	(0x804c + (slice)*0x4)
6965  #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
6966  #define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice)*2))
6967  
6968  #define GEN9_SS01_EU_PGCTL_ACK(slice)	(0x805c + (slice)*0x8)
6969  #define GEN9_SS23_EU_PGCTL_ACK(slice)	(0x8060 + (slice)*0x8)
6970  #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
6971  #define   GEN9_PGCTL_SSA_EU19_ACK	(1 << 2)
6972  #define   GEN9_PGCTL_SSA_EU210_ACK	(1 << 4)
6973  #define   GEN9_PGCTL_SSA_EU311_ACK	(1 << 6)
6974  #define   GEN9_PGCTL_SSB_EU08_ACK	(1 << 8)
6975  #define   GEN9_PGCTL_SSB_EU19_ACK	(1 << 10)
6976  #define   GEN9_PGCTL_SSB_EU210_ACK	(1 << 12)
6977  #define   GEN9_PGCTL_SSB_EU311_ACK	(1 << 14)
6978  
6979  #define GEN7_MISCCPCTL			(0x9424)
6980  #define   GEN7_DOP_CLOCK_GATE_ENABLE		(1<<0)
6981  #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1<<2)
6982  #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1<<4)
6983  #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1<<6)
6984  
6985  #define GEN8_GARBCNTL                   0xB004
6986  #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
6987  
6988  /* IVYBRIDGE DPF */
6989  #define GEN7_L3CDERRST1			0xB008 /* L3CD Error Status 1 */
6990  #define HSW_L3CDERRST11			0xB208 /* L3CD Error Status register 1 slice 1 */
6991  #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
6992  #define   GEN7_PARITY_ERROR_VALID	(1<<13)
6993  #define   GEN7_L3CDERRST1_BANK_MASK	(3<<11)
6994  #define   GEN7_L3CDERRST1_SUBBANK_MASK	(7<<8)
6995  #define GEN7_PARITY_ERROR_ROW(reg) \
6996  		((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
6997  #define GEN7_PARITY_ERROR_BANK(reg) \
6998  		((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
6999  #define GEN7_PARITY_ERROR_SUBBANK(reg) \
7000  		((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
7001  #define   GEN7_L3CDERRST1_ENABLE	(1<<7)
7002  
7003  #define GEN7_L3LOG_BASE			0xB070
7004  #define HSW_L3LOG_BASE_SLICE1		0xB270
7005  #define GEN7_L3LOG_SIZE			0x80
7006  
7007  #define GEN7_HALF_SLICE_CHICKEN1	0xe100 /* IVB GT1 + VLV */
7008  #define GEN7_HALF_SLICE_CHICKEN1_GT2	0xf100
7009  #define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
7010  #define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1<<10)
7011  #define   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE	(1<<4)
7012  #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
7013  
7014  #define GEN9_HALF_SLICE_CHICKEN5	0xe188
7015  #define   GEN9_DG_MIRROR_FIX_ENABLE	(1<<5)
7016  #define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1<<3)
7017  
7018  #define GEN8_ROW_CHICKEN		0xe4f0
7019  #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
7020  #define   STALL_DOP_GATING_DISABLE		(1<<5)
7021  
7022  #define GEN7_ROW_CHICKEN2		0xe4f4
7023  #define GEN7_ROW_CHICKEN2_GT2		0xf4f4
7024  #define   DOP_CLOCK_GATING_DISABLE	(1<<0)
7025  
7026  #define HSW_ROW_CHICKEN3		0xe49c
7027  #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
7028  
7029  #define HALF_SLICE_CHICKEN2		0xe180
7030  #define   GEN8_ST_PO_DISABLE		(1<<13)
7031  
7032  #define HALF_SLICE_CHICKEN3		0xe184
7033  #define   HSW_SAMPLE_C_PERFORMANCE	(1<<9)
7034  #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
7035  #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC	(1<<5)
7036  #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1<<1)
7037  
7038  #define GEN9_HALF_SLICE_CHICKEN7	0xe194
7039  #define   GEN9_ENABLE_YV12_BUGFIX	(1<<4)
7040  
7041  /* Audio */
7042  #define G4X_AUD_VID_DID			(dev_priv->info.display_mmio_offset + 0x62020)
7043  #define   INTEL_AUDIO_DEVCL		0x808629FB
7044  #define   INTEL_AUDIO_DEVBLC		0x80862801
7045  #define   INTEL_AUDIO_DEVCTG		0x80862802
7046  
7047  #define G4X_AUD_CNTL_ST			0x620B4
7048  #define   G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
7049  #define   G4X_ELDV_DEVCTG		(1 << 14)
7050  #define   G4X_ELD_ADDR_MASK		(0xf << 5)
7051  #define   G4X_ELD_ACK			(1 << 4)
7052  #define G4X_HDMIW_HDMIEDID		0x6210C
7053  
7054  #define _IBX_HDMIW_HDMIEDID_A		0xE2050
7055  #define _IBX_HDMIW_HDMIEDID_B		0xE2150
7056  #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
7057  					_IBX_HDMIW_HDMIEDID_A, \
7058  					_IBX_HDMIW_HDMIEDID_B)
7059  #define _IBX_AUD_CNTL_ST_A		0xE20B4
7060  #define _IBX_AUD_CNTL_ST_B		0xE21B4
7061  #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
7062  					_IBX_AUD_CNTL_ST_A, \
7063  					_IBX_AUD_CNTL_ST_B)
7064  #define   IBX_ELD_BUFFER_SIZE_MASK	(0x1f << 10)
7065  #define   IBX_ELD_ADDRESS_MASK		(0x1f << 5)
7066  #define   IBX_ELD_ACK			(1 << 4)
7067  #define IBX_AUD_CNTL_ST2		0xE20C0
7068  #define   IBX_CP_READY(port)		((1 << 1) << (((port) - 1) * 4))
7069  #define   IBX_ELD_VALID(port)		((1 << 0) << (((port) - 1) * 4))
7070  
7071  #define _CPT_HDMIW_HDMIEDID_A		0xE5050
7072  #define _CPT_HDMIW_HDMIEDID_B		0xE5150
7073  #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
7074  					_CPT_HDMIW_HDMIEDID_A, \
7075  					_CPT_HDMIW_HDMIEDID_B)
7076  #define _CPT_AUD_CNTL_ST_A		0xE50B4
7077  #define _CPT_AUD_CNTL_ST_B		0xE51B4
7078  #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
7079  					_CPT_AUD_CNTL_ST_A, \
7080  					_CPT_AUD_CNTL_ST_B)
7081  #define CPT_AUD_CNTRL_ST2		0xE50C0
7082  
7083  #define _VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
7084  #define _VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
7085  #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
7086  					_VLV_HDMIW_HDMIEDID_A, \
7087  					_VLV_HDMIW_HDMIEDID_B)
7088  #define _VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
7089  #define _VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
7090  #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
7091  					_VLV_AUD_CNTL_ST_A, \
7092  					_VLV_AUD_CNTL_ST_B)
7093  #define VLV_AUD_CNTL_ST2		(VLV_DISPLAY_BASE + 0x620C0)
7094  
7095  /* These are the 4 32-bit write offset registers for each stream
7096   * output buffer.  It determines the offset from the
7097   * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
7098   */
7099  #define GEN7_SO_WRITE_OFFSET(n)		(0x5280 + (n) * 4)
7100  
7101  #define _IBX_AUD_CONFIG_A		0xe2000
7102  #define _IBX_AUD_CONFIG_B		0xe2100
7103  #define IBX_AUD_CFG(pipe) _PIPE(pipe, \
7104  					_IBX_AUD_CONFIG_A, \
7105  					_IBX_AUD_CONFIG_B)
7106  #define _CPT_AUD_CONFIG_A		0xe5000
7107  #define _CPT_AUD_CONFIG_B		0xe5100
7108  #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
7109  					_CPT_AUD_CONFIG_A, \
7110  					_CPT_AUD_CONFIG_B)
7111  #define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
7112  #define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
7113  #define VLV_AUD_CFG(pipe) _PIPE(pipe, \
7114  					_VLV_AUD_CONFIG_A, \
7115  					_VLV_AUD_CONFIG_B)
7116  
7117  #define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
7118  #define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
7119  #define   AUD_CONFIG_UPPER_N_SHIFT		20
7120  #define   AUD_CONFIG_UPPER_N_MASK		(0xff << 20)
7121  #define   AUD_CONFIG_LOWER_N_SHIFT		4
7122  #define   AUD_CONFIG_LOWER_N_MASK		(0xfff << 4)
7123  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16
7124  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK	(0xf << 16)
7125  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175	(0 << 16)
7126  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25200	(1 << 16)
7127  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27000	(2 << 16)
7128  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27027	(3 << 16)
7129  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54000	(4 << 16)
7130  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54054	(5 << 16)
7131  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74176	(6 << 16)
7132  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250	(7 << 16)
7133  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352	(8 << 16)
7134  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500	(9 << 16)
7135  #define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
7136  
7137  /* HSW Audio */
7138  #define _HSW_AUD_CONFIG_A		0x65000
7139  #define _HSW_AUD_CONFIG_B		0x65100
7140  #define HSW_AUD_CFG(pipe) _PIPE(pipe, \
7141  					_HSW_AUD_CONFIG_A, \
7142  					_HSW_AUD_CONFIG_B)
7143  
7144  #define _HSW_AUD_MISC_CTRL_A		0x65010
7145  #define _HSW_AUD_MISC_CTRL_B		0x65110
7146  #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
7147  					_HSW_AUD_MISC_CTRL_A, \
7148  					_HSW_AUD_MISC_CTRL_B)
7149  
7150  #define _HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4
7151  #define _HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4
7152  #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
7153  					_HSW_AUD_DIP_ELD_CTRL_ST_A, \
7154  					_HSW_AUD_DIP_ELD_CTRL_ST_B)
7155  
7156  /* Audio Digital Converter */
7157  #define _HSW_AUD_DIG_CNVT_1		0x65080
7158  #define _HSW_AUD_DIG_CNVT_2		0x65180
7159  #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
7160  					_HSW_AUD_DIG_CNVT_1, \
7161  					_HSW_AUD_DIG_CNVT_2)
7162  #define DIP_PORT_SEL_MASK		0x3
7163  
7164  #define _HSW_AUD_EDID_DATA_A		0x65050
7165  #define _HSW_AUD_EDID_DATA_B		0x65150
7166  #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
7167  					_HSW_AUD_EDID_DATA_A, \
7168  					_HSW_AUD_EDID_DATA_B)
7169  
7170  #define HSW_AUD_PIPE_CONV_CFG		0x6507c
7171  #define HSW_AUD_PIN_ELD_CP_VLD		0x650c0
7172  #define   AUDIO_INACTIVE(trans)		((1 << 3) << ((trans) * 4))
7173  #define   AUDIO_OUTPUT_ENABLE(trans)	((1 << 2) << ((trans) * 4))
7174  #define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
7175  #define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
7176  
7177  #define HSW_AUD_CHICKENBIT			0x65f10
7178  #define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
7179  
7180  /* HSW Power Wells */
7181  #define HSW_PWR_WELL_BIOS			0x45400 /* CTL1 */
7182  #define HSW_PWR_WELL_DRIVER			0x45404 /* CTL2 */
7183  #define HSW_PWR_WELL_KVMR			0x45408 /* CTL3 */
7184  #define HSW_PWR_WELL_DEBUG			0x4540C /* CTL4 */
7185  #define   HSW_PWR_WELL_ENABLE_REQUEST		(1<<31)
7186  #define   HSW_PWR_WELL_STATE_ENABLED		(1<<30)
7187  #define HSW_PWR_WELL_CTL5			0x45410
7188  #define   HSW_PWR_WELL_ENABLE_SINGLE_STEP	(1<<31)
7189  #define   HSW_PWR_WELL_PWR_GATE_OVERRIDE	(1<<20)
7190  #define   HSW_PWR_WELL_FORCE_ON			(1<<19)
7191  #define HSW_PWR_WELL_CTL6			0x45414
7192  
7193  /* SKL Fuse Status */
7194  #define SKL_FUSE_STATUS				0x42000
7195  #define  SKL_FUSE_DOWNLOAD_STATUS              (1<<31)
7196  #define  SKL_FUSE_PG0_DIST_STATUS              (1<<27)
7197  #define  SKL_FUSE_PG1_DIST_STATUS              (1<<26)
7198  #define  SKL_FUSE_PG2_DIST_STATUS              (1<<25)
7199  
7200  /* Per-pipe DDI Function Control */
7201  #define TRANS_DDI_FUNC_CTL_A		0x60400
7202  #define TRANS_DDI_FUNC_CTL_B		0x61400
7203  #define TRANS_DDI_FUNC_CTL_C		0x62400
7204  #define TRANS_DDI_FUNC_CTL_EDP		0x6F400
7205  #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
7206  
7207  #define  TRANS_DDI_FUNC_ENABLE		(1<<31)
7208  /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
7209  #define  TRANS_DDI_PORT_MASK		(7<<28)
7210  #define  TRANS_DDI_PORT_SHIFT		28
7211  #define  TRANS_DDI_SELECT_PORT(x)	((x)<<28)
7212  #define  TRANS_DDI_PORT_NONE		(0<<28)
7213  #define  TRANS_DDI_MODE_SELECT_MASK	(7<<24)
7214  #define  TRANS_DDI_MODE_SELECT_HDMI	(0<<24)
7215  #define  TRANS_DDI_MODE_SELECT_DVI	(1<<24)
7216  #define  TRANS_DDI_MODE_SELECT_DP_SST	(2<<24)
7217  #define  TRANS_DDI_MODE_SELECT_DP_MST	(3<<24)
7218  #define  TRANS_DDI_MODE_SELECT_FDI	(4<<24)
7219  #define  TRANS_DDI_BPC_MASK		(7<<20)
7220  #define  TRANS_DDI_BPC_8		(0<<20)
7221  #define  TRANS_DDI_BPC_10		(1<<20)
7222  #define  TRANS_DDI_BPC_6		(2<<20)
7223  #define  TRANS_DDI_BPC_12		(3<<20)
7224  #define  TRANS_DDI_PVSYNC		(1<<17)
7225  #define  TRANS_DDI_PHSYNC		(1<<16)
7226  #define  TRANS_DDI_EDP_INPUT_MASK	(7<<12)
7227  #define  TRANS_DDI_EDP_INPUT_A_ON	(0<<12)
7228  #define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4<<12)
7229  #define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5<<12)
7230  #define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6<<12)
7231  #define  TRANS_DDI_DP_VC_PAYLOAD_ALLOC	(1<<8)
7232  #define  TRANS_DDI_BFI_ENABLE		(1<<4)
7233  
7234  /* DisplayPort Transport Control */
7235  #define DP_TP_CTL_A			0x64040
7236  #define DP_TP_CTL_B			0x64140
7237  #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
7238  #define  DP_TP_CTL_ENABLE			(1<<31)
7239  #define  DP_TP_CTL_MODE_SST			(0<<27)
7240  #define  DP_TP_CTL_MODE_MST			(1<<27)
7241  #define  DP_TP_CTL_FORCE_ACT			(1<<25)
7242  #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE	(1<<18)
7243  #define  DP_TP_CTL_FDI_AUTOTRAIN		(1<<15)
7244  #define  DP_TP_CTL_LINK_TRAIN_MASK		(7<<8)
7245  #define  DP_TP_CTL_LINK_TRAIN_PAT1		(0<<8)
7246  #define  DP_TP_CTL_LINK_TRAIN_PAT2		(1<<8)
7247  #define  DP_TP_CTL_LINK_TRAIN_PAT3		(4<<8)
7248  #define  DP_TP_CTL_LINK_TRAIN_IDLE		(2<<8)
7249  #define  DP_TP_CTL_LINK_TRAIN_NORMAL		(3<<8)
7250  #define  DP_TP_CTL_SCRAMBLE_DISABLE		(1<<7)
7251  
7252  /* DisplayPort Transport Status */
7253  #define DP_TP_STATUS_A			0x64044
7254  #define DP_TP_STATUS_B			0x64144
7255  #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
7256  #define  DP_TP_STATUS_IDLE_DONE			(1<<25)
7257  #define  DP_TP_STATUS_ACT_SENT			(1<<24)
7258  #define  DP_TP_STATUS_MODE_STATUS_MST		(1<<23)
7259  #define  DP_TP_STATUS_AUTOTRAIN_DONE		(1<<12)
7260  #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC2	(3 << 8)
7261  #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC1	(3 << 4)
7262  #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC0	(3 << 0)
7263  
7264  /* DDI Buffer Control */
7265  #define DDI_BUF_CTL_A				0x64000
7266  #define DDI_BUF_CTL_B				0x64100
7267  #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
7268  #define  DDI_BUF_CTL_ENABLE			(1<<31)
7269  #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
7270  #define  DDI_BUF_EMP_MASK			(0xf<<24)
7271  #define  DDI_BUF_PORT_REVERSAL			(1<<16)
7272  #define  DDI_BUF_IS_IDLE			(1<<7)
7273  #define  DDI_A_4_LANES				(1<<4)
7274  #define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
7275  #define  DDI_PORT_WIDTH_MASK			(7 << 1)
7276  #define  DDI_PORT_WIDTH_SHIFT			1
7277  #define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
7278  
7279  /* DDI Buffer Translations */
7280  #define DDI_BUF_TRANS_A				0x64E00
7281  #define DDI_BUF_TRANS_B				0x64E60
7282  #define DDI_BUF_TRANS_LO(port, i) (_PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) + (i) * 8)
7283  #define DDI_BUF_TRANS_HI(port, i) (_PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) + (i) * 8 + 4)
7284  
7285  /* Sideband Interface (SBI) is programmed indirectly, via
7286   * SBI_ADDR, which contains the register offset; and SBI_DATA,
7287   * which contains the payload */
7288  #define SBI_ADDR			0xC6000
7289  #define SBI_DATA			0xC6004
7290  #define SBI_CTL_STAT			0xC6008
7291  #define  SBI_CTL_DEST_ICLK		(0x0<<16)
7292  #define  SBI_CTL_DEST_MPHY		(0x1<<16)
7293  #define  SBI_CTL_OP_IORD		(0x2<<8)
7294  #define  SBI_CTL_OP_IOWR		(0x3<<8)
7295  #define  SBI_CTL_OP_CRRD		(0x6<<8)
7296  #define  SBI_CTL_OP_CRWR		(0x7<<8)
7297  #define  SBI_RESPONSE_FAIL		(0x1<<1)
7298  #define  SBI_RESPONSE_SUCCESS		(0x0<<1)
7299  #define  SBI_BUSY			(0x1<<0)
7300  #define  SBI_READY			(0x0<<0)
7301  
7302  /* SBI offsets */
7303  #define  SBI_SSCDIVINTPHASE6			0x0600
7304  #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	((0x7f)<<1)
7305  #define   SBI_SSCDIVINTPHASE_DIVSEL(x)		((x)<<1)
7306  #define   SBI_SSCDIVINTPHASE_INCVAL_MASK	((0x7f)<<8)
7307  #define   SBI_SSCDIVINTPHASE_INCVAL(x)		((x)<<8)
7308  #define   SBI_SSCDIVINTPHASE_DIR(x)		((x)<<15)
7309  #define   SBI_SSCDIVINTPHASE_PROPAGATE		(1<<0)
7310  #define  SBI_SSCCTL				0x020c
7311  #define  SBI_SSCCTL6				0x060C
7312  #define   SBI_SSCCTL_PATHALT			(1<<3)
7313  #define   SBI_SSCCTL_DISABLE			(1<<0)
7314  #define  SBI_SSCAUXDIV6				0x0610
7315  #define   SBI_SSCAUXDIV_FINALDIV2SEL(x)		((x)<<4)
7316  #define  SBI_DBUFF0				0x2a00
7317  #define  SBI_GEN0				0x1f00
7318  #define   SBI_GEN0_CFG_BUFFENABLE_DISABLE	(1<<0)
7319  
7320  /* LPT PIXCLK_GATE */
7321  #define PIXCLK_GATE			0xC6020
7322  #define  PIXCLK_GATE_UNGATE		(1<<0)
7323  #define  PIXCLK_GATE_GATE		(0<<0)
7324  
7325  /* SPLL */
7326  #define SPLL_CTL			0x46020
7327  #define  SPLL_PLL_ENABLE		(1<<31)
7328  #define  SPLL_PLL_SSC			(1<<28)
7329  #define  SPLL_PLL_NON_SSC		(2<<28)
7330  #define  SPLL_PLL_LCPLL			(3<<28)
7331  #define  SPLL_PLL_REF_MASK		(3<<28)
7332  #define  SPLL_PLL_FREQ_810MHz		(0<<26)
7333  #define  SPLL_PLL_FREQ_1350MHz		(1<<26)
7334  #define  SPLL_PLL_FREQ_2700MHz		(2<<26)
7335  #define  SPLL_PLL_FREQ_MASK		(3<<26)
7336  
7337  /* WRPLL */
7338  #define WRPLL_CTL1			0x46040
7339  #define WRPLL_CTL2			0x46060
7340  #define WRPLL_CTL(pll)			(pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
7341  #define  WRPLL_PLL_ENABLE		(1<<31)
7342  #define  WRPLL_PLL_SSC			(1<<28)
7343  #define  WRPLL_PLL_NON_SSC		(2<<28)
7344  #define  WRPLL_PLL_LCPLL		(3<<28)
7345  #define  WRPLL_PLL_REF_MASK		(3<<28)
7346  /* WRPLL divider programming */
7347  #define  WRPLL_DIVIDER_REFERENCE(x)	((x)<<0)
7348  #define  WRPLL_DIVIDER_REF_MASK		(0xff)
7349  #define  WRPLL_DIVIDER_POST(x)		((x)<<8)
7350  #define  WRPLL_DIVIDER_POST_MASK	(0x3f<<8)
7351  #define  WRPLL_DIVIDER_POST_SHIFT	8
7352  #define  WRPLL_DIVIDER_FEEDBACK(x)	((x)<<16)
7353  #define  WRPLL_DIVIDER_FB_SHIFT		16
7354  #define  WRPLL_DIVIDER_FB_MASK		(0xff<<16)
7355  
7356  /* Port clock selection */
7357  #define PORT_CLK_SEL_A			0x46100
7358  #define PORT_CLK_SEL_B			0x46104
7359  #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
7360  #define  PORT_CLK_SEL_LCPLL_2700	(0<<29)
7361  #define  PORT_CLK_SEL_LCPLL_1350	(1<<29)
7362  #define  PORT_CLK_SEL_LCPLL_810		(2<<29)
7363  #define  PORT_CLK_SEL_SPLL		(3<<29)
7364  #define  PORT_CLK_SEL_WRPLL(pll)	(((pll)+4)<<29)
7365  #define  PORT_CLK_SEL_WRPLL1		(4<<29)
7366  #define  PORT_CLK_SEL_WRPLL2		(5<<29)
7367  #define  PORT_CLK_SEL_NONE		(7<<29)
7368  #define  PORT_CLK_SEL_MASK		(7<<29)
7369  
7370  /* Transcoder clock selection */
7371  #define TRANS_CLK_SEL_A			0x46140
7372  #define TRANS_CLK_SEL_B			0x46144
7373  #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
7374  /* For each transcoder, we need to select the corresponding port clock */
7375  #define  TRANS_CLK_SEL_DISABLED		(0x0<<29)
7376  #define  TRANS_CLK_SEL_PORT(x)		(((x)+1)<<29)
7377  
7378  #define CDCLK_FREQ			0x46200
7379  
7380  #define TRANSA_MSA_MISC			0x60410
7381  #define TRANSB_MSA_MISC			0x61410
7382  #define TRANSC_MSA_MISC			0x62410
7383  #define TRANS_EDP_MSA_MISC		0x6f410
7384  #define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)
7385  
7386  #define  TRANS_MSA_SYNC_CLK		(1<<0)
7387  #define  TRANS_MSA_6_BPC		(0<<5)
7388  #define  TRANS_MSA_8_BPC		(1<<5)
7389  #define  TRANS_MSA_10_BPC		(2<<5)
7390  #define  TRANS_MSA_12_BPC		(3<<5)
7391  #define  TRANS_MSA_16_BPC		(4<<5)
7392  
7393  /* LCPLL Control */
7394  #define LCPLL_CTL			0x130040
7395  #define  LCPLL_PLL_DISABLE		(1<<31)
7396  #define  LCPLL_PLL_LOCK			(1<<30)
7397  #define  LCPLL_CLK_FREQ_MASK		(3<<26)
7398  #define  LCPLL_CLK_FREQ_450		(0<<26)
7399  #define  LCPLL_CLK_FREQ_54O_BDW		(1<<26)
7400  #define  LCPLL_CLK_FREQ_337_5_BDW	(2<<26)
7401  #define  LCPLL_CLK_FREQ_675_BDW		(3<<26)
7402  #define  LCPLL_CD_CLOCK_DISABLE		(1<<25)
7403  #define  LCPLL_ROOT_CD_CLOCK_DISABLE	(1<<24)
7404  #define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
7405  #define  LCPLL_POWER_DOWN_ALLOW		(1<<22)
7406  #define  LCPLL_CD_SOURCE_FCLK		(1<<21)
7407  #define  LCPLL_CD_SOURCE_FCLK_DONE	(1<<19)
7408  
7409  /*
7410   * SKL Clocks
7411   */
7412  
7413  /* CDCLK_CTL */
7414  #define CDCLK_CTL			0x46000
7415  #define  CDCLK_FREQ_SEL_MASK		(3<<26)
7416  #define  CDCLK_FREQ_450_432		(0<<26)
7417  #define  CDCLK_FREQ_540			(1<<26)
7418  #define  CDCLK_FREQ_337_308		(2<<26)
7419  #define  CDCLK_FREQ_675_617		(3<<26)
7420  #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
7421  
7422  #define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3<<22)
7423  #define  BXT_CDCLK_CD2X_DIV_SEL_1	(0<<22)
7424  #define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1<<22)
7425  #define  BXT_CDCLK_CD2X_DIV_SEL_2	(2<<22)
7426  #define  BXT_CDCLK_CD2X_DIV_SEL_4	(3<<22)
7427  #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
7428  
7429  /* LCPLL_CTL */
7430  #define LCPLL1_CTL		0x46010
7431  #define LCPLL2_CTL		0x46014
7432  #define  LCPLL_PLL_ENABLE	(1<<31)
7433  
7434  /* DPLL control1 */
7435  #define DPLL_CTRL1		0x6C058
7436  #define  DPLL_CTRL1_HDMI_MODE(id)		(1<<((id)*6+5))
7437  #define  DPLL_CTRL1_SSC(id)			(1<<((id)*6+4))
7438  #define  DPLL_CTRL1_LINK_RATE_MASK(id)		(7<<((id)*6+1))
7439  #define  DPLL_CTRL1_LINK_RATE_SHIFT(id)		((id)*6+1)
7440  #define  DPLL_CTRL1_LINK_RATE(linkrate, id)	((linkrate)<<((id)*6+1))
7441  #define  DPLL_CTRL1_OVERRIDE(id)		(1<<((id)*6))
7442  #define  DPLL_CTRL1_LINK_RATE_2700		0
7443  #define  DPLL_CTRL1_LINK_RATE_1350		1
7444  #define  DPLL_CTRL1_LINK_RATE_810		2
7445  #define  DPLL_CTRL1_LINK_RATE_1620		3
7446  #define  DPLL_CTRL1_LINK_RATE_1080		4
7447  #define  DPLL_CTRL1_LINK_RATE_2160		5
7448  
7449  /* DPLL control2 */
7450  #define DPLL_CTRL2				0x6C05C
7451  #define  DPLL_CTRL2_DDI_CLK_OFF(port)		(1<<((port)+15))
7452  #define  DPLL_CTRL2_DDI_CLK_SEL_MASK(port)	(3<<((port)*3+1))
7453  #define  DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port)    ((port)*3+1)
7454  #define  DPLL_CTRL2_DDI_CLK_SEL(clk, port)	((clk)<<((port)*3+1))
7455  #define  DPLL_CTRL2_DDI_SEL_OVERRIDE(port)     (1<<((port)*3))
7456  
7457  /* DPLL Status */
7458  #define DPLL_STATUS	0x6C060
7459  #define  DPLL_LOCK(id) (1<<((id)*8))
7460  
7461  /* DPLL cfg */
7462  #define DPLL1_CFGCR1	0x6C040
7463  #define DPLL2_CFGCR1	0x6C048
7464  #define DPLL3_CFGCR1	0x6C050
7465  #define  DPLL_CFGCR1_FREQ_ENABLE	(1<<31)
7466  #define  DPLL_CFGCR1_DCO_FRACTION_MASK	(0x7fff<<9)
7467  #define  DPLL_CFGCR1_DCO_FRACTION(x)	((x)<<9)
7468  #define  DPLL_CFGCR1_DCO_INTEGER_MASK	(0x1ff)
7469  
7470  #define DPLL1_CFGCR2	0x6C044
7471  #define DPLL2_CFGCR2	0x6C04C
7472  #define DPLL3_CFGCR2	0x6C054
7473  #define  DPLL_CFGCR2_QDIV_RATIO_MASK	(0xff<<8)
7474  #define  DPLL_CFGCR2_QDIV_RATIO(x)	((x)<<8)
7475  #define  DPLL_CFGCR2_QDIV_MODE(x)	((x)<<7)
7476  #define  DPLL_CFGCR2_KDIV_MASK		(3<<5)
7477  #define  DPLL_CFGCR2_KDIV(x)		((x)<<5)
7478  #define  DPLL_CFGCR2_KDIV_5 (0<<5)
7479  #define  DPLL_CFGCR2_KDIV_2 (1<<5)
7480  #define  DPLL_CFGCR2_KDIV_3 (2<<5)
7481  #define  DPLL_CFGCR2_KDIV_1 (3<<5)
7482  #define  DPLL_CFGCR2_PDIV_MASK		(7<<2)
7483  #define  DPLL_CFGCR2_PDIV(x)		((x)<<2)
7484  #define  DPLL_CFGCR2_PDIV_1 (0<<2)
7485  #define  DPLL_CFGCR2_PDIV_2 (1<<2)
7486  #define  DPLL_CFGCR2_PDIV_3 (2<<2)
7487  #define  DPLL_CFGCR2_PDIV_7 (4<<2)
7488  #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
7489  
7490  #define DPLL_CFGCR1(id) (DPLL1_CFGCR1 + ((id) - SKL_DPLL1) * 8)
7491  #define DPLL_CFGCR2(id) (DPLL1_CFGCR2 + ((id) - SKL_DPLL1) * 8)
7492  
7493  /* BXT display engine PLL */
7494  #define BXT_DE_PLL_CTL			0x6d000
7495  #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
7496  #define   BXT_DE_PLL_RATIO_MASK		0xff
7497  
7498  #define BXT_DE_PLL_ENABLE		0x46070
7499  #define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
7500  #define   BXT_DE_PLL_LOCK		(1 << 30)
7501  
7502  /* GEN9 DC */
7503  #define DC_STATE_EN			0x45504
7504  #define  DC_STATE_EN_UPTO_DC5		(1<<0)
7505  #define  DC_STATE_EN_DC9		(1<<3)
7506  #define  DC_STATE_EN_UPTO_DC6		(2<<0)
7507  #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
7508  
7509  #define  DC_STATE_DEBUG                  0x45520
7510  #define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1<<1)
7511  
7512  /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
7513   * since on HSW we can't write to it using I915_WRITE. */
7514  #define D_COMP_HSW			(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
7515  #define D_COMP_BDW			0x138144
7516  #define  D_COMP_RCOMP_IN_PROGRESS	(1<<9)
7517  #define  D_COMP_COMP_FORCE		(1<<8)
7518  #define  D_COMP_COMP_DISABLE		(1<<0)
7519  
7520  /* Pipe WM_LINETIME - watermark line time */
7521  #define PIPE_WM_LINETIME_A		0x45270
7522  #define PIPE_WM_LINETIME_B		0x45274
7523  #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
7524  					   PIPE_WM_LINETIME_B)
7525  #define   PIPE_WM_LINETIME_MASK			(0x1ff)
7526  #define   PIPE_WM_LINETIME_TIME(x)		((x))
7527  #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff<<16)
7528  #define   PIPE_WM_LINETIME_IPS_LINETIME(x)	((x)<<16)
7529  
7530  /* SFUSE_STRAP */
7531  #define SFUSE_STRAP			0xc2014
7532  #define  SFUSE_STRAP_FUSE_LOCK		(1<<13)
7533  #define  SFUSE_STRAP_DISPLAY_DISABLED	(1<<7)
7534  #define  SFUSE_STRAP_DDIB_DETECTED	(1<<2)
7535  #define  SFUSE_STRAP_DDIC_DETECTED	(1<<1)
7536  #define  SFUSE_STRAP_DDID_DETECTED	(1<<0)
7537  
7538  #define WM_MISC				0x45260
7539  #define  WM_MISC_DATA_PARTITION_5_6	(1 << 0)
7540  
7541  #define WM_DBG				0x45280
7542  #define  WM_DBG_DISALLOW_MULTIPLE_LP	(1<<0)
7543  #define  WM_DBG_DISALLOW_MAXFIFO	(1<<1)
7544  #define  WM_DBG_DISALLOW_SPRITE		(1<<2)
7545  
7546  /* pipe CSC */
7547  #define _PIPE_A_CSC_COEFF_RY_GY	0x49010
7548  #define _PIPE_A_CSC_COEFF_BY	0x49014
7549  #define _PIPE_A_CSC_COEFF_RU_GU	0x49018
7550  #define _PIPE_A_CSC_COEFF_BU	0x4901c
7551  #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
7552  #define _PIPE_A_CSC_COEFF_BV	0x49024
7553  #define _PIPE_A_CSC_MODE	0x49028
7554  #define   CSC_BLACK_SCREEN_OFFSET	(1 << 2)
7555  #define   CSC_POSITION_BEFORE_GAMMA	(1 << 1)
7556  #define   CSC_MODE_YUV_TO_RGB		(1 << 0)
7557  #define _PIPE_A_CSC_PREOFF_HI	0x49030
7558  #define _PIPE_A_CSC_PREOFF_ME	0x49034
7559  #define _PIPE_A_CSC_PREOFF_LO	0x49038
7560  #define _PIPE_A_CSC_POSTOFF_HI	0x49040
7561  #define _PIPE_A_CSC_POSTOFF_ME	0x49044
7562  #define _PIPE_A_CSC_POSTOFF_LO	0x49048
7563  
7564  #define _PIPE_B_CSC_COEFF_RY_GY	0x49110
7565  #define _PIPE_B_CSC_COEFF_BY	0x49114
7566  #define _PIPE_B_CSC_COEFF_RU_GU	0x49118
7567  #define _PIPE_B_CSC_COEFF_BU	0x4911c
7568  #define _PIPE_B_CSC_COEFF_RV_GV	0x49120
7569  #define _PIPE_B_CSC_COEFF_BV	0x49124
7570  #define _PIPE_B_CSC_MODE	0x49128
7571  #define _PIPE_B_CSC_PREOFF_HI	0x49130
7572  #define _PIPE_B_CSC_PREOFF_ME	0x49134
7573  #define _PIPE_B_CSC_PREOFF_LO	0x49138
7574  #define _PIPE_B_CSC_POSTOFF_HI	0x49140
7575  #define _PIPE_B_CSC_POSTOFF_ME	0x49144
7576  #define _PIPE_B_CSC_POSTOFF_LO	0x49148
7577  
7578  #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
7579  #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
7580  #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
7581  #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
7582  #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
7583  #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
7584  #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
7585  #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
7586  #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
7587  #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
7588  #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
7589  #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
7590  #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
7591  
7592  /* MIPI DSI registers */
7593  
7594  #define _MIPI_PORT(port, a, c)	_PORT3(port, a, 0, c)	/* ports A and C only */
7595  
7596  /* BXT MIPI clock controls */
7597  #define BXT_MAX_VAR_OUTPUT_KHZ			39500
7598  
7599  #define BXT_MIPI_CLOCK_CTL			0x46090
7600  #define  BXT_MIPI1_DIV_SHIFT			26
7601  #define  BXT_MIPI2_DIV_SHIFT			10
7602  #define  BXT_MIPI_DIV_SHIFT(port)		\
7603  			_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
7604  					BXT_MIPI2_DIV_SHIFT)
7605  /* Var clock divider to generate TX source. Result must be < 39.5 M */
7606  #define  BXT_MIPI1_ESCLK_VAR_DIV_MASK		(0x3F << 26)
7607  #define  BXT_MIPI2_ESCLK_VAR_DIV_MASK		(0x3F << 10)
7608  #define  BXT_MIPI_ESCLK_VAR_DIV_MASK(port)	\
7609  			_MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
7610  						BXT_MIPI2_ESCLK_VAR_DIV_MASK)
7611  
7612  #define  BXT_MIPI_ESCLK_VAR_DIV(port, val)	\
7613  			(val << BXT_MIPI_DIV_SHIFT(port))
7614  /* TX control divider to select actual TX clock output from (8x/var) */
7615  #define  BXT_MIPI1_TX_ESCLK_SHIFT		21
7616  #define  BXT_MIPI2_TX_ESCLK_SHIFT		5
7617  #define  BXT_MIPI_TX_ESCLK_SHIFT(port)		\
7618  			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
7619  					BXT_MIPI2_TX_ESCLK_SHIFT)
7620  #define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK		(3 << 21)
7621  #define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK		(3 << 5)
7622  #define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)	\
7623  			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
7624  						BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
7625  #define  BXT_MIPI_TX_ESCLK_8XDIV_BY2(port)	\
7626  		(0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
7627  #define  BXT_MIPI_TX_ESCLK_8XDIV_BY4(port)	\
7628  		(0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
7629  #define  BXT_MIPI_TX_ESCLK_8XDIV_BY8(port)	\
7630  		(0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
7631  /* RX control divider to select actual RX clock output from 8x*/
7632  #define  BXT_MIPI1_RX_ESCLK_SHIFT		19
7633  #define  BXT_MIPI2_RX_ESCLK_SHIFT		3
7634  #define  BXT_MIPI_RX_ESCLK_SHIFT(port)		\
7635  			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
7636  					BXT_MIPI2_RX_ESCLK_SHIFT)
7637  #define  BXT_MIPI1_RX_ESCLK_FIXDIV_MASK		(3 << 19)
7638  #define  BXT_MIPI2_RX_ESCLK_FIXDIV_MASK		(3 << 3)
7639  #define  BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)	\
7640  		(3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7641  #define  BXT_MIPI_RX_ESCLK_8X_BY2(port)	\
7642  		(1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7643  #define  BXT_MIPI_RX_ESCLK_8X_BY3(port)	\
7644  		(2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7645  #define  BXT_MIPI_RX_ESCLK_8X_BY4(port)	\
7646  		(3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7647  /* BXT-A WA: Always prog DPHY dividers to 00 */
7648  #define  BXT_MIPI1_DPHY_DIV_SHIFT		16
7649  #define  BXT_MIPI2_DPHY_DIV_SHIFT		0
7650  #define  BXT_MIPI_DPHY_DIV_SHIFT(port)		\
7651  			_MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
7652  					BXT_MIPI2_DPHY_DIV_SHIFT)
7653  #define  BXT_MIPI_1_DPHY_DIVIDER_MASK		(3 << 16)
7654  #define  BXT_MIPI_2_DPHY_DIVIDER_MASK		(3 << 0)
7655  #define  BXT_MIPI_DPHY_DIVIDER_MASK(port)	\
7656  		(3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
7657  
7658  /* BXT MIPI mode configure */
7659  #define  _BXT_MIPIA_TRANS_HACTIVE			0x6B0F8
7660  #define  _BXT_MIPIC_TRANS_HACTIVE			0x6B8F8
7661  #define  BXT_MIPI_TRANS_HACTIVE(tc)	_MIPI_PORT(tc, \
7662  		_BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
7663  
7664  #define  _BXT_MIPIA_TRANS_VACTIVE			0x6B0FC
7665  #define  _BXT_MIPIC_TRANS_VACTIVE			0x6B8FC
7666  #define  BXT_MIPI_TRANS_VACTIVE(tc)	_MIPI_PORT(tc, \
7667  		_BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
7668  
7669  #define  _BXT_MIPIA_TRANS_VTOTAL			0x6B100
7670  #define  _BXT_MIPIC_TRANS_VTOTAL			0x6B900
7671  #define  BXT_MIPI_TRANS_VTOTAL(tc)	_MIPI_PORT(tc, \
7672  		_BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
7673  
7674  #define BXT_DSI_PLL_CTL			0x161000
7675  #define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16
7676  #define  BXT_DSI_PLL_PVD_RATIO_MASK	(3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
7677  #define  BXT_DSI_PLL_PVD_RATIO_1	(1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
7678  #define  BXT_DSIC_16X_BY2		(1 << 10)
7679  #define  BXT_DSIC_16X_BY3		(2 << 10)
7680  #define  BXT_DSIC_16X_BY4		(3 << 10)
7681  #define  BXT_DSIA_16X_BY2		(1 << 8)
7682  #define  BXT_DSIA_16X_BY3		(2 << 8)
7683  #define  BXT_DSIA_16X_BY4		(3 << 8)
7684  #define  BXT_DSI_FREQ_SEL_SHIFT		8
7685  #define  BXT_DSI_FREQ_SEL_MASK		(0xF << BXT_DSI_FREQ_SEL_SHIFT)
7686  
7687  #define BXT_DSI_PLL_RATIO_MAX		0x7D
7688  #define BXT_DSI_PLL_RATIO_MIN		0x22
7689  #define BXT_DSI_PLL_RATIO_MASK		0xFF
7690  #define BXT_REF_CLOCK_KHZ		19500
7691  
7692  #define BXT_DSI_PLL_ENABLE		0x46080
7693  #define  BXT_DSI_PLL_DO_ENABLE		(1 << 31)
7694  #define  BXT_DSI_PLL_LOCKED		(1 << 30)
7695  
7696  #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
7697  #define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
7698  #define MIPI_PORT_CTRL(port)	_MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
7699  
7700   /* BXT port control */
7701  #define _BXT_MIPIA_PORT_CTRL				0x6B0C0
7702  #define _BXT_MIPIC_PORT_CTRL				0x6B8C0
7703  #define BXT_MIPI_PORT_CTRL(tc)	_MIPI_PORT(tc, _BXT_MIPIA_PORT_CTRL, \
7704  						_BXT_MIPIC_PORT_CTRL)
7705  
7706  #define  DPI_ENABLE					(1 << 31) /* A + C */
7707  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
7708  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
7709  #define  DUAL_LINK_MODE_SHIFT				26
7710  #define  DUAL_LINK_MODE_MASK				(1 << 26)
7711  #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
7712  #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
7713  #define  DITHERING_ENABLE				(1 << 25) /* A + C */
7714  #define  FLOPPED_HSTX					(1 << 23)
7715  #define  DE_INVERT					(1 << 19) /* XXX */
7716  #define  MIPIA_FLISDSI_DELAY_COUNT_SHIFT		18
7717  #define  MIPIA_FLISDSI_DELAY_COUNT_MASK			(0xf << 18)
7718  #define  AFE_LATCHOUT					(1 << 17)
7719  #define  LP_OUTPUT_HOLD					(1 << 16)
7720  #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT		15
7721  #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK		(1 << 15)
7722  #define  MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT		11
7723  #define  MIPIC_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 11)
7724  #define  CSB_SHIFT					9
7725  #define  CSB_MASK					(3 << 9)
7726  #define  CSB_20MHZ					(0 << 9)
7727  #define  CSB_10MHZ					(1 << 9)
7728  #define  CSB_40MHZ					(2 << 9)
7729  #define  BANDGAP_MASK					(1 << 8)
7730  #define  BANDGAP_PNW_CIRCUIT				(0 << 8)
7731  #define  BANDGAP_LNC_CIRCUIT				(1 << 8)
7732  #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT		5
7733  #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK		(7 << 5)
7734  #define  TEARING_EFFECT_DELAY				(1 << 4) /* A + C */
7735  #define  TEARING_EFFECT_SHIFT				2 /* A + C */
7736  #define  TEARING_EFFECT_MASK				(3 << 2)
7737  #define  TEARING_EFFECT_OFF				(0 << 2)
7738  #define  TEARING_EFFECT_DSI				(1 << 2)
7739  #define  TEARING_EFFECT_GPIO				(2 << 2)
7740  #define  LANE_CONFIGURATION_SHIFT			0
7741  #define  LANE_CONFIGURATION_MASK			(3 << 0)
7742  #define  LANE_CONFIGURATION_4LANE			(0 << 0)
7743  #define  LANE_CONFIGURATION_DUAL_LINK_A			(1 << 0)
7744  #define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)
7745  
7746  #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
7747  #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
7748  #define MIPI_TEARING_CTRL(port)			_MIPI_PORT(port, \
7749  				_MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
7750  #define  TEARING_EFFECT_DELAY_SHIFT			0
7751  #define  TEARING_EFFECT_DELAY_MASK			(0xffff << 0)
7752  
7753  /* XXX: all bits reserved */
7754  #define _MIPIA_AUTOPWG			(VLV_DISPLAY_BASE + 0x611a0)
7755  
7756  /* MIPI DSI Controller and D-PHY registers */
7757  
7758  #define _MIPIA_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb000)
7759  #define _MIPIC_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb800)
7760  #define MIPI_DEVICE_READY(port)		_MIPI_PORT(port, _MIPIA_DEVICE_READY, \
7761  						_MIPIC_DEVICE_READY)
7762  #define  BUS_POSSESSION					(1 << 3) /* set to give bus to receiver */
7763  #define  ULPS_STATE_MASK				(3 << 1)
7764  #define  ULPS_STATE_ENTER				(2 << 1)
7765  #define  ULPS_STATE_EXIT				(1 << 1)
7766  #define  ULPS_STATE_NORMAL_OPERATION			(0 << 1)
7767  #define  DEVICE_READY					(1 << 0)
7768  
7769  #define _MIPIA_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb004)
7770  #define _MIPIC_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb804)
7771  #define MIPI_INTR_STAT(port)		_MIPI_PORT(port, _MIPIA_INTR_STAT, \
7772  					_MIPIC_INTR_STAT)
7773  #define _MIPIA_INTR_EN			(dev_priv->mipi_mmio_base + 0xb008)
7774  #define _MIPIC_INTR_EN			(dev_priv->mipi_mmio_base + 0xb808)
7775  #define MIPI_INTR_EN(port)		_MIPI_PORT(port, _MIPIA_INTR_EN, \
7776  					_MIPIC_INTR_EN)
7777  #define  TEARING_EFFECT					(1 << 31)
7778  #define  SPL_PKT_SENT_INTERRUPT				(1 << 30)
7779  #define  GEN_READ_DATA_AVAIL				(1 << 29)
7780  #define  LP_GENERIC_WR_FIFO_FULL			(1 << 28)
7781  #define  HS_GENERIC_WR_FIFO_FULL			(1 << 27)
7782  #define  RX_PROT_VIOLATION				(1 << 26)
7783  #define  RX_INVALID_TX_LENGTH				(1 << 25)
7784  #define  ACK_WITH_NO_ERROR				(1 << 24)
7785  #define  TURN_AROUND_ACK_TIMEOUT			(1 << 23)
7786  #define  LP_RX_TIMEOUT					(1 << 22)
7787  #define  HS_TX_TIMEOUT					(1 << 21)
7788  #define  DPI_FIFO_UNDERRUN				(1 << 20)
7789  #define  LOW_CONTENTION					(1 << 19)
7790  #define  HIGH_CONTENTION				(1 << 18)
7791  #define  TXDSI_VC_ID_INVALID				(1 << 17)
7792  #define  TXDSI_DATA_TYPE_NOT_RECOGNISED			(1 << 16)
7793  #define  TXCHECKSUM_ERROR				(1 << 15)
7794  #define  TXECC_MULTIBIT_ERROR				(1 << 14)
7795  #define  TXECC_SINGLE_BIT_ERROR				(1 << 13)
7796  #define  TXFALSE_CONTROL_ERROR				(1 << 12)
7797  #define  RXDSI_VC_ID_INVALID				(1 << 11)
7798  #define  RXDSI_DATA_TYPE_NOT_REGOGNISED			(1 << 10)
7799  #define  RXCHECKSUM_ERROR				(1 << 9)
7800  #define  RXECC_MULTIBIT_ERROR				(1 << 8)
7801  #define  RXECC_SINGLE_BIT_ERROR				(1 << 7)
7802  #define  RXFALSE_CONTROL_ERROR				(1 << 6)
7803  #define  RXHS_RECEIVE_TIMEOUT_ERROR			(1 << 5)
7804  #define  RX_LP_TX_SYNC_ERROR				(1 << 4)
7805  #define  RXEXCAPE_MODE_ENTRY_ERROR			(1 << 3)
7806  #define  RXEOT_SYNC_ERROR				(1 << 2)
7807  #define  RXSOT_SYNC_ERROR				(1 << 1)
7808  #define  RXSOT_ERROR					(1 << 0)
7809  
7810  #define _MIPIA_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb00c)
7811  #define _MIPIC_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb80c)
7812  #define MIPI_DSI_FUNC_PRG(port)		_MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \
7813  						_MIPIC_DSI_FUNC_PRG)
7814  #define  CMD_MODE_DATA_WIDTH_MASK			(7 << 13)
7815  #define  CMD_MODE_NOT_SUPPORTED				(0 << 13)
7816  #define  CMD_MODE_DATA_WIDTH_16_BIT			(1 << 13)
7817  #define  CMD_MODE_DATA_WIDTH_9_BIT			(2 << 13)
7818  #define  CMD_MODE_DATA_WIDTH_8_BIT			(3 << 13)
7819  #define  CMD_MODE_DATA_WIDTH_OPTION1			(4 << 13)
7820  #define  CMD_MODE_DATA_WIDTH_OPTION2			(5 << 13)
7821  #define  VID_MODE_FORMAT_MASK				(0xf << 7)
7822  #define  VID_MODE_NOT_SUPPORTED				(0 << 7)
7823  #define  VID_MODE_FORMAT_RGB565				(1 << 7)
7824  #define  VID_MODE_FORMAT_RGB666				(2 << 7)
7825  #define  VID_MODE_FORMAT_RGB666_LOOSE			(3 << 7)
7826  #define  VID_MODE_FORMAT_RGB888				(4 << 7)
7827  #define  CMD_MODE_CHANNEL_NUMBER_SHIFT			5
7828  #define  CMD_MODE_CHANNEL_NUMBER_MASK			(3 << 5)
7829  #define  VID_MODE_CHANNEL_NUMBER_SHIFT			3
7830  #define  VID_MODE_CHANNEL_NUMBER_MASK			(3 << 3)
7831  #define  DATA_LANES_PRG_REG_SHIFT			0
7832  #define  DATA_LANES_PRG_REG_MASK			(7 << 0)
7833  
7834  #define _MIPIA_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb010)
7835  #define _MIPIC_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb810)
7836  #define MIPI_HS_TX_TIMEOUT(port)	_MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \
7837  					_MIPIC_HS_TX_TIMEOUT)
7838  #define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK		0xffffff
7839  
7840  #define _MIPIA_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb014)
7841  #define _MIPIC_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb814)
7842  #define MIPI_LP_RX_TIMEOUT(port)	_MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \
7843  					_MIPIC_LP_RX_TIMEOUT)
7844  #define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK		0xffffff
7845  
7846  #define _MIPIA_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb018)
7847  #define _MIPIC_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb818)
7848  #define MIPI_TURN_AROUND_TIMEOUT(port)	_MIPI_PORT(port, \
7849  			_MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
7850  #define  TURN_AROUND_TIMEOUT_MASK			0x3f
7851  
7852  #define _MIPIA_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb01c)
7853  #define _MIPIC_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb81c)
7854  #define MIPI_DEVICE_RESET_TIMER(port)	_MIPI_PORT(port, \
7855  			_MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
7856  #define  DEVICE_RESET_TIMER_MASK			0xffff
7857  
7858  #define _MIPIA_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb020)
7859  #define _MIPIC_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb820)
7860  #define MIPI_DPI_RESOLUTION(port)	_MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \
7861  					_MIPIC_DPI_RESOLUTION)
7862  #define  VERTICAL_ADDRESS_SHIFT				16
7863  #define  VERTICAL_ADDRESS_MASK				(0xffff << 16)
7864  #define  HORIZONTAL_ADDRESS_SHIFT			0
7865  #define  HORIZONTAL_ADDRESS_MASK			0xffff
7866  
7867  #define _MIPIA_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb024)
7868  #define _MIPIC_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb824)
7869  #define MIPI_DBI_FIFO_THROTTLE(port)	_MIPI_PORT(port, \
7870  			_MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
7871  #define  DBI_FIFO_EMPTY_HALF				(0 << 0)
7872  #define  DBI_FIFO_EMPTY_QUARTER				(1 << 0)
7873  #define  DBI_FIFO_EMPTY_7_LOCATIONS			(2 << 0)
7874  
7875  /* regs below are bits 15:0 */
7876  #define _MIPIA_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb028)
7877  #define _MIPIC_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb828)
7878  #define MIPI_HSYNC_PADDING_COUNT(port)	_MIPI_PORT(port, \
7879  			_MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
7880  
7881  #define _MIPIA_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb02c)
7882  #define _MIPIC_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb82c)
7883  #define MIPI_HBP_COUNT(port)		_MIPI_PORT(port, _MIPIA_HBP_COUNT, \
7884  					_MIPIC_HBP_COUNT)
7885  
7886  #define _MIPIA_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb030)
7887  #define _MIPIC_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb830)
7888  #define MIPI_HFP_COUNT(port)		_MIPI_PORT(port, _MIPIA_HFP_COUNT, \
7889  					_MIPIC_HFP_COUNT)
7890  
7891  #define _MIPIA_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb034)
7892  #define _MIPIC_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb834)
7893  #define MIPI_HACTIVE_AREA_COUNT(port)	_MIPI_PORT(port, \
7894  			_MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
7895  
7896  #define _MIPIA_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb038)
7897  #define _MIPIC_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb838)
7898  #define MIPI_VSYNC_PADDING_COUNT(port)	_MIPI_PORT(port, \
7899  			_MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
7900  
7901  #define _MIPIA_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb03c)
7902  #define _MIPIC_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb83c)
7903  #define MIPI_VBP_COUNT(port)		_MIPI_PORT(port, _MIPIA_VBP_COUNT, \
7904  					_MIPIC_VBP_COUNT)
7905  
7906  #define _MIPIA_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb040)
7907  #define _MIPIC_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb840)
7908  #define MIPI_VFP_COUNT(port)		_MIPI_PORT(port, _MIPIA_VFP_COUNT, \
7909  					_MIPIC_VFP_COUNT)
7910  
7911  #define _MIPIA_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb044)
7912  #define _MIPIC_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb844)
7913  #define MIPI_HIGH_LOW_SWITCH_COUNT(port)	_MIPI_PORT(port,	\
7914  		_MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
7915  
7916  /* regs above are bits 15:0 */
7917  
7918  #define _MIPIA_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb048)
7919  #define _MIPIC_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb848)
7920  #define MIPI_DPI_CONTROL(port)		_MIPI_PORT(port, _MIPIA_DPI_CONTROL, \
7921  					_MIPIC_DPI_CONTROL)
7922  #define  DPI_LP_MODE					(1 << 6)
7923  #define  BACKLIGHT_OFF					(1 << 5)
7924  #define  BACKLIGHT_ON					(1 << 4)
7925  #define  COLOR_MODE_OFF					(1 << 3)
7926  #define  COLOR_MODE_ON					(1 << 2)
7927  #define  TURN_ON					(1 << 1)
7928  #define  SHUTDOWN					(1 << 0)
7929  
7930  #define _MIPIA_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb04c)
7931  #define _MIPIC_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb84c)
7932  #define MIPI_DPI_DATA(port)		_MIPI_PORT(port, _MIPIA_DPI_DATA, \
7933  					_MIPIC_DPI_DATA)
7934  #define  COMMAND_BYTE_SHIFT				0
7935  #define  COMMAND_BYTE_MASK				(0x3f << 0)
7936  
7937  #define _MIPIA_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb050)
7938  #define _MIPIC_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb850)
7939  #define MIPI_INIT_COUNT(port)		_MIPI_PORT(port, _MIPIA_INIT_COUNT, \
7940  					_MIPIC_INIT_COUNT)
7941  #define  MASTER_INIT_TIMER_SHIFT			0
7942  #define  MASTER_INIT_TIMER_MASK				(0xffff << 0)
7943  
7944  #define _MIPIA_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb054)
7945  #define _MIPIC_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb854)
7946  #define MIPI_MAX_RETURN_PKT_SIZE(port)	_MIPI_PORT(port, \
7947  			_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
7948  #define  MAX_RETURN_PKT_SIZE_SHIFT			0
7949  #define  MAX_RETURN_PKT_SIZE_MASK			(0x3ff << 0)
7950  
7951  #define _MIPIA_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb058)
7952  #define _MIPIC_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb858)
7953  #define MIPI_VIDEO_MODE_FORMAT(port)	_MIPI_PORT(port, \
7954  			_MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
7955  #define  RANDOM_DPI_DISPLAY_RESOLUTION			(1 << 4)
7956  #define  DISABLE_VIDEO_BTA				(1 << 3)
7957  #define  IP_TG_CONFIG					(1 << 2)
7958  #define  VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE		(1 << 0)
7959  #define  VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS		(2 << 0)
7960  #define  VIDEO_MODE_BURST				(3 << 0)
7961  
7962  #define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)
7963  #define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)
7964  #define MIPI_EOT_DISABLE(port)		_MIPI_PORT(port, _MIPIA_EOT_DISABLE, \
7965  					_MIPIC_EOT_DISABLE)
7966  #define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 7)
7967  #define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 6)
7968  #define  LOW_CONTENTION_RECOVERY_DISABLE		(1 << 5)
7969  #define  HIGH_CONTENTION_RECOVERY_DISABLE		(1 << 4)
7970  #define  TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
7971  #define  TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE		(1 << 2)
7972  #define  CLOCKSTOP					(1 << 1)
7973  #define  EOT_DISABLE					(1 << 0)
7974  
7975  #define _MIPIA_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb060)
7976  #define _MIPIC_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb860)
7977  #define MIPI_LP_BYTECLK(port)		_MIPI_PORT(port, _MIPIA_LP_BYTECLK, \
7978  					_MIPIC_LP_BYTECLK)
7979  #define  LP_BYTECLK_SHIFT				0
7980  #define  LP_BYTECLK_MASK				(0xffff << 0)
7981  
7982  /* bits 31:0 */
7983  #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
7984  #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
7985  #define MIPI_LP_GEN_DATA(port)		_MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \
7986  					_MIPIC_LP_GEN_DATA)
7987  
7988  /* bits 31:0 */
7989  #define _MIPIA_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb068)
7990  #define _MIPIC_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb868)
7991  #define MIPI_HS_GEN_DATA(port)		_MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \
7992  					_MIPIC_HS_GEN_DATA)
7993  
7994  #define _MIPIA_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb06c)
7995  #define _MIPIC_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb86c)
7996  #define MIPI_LP_GEN_CTRL(port)		_MIPI_PORT(port, _MIPIA_LP_GEN_CTRL, \
7997  					_MIPIC_LP_GEN_CTRL)
7998  #define _MIPIA_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb070)
7999  #define _MIPIC_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb870)
8000  #define MIPI_HS_GEN_CTRL(port)		_MIPI_PORT(port, _MIPIA_HS_GEN_CTRL, \
8001  					_MIPIC_HS_GEN_CTRL)
8002  #define  LONG_PACKET_WORD_COUNT_SHIFT			8
8003  #define  LONG_PACKET_WORD_COUNT_MASK			(0xffff << 8)
8004  #define  SHORT_PACKET_PARAM_SHIFT			8
8005  #define  SHORT_PACKET_PARAM_MASK			(0xffff << 8)
8006  #define  VIRTUAL_CHANNEL_SHIFT				6
8007  #define  VIRTUAL_CHANNEL_MASK				(3 << 6)
8008  #define  DATA_TYPE_SHIFT				0
8009  #define  DATA_TYPE_MASK					(0x3f << 0)
8010  /* data type values, see include/video/mipi_display.h */
8011  
8012  #define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)
8013  #define _MIPIC_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb874)
8014  #define MIPI_GEN_FIFO_STAT(port)	_MIPI_PORT(port, _MIPIA_GEN_FIFO_STAT, \
8015  					_MIPIC_GEN_FIFO_STAT)
8016  #define  DPI_FIFO_EMPTY					(1 << 28)
8017  #define  DBI_FIFO_EMPTY					(1 << 27)
8018  #define  LP_CTRL_FIFO_EMPTY				(1 << 26)
8019  #define  LP_CTRL_FIFO_HALF_EMPTY			(1 << 25)
8020  #define  LP_CTRL_FIFO_FULL				(1 << 24)
8021  #define  HS_CTRL_FIFO_EMPTY				(1 << 18)
8022  #define  HS_CTRL_FIFO_HALF_EMPTY			(1 << 17)
8023  #define  HS_CTRL_FIFO_FULL				(1 << 16)
8024  #define  LP_DATA_FIFO_EMPTY				(1 << 10)
8025  #define  LP_DATA_FIFO_HALF_EMPTY			(1 << 9)
8026  #define  LP_DATA_FIFO_FULL				(1 << 8)
8027  #define  HS_DATA_FIFO_EMPTY				(1 << 2)
8028  #define  HS_DATA_FIFO_HALF_EMPTY			(1 << 1)
8029  #define  HS_DATA_FIFO_FULL				(1 << 0)
8030  
8031  #define _MIPIA_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb078)
8032  #define _MIPIC_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb878)
8033  #define MIPI_HS_LP_DBI_ENABLE(port)	_MIPI_PORT(port, \
8034  			_MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
8035  #define  DBI_HS_LP_MODE_MASK				(1 << 0)
8036  #define  DBI_LP_MODE					(1 << 0)
8037  #define  DBI_HS_MODE					(0 << 0)
8038  
8039  #define _MIPIA_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb080)
8040  #define _MIPIC_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb880)
8041  #define MIPI_DPHY_PARAM(port)		_MIPI_PORT(port, _MIPIA_DPHY_PARAM, \
8042  					_MIPIC_DPHY_PARAM)
8043  #define  EXIT_ZERO_COUNT_SHIFT				24
8044  #define  EXIT_ZERO_COUNT_MASK				(0x3f << 24)
8045  #define  TRAIL_COUNT_SHIFT				16
8046  #define  TRAIL_COUNT_MASK				(0x1f << 16)
8047  #define  CLK_ZERO_COUNT_SHIFT				8
8048  #define  CLK_ZERO_COUNT_MASK				(0xff << 8)
8049  #define  PREPARE_COUNT_SHIFT				0
8050  #define  PREPARE_COUNT_MASK				(0x3f << 0)
8051  
8052  /* bits 31:0 */
8053  #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
8054  #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
8055  #define MIPI_DBI_BW_CTRL(port)		_MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \
8056  					_MIPIC_DBI_BW_CTRL)
8057  
8058  #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base \
8059  							+ 0xb088)
8060  #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base \
8061  							+ 0xb888)
8062  #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)	_MIPI_PORT(port, \
8063  	_MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
8064  #define  LP_HS_SSW_CNT_SHIFT				16
8065  #define  LP_HS_SSW_CNT_MASK				(0xffff << 16)
8066  #define  HS_LP_PWR_SW_CNT_SHIFT				0
8067  #define  HS_LP_PWR_SW_CNT_MASK				(0xffff << 0)
8068  
8069  #define _MIPIA_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb08c)
8070  #define _MIPIC_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb88c)
8071  #define MIPI_STOP_STATE_STALL(port)	_MIPI_PORT(port, \
8072  			_MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
8073  #define  STOP_STATE_STALL_COUNTER_SHIFT			0
8074  #define  STOP_STATE_STALL_COUNTER_MASK			(0xff << 0)
8075  
8076  #define _MIPIA_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb090)
8077  #define _MIPIC_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb890)
8078  #define MIPI_INTR_STAT_REG_1(port)	_MIPI_PORT(port, \
8079  				_MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
8080  #define _MIPIA_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb094)
8081  #define _MIPIC_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb894)
8082  #define MIPI_INTR_EN_REG_1(port)	_MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \
8083  					_MIPIC_INTR_EN_REG_1)
8084  #define  RX_CONTENTION_DETECTED				(1 << 0)
8085  
8086  /* XXX: only pipe A ?!? */
8087  #define MIPIA_DBI_TYPEC_CTRL		(dev_priv->mipi_mmio_base + 0xb100)
8088  #define  DBI_TYPEC_ENABLE				(1 << 31)
8089  #define  DBI_TYPEC_WIP					(1 << 30)
8090  #define  DBI_TYPEC_OPTION_SHIFT				28
8091  #define  DBI_TYPEC_OPTION_MASK				(3 << 28)
8092  #define  DBI_TYPEC_FREQ_SHIFT				24
8093  #define  DBI_TYPEC_FREQ_MASK				(0xf << 24)
8094  #define  DBI_TYPEC_OVERRIDE				(1 << 8)
8095  #define  DBI_TYPEC_OVERRIDE_COUNTER_SHIFT		0
8096  #define  DBI_TYPEC_OVERRIDE_COUNTER_MASK		(0xff << 0)
8097  
8098  
8099  /* MIPI adapter registers */
8100  
8101  #define _MIPIA_CTRL			(dev_priv->mipi_mmio_base + 0xb104)
8102  #define _MIPIC_CTRL			(dev_priv->mipi_mmio_base + 0xb904)
8103  #define MIPI_CTRL(port)			_MIPI_PORT(port, _MIPIA_CTRL, \
8104  					_MIPIC_CTRL)
8105  #define  ESCAPE_CLOCK_DIVIDER_SHIFT			5 /* A only */
8106  #define  ESCAPE_CLOCK_DIVIDER_MASK			(3 << 5)
8107  #define  ESCAPE_CLOCK_DIVIDER_1				(0 << 5)
8108  #define  ESCAPE_CLOCK_DIVIDER_2				(1 << 5)
8109  #define  ESCAPE_CLOCK_DIVIDER_4				(2 << 5)
8110  #define  READ_REQUEST_PRIORITY_SHIFT			3
8111  #define  READ_REQUEST_PRIORITY_MASK			(3 << 3)
8112  #define  READ_REQUEST_PRIORITY_LOW			(0 << 3)
8113  #define  READ_REQUEST_PRIORITY_HIGH			(3 << 3)
8114  #define  RGB_FLIP_TO_BGR				(1 << 2)
8115  
8116  #define  BXT_PIPE_SELECT_MASK				(7 << 7)
8117  #define  BXT_PIPE_SELECT_C				(2 << 7)
8118  #define  BXT_PIPE_SELECT_B				(1 << 7)
8119  #define  BXT_PIPE_SELECT_A				(0 << 7)
8120  
8121  #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
8122  #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
8123  #define MIPI_DATA_ADDRESS(port)		_MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
8124  					_MIPIC_DATA_ADDRESS)
8125  #define  DATA_MEM_ADDRESS_SHIFT				5
8126  #define  DATA_MEM_ADDRESS_MASK				(0x7ffffff << 5)
8127  #define  DATA_VALID					(1 << 0)
8128  
8129  #define _MIPIA_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb10c)
8130  #define _MIPIC_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb90c)
8131  #define MIPI_DATA_LENGTH(port)		_MIPI_PORT(port, _MIPIA_DATA_LENGTH, \
8132  					_MIPIC_DATA_LENGTH)
8133  #define  DATA_LENGTH_SHIFT				0
8134  #define  DATA_LENGTH_MASK				(0xfffff << 0)
8135  
8136  #define _MIPIA_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb110)
8137  #define _MIPIC_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb910)
8138  #define MIPI_COMMAND_ADDRESS(port)	_MIPI_PORT(port, \
8139  				_MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
8140  #define  COMMAND_MEM_ADDRESS_SHIFT			5
8141  #define  COMMAND_MEM_ADDRESS_MASK			(0x7ffffff << 5)
8142  #define  AUTO_PWG_ENABLE				(1 << 2)
8143  #define  MEMORY_WRITE_DATA_FROM_PIPE_RENDERING		(1 << 1)
8144  #define  COMMAND_VALID					(1 << 0)
8145  
8146  #define _MIPIA_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb114)
8147  #define _MIPIC_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb914)
8148  #define MIPI_COMMAND_LENGTH(port)	_MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \
8149  					_MIPIC_COMMAND_LENGTH)
8150  #define  COMMAND_LENGTH_SHIFT(n)			(8 * (n)) /* n: 0...3 */
8151  #define  COMMAND_LENGTH_MASK(n)				(0xff << (8 * (n)))
8152  
8153  #define _MIPIA_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb118)
8154  #define _MIPIC_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb918)
8155  #define MIPI_READ_DATA_RETURN(port, n) \
8156  	(_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \
8157  					+ 4 * (n)) /* n: 0...7 */
8158  
8159  #define _MIPIA_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb138)
8160  #define _MIPIC_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb938)
8161  #define MIPI_READ_DATA_VALID(port)	_MIPI_PORT(port, \
8162  				_MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
8163  #define  READ_DATA_VALID(n)				(1 << (n))
8164  
8165  /* For UMS only (deprecated): */
8166  #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
8167  #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
8168  
8169  /* MOCS (Memory Object Control State) registers */
8170  #define GEN9_LNCFCMOCS0		0xb020	/* L3 Cache Control base */
8171  
8172  #define GEN9_GFX_MOCS_0		0xc800	/* Graphics MOCS base register*/
8173  #define GEN9_MFX0_MOCS_0	0xc900	/* Media 0 MOCS base register*/
8174  #define GEN9_MFX1_MOCS_0	0xca00	/* Media 1 MOCS base register*/
8175  #define GEN9_VEBOX_MOCS_0	0xcb00	/* Video MOCS base register*/
8176  #define GEN9_BLT_MOCS_0		0xcc00	/* Blitter MOCS base register*/
8177  
8178  #endif /* _I915_REG_H_ */
8179