1 /* 2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 3 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License, version 2, as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 19 #ifndef __ARM_KVM_ASM_H__ 20 #define __ARM_KVM_ASM_H__ 21 22 /* 0 is reserved as an invalid value. */ 23 #define c0_MPIDR 1 /* MultiProcessor ID Register */ 24 #define c0_CSSELR 2 /* Cache Size Selection Register */ 25 #define c1_SCTLR 3 /* System Control Register */ 26 #define c1_ACTLR 4 /* Auxiliary Control Register */ 27 #define c1_CPACR 5 /* Coprocessor Access Control */ 28 #define c2_TTBR0 6 /* Translation Table Base Register 0 */ 29 #define c2_TTBR0_high 7 /* TTBR0 top 32 bits */ 30 #define c2_TTBR1 8 /* Translation Table Base Register 1 */ 31 #define c2_TTBR1_high 9 /* TTBR1 top 32 bits */ 32 #define c2_TTBCR 10 /* Translation Table Base Control R. */ 33 #define c3_DACR 11 /* Domain Access Control Register */ 34 #define c5_DFSR 12 /* Data Fault Status Register */ 35 #define c5_IFSR 13 /* Instruction Fault Status Register */ 36 #define c5_ADFSR 14 /* Auxilary Data Fault Status R */ 37 #define c5_AIFSR 15 /* Auxilary Instrunction Fault Status R */ 38 #define c6_DFAR 16 /* Data Fault Address Register */ 39 #define c6_IFAR 17 /* Instruction Fault Address Register */ 40 #define c7_PAR 18 /* Physical Address Register */ 41 #define c7_PAR_high 19 /* PAR top 32 bits */ 42 #define c9_L2CTLR 20 /* Cortex A15/A7 L2 Control Register */ 43 #define c10_PRRR 21 /* Primary Region Remap Register */ 44 #define c10_NMRR 22 /* Normal Memory Remap Register */ 45 #define c12_VBAR 23 /* Vector Base Address Register */ 46 #define c13_CID 24 /* Context ID Register */ 47 #define c13_TID_URW 25 /* Thread ID, User R/W */ 48 #define c13_TID_URO 26 /* Thread ID, User R/O */ 49 #define c13_TID_PRIV 27 /* Thread ID, Privileged */ 50 #define c14_CNTKCTL 28 /* Timer Control Register (PL1) */ 51 #define c10_AMAIR0 29 /* Auxilary Memory Attribute Indirection Reg0 */ 52 #define c10_AMAIR1 30 /* Auxilary Memory Attribute Indirection Reg1 */ 53 #define NR_CP15_REGS 31 /* Number of regs (incl. invalid) */ 54 55 #define ARM_EXCEPTION_RESET 0 56 #define ARM_EXCEPTION_UNDEFINED 1 57 #define ARM_EXCEPTION_SOFTWARE 2 58 #define ARM_EXCEPTION_PREF_ABORT 3 59 #define ARM_EXCEPTION_DATA_ABORT 4 60 #define ARM_EXCEPTION_IRQ 5 61 #define ARM_EXCEPTION_FIQ 6 62 #define ARM_EXCEPTION_HVC 7 63 64 /* 65 * The rr_lo_hi macro swaps a pair of registers depending on 66 * current endianness. It is used in conjunction with ldrd and strd 67 * instructions that load/store a 64-bit value from/to memory to/from 68 * a pair of registers which are used with the mrrc and mcrr instructions. 69 * If used with the ldrd/strd instructions, the a1 parameter is the first 70 * source/destination register and the a2 parameter is the second 71 * source/destination register. Note that the ldrd/strd instructions 72 * already swap the bytes within the words correctly according to the 73 * endianness setting, but the order of the registers need to be effectively 74 * swapped when used with the mrrc/mcrr instructions. 75 */ 76 #ifdef CONFIG_CPU_ENDIAN_BE8 77 #define rr_lo_hi(a1, a2) a2, a1 78 #else 79 #define rr_lo_hi(a1, a2) a1, a2 80 #endif 81 82 #define kvm_ksym_ref(kva) (kva) 83 84 #ifndef __ASSEMBLY__ 85 struct kvm; 86 struct kvm_vcpu; 87 88 extern char __kvm_hyp_init[]; 89 extern char __kvm_hyp_init_end[]; 90 91 extern char __kvm_hyp_exit[]; 92 extern char __kvm_hyp_exit_end[]; 93 94 extern char __kvm_hyp_vector[]; 95 96 extern char __kvm_hyp_code_start[]; 97 extern char __kvm_hyp_code_end[]; 98 99 extern void __kvm_flush_vm_context(void); 100 extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa); 101 extern void __kvm_tlb_flush_vmid(struct kvm *kvm); 102 103 extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu); 104 #endif 105 106 #endif /* __ARM_KVM_ASM_H__ */ 107