1 /* 2 * asm/metag_isa.h 3 * 4 * Copyright (C) 2000-2007, 2012 Imagination Technologies. 5 * 6 * This program is free software; you can redistribute it and/or modify it under 7 * the terms of the GNU General Public License version 2 as published by the 8 * Free Software Foundation. 9 * 10 * Various defines for Meta instruction set. 11 */ 12 13 #ifndef _ASM_METAG_ISA_H_ 14 #define _ASM_METAG_ISA_H_ 15 16 17 /* L1 cache layout */ 18 19 /* Data cache line size as bytes and shift */ 20 #define DCACHE_LINE_BYTES 64 21 #define DCACHE_LINE_S 6 22 23 /* Number of ways in the data cache */ 24 #define DCACHE_WAYS 4 25 26 /* Instruction cache line size as bytes and shift */ 27 #define ICACHE_LINE_BYTES 64 28 #define ICACHE_LINE_S 6 29 30 /* Number of ways in the instruction cache */ 31 #define ICACHE_WAYS 4 32 33 34 /* 35 * CACHEWD/CACHEWL instructions use the bottom 8 bits of the data presented to 36 * control the operation actually achieved. 37 */ 38 /* Use of these two bits should be discouraged since the bits dont have 39 * consistent meanings 40 */ 41 #define CACHEW_ICACHE_BIT 0x01 42 #define CACHEW_TLBFLUSH_BIT 0x02 43 44 #define CACHEW_FLUSH_L1D_L2 0x0 45 #define CACHEW_INVALIDATE_L1I 0x1 46 #define CACHEW_INVALIDATE_L1DTLB 0x2 47 #define CACHEW_INVALIDATE_L1ITLB 0x3 48 #define CACHEW_WRITEBACK_L1D_L2 0x4 49 #define CACHEW_INVALIDATE_L1D 0x8 50 #define CACHEW_INVALIDATE_L1D_L2 0xC 51 52 /* 53 * CACHERD/CACHERL instructions use bits 3:5 of the address presented to 54 * control the operation achieved and hence the specific result. 55 */ 56 #define CACHER_ADDR_BITS 0xFFFFFFC0 57 #define CACHER_OPER_BITS 0x00000030 58 #define CACHER_OPER_S 4 59 #define CACHER_OPER_LINPHY 0 60 #define CACHER_ICACHE_BIT 0x00000008 61 #define CACHER_ICACHE_S 3 62 63 /* 64 * CACHERD/CACHERL LINPHY Oper result is one/two 32-bit words 65 * 66 * If CRLINPHY0_VAL_BIT (Bit 0) set then, 67 * Lower 32-bits corresponds to MMCU_ENTRY_* above. 68 * Upper 32-bits corresponds to CRLINPHY1_* values below (if requested). 69 * else 70 * Lower 32-bits corresponds to CRLINPHY0_* values below. 71 * Upper 32-bits undefined. 72 */ 73 #define CRLINPHY0_VAL_BIT 0x00000001 74 #define CRLINPHY0_FIRST_BIT 0x00000004 /* Set if VAL=0 due to first level */ 75 76 #define CRLINPHY1_READ_BIT 0x00000001 /* Set if reads permitted */ 77 #define CRLINPHY1_SINGLE_BIT 0x00000004 /* Set if TLB does not cache entry */ 78 #define CRLINPHY1_PAGEMSK_BITS 0x0000FFF0 /* Set to ((2^n-1)>>12) value */ 79 #define CRLINPHY1_PAGEMSK_S 4 80 81 #endif /* _ASM_METAG_ISA_H_ */ 82