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1 /*
2  * Cell Broadband Engine Performance Monitor
3  *
4  * (C) Copyright IBM Corporation 2006
5  *
6  * Author:
7  *   David Erb (djerb@us.ibm.com)
8  *   Kevin Corry (kevcorry@us.ibm.com)
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2, or (at your option)
13  * any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23  */
24 
25 #ifndef __ASM_CELL_PMU_H__
26 #define __ASM_CELL_PMU_H__
27 
28 /* The Cell PMU has four hardware performance counters, which can be
29  * configured as four 32-bit counters or eight 16-bit counters.
30  */
31 #define NR_PHYS_CTRS 4
32 #define NR_CTRS      (NR_PHYS_CTRS * 2)
33 
34 /* Macros for the pm_control register. */
35 #define CBE_PM_16BIT_CTR(ctr)              (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
36 #define CBE_PM_ENABLE_PERF_MON             0x80000000
37 #define CBE_PM_STOP_AT_MAX                 0x40000000
38 #define CBE_PM_TRACE_MODE_GET(pm_control)  (((pm_control) >> 28) & 0x3)
39 #define CBE_PM_TRACE_MODE_SET(mode)        (((mode)  & 0x3) << 28)
40 #define CBE_PM_TRACE_BUF_OVFLW(bit)        (((bit) & 0x1) << 17)
41 #define CBE_PM_COUNT_MODE_SET(count)       (((count) & 0x3) << 18)
42 #define CBE_PM_FREEZE_ALL_CTRS             0x00100000
43 #define CBE_PM_ENABLE_EXT_TRACE            0x00008000
44 #define CBE_PM_SPU_ADDR_TRACE_SET(msk)     (((msk) & 0x3) << 9)
45 
46 /* Macros for the trace_address register. */
47 #define CBE_PM_TRACE_BUF_FULL              0x00000800
48 #define CBE_PM_TRACE_BUF_EMPTY             0x00000400
49 #define CBE_PM_TRACE_BUF_DATA_COUNT(ta)    ((ta) & 0x3ff)
50 #define CBE_PM_TRACE_BUF_MAX_COUNT         0x400
51 
52 /* Macros for the pm07_control registers. */
53 #define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)
54 #define CBE_PM_CTR_INPUT_CONTROL           0x02000000
55 #define CBE_PM_CTR_POLARITY                0x01000000
56 #define CBE_PM_CTR_COUNT_CYCLES            0x00800000
57 #define CBE_PM_CTR_ENABLE                  0x00400000
58 #define PM07_CTR_INPUT_MUX(x)              (((x) & 0x3F) << 26)
59 #define PM07_CTR_INPUT_CONTROL(x)          (((x) & 1) << 25)
60 #define PM07_CTR_POLARITY(x)               (((x) & 1) << 24)
61 #define PM07_CTR_COUNT_CYCLES(x)           (((x) & 1) << 23)
62 #define PM07_CTR_ENABLE(x)                 (((x) & 1) << 22)
63 
64 /* Macros for the pm_status register. */
65 #define CBE_PM_CTR_OVERFLOW_INTR(ctr)      (1 << (31 - ((ctr) & 7)))
66 
67 enum pm_reg_name {
68 	group_control,
69 	debug_bus_control,
70 	trace_address,
71 	ext_tr_timer,
72 	pm_status,
73 	pm_control,
74 	pm_interval,
75 	pm_start_stop,
76 };
77 
78 /* Routines for reading/writing the PMU registers. */
79 extern u32  cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
80 extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
81 extern u32  cbe_read_ctr(u32 cpu, u32 ctr);
82 extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
83 
84 extern u32  cbe_read_pm07_control(u32 cpu, u32 ctr);
85 extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
86 extern u32  cbe_read_pm(u32 cpu, enum pm_reg_name reg);
87 extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
88 
89 extern u32  cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
90 extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
91 
92 extern void cbe_enable_pm(u32 cpu);
93 extern void cbe_disable_pm(u32 cpu);
94 
95 extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);
96 
97 extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
98 extern void cbe_disable_pm_interrupts(u32 cpu);
99 extern u32  cbe_get_and_clear_pm_interrupts(u32 cpu);
100 extern void cbe_sync_irq(int node);
101 
102 #define CBE_COUNT_SUPERVISOR_MODE       0
103 #define CBE_COUNT_HYPERVISOR_MODE       1
104 #define CBE_COUNT_PROBLEM_MODE          2
105 #define CBE_COUNT_ALL_MODES             3
106 
107 #endif /* __ASM_CELL_PMU_H__ */
108