1config MMU 2 def_bool n 3 4config FPU 5 def_bool n 6 7config RWSEM_GENERIC_SPINLOCK 8 def_bool y 9 10config RWSEM_XCHGADD_ALGORITHM 11 def_bool n 12 13config BLACKFIN 14 def_bool y 15 select HAVE_ARCH_KGDB 16 select HAVE_ARCH_TRACEHOOK 17 select HAVE_DYNAMIC_FTRACE 18 select HAVE_FTRACE_MCOUNT_RECORD 19 select HAVE_FUNCTION_GRAPH_TRACER 20 select HAVE_FUNCTION_TRACER 21 select HAVE_IDE 22 select HAVE_KERNEL_GZIP if RAMKERNEL 23 select HAVE_KERNEL_BZIP2 if RAMKERNEL 24 select HAVE_KERNEL_LZMA if RAMKERNEL 25 select HAVE_KERNEL_LZO if RAMKERNEL 26 select HAVE_OPROFILE 27 select HAVE_PERF_EVENTS 28 select ARCH_HAVE_CUSTOM_GPIO_H 29 select ARCH_REQUIRE_GPIOLIB 30 select HAVE_UID16 31 select HAVE_UNDERSCORE_SYMBOL_PREFIX 32 select VIRT_TO_BUS 33 select ARCH_WANT_IPC_PARSE_VERSION 34 select GENERIC_ATOMIC64 35 select GENERIC_IRQ_PROBE 36 select GENERIC_IRQ_SHOW 37 select HAVE_NMI_WATCHDOG if NMI_WATCHDOG 38 select GENERIC_SMP_IDLE_THREAD 39 select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS 40 select HAVE_MOD_ARCH_SPECIFIC 41 select MODULES_USE_ELF_RELA 42 select HAVE_DEBUG_STACKOVERFLOW 43 44config GENERIC_CSUM 45 def_bool y 46 47config GENERIC_BUG 48 def_bool y 49 depends on BUG 50 51config ZONE_DMA 52 def_bool y 53 54config FORCE_MAX_ZONEORDER 55 int 56 default "14" 57 58config GENERIC_CALIBRATE_DELAY 59 def_bool y 60 61config LOCKDEP_SUPPORT 62 def_bool y 63 64config STACKTRACE_SUPPORT 65 def_bool y 66 67config TRACE_IRQFLAGS_SUPPORT 68 def_bool y 69 70source "init/Kconfig" 71 72source "kernel/Kconfig.preempt" 73 74source "kernel/Kconfig.freezer" 75 76menu "Blackfin Processor Options" 77 78comment "Processor and Board Settings" 79 80choice 81 prompt "CPU" 82 default BF533 83 84config BF512 85 bool "BF512" 86 help 87 BF512 Processor Support. 88 89config BF514 90 bool "BF514" 91 help 92 BF514 Processor Support. 93 94config BF516 95 bool "BF516" 96 help 97 BF516 Processor Support. 98 99config BF518 100 bool "BF518" 101 help 102 BF518 Processor Support. 103 104config BF522 105 bool "BF522" 106 help 107 BF522 Processor Support. 108 109config BF523 110 bool "BF523" 111 help 112 BF523 Processor Support. 113 114config BF524 115 bool "BF524" 116 help 117 BF524 Processor Support. 118 119config BF525 120 bool "BF525" 121 help 122 BF525 Processor Support. 123 124config BF526 125 bool "BF526" 126 help 127 BF526 Processor Support. 128 129config BF527 130 bool "BF527" 131 help 132 BF527 Processor Support. 133 134config BF531 135 bool "BF531" 136 help 137 BF531 Processor Support. 138 139config BF532 140 bool "BF532" 141 help 142 BF532 Processor Support. 143 144config BF533 145 bool "BF533" 146 help 147 BF533 Processor Support. 148 149config BF534 150 bool "BF534" 151 help 152 BF534 Processor Support. 153 154config BF536 155 bool "BF536" 156 help 157 BF536 Processor Support. 158 159config BF537 160 bool "BF537" 161 help 162 BF537 Processor Support. 163 164config BF538 165 bool "BF538" 166 help 167 BF538 Processor Support. 168 169config BF539 170 bool "BF539" 171 help 172 BF539 Processor Support. 173 174config BF542_std 175 bool "BF542" 176 help 177 BF542 Processor Support. 178 179config BF542M 180 bool "BF542m" 181 help 182 BF542 Processor Support. 183 184config BF544_std 185 bool "BF544" 186 help 187 BF544 Processor Support. 188 189config BF544M 190 bool "BF544m" 191 help 192 BF544 Processor Support. 193 194config BF547_std 195 bool "BF547" 196 help 197 BF547 Processor Support. 198 199config BF547M 200 bool "BF547m" 201 help 202 BF547 Processor Support. 203 204config BF548_std 205 bool "BF548" 206 help 207 BF548 Processor Support. 208 209config BF548M 210 bool "BF548m" 211 help 212 BF548 Processor Support. 213 214config BF549_std 215 bool "BF549" 216 help 217 BF549 Processor Support. 218 219config BF549M 220 bool "BF549m" 221 help 222 BF549 Processor Support. 223 224config BF561 225 bool "BF561" 226 help 227 BF561 Processor Support. 228 229config BF609 230 bool "BF609" 231 select CLKDEV_LOOKUP 232 help 233 BF609 Processor Support. 234 235endchoice 236 237config SMP 238 depends on BF561 239 select TICKSOURCE_CORETMR 240 bool "Symmetric multi-processing support" 241 ---help--- 242 This enables support for systems with more than one CPU, 243 like the dual core BF561. If you have a system with only one 244 CPU, say N. If you have a system with more than one CPU, say Y. 245 246 If you don't know what to do here, say N. 247 248config NR_CPUS 249 int 250 depends on SMP 251 default 2 if BF561 252 253config HOTPLUG_CPU 254 bool "Support for hot-pluggable CPUs" 255 depends on SMP 256 default y 257 258config BF_REV_MIN 259 int 260 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x 261 default 2 if (BF537 || BF536 || BF534) 262 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) 263 default 4 if (BF538 || BF539) 264 265config BF_REV_MAX 266 int 267 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x 268 default 3 if (BF537 || BF536 || BF534 || BF54xM) 269 default 5 if (BF561 || BF538 || BF539) 270 default 6 if (BF533 || BF532 || BF531) 271 272choice 273 prompt "Silicon Rev" 274 default BF_REV_0_0 if (BF51x || BF52x || BF60x) 275 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) 276 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) 277 278config BF_REV_0_0 279 bool "0.0" 280 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) 281 282config BF_REV_0_1 283 bool "0.1" 284 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) 285 286config BF_REV_0_2 287 bool "0.2" 288 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) 289 290config BF_REV_0_3 291 bool "0.3" 292 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) 293 294config BF_REV_0_4 295 bool "0.4" 296 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x) 297 298config BF_REV_0_5 299 bool "0.5" 300 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) 301 302config BF_REV_0_6 303 bool "0.6" 304 depends on (BF533 || BF532 || BF531) 305 306config BF_REV_ANY 307 bool "any" 308 309config BF_REV_NONE 310 bool "none" 311 312endchoice 313 314config BF53x 315 bool 316 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) 317 default y 318 319config GPIO_ADI 320 def_bool y 321 depends on !PINCTRL 322 depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561) 323 324config PINCTRL_BLACKFIN_ADI2 325 def_bool y 326 depends on (BF54x || BF60x) 327 select PINCTRL 328 select PINCTRL_ADI2 329 330config MEM_MT48LC64M4A2FB_7E 331 bool 332 depends on (BFIN533_STAMP) 333 default y 334 335config MEM_MT48LC16M16A2TG_75 336 bool 337 depends on (BFIN533_EZKIT || BFIN561_EZKIT \ 338 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ 339 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ 340 || BFIN527_BLUETECHNIX_CM) 341 default y 342 343config MEM_MT48LC32M8A2_75 344 bool 345 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) 346 default y 347 348config MEM_MT48LC8M32B2B5_7 349 bool 350 depends on (BFIN561_BLUETECHNIX_CM) 351 default y 352 353config MEM_MT48LC32M16A2TG_75 354 bool 355 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL) 356 default y 357 358config MEM_MT48H32M16LFCJ_75 359 bool 360 depends on (BFIN526_EZBRD) 361 default y 362 363config MEM_MT47H64M16 364 bool 365 depends on (BFIN609_EZKIT) 366 default y 367 368source "arch/blackfin/mach-bf518/Kconfig" 369source "arch/blackfin/mach-bf527/Kconfig" 370source "arch/blackfin/mach-bf533/Kconfig" 371source "arch/blackfin/mach-bf561/Kconfig" 372source "arch/blackfin/mach-bf537/Kconfig" 373source "arch/blackfin/mach-bf538/Kconfig" 374source "arch/blackfin/mach-bf548/Kconfig" 375source "arch/blackfin/mach-bf609/Kconfig" 376 377menu "Board customizations" 378 379config CMDLINE_BOOL 380 bool "Default bootloader kernel arguments" 381 382config CMDLINE 383 string "Initial kernel command string" 384 depends on CMDLINE_BOOL 385 default "console=ttyBF0,57600" 386 help 387 If you don't have a boot loader capable of passing a command line string 388 to the kernel, you may specify one here. As a minimum, you should specify 389 the memory size and the root device (e.g., mem=8M, root=/dev/nfs). 390 391config BOOT_LOAD 392 hex "Kernel load address for booting" 393 default "0x1000" 394 range 0x1000 0x20000000 395 help 396 This option allows you to set the load address of the kernel. 397 This can be useful if you are on a board which has a small amount 398 of memory or you wish to reserve some memory at the beginning of 399 the address space. 400 401 Note that you need to keep this value above 4k (0x1000) as this 402 memory region is used to capture NULL pointer references as well 403 as some core kernel functions. 404 405config PHY_RAM_BASE_ADDRESS 406 hex "Physical RAM Base" 407 default 0x0 408 help 409 set BF609 FPGA physical SRAM base address 410 411config ROM_BASE 412 hex "Kernel ROM Base" 413 depends on ROMKERNEL 414 default "0x20040040" 415 range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x) 416 range 0x20000000 0x30000000 if (BF54x || BF561) 417 range 0xB0000000 0xC0000000 if (BF60x) 418 help 419 Make sure your ROM base does not include any file-header 420 information that is prepended to the kernel. 421 422 For example, the bootable U-Boot format (created with 423 mkimage) has a 64 byte header (0x40). So while the image 424 you write to flash might start at say 0x20080000, you have 425 to add 0x40 to get the kernel's ROM base as it will come 426 after the header. 427 428comment "Clock/PLL Setup" 429 430config CLKIN_HZ 431 int "Frequency of the crystal on the board in Hz" 432 default "10000000" if BFIN532_IP0X 433 default "11059200" if BFIN533_STAMP 434 default "24576000" if PNAV10 435 default "25000000" # most people use this 436 default "27000000" if BFIN533_EZKIT 437 default "30000000" if BFIN561_EZKIT 438 default "24000000" if BFIN527_AD7160EVAL 439 help 440 The frequency of CLKIN crystal oscillator on the board in Hz. 441 Warning: This value should match the crystal on the board. Otherwise, 442 peripherals won't work properly. 443 444config BFIN_KERNEL_CLOCK 445 bool "Re-program Clocks while Kernel boots?" 446 default n 447 help 448 This option decides if kernel clocks are re-programed from the 449 bootloader settings. If the clocks are not set, the SDRAM settings 450 are also not changed, and the Bootloader does 100% of the hardware 451 configuration. 452 453config PLL_BYPASS 454 bool "Bypass PLL" 455 depends on BFIN_KERNEL_CLOCK && (!BF60x) 456 default n 457 458config CLKIN_HALF 459 bool "Half Clock In" 460 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) 461 default n 462 help 463 If this is set the clock will be divided by 2, before it goes to the PLL. 464 465config VCO_MULT 466 int "VCO Multiplier" 467 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) 468 range 1 64 469 default "22" if BFIN533_EZKIT 470 default "45" if BFIN533_STAMP 471 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) 472 default "22" if BFIN533_BLUETECHNIX_CM 473 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) 474 default "20" if (BFIN561_EZKIT || BF609) 475 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) 476 default "25" if BFIN527_AD7160EVAL 477 help 478 This controls the frequency of the on-chip PLL. This can be between 1 and 64. 479 PLL Frequency = (Crystal Frequency) * (this setting) 480 481choice 482 prompt "Core Clock Divider" 483 depends on BFIN_KERNEL_CLOCK 484 default CCLK_DIV_1 485 help 486 This sets the frequency of the core. It can be 1, 2, 4 or 8 487 Core Frequency = (PLL frequency) / (this setting) 488 489config CCLK_DIV_1 490 bool "1" 491 492config CCLK_DIV_2 493 bool "2" 494 495config CCLK_DIV_4 496 bool "4" 497 498config CCLK_DIV_8 499 bool "8" 500endchoice 501 502config SCLK_DIV 503 int "System Clock Divider" 504 depends on BFIN_KERNEL_CLOCK 505 range 1 15 506 default 4 507 help 508 This sets the frequency of the system clock (including SDRAM or DDR) on 509 !BF60x else it set the clock for system buses and provides the 510 source from which SCLK0 and SCLK1 are derived. 511 This can be between 1 and 15 512 System Clock = (PLL frequency) / (this setting) 513 514config SCLK0_DIV 515 int "System Clock0 Divider" 516 depends on BFIN_KERNEL_CLOCK && BF60x 517 range 1 15 518 default 1 519 help 520 This sets the frequency of the system clock0 for PVP and all other 521 peripherals not clocked by SCLK1. 522 This can be between 1 and 15 523 System Clock0 = (System Clock) / (this setting) 524 525config SCLK1_DIV 526 int "System Clock1 Divider" 527 depends on BFIN_KERNEL_CLOCK && BF60x 528 range 1 15 529 default 1 530 help 531 This sets the frequency of the system clock1 (including SPORT, SPI and ACM). 532 This can be between 1 and 15 533 System Clock1 = (System Clock) / (this setting) 534 535config DCLK_DIV 536 int "DDR Clock Divider" 537 depends on BFIN_KERNEL_CLOCK && BF60x 538 range 1 15 539 default 2 540 help 541 This sets the frequency of the DDR memory. 542 This can be between 1 and 15 543 DDR Clock = (PLL frequency) / (this setting) 544 545choice 546 prompt "DDR SDRAM Chip Type" 547 depends on BFIN_KERNEL_CLOCK 548 depends on BF54x 549 default MEM_MT46V32M16_5B 550 551config MEM_MT46V32M16_6T 552 bool "MT46V32M16_6T" 553 554config MEM_MT46V32M16_5B 555 bool "MT46V32M16_5B" 556endchoice 557 558choice 559 prompt "DDR/SDRAM Timing" 560 depends on BFIN_KERNEL_CLOCK && !BF60x 561 default BFIN_KERNEL_CLOCK_MEMINIT_CALC 562 help 563 This option allows you to specify Blackfin SDRAM/DDR Timing parameters 564 The calculated SDRAM timing parameters may not be 100% 565 accurate - This option is therefore marked experimental. 566 567config BFIN_KERNEL_CLOCK_MEMINIT_CALC 568 bool "Calculate Timings" 569 570config BFIN_KERNEL_CLOCK_MEMINIT_SPEC 571 bool "Provide accurate Timings based on target SCLK" 572 help 573 Please consult the Blackfin Hardware Reference Manuals as well 574 as the memory device datasheet. 575 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram 576endchoice 577 578menu "Memory Init Control" 579 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC 580 581config MEM_DDRCTL0 582 depends on BF54x 583 hex "DDRCTL0" 584 default 0x0 585 586config MEM_DDRCTL1 587 depends on BF54x 588 hex "DDRCTL1" 589 default 0x0 590 591config MEM_DDRCTL2 592 depends on BF54x 593 hex "DDRCTL2" 594 default 0x0 595 596config MEM_EBIU_DDRQUE 597 depends on BF54x 598 hex "DDRQUE" 599 default 0x0 600 601config MEM_SDRRC 602 depends on !BF54x 603 hex "SDRRC" 604 default 0x0 605 606config MEM_SDGCTL 607 depends on !BF54x 608 hex "SDGCTL" 609 default 0x0 610endmenu 611 612# 613# Max & Min Speeds for various Chips 614# 615config MAX_VCO_HZ 616 int 617 default 400000000 if BF512 618 default 400000000 if BF514 619 default 400000000 if BF516 620 default 400000000 if BF518 621 default 400000000 if BF522 622 default 600000000 if BF523 623 default 400000000 if BF524 624 default 600000000 if BF525 625 default 400000000 if BF526 626 default 600000000 if BF527 627 default 400000000 if BF531 628 default 400000000 if BF532 629 default 750000000 if BF533 630 default 500000000 if BF534 631 default 400000000 if BF536 632 default 600000000 if BF537 633 default 533333333 if BF538 634 default 533333333 if BF539 635 default 600000000 if BF542 636 default 533333333 if BF544 637 default 600000000 if BF547 638 default 600000000 if BF548 639 default 533333333 if BF549 640 default 600000000 if BF561 641 default 800000000 if BF609 642 643config MIN_VCO_HZ 644 int 645 default 50000000 646 647config MAX_SCLK_HZ 648 int 649 default 200000000 if BF609 650 default 133333333 651 652config MIN_SCLK_HZ 653 int 654 default 27000000 655 656comment "Kernel Timer/Scheduler" 657 658source kernel/Kconfig.hz 659 660config SET_GENERIC_CLOCKEVENTS 661 bool "Generic clock events" 662 default y 663 select GENERIC_CLOCKEVENTS 664 665menu "Clock event device" 666 depends on GENERIC_CLOCKEVENTS 667config TICKSOURCE_GPTMR0 668 bool "GPTimer0" 669 depends on !SMP 670 select BFIN_GPTIMERS 671 672config TICKSOURCE_CORETMR 673 bool "Core timer" 674 default y 675endmenu 676 677menu "Clock source" 678 depends on GENERIC_CLOCKEVENTS 679config CYCLES_CLOCKSOURCE 680 bool "CYCLES" 681 default y 682 depends on !BFIN_SCRATCH_REG_CYCLES 683 depends on !SMP 684 help 685 If you say Y here, you will enable support for using the 'cycles' 686 registers as a clock source. Doing so means you will be unable to 687 safely write to the 'cycles' register during runtime. You will 688 still be able to read it (such as for performance monitoring), but 689 writing the registers will most likely crash the kernel. 690 691config GPTMR0_CLOCKSOURCE 692 bool "GPTimer0" 693 select BFIN_GPTIMERS 694 depends on !TICKSOURCE_GPTMR0 695endmenu 696 697comment "Misc" 698 699choice 700 prompt "Blackfin Exception Scratch Register" 701 default BFIN_SCRATCH_REG_RETN 702 help 703 Select the resource to reserve for the Exception handler: 704 - RETN: Non-Maskable Interrupt (NMI) 705 - RETE: Exception Return (JTAG/ICE) 706 - CYCLES: Performance counter 707 708 If you are unsure, please select "RETN". 709 710config BFIN_SCRATCH_REG_RETN 711 bool "RETN" 712 help 713 Use the RETN register in the Blackfin exception handler 714 as a stack scratch register. This means you cannot 715 safely use NMI on the Blackfin while running Linux, but 716 you can debug the system with a JTAG ICE and use the 717 CYCLES performance registers. 718 719 If you are unsure, please select "RETN". 720 721config BFIN_SCRATCH_REG_RETE 722 bool "RETE" 723 help 724 Use the RETE register in the Blackfin exception handler 725 as a stack scratch register. This means you cannot 726 safely use a JTAG ICE while debugging a Blackfin board, 727 but you can safely use the CYCLES performance registers 728 and the NMI. 729 730 If you are unsure, please select "RETN". 731 732config BFIN_SCRATCH_REG_CYCLES 733 bool "CYCLES" 734 help 735 Use the CYCLES register in the Blackfin exception handler 736 as a stack scratch register. This means you cannot 737 safely use the CYCLES performance registers on a Blackfin 738 board at anytime, but you can debug the system with a JTAG 739 ICE and use the NMI. 740 741 If you are unsure, please select "RETN". 742 743endchoice 744 745endmenu 746 747 748menu "Blackfin Kernel Optimizations" 749 750comment "Memory Optimizations" 751 752config I_ENTRY_L1 753 bool "Locate interrupt entry code in L1 Memory" 754 default y 755 depends on !SMP 756 help 757 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked 758 into L1 instruction memory. (less latency) 759 760config EXCPT_IRQ_SYSC_L1 761 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" 762 default y 763 depends on !SMP 764 help 765 If enabled, the entire ASM lowlevel exception and interrupt entry code 766 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. 767 (less latency) 768 769config DO_IRQ_L1 770 bool "Locate frequently called do_irq dispatcher function in L1 Memory" 771 default y 772 depends on !SMP 773 help 774 If enabled, the frequently called do_irq dispatcher function is linked 775 into L1 instruction memory. (less latency) 776 777config CORE_TIMER_IRQ_L1 778 bool "Locate frequently called timer_interrupt() function in L1 Memory" 779 default y 780 depends on !SMP 781 help 782 If enabled, the frequently called timer_interrupt() function is linked 783 into L1 instruction memory. (less latency) 784 785config IDLE_L1 786 bool "Locate frequently idle function in L1 Memory" 787 default y 788 depends on !SMP 789 help 790 If enabled, the frequently called idle function is linked 791 into L1 instruction memory. (less latency) 792 793config SCHEDULE_L1 794 bool "Locate kernel schedule function in L1 Memory" 795 default y 796 depends on !SMP 797 help 798 If enabled, the frequently called kernel schedule is linked 799 into L1 instruction memory. (less latency) 800 801config ARITHMETIC_OPS_L1 802 bool "Locate kernel owned arithmetic functions in L1 Memory" 803 default y 804 depends on !SMP 805 help 806 If enabled, arithmetic functions are linked 807 into L1 instruction memory. (less latency) 808 809config ACCESS_OK_L1 810 bool "Locate access_ok function in L1 Memory" 811 default y 812 depends on !SMP 813 help 814 If enabled, the access_ok function is linked 815 into L1 instruction memory. (less latency) 816 817config MEMSET_L1 818 bool "Locate memset function in L1 Memory" 819 default y 820 depends on !SMP 821 help 822 If enabled, the memset function is linked 823 into L1 instruction memory. (less latency) 824 825config MEMCPY_L1 826 bool "Locate memcpy function in L1 Memory" 827 default y 828 depends on !SMP 829 help 830 If enabled, the memcpy function is linked 831 into L1 instruction memory. (less latency) 832 833config STRCMP_L1 834 bool "locate strcmp function in L1 Memory" 835 default y 836 depends on !SMP 837 help 838 If enabled, the strcmp function is linked 839 into L1 instruction memory (less latency). 840 841config STRNCMP_L1 842 bool "locate strncmp function in L1 Memory" 843 default y 844 depends on !SMP 845 help 846 If enabled, the strncmp function is linked 847 into L1 instruction memory (less latency). 848 849config STRCPY_L1 850 bool "locate strcpy function in L1 Memory" 851 default y 852 depends on !SMP 853 help 854 If enabled, the strcpy function is linked 855 into L1 instruction memory (less latency). 856 857config STRNCPY_L1 858 bool "locate strncpy function in L1 Memory" 859 default y 860 depends on !SMP 861 help 862 If enabled, the strncpy function is linked 863 into L1 instruction memory (less latency). 864 865config SYS_BFIN_SPINLOCK_L1 866 bool "Locate sys_bfin_spinlock function in L1 Memory" 867 default y 868 depends on !SMP 869 help 870 If enabled, sys_bfin_spinlock function is linked 871 into L1 instruction memory. (less latency) 872 873config CACHELINE_ALIGNED_L1 874 bool "Locate cacheline_aligned data to L1 Data Memory" 875 default y if !BF54x 876 default n if BF54x 877 depends on !SMP && !BF531 && !CRC32 878 help 879 If enabled, cacheline_aligned data is linked 880 into L1 data memory. (less latency) 881 882config SYSCALL_TAB_L1 883 bool "Locate Syscall Table L1 Data Memory" 884 default n 885 depends on !SMP && !BF531 886 help 887 If enabled, the Syscall LUT is linked 888 into L1 data memory. (less latency) 889 890config CPLB_SWITCH_TAB_L1 891 bool "Locate CPLB Switch Tables L1 Data Memory" 892 default n 893 depends on !SMP && !BF531 894 help 895 If enabled, the CPLB Switch Tables are linked 896 into L1 data memory. (less latency) 897 898config ICACHE_FLUSH_L1 899 bool "Locate icache flush funcs in L1 Inst Memory" 900 default y 901 help 902 If enabled, the Blackfin icache flushing functions are linked 903 into L1 instruction memory. 904 905 Note that this might be required to address anomalies, but 906 these functions are pretty small, so it shouldn't be too bad. 907 If you are using a processor affected by an anomaly, the build 908 system will double check for you and prevent it. 909 910config DCACHE_FLUSH_L1 911 bool "Locate dcache flush funcs in L1 Inst Memory" 912 default y 913 depends on !SMP 914 help 915 If enabled, the Blackfin dcache flushing functions are linked 916 into L1 instruction memory. 917 918config APP_STACK_L1 919 bool "Support locating application stack in L1 Scratch Memory" 920 default y 921 depends on !SMP 922 help 923 If enabled the application stack can be located in L1 924 scratch memory (less latency). 925 926 Currently only works with FLAT binaries. 927 928config EXCEPTION_L1_SCRATCH 929 bool "Locate exception stack in L1 Scratch Memory" 930 default n 931 depends on !SMP && !APP_STACK_L1 932 help 933 Whenever an exception occurs, use the L1 Scratch memory for 934 stack storage. You cannot place the stacks of FLAT binaries 935 in L1 when using this option. 936 937 If you don't use L1 Scratch, then you should say Y here. 938 939comment "Speed Optimizations" 940config BFIN_INS_LOWOVERHEAD 941 bool "ins[bwl] low overhead, higher interrupt latency" 942 default y 943 depends on !SMP 944 help 945 Reads on the Blackfin are speculative. In Blackfin terms, this means 946 they can be interrupted at any time (even after they have been issued 947 on to the external bus), and re-issued after the interrupt occurs. 948 For memory - this is not a big deal, since memory does not change if 949 it sees a read. 950 951 If a FIFO is sitting on the end of the read, it will see two reads, 952 when the core only sees one since the FIFO receives both the read 953 which is cancelled (and not delivered to the core) and the one which 954 is re-issued (which is delivered to the core). 955 956 To solve this, interrupts are turned off before reads occur to 957 I/O space. This option controls which the overhead/latency of 958 controlling interrupts during this time 959 "n" turns interrupts off every read 960 (higher overhead, but lower interrupt latency) 961 "y" turns interrupts off every loop 962 (low overhead, but longer interrupt latency) 963 964 default behavior is to leave this set to on (type "Y"). If you are experiencing 965 interrupt latency issues, it is safe and OK to turn this off. 966 967endmenu 968 969choice 970 prompt "Kernel executes from" 971 help 972 Choose the memory type that the kernel will be running in. 973 974config RAMKERNEL 975 bool "RAM" 976 help 977 The kernel will be resident in RAM when running. 978 979config ROMKERNEL 980 bool "ROM" 981 help 982 The kernel will be resident in FLASH/ROM when running. 983 984endchoice 985 986# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both 987config XIP_KERNEL 988 bool 989 default y 990 depends on ROMKERNEL 991 992source "mm/Kconfig" 993 994config BFIN_GPTIMERS 995 tristate "Enable Blackfin General Purpose Timers API" 996 default n 997 help 998 Enable support for the General Purpose Timers API. If you 999 are unsure, say N. 1000 1001 To compile this driver as a module, choose M here: the module 1002 will be called gptimers. 1003 1004choice 1005 prompt "Uncached DMA region" 1006 default DMA_UNCACHED_1M 1007config DMA_UNCACHED_32M 1008 bool "Enable 32M DMA region" 1009config DMA_UNCACHED_16M 1010 bool "Enable 16M DMA region" 1011config DMA_UNCACHED_8M 1012 bool "Enable 8M DMA region" 1013config DMA_UNCACHED_4M 1014 bool "Enable 4M DMA region" 1015config DMA_UNCACHED_2M 1016 bool "Enable 2M DMA region" 1017config DMA_UNCACHED_1M 1018 bool "Enable 1M DMA region" 1019config DMA_UNCACHED_512K 1020 bool "Enable 512K DMA region" 1021config DMA_UNCACHED_256K 1022 bool "Enable 256K DMA region" 1023config DMA_UNCACHED_128K 1024 bool "Enable 128K DMA region" 1025config DMA_UNCACHED_NONE 1026 bool "Disable DMA region" 1027endchoice 1028 1029 1030comment "Cache Support" 1031 1032config BFIN_ICACHE 1033 bool "Enable ICACHE" 1034 default y 1035config BFIN_EXTMEM_ICACHEABLE 1036 bool "Enable ICACHE for external memory" 1037 depends on BFIN_ICACHE 1038 default y 1039config BFIN_L2_ICACHEABLE 1040 bool "Enable ICACHE for L2 SRAM" 1041 depends on BFIN_ICACHE 1042 depends on (BF54x || BF561 || BF60x) && !SMP 1043 default n 1044 1045config BFIN_DCACHE 1046 bool "Enable DCACHE" 1047 default y 1048config BFIN_DCACHE_BANKA 1049 bool "Enable only 16k BankA DCACHE - BankB is SRAM" 1050 depends on BFIN_DCACHE && !BF531 1051 default n 1052config BFIN_EXTMEM_DCACHEABLE 1053 bool "Enable DCACHE for external memory" 1054 depends on BFIN_DCACHE 1055 default y 1056choice 1057 prompt "External memory DCACHE policy" 1058 depends on BFIN_EXTMEM_DCACHEABLE 1059 default BFIN_EXTMEM_WRITEBACK if !SMP 1060 default BFIN_EXTMEM_WRITETHROUGH if SMP 1061config BFIN_EXTMEM_WRITEBACK 1062 bool "Write back" 1063 depends on !SMP 1064 help 1065 Write Back Policy: 1066 Cached data will be written back to SDRAM only when needed. 1067 This can give a nice increase in performance, but beware of 1068 broken drivers that do not properly invalidate/flush their 1069 cache. 1070 1071 Write Through Policy: 1072 Cached data will always be written back to SDRAM when the 1073 cache is updated. This is a completely safe setting, but 1074 performance is worse than Write Back. 1075 1076 If you are unsure of the options and you want to be safe, 1077 then go with Write Through. 1078 1079config BFIN_EXTMEM_WRITETHROUGH 1080 bool "Write through" 1081 help 1082 Write Back Policy: 1083 Cached data will be written back to SDRAM only when needed. 1084 This can give a nice increase in performance, but beware of 1085 broken drivers that do not properly invalidate/flush their 1086 cache. 1087 1088 Write Through Policy: 1089 Cached data will always be written back to SDRAM when the 1090 cache is updated. This is a completely safe setting, but 1091 performance is worse than Write Back. 1092 1093 If you are unsure of the options and you want to be safe, 1094 then go with Write Through. 1095 1096endchoice 1097 1098config BFIN_L2_DCACHEABLE 1099 bool "Enable DCACHE for L2 SRAM" 1100 depends on BFIN_DCACHE 1101 depends on (BF54x || BF561 || BF60x) && !SMP 1102 default n 1103choice 1104 prompt "L2 SRAM DCACHE policy" 1105 depends on BFIN_L2_DCACHEABLE 1106 default BFIN_L2_WRITEBACK 1107config BFIN_L2_WRITEBACK 1108 bool "Write back" 1109 1110config BFIN_L2_WRITETHROUGH 1111 bool "Write through" 1112endchoice 1113 1114 1115comment "Memory Protection Unit" 1116config MPU 1117 bool "Enable the memory protection unit" 1118 default n 1119 help 1120 Use the processor's MPU to protect applications from accessing 1121 memory they do not own. This comes at a performance penalty 1122 and is recommended only for debugging. 1123 1124comment "Asynchronous Memory Configuration" 1125 1126menu "EBIU_AMGCTL Global Control" 1127 depends on !BF60x 1128config C_AMCKEN 1129 bool "Enable CLKOUT" 1130 default y 1131 1132config C_CDPRIO 1133 bool "DMA has priority over core for ext. accesses" 1134 default n 1135 1136config C_B0PEN 1137 depends on BF561 1138 bool "Bank 0 16 bit packing enable" 1139 default y 1140 1141config C_B1PEN 1142 depends on BF561 1143 bool "Bank 1 16 bit packing enable" 1144 default y 1145 1146config C_B2PEN 1147 depends on BF561 1148 bool "Bank 2 16 bit packing enable" 1149 default y 1150 1151config C_B3PEN 1152 depends on BF561 1153 bool "Bank 3 16 bit packing enable" 1154 default n 1155 1156choice 1157 prompt "Enable Asynchronous Memory Banks" 1158 default C_AMBEN_ALL 1159 1160config C_AMBEN 1161 bool "Disable All Banks" 1162 1163config C_AMBEN_B0 1164 bool "Enable Bank 0" 1165 1166config C_AMBEN_B0_B1 1167 bool "Enable Bank 0 & 1" 1168 1169config C_AMBEN_B0_B1_B2 1170 bool "Enable Bank 0 & 1 & 2" 1171 1172config C_AMBEN_ALL 1173 bool "Enable All Banks" 1174endchoice 1175endmenu 1176 1177menu "EBIU_AMBCTL Control" 1178 depends on !BF60x 1179config BANK_0 1180 hex "Bank 0 (AMBCTL0.L)" 1181 default 0x7BB0 1182 help 1183 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are 1184 used to control the Asynchronous Memory Bank 0 settings. 1185 1186config BANK_1 1187 hex "Bank 1 (AMBCTL0.H)" 1188 default 0x7BB0 1189 default 0x5558 if BF54x 1190 help 1191 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are 1192 used to control the Asynchronous Memory Bank 1 settings. 1193 1194config BANK_2 1195 hex "Bank 2 (AMBCTL1.L)" 1196 default 0x7BB0 1197 help 1198 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are 1199 used to control the Asynchronous Memory Bank 2 settings. 1200 1201config BANK_3 1202 hex "Bank 3 (AMBCTL1.H)" 1203 default 0x99B3 1204 help 1205 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are 1206 used to control the Asynchronous Memory Bank 3 settings. 1207 1208endmenu 1209 1210config EBIU_MBSCTLVAL 1211 hex "EBIU Bank Select Control Register" 1212 depends on BF54x 1213 default 0 1214 1215config EBIU_MODEVAL 1216 hex "Flash Memory Mode Control Register" 1217 depends on BF54x 1218 default 1 1219 1220config EBIU_FCTLVAL 1221 hex "Flash Memory Bank Control Register" 1222 depends on BF54x 1223 default 6 1224endmenu 1225 1226############################################################################# 1227menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" 1228 1229config PCI 1230 bool "PCI support" 1231 depends on BROKEN 1232 help 1233 Support for PCI bus. 1234 1235source "drivers/pci/Kconfig" 1236 1237source "drivers/pcmcia/Kconfig" 1238 1239source "drivers/pci/hotplug/Kconfig" 1240 1241endmenu 1242 1243menu "Executable file formats" 1244 1245source "fs/Kconfig.binfmt" 1246 1247endmenu 1248 1249menu "Power management options" 1250 1251source "kernel/power/Kconfig" 1252 1253config ARCH_SUSPEND_POSSIBLE 1254 def_bool y 1255 1256choice 1257 prompt "Standby Power Saving Mode" 1258 depends on PM && !BF60x 1259 default PM_BFIN_SLEEP_DEEPER 1260config PM_BFIN_SLEEP_DEEPER 1261 bool "Sleep Deeper" 1262 help 1263 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic 1264 power dissipation by disabling the clock to the processor core (CCLK). 1265 Furthermore, Standby sets the internal power supply voltage (VDDINT) 1266 to 0.85 V to provide the greatest power savings, while preserving the 1267 processor state. 1268 The PLL and system clock (SCLK) continue to operate at a very low 1269 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, 1270 the SDRAM is put into Self Refresh Mode. Typically an external event 1271 such as GPIO interrupt or RTC activity wakes up the processor. 1272 Various Peripherals such as UART, SPORT, PPI may not function as 1273 normal during Sleep Deeper, due to the reduced SCLK frequency. 1274 When in the sleep mode, system DMA access to L1 memory is not supported. 1275 1276 If unsure, select "Sleep Deeper". 1277 1278config PM_BFIN_SLEEP 1279 bool "Sleep" 1280 help 1281 Sleep Mode (High Power Savings) - The sleep mode reduces power 1282 dissipation by disabling the clock to the processor core (CCLK). 1283 The PLL and system clock (SCLK), however, continue to operate in 1284 this mode. Typically an external event or RTC activity will wake 1285 up the processor. When in the sleep mode, system DMA access to L1 1286 memory is not supported. 1287 1288 If unsure, select "Sleep Deeper". 1289endchoice 1290 1291comment "Possible Suspend Mem / Hibernate Wake-Up Sources" 1292 depends on PM 1293 1294config PM_BFIN_WAKE_PH6 1295 bool "Allow Wake-Up from on-chip PHY or PH6 GP" 1296 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) 1297 default n 1298 help 1299 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) 1300 1301config PM_BFIN_WAKE_GP 1302 bool "Allow Wake-Up from GPIOs" 1303 depends on PM && BF54x 1304 default n 1305 help 1306 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) 1307 (all processors, except ADSP-BF549). This option sets 1308 the general-purpose wake-up enable (GPWE) control bit to enable 1309 wake-up upon detection of an active low signal on the /GPW (PH7) pin. 1310 On ADSP-BF549 this option enables the same functionality on the 1311 /MRXON pin also PH7. 1312 1313config PM_BFIN_WAKE_PA15 1314 bool "Allow Wake-Up from PA15" 1315 depends on PM && BF60x 1316 default n 1317 help 1318 Enable PA15 Wake-Up 1319 1320config PM_BFIN_WAKE_PA15_POL 1321 int "Wake-up priority" 1322 depends on PM_BFIN_WAKE_PA15 1323 default 0 1324 help 1325 Wake-Up priority 0(low) 1(high) 1326 1327config PM_BFIN_WAKE_PB15 1328 bool "Allow Wake-Up from PB15" 1329 depends on PM && BF60x 1330 default n 1331 help 1332 Enable PB15 Wake-Up 1333 1334config PM_BFIN_WAKE_PB15_POL 1335 int "Wake-up priority" 1336 depends on PM_BFIN_WAKE_PB15 1337 default 0 1338 help 1339 Wake-Up priority 0(low) 1(high) 1340 1341config PM_BFIN_WAKE_PC15 1342 bool "Allow Wake-Up from PC15" 1343 depends on PM && BF60x 1344 default n 1345 help 1346 Enable PC15 Wake-Up 1347 1348config PM_BFIN_WAKE_PC15_POL 1349 int "Wake-up priority" 1350 depends on PM_BFIN_WAKE_PC15 1351 default 0 1352 help 1353 Wake-Up priority 0(low) 1(high) 1354 1355config PM_BFIN_WAKE_PD06 1356 bool "Allow Wake-Up from PD06(ETH0_PHYINT)" 1357 depends on PM && BF60x 1358 default n 1359 help 1360 Enable PD06(ETH0_PHYINT) Wake-up 1361 1362config PM_BFIN_WAKE_PD06_POL 1363 int "Wake-up priority" 1364 depends on PM_BFIN_WAKE_PD06 1365 default 0 1366 help 1367 Wake-Up priority 0(low) 1(high) 1368 1369config PM_BFIN_WAKE_PE12 1370 bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)" 1371 depends on PM && BF60x 1372 default n 1373 help 1374 Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up 1375 1376config PM_BFIN_WAKE_PE12_POL 1377 int "Wake-up priority" 1378 depends on PM_BFIN_WAKE_PE12 1379 default 0 1380 help 1381 Wake-Up priority 0(low) 1(high) 1382 1383config PM_BFIN_WAKE_PG04 1384 bool "Allow Wake-Up from PG04(CAN0_RX)" 1385 depends on PM && BF60x 1386 default n 1387 help 1388 Enable PG04(CAN0_RX) Wake-up 1389 1390config PM_BFIN_WAKE_PG04_POL 1391 int "Wake-up priority" 1392 depends on PM_BFIN_WAKE_PG04 1393 default 0 1394 help 1395 Wake-Up priority 0(low) 1(high) 1396 1397config PM_BFIN_WAKE_PG13 1398 bool "Allow Wake-Up from PG13" 1399 depends on PM && BF60x 1400 default n 1401 help 1402 Enable PG13 Wake-Up 1403 1404config PM_BFIN_WAKE_PG13_POL 1405 int "Wake-up priority" 1406 depends on PM_BFIN_WAKE_PG13 1407 default 0 1408 help 1409 Wake-Up priority 0(low) 1(high) 1410 1411config PM_BFIN_WAKE_USB 1412 bool "Allow Wake-Up from (USB)" 1413 depends on PM && BF60x 1414 default n 1415 help 1416 Enable (USB) Wake-up 1417 1418config PM_BFIN_WAKE_USB_POL 1419 int "Wake-up priority" 1420 depends on PM_BFIN_WAKE_USB 1421 default 0 1422 help 1423 Wake-Up priority 0(low) 1(high) 1424 1425endmenu 1426 1427menu "CPU Frequency scaling" 1428 1429source "drivers/cpufreq/Kconfig" 1430 1431config BFIN_CPU_FREQ 1432 bool 1433 depends on CPU_FREQ 1434 default y 1435 1436config CPU_VOLTAGE 1437 bool "CPU Voltage scaling" 1438 depends on CPU_FREQ 1439 default n 1440 help 1441 Say Y here if you want CPU voltage scaling according to the CPU frequency. 1442 This option violates the PLL BYPASS recommendation in the Blackfin Processor 1443 manuals. There is a theoretical risk that during VDDINT transitions 1444 the PLL may unlock. 1445 1446endmenu 1447 1448source "net/Kconfig" 1449 1450source "drivers/Kconfig" 1451 1452source "drivers/firmware/Kconfig" 1453 1454source "fs/Kconfig" 1455 1456source "arch/blackfin/Kconfig.debug" 1457 1458source "security/Kconfig" 1459 1460source "crypto/Kconfig" 1461 1462source "lib/Kconfig" 1463