1config PPC_CELL 2 bool 3 default n 4 5config PPC_CELL_COMMON 6 bool 7 select PPC_CELL 8 select PPC_DCR_MMIO 9 select PPC_INDIRECT_PIO 10 select PPC_INDIRECT_MMIO 11 select PPC_NATIVE 12 select PPC_RTAS 13 select IRQ_EDGE_EOI_HANDLER 14 15config PPC_CELL_NATIVE 16 bool 17 select PPC_CELL_COMMON 18 select MPIC 19 select PPC_IO_WORKAROUNDS 20 select IBM_EMAC_EMAC4 21 select IBM_EMAC_RGMII 22 select IBM_EMAC_ZMII #test only 23 select IBM_EMAC_TAH #test only 24 default n 25 26config PPC_IBM_CELL_BLADE 27 bool "IBM Cell Blade" 28 depends on PPC64 && PPC_BOOK3S && CPU_BIG_ENDIAN 29 select PPC_CELL_NATIVE 30 select PPC_OF_PLATFORM_PCI 31 select PCI 32 select MMIO_NVRAM 33 select PPC_UDBG_16550 34 select UDBG_RTAS_CONSOLE 35 36config PPC_CELL_QPACE 37 bool "IBM Cell - QPACE" 38 depends on PPC64 && PPC_BOOK3S && CPU_BIG_ENDIAN 39 select PPC_CELL_COMMON 40 41config AXON_MSI 42 bool 43 depends on PPC_IBM_CELL_BLADE && PCI_MSI 44 default y 45 46menu "Cell Broadband Engine options" 47 depends on PPC_CELL 48 49config SPU_FS 50 tristate "SPU file system" 51 default m 52 depends on PPC_CELL 53 depends on COREDUMP 54 select SPU_BASE 55 select MEMORY_HOTPLUG 56 help 57 The SPU file system is used to access Synergistic Processing 58 Units on machines implementing the Broadband Processor 59 Architecture. 60 61config SPU_BASE 62 bool 63 default n 64 select PPC_COPRO_BASE 65 66config CBE_RAS 67 bool "RAS features for bare metal Cell BE" 68 depends on PPC_CELL_NATIVE 69 default y 70 71config PPC_IBM_CELL_RESETBUTTON 72 bool "IBM Cell Blade Pinhole reset button" 73 depends on CBE_RAS && PPC_IBM_CELL_BLADE 74 default y 75 help 76 Support Pinhole Resetbutton on IBM Cell blades. 77 This adds a method to trigger system reset via front panel pinhole button. 78 79config PPC_IBM_CELL_POWERBUTTON 80 tristate "IBM Cell Blade power button" 81 depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV 82 default y 83 help 84 Support Powerbutton on IBM Cell blades. 85 This will enable the powerbutton as an input device. 86 87config CBE_THERM 88 tristate "CBE thermal support" 89 default m 90 depends on CBE_RAS && SPU_BASE 91 92config PPC_PMI 93 tristate 94 default y 95 depends on CPU_FREQ_CBE_PMI || PPC_IBM_CELL_POWERBUTTON 96 help 97 PMI (Platform Management Interrupt) is a way to 98 communicate with the BMC (Baseboard Management Controller). 99 It is used in some IBM Cell blades. 100 101config CBE_CPUFREQ_SPU_GOVERNOR 102 tristate "CBE frequency scaling based on SPU usage" 103 depends on SPU_FS && CPU_FREQ 104 default m 105 help 106 This governor checks for spu usage to adjust the cpu frequency. 107 If no spu is running on a given cpu, that cpu will be throttled to 108 the minimal possible frequency. 109 110endmenu 111 112config OPROFILE_CELL 113 def_bool y 114 depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y) && SPU_BASE 115 116