1config ARM 2 bool 3 default y 4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 5 select ARCH_HAS_ELF_RANDOMIZE 6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 7 select ARCH_HAVE_CUSTOM_GPIO_H 8 select ARCH_HAS_GCOV_PROFILE_ALL 9 select ARCH_MIGHT_HAVE_PC_PARPORT 10 select ARCH_SUPPORTS_ATOMIC_RMW 11 select ARCH_USE_BUILTIN_BSWAP 12 select ARCH_USE_CMPXCHG_LOCKREF 13 select ARCH_WANT_IPC_PARSE_VERSION 14 select BUILDTIME_EXTABLE_SORT if MMU 15 select CLONE_BACKWARDS 16 select CPU_PM if (SUSPEND || CPU_IDLE) 17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 18 select EDAC_SUPPORT 19 select EDAC_ATOMIC_SCRUB 20 select GENERIC_ALLOCATOR 21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 23 select GENERIC_IDLE_POLL_SETUP 24 select GENERIC_IRQ_PROBE 25 select GENERIC_IRQ_SHOW 26 select GENERIC_IRQ_SHOW_LEVEL 27 select GENERIC_PCI_IOMAP 28 select GENERIC_SCHED_CLOCK 29 select GENERIC_SMP_IDLE_THREAD 30 select GENERIC_STRNCPY_FROM_USER 31 select GENERIC_STRNLEN_USER 32 select HANDLE_DOMAIN_IRQ 33 select HARDIRQS_SW_RESEND 34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 36 select HAVE_ARCH_HARDENED_USERCOPY 37 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 38 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 39 select HAVE_ARCH_MMAP_RND_BITS if MMU 40 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 41 select HAVE_ARCH_TRACEHOOK 42 select HAVE_ARM_SMCCC if CPU_V7 43 select HAVE_BPF_JIT 44 select HAVE_CC_STACKPROTECTOR 45 select HAVE_CONTEXT_TRACKING 46 select HAVE_C_RECORDMCOUNT 47 select HAVE_DEBUG_KMEMLEAK 48 select HAVE_DMA_API_DEBUG 49 select HAVE_DMA_ATTRS 50 select HAVE_DMA_CONTIGUOUS if MMU 51 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 52 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 53 select HAVE_EXIT_THREAD 54 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 55 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 56 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 57 select HAVE_FUTEX_CMPXCHG if FUTEX 58 select HAVE_GENERIC_DMA_COHERENT 59 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 60 select HAVE_IDE if PCI || ISA || PCMCIA 61 select HAVE_IRQ_TIME_ACCOUNTING 62 select HAVE_KERNEL_GZIP 63 select HAVE_KERNEL_LZ4 64 select HAVE_KERNEL_LZMA 65 select HAVE_KERNEL_LZO 66 select HAVE_KERNEL_XZ 67 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 68 select HAVE_KRETPROBES if (HAVE_KPROBES) 69 select HAVE_MEMBLOCK 70 select HAVE_MOD_ARCH_SPECIFIC 71 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 72 select HAVE_OPTPROBES if !THUMB2_KERNEL 73 select HAVE_PERF_EVENTS 74 select HAVE_PERF_REGS 75 select HAVE_PERF_USER_STACK_DUMP 76 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) 77 select HAVE_REGS_AND_STACK_ACCESS_API 78 select HAVE_SYSCALL_TRACEPOINTS 79 select HAVE_UID16 80 select HAVE_VIRT_CPU_ACCOUNTING_GEN 81 select IRQ_FORCED_THREADING 82 select MODULES_USE_ELF_REL 83 select NO_BOOTMEM 84 select OF_EARLY_FLATTREE if OF 85 select OF_RESERVED_MEM if OF 86 select OLD_SIGACTION 87 select OLD_SIGSUSPEND3 88 select PERF_USE_VMALLOC 89 select RTC_LIB 90 select SYS_SUPPORTS_APM_EMULATION 91 # Above selects are sorted alphabetically; please add new ones 92 # according to that. Thanks. 93 help 94 The ARM series is a line of low-power-consumption RISC chip designs 95 licensed by ARM Ltd and targeted at embedded applications and 96 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 97 manufactured, but legacy ARM-based PC hardware remains popular in 98 Europe. There is an ARM Linux project with a web page at 99 <http://www.arm.linux.org.uk/>. 100 101config ARM_HAS_SG_CHAIN 102 select ARCH_HAS_SG_CHAIN 103 bool 104 105config NEED_SG_DMA_LENGTH 106 bool 107 108config ARM_DMA_USE_IOMMU 109 bool 110 select ARM_HAS_SG_CHAIN 111 select NEED_SG_DMA_LENGTH 112 113if ARM_DMA_USE_IOMMU 114 115config ARM_DMA_IOMMU_ALIGNMENT 116 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 117 range 4 9 118 default 8 119 help 120 DMA mapping framework by default aligns all buffers to the smallest 121 PAGE_SIZE order which is greater than or equal to the requested buffer 122 size. This works well for buffers up to a few hundreds kilobytes, but 123 for larger buffers it just a waste of address space. Drivers which has 124 relatively small addressing window (like 64Mib) might run out of 125 virtual space with just a few allocations. 126 127 With this parameter you can specify the maximum PAGE_SIZE order for 128 DMA IOMMU buffers. Larger buffers will be aligned only to this 129 specified order. The order is expressed as a power of two multiplied 130 by the PAGE_SIZE. 131 132endif 133 134config MIGHT_HAVE_PCI 135 bool 136 137config SYS_SUPPORTS_APM_EMULATION 138 bool 139 140config HAVE_TCM 141 bool 142 select GENERIC_ALLOCATOR 143 144config HAVE_PROC_CPU 145 bool 146 147config NO_IOPORT_MAP 148 bool 149 150config EISA 151 bool 152 ---help--- 153 The Extended Industry Standard Architecture (EISA) bus was 154 developed as an open alternative to the IBM MicroChannel bus. 155 156 The EISA bus provided some of the features of the IBM MicroChannel 157 bus while maintaining backward compatibility with cards made for 158 the older ISA bus. The EISA bus saw limited use between 1988 and 159 1995 when it was made obsolete by the PCI bus. 160 161 Say Y here if you are building a kernel for an EISA-based machine. 162 163 Otherwise, say N. 164 165config SBUS 166 bool 167 168config STACKTRACE_SUPPORT 169 bool 170 default y 171 172config HAVE_LATENCYTOP_SUPPORT 173 bool 174 depends on !SMP 175 default y 176 177config LOCKDEP_SUPPORT 178 bool 179 default y 180 181config TRACE_IRQFLAGS_SUPPORT 182 bool 183 default !CPU_V7M 184 185config RWSEM_XCHGADD_ALGORITHM 186 bool 187 default y 188 189config ARCH_HAS_ILOG2_U32 190 bool 191 192config ARCH_HAS_ILOG2_U64 193 bool 194 195config ARCH_HAS_BANDGAP 196 bool 197 198config FIX_EARLYCON_MEM 199 def_bool y if MMU 200 201config GENERIC_HWEIGHT 202 bool 203 default y 204 205config GENERIC_CALIBRATE_DELAY 206 bool 207 default y 208 209config ARCH_MAY_HAVE_PC_FDC 210 bool 211 212config ZONE_DMA 213 bool 214 215config NEED_DMA_MAP_STATE 216 def_bool y 217 218config ARCH_SUPPORTS_UPROBES 219 def_bool y 220 221config ARCH_HAS_DMA_SET_COHERENT_MASK 222 bool 223 224config GENERIC_ISA_DMA 225 bool 226 227config FIQ 228 bool 229 230config NEED_RET_TO_USER 231 bool 232 233config ARCH_MTD_XIP 234 bool 235 236config VECTORS_BASE 237 hex 238 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 239 default DRAM_BASE if REMAP_VECTORS_TO_RAM 240 default 0x00000000 241 help 242 The base address of exception vectors. This must be two pages 243 in size. 244 245config ARM_PATCH_PHYS_VIRT 246 bool "Patch physical to virtual translations at runtime" if EMBEDDED 247 default y 248 depends on !XIP_KERNEL && MMU 249 depends on !ARCH_REALVIEW || !SPARSEMEM 250 help 251 Patch phys-to-virt and virt-to-phys translation functions at 252 boot and module load time according to the position of the 253 kernel in system memory. 254 255 This can only be used with non-XIP MMU kernels where the base 256 of physical memory is at a 16MB boundary. 257 258 Only disable this option if you know that you do not require 259 this feature (eg, building a kernel for a single machine) and 260 you need to shrink the kernel to the minimal size. 261 262config NEED_MACH_IO_H 263 bool 264 help 265 Select this when mach/io.h is required to provide special 266 definitions for this platform. The need for mach/io.h should 267 be avoided when possible. 268 269config NEED_MACH_MEMORY_H 270 bool 271 help 272 Select this when mach/memory.h is required to provide special 273 definitions for this platform. The need for mach/memory.h should 274 be avoided when possible. 275 276config PHYS_OFFSET 277 hex "Physical address of main memory" if MMU 278 depends on !ARM_PATCH_PHYS_VIRT 279 default DRAM_BASE if !MMU 280 default 0x00000000 if ARCH_EBSA110 || \ 281 ARCH_FOOTBRIDGE || \ 282 ARCH_INTEGRATOR || \ 283 ARCH_IOP13XX || \ 284 ARCH_KS8695 || \ 285 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET) 286 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 287 default 0x20000000 if ARCH_S5PV210 288 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET 289 default 0xc0000000 if ARCH_SA1100 290 help 291 Please provide the physical address corresponding to the 292 location of main memory in your system. 293 294config GENERIC_BUG 295 def_bool y 296 depends on BUG 297 298config PGTABLE_LEVELS 299 int 300 default 3 if ARM_LPAE 301 default 2 302 303source "init/Kconfig" 304 305source "kernel/Kconfig.freezer" 306 307menu "System Type" 308 309config MMU 310 bool "MMU-based Paged Memory Management Support" 311 default y 312 help 313 Select if you want MMU-based virtualised addressing space 314 support by paged memory management. If unsure, say 'Y'. 315 316config ARCH_MMAP_RND_BITS_MIN 317 default 8 318 319config ARCH_MMAP_RND_BITS_MAX 320 default 14 if PAGE_OFFSET=0x40000000 321 default 15 if PAGE_OFFSET=0x80000000 322 default 16 323 324# 325# The "ARM system type" choice list is ordered alphabetically by option 326# text. Please add new entries in the option alphabetic order. 327# 328choice 329 prompt "ARM system type" 330 default ARCH_VERSATILE if !MMU 331 default ARCH_MULTIPLATFORM if MMU 332 333config ARCH_MULTIPLATFORM 334 bool "Allow multiple platforms to be selected" 335 depends on MMU 336 select ARCH_WANT_OPTIONAL_GPIOLIB 337 select ARM_HAS_SG_CHAIN 338 select ARM_PATCH_PHYS_VIRT 339 select AUTO_ZRELADDR 340 select CLKSRC_OF 341 select COMMON_CLK 342 select GENERIC_CLOCKEVENTS 343 select MIGHT_HAVE_PCI 344 select MULTI_IRQ_HANDLER 345 select SPARSE_IRQ 346 select USE_OF 347 348config ARM_SINGLE_ARMV7M 349 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 350 depends on !MMU 351 select ARCH_WANT_OPTIONAL_GPIOLIB 352 select ARM_NVIC 353 select AUTO_ZRELADDR 354 select CLKSRC_OF 355 select COMMON_CLK 356 select CPU_V7M 357 select GENERIC_CLOCKEVENTS 358 select NO_IOPORT_MAP 359 select SPARSE_IRQ 360 select USE_OF 361 362config ARCH_REALVIEW 363 bool "ARM Ltd. RealView family" 364 select ARCH_WANT_OPTIONAL_GPIOLIB 365 select ARM_AMBA 366 select ARM_TIMER_SP804 367 select COMMON_CLK 368 select COMMON_CLK_VERSATILE 369 select GENERIC_CLOCKEVENTS 370 select GPIO_PL061 if GPIOLIB 371 select ICST 372 select NEED_MACH_MEMORY_H 373 select PLAT_VERSATILE 374 select PLAT_VERSATILE_SCHED_CLOCK 375 help 376 This enables support for ARM Ltd RealView boards. 377 378config ARCH_VERSATILE 379 bool "ARM Ltd. Versatile family" 380 select ARCH_WANT_OPTIONAL_GPIOLIB 381 select ARM_AMBA 382 select ARM_TIMER_SP804 383 select ARM_VIC 384 select CLKDEV_LOOKUP 385 select GENERIC_CLOCKEVENTS 386 select HAVE_MACH_CLKDEV 387 select ICST 388 select PLAT_VERSATILE 389 select PLAT_VERSATILE_CLOCK 390 select PLAT_VERSATILE_SCHED_CLOCK 391 select VERSATILE_FPGA_IRQ 392 help 393 This enables support for ARM Ltd Versatile board. 394 395config ARCH_CLPS711X 396 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 397 select ARCH_REQUIRE_GPIOLIB 398 select AUTO_ZRELADDR 399 select CLKSRC_MMIO 400 select COMMON_CLK 401 select CPU_ARM720T 402 select GENERIC_CLOCKEVENTS 403 select MFD_SYSCON 404 select SOC_BUS 405 help 406 Support for Cirrus Logic 711x/721x/731x based boards. 407 408config ARCH_GEMINI 409 bool "Cortina Systems Gemini" 410 select ARCH_REQUIRE_GPIOLIB 411 select CLKSRC_MMIO 412 select CPU_FA526 413 select GENERIC_CLOCKEVENTS 414 help 415 Support for the Cortina Systems Gemini family SoCs 416 417config ARCH_EBSA110 418 bool "EBSA-110" 419 select ARCH_USES_GETTIMEOFFSET 420 select CPU_SA110 421 select ISA 422 select NEED_MACH_IO_H 423 select NEED_MACH_MEMORY_H 424 select NO_IOPORT_MAP 425 help 426 This is an evaluation board for the StrongARM processor available 427 from Digital. It has limited hardware on-board, including an 428 Ethernet interface, two PCMCIA sockets, two serial ports and a 429 parallel port. 430 431config ARCH_EP93XX 432 bool "EP93xx-based" 433 select ARCH_HAS_HOLES_MEMORYMODEL 434 select ARCH_REQUIRE_GPIOLIB 435 select ARM_AMBA 436 select ARM_PATCH_PHYS_VIRT 437 select ARM_VIC 438 select AUTO_ZRELADDR 439 select CLKDEV_LOOKUP 440 select CLKSRC_MMIO 441 select CPU_ARM920T 442 select GENERIC_CLOCKEVENTS 443 help 444 This enables support for the Cirrus EP93xx series of CPUs. 445 446config ARCH_FOOTBRIDGE 447 bool "FootBridge" 448 select CPU_SA110 449 select FOOTBRIDGE 450 select GENERIC_CLOCKEVENTS 451 select HAVE_IDE 452 select NEED_MACH_IO_H if !MMU 453 select NEED_MACH_MEMORY_H 454 help 455 Support for systems based on the DC21285 companion chip 456 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 457 458config ARCH_NETX 459 bool "Hilscher NetX based" 460 select ARM_VIC 461 select CLKSRC_MMIO 462 select CPU_ARM926T 463 select GENERIC_CLOCKEVENTS 464 help 465 This enables support for systems based on the Hilscher NetX Soc 466 467config ARCH_IOP13XX 468 bool "IOP13xx-based" 469 depends on MMU 470 select CPU_XSC3 471 select NEED_MACH_MEMORY_H 472 select NEED_RET_TO_USER 473 select PCI 474 select PLAT_IOP 475 select VMSPLIT_1G 476 select SPARSE_IRQ 477 help 478 Support for Intel's IOP13XX (XScale) family of processors. 479 480config ARCH_IOP32X 481 bool "IOP32x-based" 482 depends on MMU 483 select ARCH_REQUIRE_GPIOLIB 484 select CPU_XSCALE 485 select GPIO_IOP 486 select NEED_RET_TO_USER 487 select PCI 488 select PLAT_IOP 489 help 490 Support for Intel's 80219 and IOP32X (XScale) family of 491 processors. 492 493config ARCH_IOP33X 494 bool "IOP33x-based" 495 depends on MMU 496 select ARCH_REQUIRE_GPIOLIB 497 select CPU_XSCALE 498 select GPIO_IOP 499 select NEED_RET_TO_USER 500 select PCI 501 select PLAT_IOP 502 help 503 Support for Intel's IOP33X (XScale) family of processors. 504 505config ARCH_IXP4XX 506 bool "IXP4xx-based" 507 depends on MMU 508 select ARCH_HAS_DMA_SET_COHERENT_MASK 509 select ARCH_REQUIRE_GPIOLIB 510 select ARCH_SUPPORTS_BIG_ENDIAN 511 select CLKSRC_MMIO 512 select CPU_XSCALE 513 select DMABOUNCE if PCI 514 select GENERIC_CLOCKEVENTS 515 select MIGHT_HAVE_PCI 516 select NEED_MACH_IO_H 517 select USB_EHCI_BIG_ENDIAN_DESC 518 select USB_EHCI_BIG_ENDIAN_MMIO 519 help 520 Support for Intel's IXP4XX (XScale) family of processors. 521 522config ARCH_DOVE 523 bool "Marvell Dove" 524 select ARCH_REQUIRE_GPIOLIB 525 select CPU_PJ4 526 select GENERIC_CLOCKEVENTS 527 select MIGHT_HAVE_PCI 528 select MVEBU_MBUS 529 select PINCTRL 530 select PINCTRL_DOVE 531 select PLAT_ORION_LEGACY 532 help 533 Support for the Marvell Dove SoC 88AP510 534 535config ARCH_MV78XX0 536 bool "Marvell MV78xx0" 537 select ARCH_REQUIRE_GPIOLIB 538 select CPU_FEROCEON 539 select GENERIC_CLOCKEVENTS 540 select MVEBU_MBUS 541 select PCI 542 select PLAT_ORION_LEGACY 543 help 544 Support for the following Marvell MV78xx0 series SoCs: 545 MV781x0, MV782x0. 546 547config ARCH_ORION5X 548 bool "Marvell Orion" 549 depends on MMU 550 select ARCH_REQUIRE_GPIOLIB 551 select CPU_FEROCEON 552 select GENERIC_CLOCKEVENTS 553 select MVEBU_MBUS 554 select PCI 555 select PLAT_ORION_LEGACY 556 select MULTI_IRQ_HANDLER 557 help 558 Support for the following Marvell Orion 5x series SoCs: 559 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 560 Orion-2 (5281), Orion-1-90 (6183). 561 562config ARCH_MMP 563 bool "Marvell PXA168/910/MMP2" 564 depends on MMU 565 select ARCH_REQUIRE_GPIOLIB 566 select CLKDEV_LOOKUP 567 select GENERIC_ALLOCATOR 568 select GENERIC_CLOCKEVENTS 569 select GPIO_PXA 570 select IRQ_DOMAIN 571 select MULTI_IRQ_HANDLER 572 select PINCTRL 573 select PLAT_PXA 574 select SPARSE_IRQ 575 help 576 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 577 578config ARCH_KS8695 579 bool "Micrel/Kendin KS8695" 580 select ARCH_REQUIRE_GPIOLIB 581 select CLKSRC_MMIO 582 select CPU_ARM922T 583 select GENERIC_CLOCKEVENTS 584 select NEED_MACH_MEMORY_H 585 help 586 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 587 System-on-Chip devices. 588 589config ARCH_W90X900 590 bool "Nuvoton W90X900 CPU" 591 select ARCH_REQUIRE_GPIOLIB 592 select CLKDEV_LOOKUP 593 select CLKSRC_MMIO 594 select CPU_ARM926T 595 select GENERIC_CLOCKEVENTS 596 help 597 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 598 At present, the w90x900 has been renamed nuc900, regarding 599 the ARM series product line, you can login the following 600 link address to know more. 601 602 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 603 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 604 605config ARCH_LPC32XX 606 bool "NXP LPC32XX" 607 select ARCH_REQUIRE_GPIOLIB 608 select ARM_AMBA 609 select CLKDEV_LOOKUP 610 select CLKSRC_MMIO 611 select CPU_ARM926T 612 select GENERIC_CLOCKEVENTS 613 select HAVE_IDE 614 select USE_OF 615 help 616 Support for the NXP LPC32XX family of processors 617 618config ARCH_PXA 619 bool "PXA2xx/PXA3xx-based" 620 depends on MMU 621 select ARCH_MTD_XIP 622 select ARCH_REQUIRE_GPIOLIB 623 select ARM_CPU_SUSPEND if PM 624 select AUTO_ZRELADDR 625 select COMMON_CLK 626 select CLKDEV_LOOKUP 627 select CLKSRC_MMIO 628 select CLKSRC_OF 629 select GENERIC_CLOCKEVENTS 630 select GPIO_PXA 631 select HAVE_IDE 632 select IRQ_DOMAIN 633 select MULTI_IRQ_HANDLER 634 select PLAT_PXA 635 select SPARSE_IRQ 636 help 637 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 638 639config ARCH_RPC 640 bool "RiscPC" 641 depends on MMU 642 select ARCH_ACORN 643 select ARCH_MAY_HAVE_PC_FDC 644 select ARCH_SPARSEMEM_ENABLE 645 select ARCH_USES_GETTIMEOFFSET 646 select CPU_SA110 647 select FIQ 648 select HAVE_IDE 649 select HAVE_PATA_PLATFORM 650 select ISA_DMA_API 651 select NEED_MACH_IO_H 652 select NEED_MACH_MEMORY_H 653 select NO_IOPORT_MAP 654 select VIRT_TO_BUS 655 help 656 On the Acorn Risc-PC, Linux can support the internal IDE disk and 657 CD-ROM interface, serial and parallel port, and the floppy drive. 658 659config ARCH_SA1100 660 bool "SA1100-based" 661 select ARCH_MTD_XIP 662 select ARCH_REQUIRE_GPIOLIB 663 select ARCH_SPARSEMEM_ENABLE 664 select CLKDEV_LOOKUP 665 select CLKSRC_MMIO 666 select CPU_FREQ 667 select CPU_SA1100 668 select GENERIC_CLOCKEVENTS 669 select HAVE_IDE 670 select IRQ_DOMAIN 671 select ISA 672 select MULTI_IRQ_HANDLER 673 select NEED_MACH_MEMORY_H 674 select SPARSE_IRQ 675 help 676 Support for StrongARM 11x0 based boards. 677 678config ARCH_S3C24XX 679 bool "Samsung S3C24XX SoCs" 680 select ARCH_REQUIRE_GPIOLIB 681 select ATAGS 682 select CLKDEV_LOOKUP 683 select CLKSRC_SAMSUNG_PWM 684 select GENERIC_CLOCKEVENTS 685 select GPIO_SAMSUNG 686 select HAVE_S3C2410_I2C if I2C 687 select HAVE_S3C2410_WATCHDOG if WATCHDOG 688 select HAVE_S3C_RTC if RTC_CLASS 689 select MULTI_IRQ_HANDLER 690 select NEED_MACH_IO_H 691 select S3C2410_WATCHDOG 692 select SAMSUNG_ATAGS 693 select WATCHDOG 694 help 695 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 696 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 697 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 698 Samsung SMDK2410 development board (and derivatives). 699 700config ARCH_S3C64XX 701 bool "Samsung S3C64XX" 702 select ARCH_REQUIRE_GPIOLIB 703 select ARM_AMBA 704 select ARM_VIC 705 select ATAGS 706 select CLKDEV_LOOKUP 707 select CLKSRC_SAMSUNG_PWM 708 select COMMON_CLK_SAMSUNG 709 select CPU_V6K 710 select GENERIC_CLOCKEVENTS 711 select GPIO_SAMSUNG 712 select HAVE_S3C2410_I2C if I2C 713 select HAVE_S3C2410_WATCHDOG if WATCHDOG 714 select HAVE_TCM 715 select NO_IOPORT_MAP 716 select PLAT_SAMSUNG 717 select PM_GENERIC_DOMAINS if PM 718 select S3C_DEV_NAND 719 select S3C_GPIO_TRACK 720 select SAMSUNG_ATAGS 721 select SAMSUNG_WAKEMASK 722 select SAMSUNG_WDT_RESET 723 help 724 Samsung S3C64XX series based systems 725 726config ARCH_DAVINCI 727 bool "TI DaVinci" 728 select ARCH_HAS_HOLES_MEMORYMODEL 729 select ARCH_REQUIRE_GPIOLIB 730 select CLKDEV_LOOKUP 731 select GENERIC_ALLOCATOR 732 select GENERIC_CLOCKEVENTS 733 select GENERIC_IRQ_CHIP 734 select HAVE_IDE 735 select USE_OF 736 select ZONE_DMA 737 help 738 Support for TI's DaVinci platform. 739 740config ARCH_OMAP1 741 bool "TI OMAP1" 742 depends on MMU 743 select ARCH_HAS_HOLES_MEMORYMODEL 744 select ARCH_OMAP 745 select ARCH_REQUIRE_GPIOLIB 746 select CLKDEV_LOOKUP 747 select CLKSRC_MMIO 748 select GENERIC_CLOCKEVENTS 749 select GENERIC_IRQ_CHIP 750 select HAVE_IDE 751 select IRQ_DOMAIN 752 select MULTI_IRQ_HANDLER 753 select NEED_MACH_IO_H if PCCARD 754 select NEED_MACH_MEMORY_H 755 select SPARSE_IRQ 756 help 757 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 758 759endchoice 760 761menu "Multiple platform selection" 762 depends on ARCH_MULTIPLATFORM 763 764comment "CPU Core family selection" 765 766config ARCH_MULTI_V4 767 bool "ARMv4 based platforms (FA526)" 768 depends on !ARCH_MULTI_V6_V7 769 select ARCH_MULTI_V4_V5 770 select CPU_FA526 771 772config ARCH_MULTI_V4T 773 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 774 depends on !ARCH_MULTI_V6_V7 775 select ARCH_MULTI_V4_V5 776 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 777 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 778 CPU_ARM925T || CPU_ARM940T) 779 780config ARCH_MULTI_V5 781 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 782 depends on !ARCH_MULTI_V6_V7 783 select ARCH_MULTI_V4_V5 784 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 785 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 786 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 787 788config ARCH_MULTI_V4_V5 789 bool 790 791config ARCH_MULTI_V6 792 bool "ARMv6 based platforms (ARM11)" 793 select ARCH_MULTI_V6_V7 794 select CPU_V6K 795 796config ARCH_MULTI_V7 797 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 798 default y 799 select ARCH_MULTI_V6_V7 800 select CPU_V7 801 select HAVE_SMP 802 803config ARCH_MULTI_V6_V7 804 bool 805 select MIGHT_HAVE_CACHE_L2X0 806 807config ARCH_MULTI_CPU_AUTO 808 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 809 select ARCH_MULTI_V5 810 811endmenu 812 813config ARCH_VIRT 814 bool "Dummy Virtual Machine" if ARCH_MULTI_V7 815 select ARM_AMBA 816 select ARM_GIC 817 select ARM_GIC_V3 818 select ARM_PSCI 819 select HAVE_ARM_ARCH_TIMER 820 821# 822# This is sorted alphabetically by mach-* pathname. However, plat-* 823# Kconfigs may be included either alphabetically (according to the 824# plat- suffix) or along side the corresponding mach-* source. 825# 826source "arch/arm/mach-mvebu/Kconfig" 827 828source "arch/arm/mach-alpine/Kconfig" 829 830source "arch/arm/mach-asm9260/Kconfig" 831 832source "arch/arm/mach-at91/Kconfig" 833 834source "arch/arm/mach-axxia/Kconfig" 835 836source "arch/arm/mach-bcm/Kconfig" 837 838source "arch/arm/mach-berlin/Kconfig" 839 840source "arch/arm/mach-clps711x/Kconfig" 841 842source "arch/arm/mach-cns3xxx/Kconfig" 843 844source "arch/arm/mach-davinci/Kconfig" 845 846source "arch/arm/mach-digicolor/Kconfig" 847 848source "arch/arm/mach-dove/Kconfig" 849 850source "arch/arm/mach-ep93xx/Kconfig" 851 852source "arch/arm/mach-footbridge/Kconfig" 853 854source "arch/arm/mach-gemini/Kconfig" 855 856source "arch/arm/mach-highbank/Kconfig" 857 858source "arch/arm/mach-hisi/Kconfig" 859 860source "arch/arm/mach-integrator/Kconfig" 861 862source "arch/arm/mach-iop32x/Kconfig" 863 864source "arch/arm/mach-iop33x/Kconfig" 865 866source "arch/arm/mach-iop13xx/Kconfig" 867 868source "arch/arm/mach-ixp4xx/Kconfig" 869 870source "arch/arm/mach-keystone/Kconfig" 871 872source "arch/arm/mach-ks8695/Kconfig" 873 874source "arch/arm/mach-meson/Kconfig" 875 876source "arch/arm/mach-moxart/Kconfig" 877 878source "arch/arm/mach-mv78xx0/Kconfig" 879 880source "arch/arm/mach-imx/Kconfig" 881 882source "arch/arm/mach-mediatek/Kconfig" 883 884source "arch/arm/mach-mxs/Kconfig" 885 886source "arch/arm/mach-netx/Kconfig" 887 888source "arch/arm/mach-nomadik/Kconfig" 889 890source "arch/arm/mach-nspire/Kconfig" 891 892source "arch/arm/plat-omap/Kconfig" 893 894source "arch/arm/mach-omap1/Kconfig" 895 896source "arch/arm/mach-omap2/Kconfig" 897 898source "arch/arm/mach-orion5x/Kconfig" 899 900source "arch/arm/mach-picoxcell/Kconfig" 901 902source "arch/arm/mach-pxa/Kconfig" 903source "arch/arm/plat-pxa/Kconfig" 904 905source "arch/arm/mach-mmp/Kconfig" 906 907source "arch/arm/mach-qcom/Kconfig" 908 909source "arch/arm/mach-realview/Kconfig" 910 911source "arch/arm/mach-rockchip/Kconfig" 912 913source "arch/arm/mach-sa1100/Kconfig" 914 915source "arch/arm/mach-socfpga/Kconfig" 916 917source "arch/arm/mach-spear/Kconfig" 918 919source "arch/arm/mach-sti/Kconfig" 920 921source "arch/arm/mach-s3c24xx/Kconfig" 922 923source "arch/arm/mach-s3c64xx/Kconfig" 924 925source "arch/arm/mach-s5pv210/Kconfig" 926 927source "arch/arm/mach-exynos/Kconfig" 928source "arch/arm/plat-samsung/Kconfig" 929 930source "arch/arm/mach-shmobile/Kconfig" 931 932source "arch/arm/mach-sunxi/Kconfig" 933 934source "arch/arm/mach-prima2/Kconfig" 935 936source "arch/arm/mach-tegra/Kconfig" 937 938source "arch/arm/mach-u300/Kconfig" 939 940source "arch/arm/mach-uniphier/Kconfig" 941 942source "arch/arm/mach-ux500/Kconfig" 943 944source "arch/arm/mach-versatile/Kconfig" 945 946source "arch/arm/mach-vexpress/Kconfig" 947source "arch/arm/plat-versatile/Kconfig" 948 949source "arch/arm/mach-vt8500/Kconfig" 950 951source "arch/arm/mach-w90x900/Kconfig" 952 953source "arch/arm/mach-zx/Kconfig" 954 955source "arch/arm/mach-zynq/Kconfig" 956 957# ARMv7-M architecture 958config ARCH_EFM32 959 bool "Energy Micro efm32" 960 depends on ARM_SINGLE_ARMV7M 961 select ARCH_REQUIRE_GPIOLIB 962 help 963 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 964 processors. 965 966config ARCH_LPC18XX 967 bool "NXP LPC18xx/LPC43xx" 968 depends on ARM_SINGLE_ARMV7M 969 select ARCH_HAS_RESET_CONTROLLER 970 select ARM_AMBA 971 select CLKSRC_LPC32XX 972 select PINCTRL 973 help 974 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 975 high performance microcontrollers. 976 977config ARCH_STM32 978 bool "STMicrolectronics STM32" 979 depends on ARM_SINGLE_ARMV7M 980 select ARCH_HAS_RESET_CONTROLLER 981 select ARMV7M_SYSTICK 982 select CLKSRC_STM32 983 select RESET_CONTROLLER 984 help 985 Support for STMicroelectronics STM32 processors. 986 987# Definitions to make life easier 988config ARCH_ACORN 989 bool 990 991config PLAT_IOP 992 bool 993 select GENERIC_CLOCKEVENTS 994 995config PLAT_ORION 996 bool 997 select CLKSRC_MMIO 998 select COMMON_CLK 999 select GENERIC_IRQ_CHIP 1000 select IRQ_DOMAIN 1001 1002config PLAT_ORION_LEGACY 1003 bool 1004 select PLAT_ORION 1005 1006config PLAT_PXA 1007 bool 1008 1009config PLAT_VERSATILE 1010 bool 1011 1012source "arch/arm/firmware/Kconfig" 1013 1014source arch/arm/mm/Kconfig 1015 1016config IWMMXT 1017 bool "Enable iWMMXt support" 1018 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 1019 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 1020 help 1021 Enable support for iWMMXt context switching at run time if 1022 running on a CPU that supports it. 1023 1024config MULTI_IRQ_HANDLER 1025 bool 1026 help 1027 Allow each machine to specify it's own IRQ handler at run time. 1028 1029if !MMU 1030source "arch/arm/Kconfig-nommu" 1031endif 1032 1033config PJ4B_ERRATA_4742 1034 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 1035 depends on CPU_PJ4B && MACH_ARMADA_370 1036 default y 1037 help 1038 When coming out of either a Wait for Interrupt (WFI) or a Wait for 1039 Event (WFE) IDLE states, a specific timing sensitivity exists between 1040 the retiring WFI/WFE instructions and the newly issued subsequent 1041 instructions. This sensitivity can result in a CPU hang scenario. 1042 Workaround: 1043 The software must insert either a Data Synchronization Barrier (DSB) 1044 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 1045 instruction 1046 1047config ARM_ERRATA_326103 1048 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 1049 depends on CPU_V6 1050 help 1051 Executing a SWP instruction to read-only memory does not set bit 11 1052 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 1053 treat the access as a read, preventing a COW from occurring and 1054 causing the faulting task to livelock. 1055 1056config ARM_ERRATA_411920 1057 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1058 depends on CPU_V6 || CPU_V6K 1059 help 1060 Invalidation of the Instruction Cache operation can 1061 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1062 It does not affect the MPCore. This option enables the ARM Ltd. 1063 recommended workaround. 1064 1065config ARM_ERRATA_430973 1066 bool "ARM errata: Stale prediction on replaced interworking branch" 1067 depends on CPU_V7 1068 help 1069 This option enables the workaround for the 430973 Cortex-A8 1070 r1p* erratum. If a code sequence containing an ARM/Thumb 1071 interworking branch is replaced with another code sequence at the 1072 same virtual address, whether due to self-modifying code or virtual 1073 to physical address re-mapping, Cortex-A8 does not recover from the 1074 stale interworking branch prediction. This results in Cortex-A8 1075 executing the new code sequence in the incorrect ARM or Thumb state. 1076 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1077 and also flushes the branch target cache at every context switch. 1078 Note that setting specific bits in the ACTLR register may not be 1079 available in non-secure mode. 1080 1081config ARM_ERRATA_458693 1082 bool "ARM errata: Processor deadlock when a false hazard is created" 1083 depends on CPU_V7 1084 depends on !ARCH_MULTIPLATFORM 1085 help 1086 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1087 erratum. For very specific sequences of memory operations, it is 1088 possible for a hazard condition intended for a cache line to instead 1089 be incorrectly associated with a different cache line. This false 1090 hazard might then cause a processor deadlock. The workaround enables 1091 the L1 caching of the NEON accesses and disables the PLD instruction 1092 in the ACTLR register. Note that setting specific bits in the ACTLR 1093 register may not be available in non-secure mode. 1094 1095config ARM_ERRATA_460075 1096 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1097 depends on CPU_V7 1098 depends on !ARCH_MULTIPLATFORM 1099 help 1100 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1101 erratum. Any asynchronous access to the L2 cache may encounter a 1102 situation in which recent store transactions to the L2 cache are lost 1103 and overwritten with stale memory contents from external memory. The 1104 workaround disables the write-allocate mode for the L2 cache via the 1105 ACTLR register. Note that setting specific bits in the ACTLR register 1106 may not be available in non-secure mode. 1107 1108config ARM_ERRATA_742230 1109 bool "ARM errata: DMB operation may be faulty" 1110 depends on CPU_V7 && SMP 1111 depends on !ARCH_MULTIPLATFORM 1112 help 1113 This option enables the workaround for the 742230 Cortex-A9 1114 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1115 between two write operations may not ensure the correct visibility 1116 ordering of the two writes. This workaround sets a specific bit in 1117 the diagnostic register of the Cortex-A9 which causes the DMB 1118 instruction to behave as a DSB, ensuring the correct behaviour of 1119 the two writes. 1120 1121config ARM_ERRATA_742231 1122 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1123 depends on CPU_V7 && SMP 1124 depends on !ARCH_MULTIPLATFORM 1125 help 1126 This option enables the workaround for the 742231 Cortex-A9 1127 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1128 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1129 accessing some data located in the same cache line, may get corrupted 1130 data due to bad handling of the address hazard when the line gets 1131 replaced from one of the CPUs at the same time as another CPU is 1132 accessing it. This workaround sets specific bits in the diagnostic 1133 register of the Cortex-A9 which reduces the linefill issuing 1134 capabilities of the processor. 1135 1136config ARM_ERRATA_643719 1137 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1138 depends on CPU_V7 && SMP 1139 default y 1140 help 1141 This option enables the workaround for the 643719 Cortex-A9 (prior to 1142 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1143 register returns zero when it should return one. The workaround 1144 corrects this value, ensuring cache maintenance operations which use 1145 it behave as intended and avoiding data corruption. 1146 1147config ARM_ERRATA_720789 1148 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1149 depends on CPU_V7 1150 help 1151 This option enables the workaround for the 720789 Cortex-A9 (prior to 1152 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1153 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1154 As a consequence of this erratum, some TLB entries which should be 1155 invalidated are not, resulting in an incoherency in the system page 1156 tables. The workaround changes the TLB flushing routines to invalidate 1157 entries regardless of the ASID. 1158 1159config ARM_ERRATA_743622 1160 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1161 depends on CPU_V7 1162 depends on !ARCH_MULTIPLATFORM 1163 help 1164 This option enables the workaround for the 743622 Cortex-A9 1165 (r2p*) erratum. Under very rare conditions, a faulty 1166 optimisation in the Cortex-A9 Store Buffer may lead to data 1167 corruption. This workaround sets a specific bit in the diagnostic 1168 register of the Cortex-A9 which disables the Store Buffer 1169 optimisation, preventing the defect from occurring. This has no 1170 visible impact on the overall performance or power consumption of the 1171 processor. 1172 1173config ARM_ERRATA_751472 1174 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1175 depends on CPU_V7 1176 depends on !ARCH_MULTIPLATFORM 1177 help 1178 This option enables the workaround for the 751472 Cortex-A9 (prior 1179 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1180 completion of a following broadcasted operation if the second 1181 operation is received by a CPU before the ICIALLUIS has completed, 1182 potentially leading to corrupted entries in the cache or TLB. 1183 1184config ARM_ERRATA_754322 1185 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1186 depends on CPU_V7 1187 help 1188 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1189 r3p*) erratum. A speculative memory access may cause a page table walk 1190 which starts prior to an ASID switch but completes afterwards. This 1191 can populate the micro-TLB with a stale entry which may be hit with 1192 the new ASID. This workaround places two dsb instructions in the mm 1193 switching code so that no page table walks can cross the ASID switch. 1194 1195config ARM_ERRATA_754327 1196 bool "ARM errata: no automatic Store Buffer drain" 1197 depends on CPU_V7 && SMP 1198 help 1199 This option enables the workaround for the 754327 Cortex-A9 (prior to 1200 r2p0) erratum. The Store Buffer does not have any automatic draining 1201 mechanism and therefore a livelock may occur if an external agent 1202 continuously polls a memory location waiting to observe an update. 1203 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1204 written polling loops from denying visibility of updates to memory. 1205 1206config ARM_ERRATA_364296 1207 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1208 depends on CPU_V6 1209 help 1210 This options enables the workaround for the 364296 ARM1136 1211 r0p2 erratum (possible cache data corruption with 1212 hit-under-miss enabled). It sets the undocumented bit 31 in 1213 the auxiliary control register and the FI bit in the control 1214 register, thus disabling hit-under-miss without putting the 1215 processor into full low interrupt latency mode. ARM11MPCore 1216 is not affected. 1217 1218config ARM_ERRATA_764369 1219 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1220 depends on CPU_V7 && SMP 1221 help 1222 This option enables the workaround for erratum 764369 1223 affecting Cortex-A9 MPCore with two or more processors (all 1224 current revisions). Under certain timing circumstances, a data 1225 cache line maintenance operation by MVA targeting an Inner 1226 Shareable memory region may fail to proceed up to either the 1227 Point of Coherency or to the Point of Unification of the 1228 system. This workaround adds a DSB instruction before the 1229 relevant cache maintenance functions and sets a specific bit 1230 in the diagnostic control register of the SCU. 1231 1232config ARM_ERRATA_775420 1233 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1234 depends on CPU_V7 1235 help 1236 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1237 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1238 operation aborts with MMU exception, it might cause the processor 1239 to deadlock. This workaround puts DSB before executing ISB if 1240 an abort may occur on cache maintenance. 1241 1242config ARM_ERRATA_798181 1243 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1244 depends on CPU_V7 && SMP 1245 help 1246 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1247 adequately shooting down all use of the old entries. This 1248 option enables the Linux kernel workaround for this erratum 1249 which sends an IPI to the CPUs that are running the same ASID 1250 as the one being invalidated. 1251 1252config ARM_ERRATA_773022 1253 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1254 depends on CPU_V7 1255 help 1256 This option enables the workaround for the 773022 Cortex-A15 1257 (up to r0p4) erratum. In certain rare sequences of code, the 1258 loop buffer may deliver incorrect instructions. This 1259 workaround disables the loop buffer to avoid the erratum. 1260 1261endmenu 1262 1263source "arch/arm/common/Kconfig" 1264 1265menu "Bus support" 1266 1267config ISA 1268 bool 1269 help 1270 Find out whether you have ISA slots on your motherboard. ISA is the 1271 name of a bus system, i.e. the way the CPU talks to the other stuff 1272 inside your box. Other bus systems are PCI, EISA, MicroChannel 1273 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1274 newer boards don't support it. If you have ISA, say Y, otherwise N. 1275 1276# Select ISA DMA controller support 1277config ISA_DMA 1278 bool 1279 select ISA_DMA_API 1280 1281# Select ISA DMA interface 1282config ISA_DMA_API 1283 bool 1284 1285config PCI 1286 bool "PCI support" if MIGHT_HAVE_PCI 1287 help 1288 Find out whether you have a PCI motherboard. PCI is the name of a 1289 bus system, i.e. the way the CPU talks to the other stuff inside 1290 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1291 VESA. If you have PCI, say Y, otherwise N. 1292 1293config PCI_DOMAINS 1294 bool 1295 depends on PCI 1296 1297config PCI_DOMAINS_GENERIC 1298 def_bool PCI_DOMAINS 1299 1300config PCI_NANOENGINE 1301 bool "BSE nanoEngine PCI support" 1302 depends on SA1100_NANOENGINE 1303 help 1304 Enable PCI on the BSE nanoEngine board. 1305 1306config PCI_SYSCALL 1307 def_bool PCI 1308 1309config PCI_HOST_ITE8152 1310 bool 1311 depends on PCI && MACH_ARMCORE 1312 default y 1313 select DMABOUNCE 1314 1315source "drivers/pci/Kconfig" 1316source "drivers/pci/pcie/Kconfig" 1317 1318source "drivers/pcmcia/Kconfig" 1319 1320endmenu 1321 1322menu "Kernel Features" 1323 1324config HAVE_SMP 1325 bool 1326 help 1327 This option should be selected by machines which have an SMP- 1328 capable CPU. 1329 1330 The only effect of this option is to make the SMP-related 1331 options available to the user for configuration. 1332 1333config SMP 1334 bool "Symmetric Multi-Processing" 1335 depends on CPU_V6K || CPU_V7 1336 depends on GENERIC_CLOCKEVENTS 1337 depends on HAVE_SMP 1338 depends on MMU || ARM_MPU 1339 select IRQ_WORK 1340 help 1341 This enables support for systems with more than one CPU. If you have 1342 a system with only one CPU, say N. If you have a system with more 1343 than one CPU, say Y. 1344 1345 If you say N here, the kernel will run on uni- and multiprocessor 1346 machines, but will use only one CPU of a multiprocessor machine. If 1347 you say Y here, the kernel will run on many, but not all, 1348 uniprocessor machines. On a uniprocessor machine, the kernel 1349 will run faster if you say N here. 1350 1351 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1352 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1353 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1354 1355 If you don't know what to do here, say N. 1356 1357config SMP_ON_UP 1358 bool "Allow booting SMP kernel on uniprocessor systems" 1359 depends on SMP && !XIP_KERNEL && MMU 1360 default y 1361 help 1362 SMP kernels contain instructions which fail on non-SMP processors. 1363 Enabling this option allows the kernel to modify itself to make 1364 these instructions safe. Disabling it allows about 1K of space 1365 savings. 1366 1367 If you don't know what to do here, say Y. 1368 1369config ARM_CPU_TOPOLOGY 1370 bool "Support cpu topology definition" 1371 depends on SMP && CPU_V7 1372 default y 1373 help 1374 Support ARM cpu topology definition. The MPIDR register defines 1375 affinity between processors which is then used to describe the cpu 1376 topology of an ARM System. 1377 1378config SCHED_MC 1379 bool "Multi-core scheduler support" 1380 depends on ARM_CPU_TOPOLOGY 1381 help 1382 Multi-core scheduler support improves the CPU scheduler's decision 1383 making when dealing with multi-core CPU chips at a cost of slightly 1384 increased overhead in some places. If unsure say N here. 1385 1386config SCHED_SMT 1387 bool "SMT scheduler support" 1388 depends on ARM_CPU_TOPOLOGY 1389 help 1390 Improves the CPU scheduler's decision making when dealing with 1391 MultiThreading at a cost of slightly increased overhead in some 1392 places. If unsure say N here. 1393 1394config HAVE_ARM_SCU 1395 bool 1396 help 1397 This option enables support for the ARM system coherency unit 1398 1399config HAVE_ARM_ARCH_TIMER 1400 bool "Architected timer support" 1401 depends on CPU_V7 1402 select ARM_ARCH_TIMER 1403 select GENERIC_CLOCKEVENTS 1404 help 1405 This option enables support for the ARM architected timer 1406 1407config HAVE_ARM_TWD 1408 bool 1409 select CLKSRC_OF if OF 1410 help 1411 This options enables support for the ARM timer and watchdog unit 1412 1413config MCPM 1414 bool "Multi-Cluster Power Management" 1415 depends on CPU_V7 && SMP 1416 help 1417 This option provides the common power management infrastructure 1418 for (multi-)cluster based systems, such as big.LITTLE based 1419 systems. 1420 1421config MCPM_QUAD_CLUSTER 1422 bool 1423 depends on MCPM 1424 help 1425 To avoid wasting resources unnecessarily, MCPM only supports up 1426 to 2 clusters by default. 1427 Platforms with 3 or 4 clusters that use MCPM must select this 1428 option to allow the additional clusters to be managed. 1429 1430config BIG_LITTLE 1431 bool "big.LITTLE support (Experimental)" 1432 depends on CPU_V7 && SMP 1433 select MCPM 1434 help 1435 This option enables support selections for the big.LITTLE 1436 system architecture. 1437 1438config BL_SWITCHER 1439 bool "big.LITTLE switcher support" 1440 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1441 select CPU_PM 1442 help 1443 The big.LITTLE "switcher" provides the core functionality to 1444 transparently handle transition between a cluster of A15's 1445 and a cluster of A7's in a big.LITTLE system. 1446 1447config BL_SWITCHER_DUMMY_IF 1448 tristate "Simple big.LITTLE switcher user interface" 1449 depends on BL_SWITCHER && DEBUG_KERNEL 1450 help 1451 This is a simple and dummy char dev interface to control 1452 the big.LITTLE switcher core code. It is meant for 1453 debugging purposes only. 1454 1455choice 1456 prompt "Memory split" 1457 depends on MMU 1458 default VMSPLIT_3G 1459 help 1460 Select the desired split between kernel and user memory. 1461 1462 If you are not absolutely sure what you are doing, leave this 1463 option alone! 1464 1465 config VMSPLIT_3G 1466 bool "3G/1G user/kernel split" 1467 config VMSPLIT_3G_OPT 1468 bool "3G/1G user/kernel split (for full 1G low memory)" 1469 config VMSPLIT_2G 1470 bool "2G/2G user/kernel split" 1471 config VMSPLIT_1G 1472 bool "1G/3G user/kernel split" 1473endchoice 1474 1475config PAGE_OFFSET 1476 hex 1477 default PHYS_OFFSET if !MMU 1478 default 0x40000000 if VMSPLIT_1G 1479 default 0x80000000 if VMSPLIT_2G 1480 default 0xB0000000 if VMSPLIT_3G_OPT 1481 default 0xC0000000 1482 1483config NR_CPUS 1484 int "Maximum number of CPUs (2-32)" 1485 range 2 32 1486 depends on SMP 1487 default "4" 1488 1489config HOTPLUG_CPU 1490 bool "Support for hot-pluggable CPUs" 1491 depends on SMP 1492 select GENERIC_IRQ_MIGRATION 1493 help 1494 Say Y here to experiment with turning CPUs off and on. CPUs 1495 can be controlled through /sys/devices/system/cpu. 1496 1497config ARM_PSCI 1498 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1499 depends on HAVE_ARM_SMCCC 1500 select ARM_PSCI_FW 1501 help 1502 Say Y here if you want Linux to communicate with system firmware 1503 implementing the PSCI specification for CPU-centric power 1504 management operations described in ARM document number ARM DEN 1505 0022A ("Power State Coordination Interface System Software on 1506 ARM processors"). 1507 1508# The GPIO number here must be sorted by descending number. In case of 1509# a multiplatform kernel, we just want the highest value required by the 1510# selected platforms. 1511config ARCH_NR_GPIO 1512 int 1513 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \ 1514 ARCH_ZYNQ 1515 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1516 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1517 default 416 if ARCH_SUNXI 1518 default 392 if ARCH_U8500 1519 default 352 if ARCH_VT8500 1520 default 288 if ARCH_ROCKCHIP 1521 default 264 if MACH_H4700 1522 default 0 1523 help 1524 Maximum number of GPIOs in the system. 1525 1526 If unsure, leave the default value. 1527 1528source kernel/Kconfig.preempt 1529 1530config HZ_FIXED 1531 int 1532 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ 1533 ARCH_S5PV210 || ARCH_EXYNOS4 1534 default 128 if SOC_AT91RM9200 1535 default 0 1536 1537choice 1538 depends on HZ_FIXED = 0 1539 prompt "Timer frequency" 1540 1541config HZ_100 1542 bool "100 Hz" 1543 1544config HZ_200 1545 bool "200 Hz" 1546 1547config HZ_250 1548 bool "250 Hz" 1549 1550config HZ_300 1551 bool "300 Hz" 1552 1553config HZ_500 1554 bool "500 Hz" 1555 1556config HZ_1000 1557 bool "1000 Hz" 1558 1559endchoice 1560 1561config HZ 1562 int 1563 default HZ_FIXED if HZ_FIXED != 0 1564 default 100 if HZ_100 1565 default 200 if HZ_200 1566 default 250 if HZ_250 1567 default 300 if HZ_300 1568 default 500 if HZ_500 1569 default 1000 1570 1571config SCHED_HRTICK 1572 def_bool HIGH_RES_TIMERS 1573 1574config THUMB2_KERNEL 1575 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1576 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1577 default y if CPU_THUMBONLY 1578 select AEABI 1579 select ARM_ASM_UNIFIED 1580 select ARM_UNWIND 1581 help 1582 By enabling this option, the kernel will be compiled in 1583 Thumb-2 mode. A compiler/assembler that understand the unified 1584 ARM-Thumb syntax is needed. 1585 1586 If unsure, say N. 1587 1588config THUMB2_AVOID_R_ARM_THM_JUMP11 1589 bool "Work around buggy Thumb-2 short branch relocations in gas" 1590 depends on THUMB2_KERNEL && MODULES 1591 default y 1592 help 1593 Various binutils versions can resolve Thumb-2 branches to 1594 locally-defined, preemptible global symbols as short-range "b.n" 1595 branch instructions. 1596 1597 This is a problem, because there's no guarantee the final 1598 destination of the symbol, or any candidate locations for a 1599 trampoline, are within range of the branch. For this reason, the 1600 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1601 relocation in modules at all, and it makes little sense to add 1602 support. 1603 1604 The symptom is that the kernel fails with an "unsupported 1605 relocation" error when loading some modules. 1606 1607 Until fixed tools are available, passing 1608 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1609 code which hits this problem, at the cost of a bit of extra runtime 1610 stack usage in some cases. 1611 1612 The problem is described in more detail at: 1613 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1614 1615 Only Thumb-2 kernels are affected. 1616 1617 Unless you are sure your tools don't have this problem, say Y. 1618 1619config ARM_ASM_UNIFIED 1620 bool 1621 1622config AEABI 1623 bool "Use the ARM EABI to compile the kernel" 1624 help 1625 This option allows for the kernel to be compiled using the latest 1626 ARM ABI (aka EABI). This is only useful if you are using a user 1627 space environment that is also compiled with EABI. 1628 1629 Since there are major incompatibilities between the legacy ABI and 1630 EABI, especially with regard to structure member alignment, this 1631 option also changes the kernel syscall calling convention to 1632 disambiguate both ABIs and allow for backward compatibility support 1633 (selected with CONFIG_OABI_COMPAT). 1634 1635 To use this you need GCC version 4.0.0 or later. 1636 1637config OABI_COMPAT 1638 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1639 depends on AEABI && !THUMB2_KERNEL 1640 help 1641 This option preserves the old syscall interface along with the 1642 new (ARM EABI) one. It also provides a compatibility layer to 1643 intercept syscalls that have structure arguments which layout 1644 in memory differs between the legacy ABI and the new ARM EABI 1645 (only for non "thumb" binaries). This option adds a tiny 1646 overhead to all syscalls and produces a slightly larger kernel. 1647 1648 The seccomp filter system will not be available when this is 1649 selected, since there is no way yet to sensibly distinguish 1650 between calling conventions during filtering. 1651 1652 If you know you'll be using only pure EABI user space then you 1653 can say N here. If this option is not selected and you attempt 1654 to execute a legacy ABI binary then the result will be 1655 UNPREDICTABLE (in fact it can be predicted that it won't work 1656 at all). If in doubt say N. 1657 1658config ARCH_HAS_HOLES_MEMORYMODEL 1659 bool 1660 1661config ARCH_SPARSEMEM_ENABLE 1662 bool 1663 1664config ARCH_SPARSEMEM_DEFAULT 1665 def_bool ARCH_SPARSEMEM_ENABLE 1666 1667config ARCH_SELECT_MEMORY_MODEL 1668 def_bool ARCH_SPARSEMEM_ENABLE 1669 1670config HAVE_ARCH_PFN_VALID 1671 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1672 1673config HAVE_GENERIC_RCU_GUP 1674 def_bool y 1675 depends on ARM_LPAE 1676 1677config HIGHMEM 1678 bool "High Memory Support" 1679 depends on MMU 1680 help 1681 The address space of ARM processors is only 4 Gigabytes large 1682 and it has to accommodate user address space, kernel address 1683 space as well as some memory mapped IO. That means that, if you 1684 have a large amount of physical memory and/or IO, not all of the 1685 memory can be "permanently mapped" by the kernel. The physical 1686 memory that is not permanently mapped is called "high memory". 1687 1688 Depending on the selected kernel/user memory split, minimum 1689 vmalloc space and actual amount of RAM, you may not need this 1690 option which should result in a slightly faster kernel. 1691 1692 If unsure, say n. 1693 1694config HIGHPTE 1695 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1696 depends on HIGHMEM 1697 default y 1698 help 1699 The VM uses one page of physical memory for each page table. 1700 For systems with a lot of processes, this can use a lot of 1701 precious low memory, eventually leading to low memory being 1702 consumed by page tables. Setting this option will allow 1703 user-space 2nd level page tables to reside in high memory. 1704 1705config CPU_SW_DOMAIN_PAN 1706 bool "Enable use of CPU domains to implement privileged no-access" 1707 depends on MMU && !ARM_LPAE 1708 default y 1709 help 1710 Increase kernel security by ensuring that normal kernel accesses 1711 are unable to access userspace addresses. This can help prevent 1712 use-after-free bugs becoming an exploitable privilege escalation 1713 by ensuring that magic values (such as LIST_POISON) will always 1714 fault when dereferenced. 1715 1716 CPUs with low-vector mappings use a best-efforts implementation. 1717 Their lower 1MB needs to remain accessible for the vectors, but 1718 the remainder of userspace will become appropriately inaccessible. 1719 1720config HW_PERF_EVENTS 1721 def_bool y 1722 depends on ARM_PMU 1723 1724config SYS_SUPPORTS_HUGETLBFS 1725 def_bool y 1726 depends on ARM_LPAE 1727 1728config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1729 def_bool y 1730 depends on ARM_LPAE 1731 1732config ARCH_WANT_GENERAL_HUGETLB 1733 def_bool y 1734 1735config ARM_MODULE_PLTS 1736 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1737 depends on MODULES 1738 help 1739 Allocate PLTs when loading modules so that jumps and calls whose 1740 targets are too far away for their relative offsets to be encoded 1741 in the instructions themselves can be bounced via veneers in the 1742 module's PLT. This allows modules to be allocated in the generic 1743 vmalloc area after the dedicated module memory area has been 1744 exhausted. The modules will use slightly more memory, but after 1745 rounding up to page size, the actual memory footprint is usually 1746 the same. 1747 1748 Say y if you are getting out of memory errors while loading modules 1749 1750source "mm/Kconfig" 1751 1752config FORCE_MAX_ZONEORDER 1753 int "Maximum zone order" 1754 default "12" if SOC_AM33XX 1755 default "9" if SA1111 || ARCH_EFM32 1756 default "11" 1757 help 1758 The kernel memory allocator divides physically contiguous memory 1759 blocks into "zones", where each zone is a power of two number of 1760 pages. This option selects the largest power of two that the kernel 1761 keeps in the memory allocator. If you need to allocate very large 1762 blocks of physically contiguous memory, then you may need to 1763 increase this value. 1764 1765 This config option is actually maximum order plus one. For example, 1766 a value of 11 means that the largest free memory block is 2^10 pages. 1767 1768config ALIGNMENT_TRAP 1769 bool 1770 depends on CPU_CP15_MMU 1771 default y if !ARCH_EBSA110 1772 select HAVE_PROC_CPU if PROC_FS 1773 help 1774 ARM processors cannot fetch/store information which is not 1775 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1776 address divisible by 4. On 32-bit ARM processors, these non-aligned 1777 fetch/store instructions will be emulated in software if you say 1778 here, which has a severe performance impact. This is necessary for 1779 correct operation of some network protocols. With an IP-only 1780 configuration it is safe to say N, otherwise say Y. 1781 1782config UACCESS_WITH_MEMCPY 1783 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1784 depends on MMU 1785 default y if CPU_FEROCEON 1786 help 1787 Implement faster copy_to_user and clear_user methods for CPU 1788 cores where a 8-word STM instruction give significantly higher 1789 memory write throughput than a sequence of individual 32bit stores. 1790 1791 A possible side effect is a slight increase in scheduling latency 1792 between threads sharing the same address space if they invoke 1793 such copy operations with large buffers. 1794 1795 However, if the CPU data cache is using a write-allocate mode, 1796 this option is unlikely to provide any performance gain. 1797 1798config SECCOMP 1799 bool 1800 prompt "Enable seccomp to safely compute untrusted bytecode" 1801 ---help--- 1802 This kernel feature is useful for number crunching applications 1803 that may need to compute untrusted bytecode during their 1804 execution. By using pipes or other transports made available to 1805 the process as file descriptors supporting the read/write 1806 syscalls, it's possible to isolate those applications in 1807 their own address space using seccomp. Once seccomp is 1808 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1809 and the task is only allowed to execute a few safe syscalls 1810 defined by each seccomp mode. 1811 1812config SWIOTLB 1813 def_bool y 1814 1815config IOMMU_HELPER 1816 def_bool SWIOTLB 1817 1818config XEN_DOM0 1819 def_bool y 1820 depends on XEN 1821 1822config XEN 1823 bool "Xen guest support on ARM" 1824 depends on ARM && AEABI && OF 1825 depends on CPU_V7 && !CPU_V6 1826 depends on !GENERIC_ATOMIC64 1827 depends on MMU 1828 select ARCH_DMA_ADDR_T_64BIT 1829 select ARM_PSCI 1830 select SWIOTLB_XEN 1831 help 1832 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1833 1834config ARM_FLUSH_CONSOLE_ON_RESTART 1835 bool "Force flush the console on restart" 1836 help 1837 If the console is locked while the system is rebooted, the messages 1838 in the temporary logbuffer would not have propogated to all the 1839 console drivers. This option forces the console lock to be 1840 released if it failed to be acquired, which will cause all the 1841 pending messages to be flushed. 1842 1843endmenu 1844 1845menu "Boot options" 1846 1847config USE_OF 1848 bool "Flattened Device Tree support" 1849 select IRQ_DOMAIN 1850 select OF 1851 help 1852 Include support for flattened device tree machine descriptions. 1853 1854config ATAGS 1855 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1856 default y 1857 help 1858 This is the traditional way of passing data to the kernel at boot 1859 time. If you are solely relying on the flattened device tree (or 1860 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1861 to remove ATAGS support from your kernel binary. If unsure, 1862 leave this to y. 1863 1864config DEPRECATED_PARAM_STRUCT 1865 bool "Provide old way to pass kernel parameters" 1866 depends on ATAGS 1867 help 1868 This was deprecated in 2001 and announced to live on for 5 years. 1869 Some old boot loaders still use this way. 1870 1871config BUILD_ARM_APPENDED_DTB_IMAGE 1872 bool "Build a concatenated zImage/dtb by default" 1873 depends on OF 1874 help 1875 Enabling this option will cause a concatenated zImage and list of 1876 DTBs to be built by default (instead of a standalone zImage.) 1877 The image will built in arch/arm/boot/zImage-dtb 1878 1879config BUILD_ARM_APPENDED_DTB_IMAGE_NAMES 1880 string "Default dtb names" 1881 depends on BUILD_ARM_APPENDED_DTB_IMAGE 1882 help 1883 Space separated list of names of dtbs to append when 1884 building a concatenated zImage-dtb. 1885 1886# Compressed boot loader in ROM. Yes, we really want to ask about 1887# TEXT and BSS so we preserve their values in the config files. 1888config ZBOOT_ROM_TEXT 1889 hex "Compressed ROM boot loader base address" 1890 default "0" 1891 help 1892 The physical address at which the ROM-able zImage is to be 1893 placed in the target. Platforms which normally make use of 1894 ROM-able zImage formats normally set this to a suitable 1895 value in their defconfig file. 1896 1897 If ZBOOT_ROM is not enabled, this has no effect. 1898 1899config ZBOOT_ROM_BSS 1900 hex "Compressed ROM boot loader BSS address" 1901 default "0" 1902 help 1903 The base address of an area of read/write memory in the target 1904 for the ROM-able zImage which must be available while the 1905 decompressor is running. It must be large enough to hold the 1906 entire decompressed kernel plus an additional 128 KiB. 1907 Platforms which normally make use of ROM-able zImage formats 1908 normally set this to a suitable value in their defconfig file. 1909 1910 If ZBOOT_ROM is not enabled, this has no effect. 1911 1912config ZBOOT_ROM 1913 bool "Compressed boot loader in ROM/flash" 1914 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1915 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1916 help 1917 Say Y here if you intend to execute your compressed kernel image 1918 (zImage) directly from ROM or flash. If unsure, say N. 1919 1920config ARM_APPENDED_DTB 1921 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1922 depends on OF 1923 help 1924 With this option, the boot code will look for a device tree binary 1925 (DTB) appended to zImage 1926 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1927 1928 This is meant as a backward compatibility convenience for those 1929 systems with a bootloader that can't be upgraded to accommodate 1930 the documented boot protocol using a device tree. 1931 1932 Beware that there is very little in terms of protection against 1933 this option being confused by leftover garbage in memory that might 1934 look like a DTB header after a reboot if no actual DTB is appended 1935 to zImage. Do not leave this option active in a production kernel 1936 if you don't intend to always append a DTB. Proper passing of the 1937 location into r2 of a bootloader provided DTB is always preferable 1938 to this option. 1939 1940config ARM_ATAG_DTB_COMPAT 1941 bool "Supplement the appended DTB with traditional ATAG information" 1942 depends on ARM_APPENDED_DTB 1943 help 1944 Some old bootloaders can't be updated to a DTB capable one, yet 1945 they provide ATAGs with memory configuration, the ramdisk address, 1946 the kernel cmdline string, etc. Such information is dynamically 1947 provided by the bootloader and can't always be stored in a static 1948 DTB. To allow a device tree enabled kernel to be used with such 1949 bootloaders, this option allows zImage to extract the information 1950 from the ATAG list and store it at run time into the appended DTB. 1951 1952choice 1953 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1954 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1955 1956config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1957 bool "Use bootloader kernel arguments if available" 1958 help 1959 Uses the command-line options passed by the boot loader instead of 1960 the device tree bootargs property. If the boot loader doesn't provide 1961 any, the device tree bootargs property will be used. 1962 1963config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1964 bool "Extend with bootloader kernel arguments" 1965 help 1966 The command-line arguments provided by the boot loader will be 1967 appended to the the device tree bootargs property. 1968 1969endchoice 1970 1971config CMDLINE 1972 string "Default kernel command string" 1973 default "" 1974 help 1975 On some architectures (EBSA110 and CATS), there is currently no way 1976 for the boot loader to pass arguments to the kernel. For these 1977 architectures, you should supply some command-line options at build 1978 time by entering them here. As a minimum, you should specify the 1979 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1980 1981choice 1982 prompt "Kernel command line type" if CMDLINE != "" 1983 default CMDLINE_FROM_BOOTLOADER 1984 depends on ATAGS 1985 1986config CMDLINE_FROM_BOOTLOADER 1987 bool "Use bootloader kernel arguments if available" 1988 help 1989 Uses the command-line options passed by the boot loader. If 1990 the boot loader doesn't provide any, the default kernel command 1991 string provided in CMDLINE will be used. 1992 1993config CMDLINE_EXTEND 1994 bool "Extend bootloader kernel arguments" 1995 help 1996 The command-line arguments provided by the boot loader will be 1997 appended to the default kernel command string. 1998 1999config CMDLINE_FORCE 2000 bool "Always use the default kernel command string" 2001 help 2002 Always use the default kernel command string, even if the boot 2003 loader passes other arguments to the kernel. 2004 This is useful if you cannot or don't want to change the 2005 command-line options your boot loader passes to the kernel. 2006endchoice 2007 2008config XIP_KERNEL 2009 bool "Kernel Execute-In-Place from ROM" 2010 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 2011 help 2012 Execute-In-Place allows the kernel to run from non-volatile storage 2013 directly addressable by the CPU, such as NOR flash. This saves RAM 2014 space since the text section of the kernel is not loaded from flash 2015 to RAM. Read-write sections, such as the data section and stack, 2016 are still copied to RAM. The XIP kernel is not compressed since 2017 it has to run directly from flash, so it will take more space to 2018 store it. The flash address used to link the kernel object files, 2019 and for storing it, is configuration dependent. Therefore, if you 2020 say Y here, you must know the proper physical address where to 2021 store the kernel image depending on your own flash memory usage. 2022 2023 Also note that the make target becomes "make xipImage" rather than 2024 "make zImage" or "make Image". The final kernel binary to put in 2025 ROM memory will be arch/arm/boot/xipImage. 2026 2027 If unsure, say N. 2028 2029config XIP_PHYS_ADDR 2030 hex "XIP Kernel Physical Location" 2031 depends on XIP_KERNEL 2032 default "0x00080000" 2033 help 2034 This is the physical address in your flash memory the kernel will 2035 be linked for and stored to. This address is dependent on your 2036 own flash usage. 2037 2038config KEXEC 2039 bool "Kexec system call (EXPERIMENTAL)" 2040 depends on (!SMP || PM_SLEEP_SMP) 2041 depends on MMU 2042 select KEXEC_CORE 2043 help 2044 kexec is a system call that implements the ability to shutdown your 2045 current kernel, and to start another kernel. It is like a reboot 2046 but it is independent of the system firmware. And like a reboot 2047 you can start any kernel with it, not just Linux. 2048 2049 It is an ongoing process to be certain the hardware in a machine 2050 is properly shutdown, so do not be surprised if this code does not 2051 initially work for you. 2052 2053config ATAGS_PROC 2054 bool "Export atags in procfs" 2055 depends on ATAGS && KEXEC 2056 default y 2057 help 2058 Should the atags used to boot the kernel be exported in an "atags" 2059 file in procfs. Useful with kexec. 2060 2061config CRASH_DUMP 2062 bool "Build kdump crash kernel (EXPERIMENTAL)" 2063 help 2064 Generate crash dump after being started by kexec. This should 2065 be normally only set in special crash dump kernels which are 2066 loaded in the main kernel with kexec-tools into a specially 2067 reserved region and then later executed after a crash by 2068 kdump/kexec. The crash dump kernel must be compiled to a 2069 memory address not used by the main kernel 2070 2071 For more details see Documentation/kdump/kdump.txt 2072 2073config AUTO_ZRELADDR 2074 bool "Auto calculation of the decompressed kernel image address" 2075 help 2076 ZRELADDR is the physical address where the decompressed kernel 2077 image will be placed. If AUTO_ZRELADDR is selected, the address 2078 will be determined at run-time by masking the current IP with 2079 0xf8000000. This assumes the zImage being placed in the first 128MB 2080 from start of memory. 2081 2082endmenu 2083 2084menu "CPU Power Management" 2085 2086source "drivers/cpufreq/Kconfig" 2087 2088source "drivers/cpuidle/Kconfig" 2089 2090endmenu 2091 2092menu "Floating point emulation" 2093 2094comment "At least one emulation must be selected" 2095 2096config FPE_NWFPE 2097 bool "NWFPE math emulation" 2098 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2099 ---help--- 2100 Say Y to include the NWFPE floating point emulator in the kernel. 2101 This is necessary to run most binaries. Linux does not currently 2102 support floating point hardware so you need to say Y here even if 2103 your machine has an FPA or floating point co-processor podule. 2104 2105 You may say N here if you are going to load the Acorn FPEmulator 2106 early in the bootup. 2107 2108config FPE_NWFPE_XP 2109 bool "Support extended precision" 2110 depends on FPE_NWFPE 2111 help 2112 Say Y to include 80-bit support in the kernel floating-point 2113 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2114 Note that gcc does not generate 80-bit operations by default, 2115 so in most cases this option only enlarges the size of the 2116 floating point emulator without any good reason. 2117 2118 You almost surely want to say N here. 2119 2120config FPE_FASTFPE 2121 bool "FastFPE math emulation (EXPERIMENTAL)" 2122 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2123 ---help--- 2124 Say Y here to include the FAST floating point emulator in the kernel. 2125 This is an experimental much faster emulator which now also has full 2126 precision for the mantissa. It does not support any exceptions. 2127 It is very simple, and approximately 3-6 times faster than NWFPE. 2128 2129 It should be sufficient for most programs. It may be not suitable 2130 for scientific calculations, but you have to check this for yourself. 2131 If you do not feel you need a faster FP emulation you should better 2132 choose NWFPE. 2133 2134config VFP 2135 bool "VFP-format floating point maths" 2136 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2137 help 2138 Say Y to include VFP support code in the kernel. This is needed 2139 if your hardware includes a VFP unit. 2140 2141 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2142 release notes and additional status information. 2143 2144 Say N if your target does not have VFP hardware. 2145 2146config VFPv3 2147 bool 2148 depends on VFP 2149 default y if CPU_V7 2150 2151config NEON 2152 bool "Advanced SIMD (NEON) Extension support" 2153 depends on VFPv3 && CPU_V7 2154 help 2155 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2156 Extension. 2157 2158config KERNEL_MODE_NEON 2159 bool "Support for NEON in kernel mode" 2160 depends on NEON && AEABI 2161 help 2162 Say Y to include support for NEON in kernel mode. 2163 2164endmenu 2165 2166menu "Userspace binary formats" 2167 2168source "fs/Kconfig.binfmt" 2169 2170endmenu 2171 2172menu "Power management options" 2173 2174source "kernel/power/Kconfig" 2175 2176config ARCH_SUSPEND_POSSIBLE 2177 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2178 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2179 def_bool y 2180 2181config ARM_CPU_SUSPEND 2182 def_bool PM_SLEEP || BL_SWITCHER 2183 depends on ARCH_SUSPEND_POSSIBLE 2184 2185config ARCH_HIBERNATION_POSSIBLE 2186 bool 2187 depends on MMU 2188 default y if ARCH_SUSPEND_POSSIBLE 2189 2190endmenu 2191 2192source "net/Kconfig" 2193 2194source "drivers/Kconfig" 2195 2196source "drivers/firmware/Kconfig" 2197 2198source "fs/Kconfig" 2199 2200source "arch/arm/Kconfig.debug" 2201 2202source "security/Kconfig" 2203 2204source "crypto/Kconfig" 2205if CRYPTO 2206source "arch/arm/crypto/Kconfig" 2207endif 2208 2209source "lib/Kconfig" 2210 2211source "arch/arm/kvm/Kconfig" 2212