1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef KFD_DBGMGR_H_ 25 #define KFD_DBGMGR_H_ 26 27 #include "kfd_priv.h" 28 29 /* must align with hsakmttypes definition */ 30 #pragma pack(push, 4) 31 32 enum HSA_DBG_WAVEOP { 33 HSA_DBG_WAVEOP_HALT = 1, /* Halts a wavefront */ 34 HSA_DBG_WAVEOP_RESUME = 2, /* Resumes a wavefront */ 35 HSA_DBG_WAVEOP_KILL = 3, /* Kills a wavefront */ 36 HSA_DBG_WAVEOP_DEBUG = 4, /* Causes wavefront to enter 37 debug mode */ 38 HSA_DBG_WAVEOP_TRAP = 5, /* Causes wavefront to take 39 a trap */ 40 HSA_DBG_NUM_WAVEOP = 5, 41 HSA_DBG_MAX_WAVEOP = 0xFFFFFFFF 42 }; 43 44 enum HSA_DBG_WAVEMODE { 45 /* send command to a single wave */ 46 HSA_DBG_WAVEMODE_SINGLE = 0, 47 /* 48 * Broadcast to all wavefronts of all processes is not 49 * supported for HSA user mode 50 */ 51 52 /* send to waves within current process */ 53 HSA_DBG_WAVEMODE_BROADCAST_PROCESS = 2, 54 /* send to waves within current process on CU */ 55 HSA_DBG_WAVEMODE_BROADCAST_PROCESS_CU = 3, 56 HSA_DBG_NUM_WAVEMODE = 3, 57 HSA_DBG_MAX_WAVEMODE = 0xFFFFFFFF 58 }; 59 60 enum HSA_DBG_WAVEMSG_TYPE { 61 HSA_DBG_WAVEMSG_AUTO = 0, 62 HSA_DBG_WAVEMSG_USER = 1, 63 HSA_DBG_WAVEMSG_ERROR = 2, 64 HSA_DBG_NUM_WAVEMSG, 65 HSA_DBG_MAX_WAVEMSG = 0xFFFFFFFF 66 }; 67 68 enum HSA_DBG_WATCH_MODE { 69 HSA_DBG_WATCH_READ = 0, /* Read operations only */ 70 HSA_DBG_WATCH_NONREAD = 1, /* Write or Atomic operations only */ 71 HSA_DBG_WATCH_ATOMIC = 2, /* Atomic Operations only */ 72 HSA_DBG_WATCH_ALL = 3, /* Read, Write or Atomic operations */ 73 HSA_DBG_WATCH_NUM, 74 HSA_DBG_WATCH_SIZE = 0xFFFFFFFF 75 }; 76 77 /* This structure is hardware specific and may change in the future */ 78 struct HsaDbgWaveMsgAMDGen2 { 79 union { 80 struct ui32 { 81 uint32_t UserData:8; /* user data */ 82 uint32_t ShaderArray:1; /* Shader array */ 83 uint32_t Priv:1; /* Privileged */ 84 uint32_t Reserved0:4; /* This field is reserved, 85 should be 0 */ 86 uint32_t WaveId:4; /* wave id */ 87 uint32_t SIMD:2; /* SIMD id */ 88 uint32_t HSACU:4; /* Compute unit */ 89 uint32_t ShaderEngine:2;/* Shader engine */ 90 uint32_t MessageType:2; /* see HSA_DBG_WAVEMSG_TYPE */ 91 uint32_t Reserved1:4; /* This field is reserved, 92 should be 0 */ 93 } ui32; 94 uint32_t Value; 95 }; 96 uint32_t Reserved2; 97 }; 98 99 union HsaDbgWaveMessageAMD { 100 struct HsaDbgWaveMsgAMDGen2 WaveMsgInfoGen2; 101 /* for future HsaDbgWaveMsgAMDGen3; */ 102 }; 103 104 struct HsaDbgWaveMessage { 105 void *MemoryVA; /* ptr to associated host-accessible data */ 106 union HsaDbgWaveMessageAMD DbgWaveMsg; 107 }; 108 109 /* 110 * TODO: This definitions to be MOVED to kfd_event, once it is implemented. 111 * 112 * HSA sync primitive, Event and HW Exception notification API definitions. 113 * The API functions allow the runtime to define a so-called sync-primitive, 114 * a SW object combining a user-mode provided "syncvar" and a scheduler event 115 * that can be signaled through a defined GPU interrupt. A syncvar is 116 * a process virtual memory location of a certain size that can be accessed 117 * by CPU and GPU shader code within the process to set and query the content 118 * within that memory. The definition of the content is determined by the HSA 119 * runtime and potentially GPU shader code interfacing with the HSA runtime. 120 * The syncvar values may be commonly written through an PM4 WRITE_DATA packet 121 * in the user mode instruction stream. The OS scheduler event is typically 122 * associated and signaled by an interrupt issued by the GPU, but other HSA 123 * system interrupt conditions from other HW (e.g. IOMMUv2) may be surfaced 124 * by the KFD by this mechanism, too. */ 125 126 /* these are the new definitions for events */ 127 enum HSA_EVENTTYPE { 128 HSA_EVENTTYPE_SIGNAL = 0, /* user-mode generated GPU signal */ 129 HSA_EVENTTYPE_NODECHANGE = 1, /* HSA node change (attach/detach) */ 130 HSA_EVENTTYPE_DEVICESTATECHANGE = 2, /* HSA device state change 131 (start/stop) */ 132 HSA_EVENTTYPE_HW_EXCEPTION = 3, /* GPU shader exception event */ 133 HSA_EVENTTYPE_SYSTEM_EVENT = 4, /* GPU SYSCALL with parameter info */ 134 HSA_EVENTTYPE_DEBUG_EVENT = 5, /* GPU signal for debugging */ 135 HSA_EVENTTYPE_PROFILE_EVENT = 6,/* GPU signal for profiling */ 136 HSA_EVENTTYPE_QUEUE_EVENT = 7, /* GPU signal queue idle state 137 (EOP pm4) */ 138 /* ... */ 139 HSA_EVENTTYPE_MAXID, 140 HSA_EVENTTYPE_TYPE_SIZE = 0xFFFFFFFF 141 }; 142 143 /* Sub-definitions for various event types: Syncvar */ 144 struct HsaSyncVar { 145 union SyncVar { 146 void *UserData; /* pointer to user mode data */ 147 uint64_t UserDataPtrValue; /* 64bit compatibility of value */ 148 } SyncVar; 149 uint64_t SyncVarSize; 150 }; 151 152 /* Sub-definitions for various event types: NodeChange */ 153 154 enum HSA_EVENTTYPE_NODECHANGE_FLAGS { 155 HSA_EVENTTYPE_NODECHANGE_ADD = 0, 156 HSA_EVENTTYPE_NODECHANGE_REMOVE = 1, 157 HSA_EVENTTYPE_NODECHANGE_SIZE = 0xFFFFFFFF 158 }; 159 160 struct HsaNodeChange { 161 /* HSA node added/removed on the platform */ 162 enum HSA_EVENTTYPE_NODECHANGE_FLAGS Flags; 163 }; 164 165 /* Sub-definitions for various event types: DeviceStateChange */ 166 enum HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS { 167 /* device started (and available) */ 168 HSA_EVENTTYPE_DEVICESTATUSCHANGE_START = 0, 169 /* device stopped (i.e. unavailable) */ 170 HSA_EVENTTYPE_DEVICESTATUSCHANGE_STOP = 1, 171 HSA_EVENTTYPE_DEVICESTATUSCHANGE_SIZE = 0xFFFFFFFF 172 }; 173 174 enum HSA_DEVICE { 175 HSA_DEVICE_CPU = 0, 176 HSA_DEVICE_GPU = 1, 177 MAX_HSA_DEVICE = 2 178 }; 179 180 struct HsaDeviceStateChange { 181 uint32_t NodeId; /* F-NUMA node that contains the device */ 182 enum HSA_DEVICE Device; /* device type: GPU or CPU */ 183 enum HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS Flags; /* event flags */ 184 }; 185 186 struct HsaEventData { 187 enum HSA_EVENTTYPE EventType; /* event type */ 188 union EventData { 189 /* 190 * return data associated with HSA_EVENTTYPE_SIGNAL 191 * and other events 192 */ 193 struct HsaSyncVar SyncVar; 194 195 /* data associated with HSA_EVENTTYPE_NODE_CHANGE */ 196 struct HsaNodeChange NodeChangeState; 197 198 /* data associated with HSA_EVENTTYPE_DEVICE_STATE_CHANGE */ 199 struct HsaDeviceStateChange DeviceState; 200 } EventData; 201 202 /* the following data entries are internal to the KFD & thunk itself */ 203 204 /* internal thunk store for Event data (OsEventHandle) */ 205 uint64_t HWData1; 206 /* internal thunk store for Event data (HWAddress) */ 207 uint64_t HWData2; 208 /* internal thunk store for Event data (HWData) */ 209 uint32_t HWData3; 210 }; 211 212 struct HsaEventDescriptor { 213 /* event type to allocate */ 214 enum HSA_EVENTTYPE EventType; 215 /* H-NUMA node containing GPU device that is event source */ 216 uint32_t NodeId; 217 /* pointer to user mode syncvar data, syncvar->UserDataPtrValue 218 * may be NULL 219 */ 220 struct HsaSyncVar SyncVar; 221 }; 222 223 struct HsaEvent { 224 uint32_t EventId; 225 struct HsaEventData EventData; 226 }; 227 228 #pragma pack(pop) 229 230 enum DBGDEV_TYPE { 231 DBGDEV_TYPE_ILLEGAL = 0, 232 DBGDEV_TYPE_NODIQ = 1, 233 DBGDEV_TYPE_DIQ = 2, 234 DBGDEV_TYPE_TEST = 3 235 }; 236 237 struct dbg_address_watch_info { 238 struct kfd_process *process; 239 enum HSA_DBG_WATCH_MODE *watch_mode; 240 uint64_t *watch_address; 241 uint64_t *watch_mask; 242 struct HsaEvent *watch_event; 243 uint32_t num_watch_points; 244 }; 245 246 struct dbg_wave_control_info { 247 struct kfd_process *process; 248 uint32_t trapId; 249 enum HSA_DBG_WAVEOP operand; 250 enum HSA_DBG_WAVEMODE mode; 251 struct HsaDbgWaveMessage dbgWave_msg; 252 }; 253 254 struct kfd_dbgdev { 255 256 /* The device that owns this data. */ 257 struct kfd_dev *dev; 258 259 /* kernel queue for DIQ */ 260 struct kernel_queue *kq; 261 262 /* a pointer to the pqm of the calling process */ 263 struct process_queue_manager *pqm; 264 265 /* type of debug device ( DIQ, non DIQ, etc. ) */ 266 enum DBGDEV_TYPE type; 267 268 /* virtualized function pointers to device dbg */ 269 int (*dbgdev_register)(struct kfd_dbgdev *dbgdev); 270 int (*dbgdev_unregister)(struct kfd_dbgdev *dbgdev); 271 int (*dbgdev_address_watch)(struct kfd_dbgdev *dbgdev, 272 struct dbg_address_watch_info *adw_info); 273 int (*dbgdev_wave_control)(struct kfd_dbgdev *dbgdev, 274 struct dbg_wave_control_info *wac_info); 275 276 }; 277 278 struct kfd_dbgmgr { 279 unsigned int pasid; 280 struct kfd_dev *dev; 281 struct kfd_dbgdev *dbgdev; 282 }; 283 284 /* prototypes for debug manager functions */ 285 struct mutex *kfd_get_dbgmgr_mutex(void); 286 void kfd_dbgmgr_destroy(struct kfd_dbgmgr *pmgr); 287 bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev); 288 long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p); 289 long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p); 290 long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr, 291 struct dbg_wave_control_info *wac_info); 292 long kfd_dbgmgr_address_watch(struct kfd_dbgmgr *pmgr, 293 struct dbg_address_watch_info *adw_info); 294 #endif /* KFD_DBGMGR_H_ */ 295