1 /* Copyright 2008-2013 Broadcom Corporation
2 * Copyright (c) 2014 QLogic Corporation
3 * All rights reserved
4 *
5 * Unless you and QLogic execute a separate written software license
6 * agreement governing use of this software, this software is licensed to you
7 * under the terms of the GNU General Public License version 2, available
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
9 *
10 * Notwithstanding the above, under no circumstances may you combine this
11 * software in any way with any other Qlogic software provided under a
12 * license other than the GPL, without Qlogic's express prior written
13 * consent.
14 *
15 * Written by Yaniv Rosner
16 *
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/kernel.h>
22 #include <linux/errno.h>
23 #include <linux/pci.h>
24 #include <linux/netdevice.h>
25 #include <linux/delay.h>
26 #include <linux/ethtool.h>
27 #include <linux/mutex.h>
28
29 #include "bnx2x.h"
30 #include "bnx2x_cmn.h"
31
32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
33 struct link_params *params,
34 u8 dev_addr, u16 addr, u8 byte_cnt,
35 u8 *o_buf, u8);
36 /********************************************************/
37 #define ETH_HLEN 14
38 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
39 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
40 #define ETH_MIN_PACKET_SIZE 60
41 #define ETH_MAX_PACKET_SIZE 1500
42 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
43 #define MDIO_ACCESS_TIMEOUT 1000
44 #define WC_LANE_MAX 4
45 #define I2C_SWITCH_WIDTH 2
46 #define I2C_BSC0 0
47 #define I2C_BSC1 1
48 #define I2C_WA_RETRY_CNT 3
49 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
50 #define MCPR_IMC_COMMAND_READ_OP 1
51 #define MCPR_IMC_COMMAND_WRITE_OP 2
52
53 /* LED Blink rate that will achieve ~15.9Hz */
54 #define LED_BLINK_RATE_VAL_E3 354
55 #define LED_BLINK_RATE_VAL_E1X_E2 480
56 /***********************************************************/
57 /* Shortcut definitions */
58 /***********************************************************/
59
60 #define NIG_LATCH_BC_ENABLE_MI_INT 0
61
62 #define NIG_STATUS_EMAC0_MI_INT \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
64 #define NIG_STATUS_XGXS0_LINK10G \
65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
66 #define NIG_STATUS_XGXS0_LINK_STATUS \
67 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
68 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
69 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
70 #define NIG_STATUS_SERDES0_LINK_STATUS \
71 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
72 #define NIG_MASK_MI_INT \
73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
74 #define NIG_MASK_XGXS0_LINK10G \
75 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
76 #define NIG_MASK_XGXS0_LINK_STATUS \
77 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
78 #define NIG_MASK_SERDES0_LINK_STATUS \
79 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
80
81 #define MDIO_AN_CL73_OR_37_COMPLETE \
82 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
83 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
84
85 #define XGXS_RESET_BITS \
86 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
90 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
91
92 #define SERDES_RESET_BITS \
93 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
94 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
95 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
96 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
97
98 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
99 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
100 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
101 #define AUTONEG_PARALLEL \
102 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
103 #define AUTONEG_SGMII_FIBER_AUTODET \
104 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
105 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
106
107 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
108 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
109 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
110 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
111 #define GP_STATUS_SPEED_MASK \
112 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
113 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
114 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
115 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
116 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
117 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
118 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
119 #define GP_STATUS_10G_HIG \
120 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
121 #define GP_STATUS_10G_CX4 \
122 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
123 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
124 #define GP_STATUS_10G_KX4 \
125 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
126 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
127 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
128 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
129 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
130 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
131 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
132 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
133 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
134 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
135 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
136 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
137 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
138 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
139 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
140 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
141 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
142 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
143 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
144 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
145 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
146
147 #define LINK_UPDATE_MASK \
148 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
149 LINK_STATUS_LINK_UP | \
150 LINK_STATUS_PHYSICAL_LINK_FLAG | \
151 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
152 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
153 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
154 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
155 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
156 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
157
158 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
159 #define SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0
160 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
161 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
162 #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
163
164
165 #define SFP_EEPROM_10G_COMP_CODE_ADDR 0x3
166 #define SFP_EEPROM_10G_COMP_CODE_SR_MASK (1<<4)
167 #define SFP_EEPROM_10G_COMP_CODE_LR_MASK (1<<5)
168 #define SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1<<6)
169
170 #define SFP_EEPROM_1G_COMP_CODE_ADDR 0x6
171 #define SFP_EEPROM_1G_COMP_CODE_SX (1<<0)
172 #define SFP_EEPROM_1G_COMP_CODE_LX (1<<1)
173 #define SFP_EEPROM_1G_COMP_CODE_CX (1<<2)
174 #define SFP_EEPROM_1G_COMP_CODE_BASE_T (1<<3)
175
176 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
177 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
178 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
179
180 #define SFP_EEPROM_OPTIONS_ADDR 0x40
181 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
182 #define SFP_EEPROM_OPTIONS_SIZE 2
183
184 #define EDC_MODE_LINEAR 0x0022
185 #define EDC_MODE_LIMITING 0x0044
186 #define EDC_MODE_PASSIVE_DAC 0x0055
187 #define EDC_MODE_ACTIVE_DAC 0x0066
188
189 /* ETS defines*/
190 #define DCBX_INVALID_COS (0xFF)
191
192 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
193 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
194 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
195 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
196 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
197
198 #define MAX_PACKET_SIZE (9700)
199 #define MAX_KR_LINK_RETRY 4
200 #define DEFAULT_TX_DRV_BRDCT 2
201 #define DEFAULT_TX_DRV_IFIR 0
202 #define DEFAULT_TX_DRV_POST2 3
203 #define DEFAULT_TX_DRV_IPRE_DRIVER 6
204
205 /**********************************************************/
206 /* INTERFACE */
207 /**********************************************************/
208
209 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
210 bnx2x_cl45_write(_bp, _phy, \
211 (_phy)->def_md_devad, \
212 (_bank + (_addr & 0xf)), \
213 _val)
214
215 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
216 bnx2x_cl45_read(_bp, _phy, \
217 (_phy)->def_md_devad, \
218 (_bank + (_addr & 0xf)), \
219 _val)
220
221 static int bnx2x_check_half_open_conn(struct link_params *params,
222 struct link_vars *vars, u8 notify);
223 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
224 struct link_params *params);
225
bnx2x_bits_en(struct bnx2x * bp,u32 reg,u32 bits)226 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
227 {
228 u32 val = REG_RD(bp, reg);
229
230 val |= bits;
231 REG_WR(bp, reg, val);
232 return val;
233 }
234
bnx2x_bits_dis(struct bnx2x * bp,u32 reg,u32 bits)235 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
236 {
237 u32 val = REG_RD(bp, reg);
238
239 val &= ~bits;
240 REG_WR(bp, reg, val);
241 return val;
242 }
243
244 /*
245 * bnx2x_check_lfa - This function checks if link reinitialization is required,
246 * or link flap can be avoided.
247 *
248 * @params: link parameters
249 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
250 * condition code.
251 */
bnx2x_check_lfa(struct link_params * params)252 static int bnx2x_check_lfa(struct link_params *params)
253 {
254 u32 link_status, cfg_idx, lfa_mask, cfg_size;
255 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
256 u32 saved_val, req_val, eee_status;
257 struct bnx2x *bp = params->bp;
258
259 additional_config =
260 REG_RD(bp, params->lfa_base +
261 offsetof(struct shmem_lfa, additional_config));
262
263 /* NOTE: must be first condition checked -
264 * to verify DCC bit is cleared in any case!
265 */
266 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
267 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
268 REG_WR(bp, params->lfa_base +
269 offsetof(struct shmem_lfa, additional_config),
270 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
271 return LFA_DCC_LFA_DISABLED;
272 }
273
274 /* Verify that link is up */
275 link_status = REG_RD(bp, params->shmem_base +
276 offsetof(struct shmem_region,
277 port_mb[params->port].link_status));
278 if (!(link_status & LINK_STATUS_LINK_UP))
279 return LFA_LINK_DOWN;
280
281 /* if loaded after BOOT from SAN, don't flap the link in any case and
282 * rely on link set by preboot driver
283 */
284 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
285 return 0;
286
287 /* Verify that loopback mode is not set */
288 if (params->loopback_mode)
289 return LFA_LOOPBACK_ENABLED;
290
291 /* Verify that MFW supports LFA */
292 if (!params->lfa_base)
293 return LFA_MFW_IS_TOO_OLD;
294
295 if (params->num_phys == 3) {
296 cfg_size = 2;
297 lfa_mask = 0xffffffff;
298 } else {
299 cfg_size = 1;
300 lfa_mask = 0xffff;
301 }
302
303 /* Compare Duplex */
304 saved_val = REG_RD(bp, params->lfa_base +
305 offsetof(struct shmem_lfa, req_duplex));
306 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
307 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
308 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
309 (saved_val & lfa_mask), (req_val & lfa_mask));
310 return LFA_DUPLEX_MISMATCH;
311 }
312 /* Compare Flow Control */
313 saved_val = REG_RD(bp, params->lfa_base +
314 offsetof(struct shmem_lfa, req_flow_ctrl));
315 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
316 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
317 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
318 (saved_val & lfa_mask), (req_val & lfa_mask));
319 return LFA_FLOW_CTRL_MISMATCH;
320 }
321 /* Compare Link Speed */
322 saved_val = REG_RD(bp, params->lfa_base +
323 offsetof(struct shmem_lfa, req_line_speed));
324 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
325 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
326 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
327 (saved_val & lfa_mask), (req_val & lfa_mask));
328 return LFA_LINK_SPEED_MISMATCH;
329 }
330
331 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
332 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
333 offsetof(struct shmem_lfa,
334 speed_cap_mask[cfg_idx]));
335
336 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
337 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
338 cur_speed_cap_mask,
339 params->speed_cap_mask[cfg_idx]);
340 return LFA_SPEED_CAP_MISMATCH;
341 }
342 }
343
344 cur_req_fc_auto_adv =
345 REG_RD(bp, params->lfa_base +
346 offsetof(struct shmem_lfa, additional_config)) &
347 REQ_FC_AUTO_ADV_MASK;
348
349 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
350 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
351 cur_req_fc_auto_adv, params->req_fc_auto_adv);
352 return LFA_FLOW_CTRL_MISMATCH;
353 }
354
355 eee_status = REG_RD(bp, params->shmem2_base +
356 offsetof(struct shmem2_region,
357 eee_status[params->port]));
358
359 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
360 (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
361 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
362 (params->eee_mode & EEE_MODE_ADV_LPI))) {
363 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
364 eee_status);
365 return LFA_EEE_MISMATCH;
366 }
367
368 /* LFA conditions are met */
369 return 0;
370 }
371 /******************************************************************/
372 /* EPIO/GPIO section */
373 /******************************************************************/
bnx2x_get_epio(struct bnx2x * bp,u32 epio_pin,u32 * en)374 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
375 {
376 u32 epio_mask, gp_oenable;
377 *en = 0;
378 /* Sanity check */
379 if (epio_pin > 31) {
380 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
381 return;
382 }
383
384 epio_mask = 1 << epio_pin;
385 /* Set this EPIO to output */
386 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
387 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
388
389 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
390 }
bnx2x_set_epio(struct bnx2x * bp,u32 epio_pin,u32 en)391 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
392 {
393 u32 epio_mask, gp_output, gp_oenable;
394
395 /* Sanity check */
396 if (epio_pin > 31) {
397 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
398 return;
399 }
400 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
401 epio_mask = 1 << epio_pin;
402 /* Set this EPIO to output */
403 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
404 if (en)
405 gp_output |= epio_mask;
406 else
407 gp_output &= ~epio_mask;
408
409 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
410
411 /* Set the value for this EPIO */
412 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
413 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
414 }
415
bnx2x_set_cfg_pin(struct bnx2x * bp,u32 pin_cfg,u32 val)416 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
417 {
418 if (pin_cfg == PIN_CFG_NA)
419 return;
420 if (pin_cfg >= PIN_CFG_EPIO0) {
421 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
422 } else {
423 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
424 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
425 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
426 }
427 }
428
bnx2x_get_cfg_pin(struct bnx2x * bp,u32 pin_cfg,u32 * val)429 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
430 {
431 if (pin_cfg == PIN_CFG_NA)
432 return -EINVAL;
433 if (pin_cfg >= PIN_CFG_EPIO0) {
434 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
435 } else {
436 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
437 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
438 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
439 }
440 return 0;
441
442 }
443 /******************************************************************/
444 /* ETS section */
445 /******************************************************************/
bnx2x_ets_e2e3a0_disabled(struct link_params * params)446 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
447 {
448 /* ETS disabled configuration*/
449 struct bnx2x *bp = params->bp;
450
451 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
452
453 /* mapping between entry priority to client number (0,1,2 -debug and
454 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
455 * 3bits client num.
456 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
457 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
458 */
459
460 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
461 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
462 * as strict. Bits 0,1,2 - debug and management entries, 3 -
463 * COS0 entry, 4 - COS1 entry.
464 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
465 * bit4 bit3 bit2 bit1 bit0
466 * MCP and debug are strict
467 */
468
469 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
470 /* defines which entries (clients) are subjected to WFQ arbitration */
471 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
472 /* For strict priority entries defines the number of consecutive
473 * slots for the highest priority.
474 */
475 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
476 /* mapping between the CREDIT_WEIGHT registers and actual client
477 * numbers
478 */
479 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
480 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
481 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
482
483 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
484 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
485 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
486 /* ETS mode disable */
487 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
488 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
489 * weight for COS0/COS1.
490 */
491 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
492 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
493 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
494 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
495 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
496 /* Defines the number of consecutive slots for the strict priority */
497 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
498 }
499 /******************************************************************************
500 * Description:
501 * Getting min_w_val will be set according to line speed .
502 *.
503 ******************************************************************************/
bnx2x_ets_get_min_w_val_nig(const struct link_vars * vars)504 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
505 {
506 u32 min_w_val = 0;
507 /* Calculate min_w_val.*/
508 if (vars->link_up) {
509 if (vars->line_speed == SPEED_20000)
510 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
511 else
512 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
513 } else
514 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
515 /* If the link isn't up (static configuration for example ) The
516 * link will be according to 20GBPS.
517 */
518 return min_w_val;
519 }
520 /******************************************************************************
521 * Description:
522 * Getting credit upper bound form min_w_val.
523 *.
524 ******************************************************************************/
bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)525 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
526 {
527 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
528 MAX_PACKET_SIZE);
529 return credit_upper_bound;
530 }
531 /******************************************************************************
532 * Description:
533 * Set credit upper bound for NIG.
534 *.
535 ******************************************************************************/
bnx2x_ets_e3b0_set_credit_upper_bound_nig(const struct link_params * params,const u32 min_w_val)536 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
537 const struct link_params *params,
538 const u32 min_w_val)
539 {
540 struct bnx2x *bp = params->bp;
541 const u8 port = params->port;
542 const u32 credit_upper_bound =
543 bnx2x_ets_get_credit_upper_bound(min_w_val);
544
545 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
546 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
547 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
548 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
550 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
551 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
552 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
553 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
554 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
555 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
556 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
557
558 if (!port) {
559 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
560 credit_upper_bound);
561 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
562 credit_upper_bound);
563 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
564 credit_upper_bound);
565 }
566 }
567 /******************************************************************************
568 * Description:
569 * Will return the NIG ETS registers to init values.Except
570 * credit_upper_bound.
571 * That isn't used in this configuration (No WFQ is enabled) and will be
572 * configured according to spec
573 *.
574 ******************************************************************************/
bnx2x_ets_e3b0_nig_disabled(const struct link_params * params,const struct link_vars * vars)575 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
576 const struct link_vars *vars)
577 {
578 struct bnx2x *bp = params->bp;
579 const u8 port = params->port;
580 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
581 /* Mapping between entry priority to client number (0,1,2 -debug and
582 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
583 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
584 * reset value or init tool
585 */
586 if (port) {
587 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
588 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
589 } else {
590 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
591 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
592 }
593 /* For strict priority entries defines the number of consecutive
594 * slots for the highest priority.
595 */
596 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
597 NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
598 /* Mapping between the CREDIT_WEIGHT registers and actual client
599 * numbers
600 */
601 if (port) {
602 /*Port 1 has 6 COS*/
603 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
604 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
605 } else {
606 /*Port 0 has 9 COS*/
607 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
608 0x43210876);
609 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
610 }
611
612 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
613 * as strict. Bits 0,1,2 - debug and management entries, 3 -
614 * COS0 entry, 4 - COS1 entry.
615 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
616 * bit4 bit3 bit2 bit1 bit0
617 * MCP and debug are strict
618 */
619 if (port)
620 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
621 else
622 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
623 /* defines which entries (clients) are subjected to WFQ arbitration */
624 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
625 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
626
627 /* Please notice the register address are note continuous and a
628 * for here is note appropriate.In 2 port mode port0 only COS0-5
629 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
630 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
631 * are never used for WFQ
632 */
633 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
634 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
635 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
636 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
637 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
638 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
639 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
640 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
641 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
642 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
643 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
644 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
645 if (!port) {
646 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
647 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
648 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
649 }
650
651 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
652 }
653 /******************************************************************************
654 * Description:
655 * Set credit upper bound for PBF.
656 *.
657 ******************************************************************************/
bnx2x_ets_e3b0_set_credit_upper_bound_pbf(const struct link_params * params,const u32 min_w_val)658 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
659 const struct link_params *params,
660 const u32 min_w_val)
661 {
662 struct bnx2x *bp = params->bp;
663 const u32 credit_upper_bound =
664 bnx2x_ets_get_credit_upper_bound(min_w_val);
665 const u8 port = params->port;
666 u32 base_upper_bound = 0;
667 u8 max_cos = 0;
668 u8 i = 0;
669 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
670 * port mode port1 has COS0-2 that can be used for WFQ.
671 */
672 if (!port) {
673 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
674 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
675 } else {
676 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
677 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
678 }
679
680 for (i = 0; i < max_cos; i++)
681 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
682 }
683
684 /******************************************************************************
685 * Description:
686 * Will return the PBF ETS registers to init values.Except
687 * credit_upper_bound.
688 * That isn't used in this configuration (No WFQ is enabled) and will be
689 * configured according to spec
690 *.
691 ******************************************************************************/
bnx2x_ets_e3b0_pbf_disabled(const struct link_params * params)692 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
693 {
694 struct bnx2x *bp = params->bp;
695 const u8 port = params->port;
696 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
697 u8 i = 0;
698 u32 base_weight = 0;
699 u8 max_cos = 0;
700
701 /* Mapping between entry priority to client number 0 - COS0
702 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
703 * TODO_ETS - Should be done by reset value or init tool
704 */
705 if (port)
706 /* 0x688 (|011|0 10|00 1|000) */
707 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
708 else
709 /* (10 1|100 |011|0 10|00 1|000) */
710 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
711
712 /* TODO_ETS - Should be done by reset value or init tool */
713 if (port)
714 /* 0x688 (|011|0 10|00 1|000)*/
715 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
716 else
717 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
718 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
719
720 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
721 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
722
723
724 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
725 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
726
727 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
728 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
729 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
730 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
731 */
732 if (!port) {
733 base_weight = PBF_REG_COS0_WEIGHT_P0;
734 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
735 } else {
736 base_weight = PBF_REG_COS0_WEIGHT_P1;
737 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
738 }
739
740 for (i = 0; i < max_cos; i++)
741 REG_WR(bp, base_weight + (0x4 * i), 0);
742
743 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
744 }
745 /******************************************************************************
746 * Description:
747 * E3B0 disable will return basically the values to init values.
748 *.
749 ******************************************************************************/
bnx2x_ets_e3b0_disabled(const struct link_params * params,const struct link_vars * vars)750 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
751 const struct link_vars *vars)
752 {
753 struct bnx2x *bp = params->bp;
754
755 if (!CHIP_IS_E3B0(bp)) {
756 DP(NETIF_MSG_LINK,
757 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
758 return -EINVAL;
759 }
760
761 bnx2x_ets_e3b0_nig_disabled(params, vars);
762
763 bnx2x_ets_e3b0_pbf_disabled(params);
764
765 return 0;
766 }
767
768 /******************************************************************************
769 * Description:
770 * Disable will return basically the values to init values.
771 *
772 ******************************************************************************/
bnx2x_ets_disabled(struct link_params * params,struct link_vars * vars)773 int bnx2x_ets_disabled(struct link_params *params,
774 struct link_vars *vars)
775 {
776 struct bnx2x *bp = params->bp;
777 int bnx2x_status = 0;
778
779 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
780 bnx2x_ets_e2e3a0_disabled(params);
781 else if (CHIP_IS_E3B0(bp))
782 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
783 else {
784 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
785 return -EINVAL;
786 }
787
788 return bnx2x_status;
789 }
790
791 /******************************************************************************
792 * Description
793 * Set the COS mappimg to SP and BW until this point all the COS are not
794 * set as SP or BW.
795 ******************************************************************************/
bnx2x_ets_e3b0_cli_map(const struct link_params * params,const struct bnx2x_ets_params * ets_params,const u8 cos_sp_bitmap,const u8 cos_bw_bitmap)796 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
797 const struct bnx2x_ets_params *ets_params,
798 const u8 cos_sp_bitmap,
799 const u8 cos_bw_bitmap)
800 {
801 struct bnx2x *bp = params->bp;
802 const u8 port = params->port;
803 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
804 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
805 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
806 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
807
808 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
809 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
810
811 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
812 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
813
814 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
815 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
816 nig_cli_subject2wfq_bitmap);
817
818 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
819 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
820 pbf_cli_subject2wfq_bitmap);
821
822 return 0;
823 }
824
825 /******************************************************************************
826 * Description:
827 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
828 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
829 ******************************************************************************/
bnx2x_ets_e3b0_set_cos_bw(struct bnx2x * bp,const u8 cos_entry,const u32 min_w_val_nig,const u32 min_w_val_pbf,const u16 total_bw,const u8 bw,const u8 port)830 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
831 const u8 cos_entry,
832 const u32 min_w_val_nig,
833 const u32 min_w_val_pbf,
834 const u16 total_bw,
835 const u8 bw,
836 const u8 port)
837 {
838 u32 nig_reg_adress_crd_weight = 0;
839 u32 pbf_reg_adress_crd_weight = 0;
840 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
841 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
842 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
843
844 switch (cos_entry) {
845 case 0:
846 nig_reg_adress_crd_weight =
847 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
848 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
849 pbf_reg_adress_crd_weight = (port) ?
850 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
851 break;
852 case 1:
853 nig_reg_adress_crd_weight = (port) ?
854 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
855 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
856 pbf_reg_adress_crd_weight = (port) ?
857 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
858 break;
859 case 2:
860 nig_reg_adress_crd_weight = (port) ?
861 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
862 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
863
864 pbf_reg_adress_crd_weight = (port) ?
865 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
866 break;
867 case 3:
868 if (port)
869 return -EINVAL;
870 nig_reg_adress_crd_weight =
871 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
872 pbf_reg_adress_crd_weight =
873 PBF_REG_COS3_WEIGHT_P0;
874 break;
875 case 4:
876 if (port)
877 return -EINVAL;
878 nig_reg_adress_crd_weight =
879 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
880 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
881 break;
882 case 5:
883 if (port)
884 return -EINVAL;
885 nig_reg_adress_crd_weight =
886 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
887 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
888 break;
889 }
890
891 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
892
893 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
894
895 return 0;
896 }
897 /******************************************************************************
898 * Description:
899 * Calculate the total BW.A value of 0 isn't legal.
900 *
901 ******************************************************************************/
bnx2x_ets_e3b0_get_total_bw(const struct link_params * params,struct bnx2x_ets_params * ets_params,u16 * total_bw)902 static int bnx2x_ets_e3b0_get_total_bw(
903 const struct link_params *params,
904 struct bnx2x_ets_params *ets_params,
905 u16 *total_bw)
906 {
907 struct bnx2x *bp = params->bp;
908 u8 cos_idx = 0;
909 u8 is_bw_cos_exist = 0;
910
911 *total_bw = 0 ;
912 /* Calculate total BW requested */
913 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
914 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
915 is_bw_cos_exist = 1;
916 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
917 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
918 "was set to 0\n");
919 /* This is to prevent a state when ramrods
920 * can't be sent
921 */
922 ets_params->cos[cos_idx].params.bw_params.bw
923 = 1;
924 }
925 *total_bw +=
926 ets_params->cos[cos_idx].params.bw_params.bw;
927 }
928 }
929
930 /* Check total BW is valid */
931 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
932 if (*total_bw == 0) {
933 DP(NETIF_MSG_LINK,
934 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
935 return -EINVAL;
936 }
937 DP(NETIF_MSG_LINK,
938 "bnx2x_ets_E3B0_config total BW should be 100\n");
939 /* We can handle a case whre the BW isn't 100 this can happen
940 * if the TC are joined.
941 */
942 }
943 return 0;
944 }
945
946 /******************************************************************************
947 * Description:
948 * Invalidate all the sp_pri_to_cos.
949 *
950 ******************************************************************************/
bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 * sp_pri_to_cos)951 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
952 {
953 u8 pri = 0;
954 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
955 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
956 }
957 /******************************************************************************
958 * Description:
959 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
960 * according to sp_pri_to_cos.
961 *
962 ******************************************************************************/
bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params * params,u8 * sp_pri_to_cos,const u8 pri,const u8 cos_entry)963 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
964 u8 *sp_pri_to_cos, const u8 pri,
965 const u8 cos_entry)
966 {
967 struct bnx2x *bp = params->bp;
968 const u8 port = params->port;
969 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
970 DCBX_E3B0_MAX_NUM_COS_PORT0;
971
972 if (pri >= max_num_of_cos) {
973 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
974 "parameter Illegal strict priority\n");
975 return -EINVAL;
976 }
977
978 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
979 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
980 "parameter There can't be two COS's with "
981 "the same strict pri\n");
982 return -EINVAL;
983 }
984
985 sp_pri_to_cos[pri] = cos_entry;
986 return 0;
987
988 }
989
990 /******************************************************************************
991 * Description:
992 * Returns the correct value according to COS and priority in
993 * the sp_pri_cli register.
994 *
995 ******************************************************************************/
bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos,const u8 cos_offset,const u8 pri_set,const u8 pri_offset,const u8 entry_size)996 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
997 const u8 pri_set,
998 const u8 pri_offset,
999 const u8 entry_size)
1000 {
1001 u64 pri_cli_nig = 0;
1002 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
1003 (pri_set + pri_offset));
1004
1005 return pri_cli_nig;
1006 }
1007 /******************************************************************************
1008 * Description:
1009 * Returns the correct value according to COS and priority in the
1010 * sp_pri_cli register for NIG.
1011 *
1012 ******************************************************************************/
bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos,const u8 pri_set)1013 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
1014 {
1015 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1016 const u8 nig_cos_offset = 3;
1017 const u8 nig_pri_offset = 3;
1018
1019 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1020 nig_pri_offset, 4);
1021
1022 }
1023 /******************************************************************************
1024 * Description:
1025 * Returns the correct value according to COS and priority in the
1026 * sp_pri_cli register for PBF.
1027 *
1028 ******************************************************************************/
bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos,const u8 pri_set)1029 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1030 {
1031 const u8 pbf_cos_offset = 0;
1032 const u8 pbf_pri_offset = 0;
1033
1034 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1035 pbf_pri_offset, 3);
1036
1037 }
1038
1039 /******************************************************************************
1040 * Description:
1041 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1042 * according to sp_pri_to_cos.(which COS has higher priority)
1043 *
1044 ******************************************************************************/
bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params * params,u8 * sp_pri_to_cos)1045 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1046 u8 *sp_pri_to_cos)
1047 {
1048 struct bnx2x *bp = params->bp;
1049 u8 i = 0;
1050 const u8 port = params->port;
1051 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1052 u64 pri_cli_nig = 0x210;
1053 u32 pri_cli_pbf = 0x0;
1054 u8 pri_set = 0;
1055 u8 pri_bitmask = 0;
1056 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1057 DCBX_E3B0_MAX_NUM_COS_PORT0;
1058
1059 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1060
1061 /* Set all the strict priority first */
1062 for (i = 0; i < max_num_of_cos; i++) {
1063 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1064 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1065 DP(NETIF_MSG_LINK,
1066 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1067 "invalid cos entry\n");
1068 return -EINVAL;
1069 }
1070
1071 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1072 sp_pri_to_cos[i], pri_set);
1073
1074 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1075 sp_pri_to_cos[i], pri_set);
1076 pri_bitmask = 1 << sp_pri_to_cos[i];
1077 /* COS is used remove it from bitmap.*/
1078 if (!(pri_bitmask & cos_bit_to_set)) {
1079 DP(NETIF_MSG_LINK,
1080 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1081 "invalid There can't be two COS's with"
1082 " the same strict pri\n");
1083 return -EINVAL;
1084 }
1085 cos_bit_to_set &= ~pri_bitmask;
1086 pri_set++;
1087 }
1088 }
1089
1090 /* Set all the Non strict priority i= COS*/
1091 for (i = 0; i < max_num_of_cos; i++) {
1092 pri_bitmask = 1 << i;
1093 /* Check if COS was already used for SP */
1094 if (pri_bitmask & cos_bit_to_set) {
1095 /* COS wasn't used for SP */
1096 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1097 i, pri_set);
1098
1099 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1100 i, pri_set);
1101 /* COS is used remove it from bitmap.*/
1102 cos_bit_to_set &= ~pri_bitmask;
1103 pri_set++;
1104 }
1105 }
1106
1107 if (pri_set != max_num_of_cos) {
1108 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1109 "entries were set\n");
1110 return -EINVAL;
1111 }
1112
1113 if (port) {
1114 /* Only 6 usable clients*/
1115 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1116 (u32)pri_cli_nig);
1117
1118 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1119 } else {
1120 /* Only 9 usable clients*/
1121 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1122 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1123
1124 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1125 pri_cli_nig_lsb);
1126 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1127 pri_cli_nig_msb);
1128
1129 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1130 }
1131 return 0;
1132 }
1133
1134 /******************************************************************************
1135 * Description:
1136 * Configure the COS to ETS according to BW and SP settings.
1137 ******************************************************************************/
bnx2x_ets_e3b0_config(const struct link_params * params,const struct link_vars * vars,struct bnx2x_ets_params * ets_params)1138 int bnx2x_ets_e3b0_config(const struct link_params *params,
1139 const struct link_vars *vars,
1140 struct bnx2x_ets_params *ets_params)
1141 {
1142 struct bnx2x *bp = params->bp;
1143 int bnx2x_status = 0;
1144 const u8 port = params->port;
1145 u16 total_bw = 0;
1146 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1147 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1148 u8 cos_bw_bitmap = 0;
1149 u8 cos_sp_bitmap = 0;
1150 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1151 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1152 DCBX_E3B0_MAX_NUM_COS_PORT0;
1153 u8 cos_entry = 0;
1154
1155 if (!CHIP_IS_E3B0(bp)) {
1156 DP(NETIF_MSG_LINK,
1157 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1158 return -EINVAL;
1159 }
1160
1161 if ((ets_params->num_of_cos > max_num_of_cos)) {
1162 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1163 "isn't supported\n");
1164 return -EINVAL;
1165 }
1166
1167 /* Prepare sp strict priority parameters*/
1168 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1169
1170 /* Prepare BW parameters*/
1171 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1172 &total_bw);
1173 if (bnx2x_status) {
1174 DP(NETIF_MSG_LINK,
1175 "bnx2x_ets_E3B0_config get_total_bw failed\n");
1176 return -EINVAL;
1177 }
1178
1179 /* Upper bound is set according to current link speed (min_w_val
1180 * should be the same for upper bound and COS credit val).
1181 */
1182 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1183 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1184
1185
1186 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1187 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1188 cos_bw_bitmap |= (1 << cos_entry);
1189 /* The function also sets the BW in HW(not the mappin
1190 * yet)
1191 */
1192 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1193 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1194 total_bw,
1195 ets_params->cos[cos_entry].params.bw_params.bw,
1196 port);
1197 } else if (bnx2x_cos_state_strict ==
1198 ets_params->cos[cos_entry].state){
1199 cos_sp_bitmap |= (1 << cos_entry);
1200
1201 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1202 params,
1203 sp_pri_to_cos,
1204 ets_params->cos[cos_entry].params.sp_params.pri,
1205 cos_entry);
1206
1207 } else {
1208 DP(NETIF_MSG_LINK,
1209 "bnx2x_ets_e3b0_config cos state not valid\n");
1210 return -EINVAL;
1211 }
1212 if (bnx2x_status) {
1213 DP(NETIF_MSG_LINK,
1214 "bnx2x_ets_e3b0_config set cos bw failed\n");
1215 return bnx2x_status;
1216 }
1217 }
1218
1219 /* Set SP register (which COS has higher priority) */
1220 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1221 sp_pri_to_cos);
1222
1223 if (bnx2x_status) {
1224 DP(NETIF_MSG_LINK,
1225 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1226 return bnx2x_status;
1227 }
1228
1229 /* Set client mapping of BW and strict */
1230 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1231 cos_sp_bitmap,
1232 cos_bw_bitmap);
1233
1234 if (bnx2x_status) {
1235 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1236 return bnx2x_status;
1237 }
1238 return 0;
1239 }
bnx2x_ets_bw_limit_common(const struct link_params * params)1240 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1241 {
1242 /* ETS disabled configuration */
1243 struct bnx2x *bp = params->bp;
1244 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1245 /* Defines which entries (clients) are subjected to WFQ arbitration
1246 * COS0 0x8
1247 * COS1 0x10
1248 */
1249 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1250 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1251 * client numbers (WEIGHT_0 does not actually have to represent
1252 * client 0)
1253 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1254 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1255 */
1256 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1257
1258 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1259 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1260 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1261 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1262
1263 /* ETS mode enabled*/
1264 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1265
1266 /* Defines the number of consecutive slots for the strict priority */
1267 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1268 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1269 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1270 * entry, 4 - COS1 entry.
1271 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1272 * bit4 bit3 bit2 bit1 bit0
1273 * MCP and debug are strict
1274 */
1275 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1276
1277 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1278 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1279 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1280 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1281 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1282 }
1283
bnx2x_ets_bw_limit(const struct link_params * params,const u32 cos0_bw,const u32 cos1_bw)1284 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1285 const u32 cos1_bw)
1286 {
1287 /* ETS disabled configuration*/
1288 struct bnx2x *bp = params->bp;
1289 const u32 total_bw = cos0_bw + cos1_bw;
1290 u32 cos0_credit_weight = 0;
1291 u32 cos1_credit_weight = 0;
1292
1293 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1294
1295 if ((!total_bw) ||
1296 (!cos0_bw) ||
1297 (!cos1_bw)) {
1298 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1299 return;
1300 }
1301
1302 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1303 total_bw;
1304 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1305 total_bw;
1306
1307 bnx2x_ets_bw_limit_common(params);
1308
1309 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1310 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1311
1312 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1313 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1314 }
1315
bnx2x_ets_strict(const struct link_params * params,const u8 strict_cos)1316 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1317 {
1318 /* ETS disabled configuration*/
1319 struct bnx2x *bp = params->bp;
1320 u32 val = 0;
1321
1322 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1323 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1324 * as strict. Bits 0,1,2 - debug and management entries,
1325 * 3 - COS0 entry, 4 - COS1 entry.
1326 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1327 * bit4 bit3 bit2 bit1 bit0
1328 * MCP and debug are strict
1329 */
1330 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1331 /* For strict priority entries defines the number of consecutive slots
1332 * for the highest priority.
1333 */
1334 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1335 /* ETS mode disable */
1336 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1337 /* Defines the number of consecutive slots for the strict priority */
1338 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1339
1340 /* Defines the number of consecutive slots for the strict priority */
1341 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1342
1343 /* Mapping between entry priority to client number (0,1,2 -debug and
1344 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1345 * 3bits client num.
1346 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1347 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1348 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1349 */
1350 val = (!strict_cos) ? 0x2318 : 0x22E0;
1351 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1352
1353 return 0;
1354 }
1355
1356 /******************************************************************/
1357 /* PFC section */
1358 /******************************************************************/
bnx2x_update_pfc_xmac(struct link_params * params,struct link_vars * vars,u8 is_lb)1359 static void bnx2x_update_pfc_xmac(struct link_params *params,
1360 struct link_vars *vars,
1361 u8 is_lb)
1362 {
1363 struct bnx2x *bp = params->bp;
1364 u32 xmac_base;
1365 u32 pause_val, pfc0_val, pfc1_val;
1366
1367 /* XMAC base adrr */
1368 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1369
1370 /* Initialize pause and pfc registers */
1371 pause_val = 0x18000;
1372 pfc0_val = 0xFFFF8000;
1373 pfc1_val = 0x2;
1374
1375 /* No PFC support */
1376 if (!(params->feature_config_flags &
1377 FEATURE_CONFIG_PFC_ENABLED)) {
1378
1379 /* RX flow control - Process pause frame in receive direction
1380 */
1381 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1382 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1383
1384 /* TX flow control - Send pause packet when buffer is full */
1385 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1386 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1387 } else {/* PFC support */
1388 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1389 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1390 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1391 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1392 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1393 /* Write pause and PFC registers */
1394 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1395 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1396 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1397 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1398
1399 }
1400
1401 /* Write pause and PFC registers */
1402 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1403 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1404 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1405
1406
1407 /* Set MAC address for source TX Pause/PFC frames */
1408 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1409 ((params->mac_addr[2] << 24) |
1410 (params->mac_addr[3] << 16) |
1411 (params->mac_addr[4] << 8) |
1412 (params->mac_addr[5])));
1413 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1414 ((params->mac_addr[0] << 8) |
1415 (params->mac_addr[1])));
1416
1417 udelay(30);
1418 }
1419
1420 /******************************************************************/
1421 /* MAC/PBF section */
1422 /******************************************************************/
bnx2x_set_mdio_clk(struct bnx2x * bp,u32 chip_id,u32 emac_base)1423 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1424 u32 emac_base)
1425 {
1426 u32 new_mode, cur_mode;
1427 u32 clc_cnt;
1428 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1429 * (a value of 49==0x31) and make sure that the AUTO poll is off
1430 */
1431 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1432
1433 if (USES_WARPCORE(bp))
1434 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1435 else
1436 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1437
1438 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1439 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1440 return;
1441
1442 new_mode = cur_mode &
1443 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1444 new_mode |= clc_cnt;
1445 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1446
1447 DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1448 cur_mode, new_mode);
1449 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1450 udelay(40);
1451 }
1452
bnx2x_set_mdio_emac_per_phy(struct bnx2x * bp,struct link_params * params)1453 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1454 struct link_params *params)
1455 {
1456 u8 phy_index;
1457 /* Set mdio clock per phy */
1458 for (phy_index = INT_PHY; phy_index < params->num_phys;
1459 phy_index++)
1460 bnx2x_set_mdio_clk(bp, params->chip_id,
1461 params->phy[phy_index].mdio_ctrl);
1462 }
1463
bnx2x_is_4_port_mode(struct bnx2x * bp)1464 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1465 {
1466 u32 port4mode_ovwr_val;
1467 /* Check 4-port override enabled */
1468 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1469 if (port4mode_ovwr_val & (1<<0)) {
1470 /* Return 4-port mode override value */
1471 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1472 }
1473 /* Return 4-port mode from input pin */
1474 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1475 }
1476
bnx2x_emac_init(struct link_params * params,struct link_vars * vars)1477 static void bnx2x_emac_init(struct link_params *params,
1478 struct link_vars *vars)
1479 {
1480 /* reset and unreset the emac core */
1481 struct bnx2x *bp = params->bp;
1482 u8 port = params->port;
1483 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1484 u32 val;
1485 u16 timeout;
1486
1487 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1488 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1489 udelay(5);
1490 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1491 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1492
1493 /* init emac - use read-modify-write */
1494 /* self clear reset */
1495 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1496 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1497
1498 timeout = 200;
1499 do {
1500 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1501 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1502 if (!timeout) {
1503 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1504 return;
1505 }
1506 timeout--;
1507 } while (val & EMAC_MODE_RESET);
1508
1509 bnx2x_set_mdio_emac_per_phy(bp, params);
1510 /* Set mac address */
1511 val = ((params->mac_addr[0] << 8) |
1512 params->mac_addr[1]);
1513 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1514
1515 val = ((params->mac_addr[2] << 24) |
1516 (params->mac_addr[3] << 16) |
1517 (params->mac_addr[4] << 8) |
1518 params->mac_addr[5]);
1519 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1520 }
1521
bnx2x_set_xumac_nig(struct link_params * params,u16 tx_pause_en,u8 enable)1522 static void bnx2x_set_xumac_nig(struct link_params *params,
1523 u16 tx_pause_en,
1524 u8 enable)
1525 {
1526 struct bnx2x *bp = params->bp;
1527
1528 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1529 enable);
1530 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1531 enable);
1532 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1533 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1534 }
1535
bnx2x_set_umac_rxtx(struct link_params * params,u8 en)1536 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1537 {
1538 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1539 u32 val;
1540 struct bnx2x *bp = params->bp;
1541 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1542 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1543 return;
1544 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1545 if (en)
1546 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1547 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1548 else
1549 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1550 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1551 /* Disable RX and TX */
1552 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1553 }
1554
bnx2x_umac_enable(struct link_params * params,struct link_vars * vars,u8 lb)1555 static void bnx2x_umac_enable(struct link_params *params,
1556 struct link_vars *vars, u8 lb)
1557 {
1558 u32 val;
1559 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1560 struct bnx2x *bp = params->bp;
1561 /* Reset UMAC */
1562 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1563 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1564 usleep_range(1000, 2000);
1565
1566 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1567 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1568
1569 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1570
1571 /* This register opens the gate for the UMAC despite its name */
1572 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1573
1574 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1575 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1576 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1577 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1578 switch (vars->line_speed) {
1579 case SPEED_10:
1580 val |= (0<<2);
1581 break;
1582 case SPEED_100:
1583 val |= (1<<2);
1584 break;
1585 case SPEED_1000:
1586 val |= (2<<2);
1587 break;
1588 case SPEED_2500:
1589 val |= (3<<2);
1590 break;
1591 default:
1592 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1593 vars->line_speed);
1594 break;
1595 }
1596 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1597 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1598
1599 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1600 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1601
1602 if (vars->duplex == DUPLEX_HALF)
1603 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1604
1605 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1606 udelay(50);
1607
1608 /* Configure UMAC for EEE */
1609 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1610 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1611 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1612 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1613 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1614 } else {
1615 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1616 }
1617
1618 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1619 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1620 ((params->mac_addr[2] << 24) |
1621 (params->mac_addr[3] << 16) |
1622 (params->mac_addr[4] << 8) |
1623 (params->mac_addr[5])));
1624 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1625 ((params->mac_addr[0] << 8) |
1626 (params->mac_addr[1])));
1627
1628 /* Enable RX and TX */
1629 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1630 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1631 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1632 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1633 udelay(50);
1634
1635 /* Remove SW Reset */
1636 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1637
1638 /* Check loopback mode */
1639 if (lb)
1640 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1641 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1642
1643 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1644 * length used by the MAC receive logic to check frames.
1645 */
1646 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1647 bnx2x_set_xumac_nig(params,
1648 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1649 vars->mac_type = MAC_TYPE_UMAC;
1650
1651 }
1652
1653 /* Define the XMAC mode */
bnx2x_xmac_init(struct link_params * params,u32 max_speed)1654 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1655 {
1656 struct bnx2x *bp = params->bp;
1657 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1658
1659 /* In 4-port mode, need to set the mode only once, so if XMAC is
1660 * already out of reset, it means the mode has already been set,
1661 * and it must not* reset the XMAC again, since it controls both
1662 * ports of the path
1663 */
1664
1665 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1666 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1667 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1668 is_port4mode &&
1669 (REG_RD(bp, MISC_REG_RESET_REG_2) &
1670 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1671 DP(NETIF_MSG_LINK,
1672 "XMAC already out of reset in 4-port mode\n");
1673 return;
1674 }
1675
1676 /* Hard reset */
1677 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1678 MISC_REGISTERS_RESET_REG_2_XMAC);
1679 usleep_range(1000, 2000);
1680
1681 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1682 MISC_REGISTERS_RESET_REG_2_XMAC);
1683 if (is_port4mode) {
1684 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1685
1686 /* Set the number of ports on the system side to up to 2 */
1687 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1688
1689 /* Set the number of ports on the Warp Core to 10G */
1690 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1691 } else {
1692 /* Set the number of ports on the system side to 1 */
1693 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1694 if (max_speed == SPEED_10000) {
1695 DP(NETIF_MSG_LINK,
1696 "Init XMAC to 10G x 1 port per path\n");
1697 /* Set the number of ports on the Warp Core to 10G */
1698 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1699 } else {
1700 DP(NETIF_MSG_LINK,
1701 "Init XMAC to 20G x 2 ports per path\n");
1702 /* Set the number of ports on the Warp Core to 20G */
1703 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1704 }
1705 }
1706 /* Soft reset */
1707 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1708 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1709 usleep_range(1000, 2000);
1710
1711 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1712 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1713
1714 }
1715
bnx2x_set_xmac_rxtx(struct link_params * params,u8 en)1716 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1717 {
1718 u8 port = params->port;
1719 struct bnx2x *bp = params->bp;
1720 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1721 u32 val;
1722
1723 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1724 MISC_REGISTERS_RESET_REG_2_XMAC) {
1725 /* Send an indication to change the state in the NIG back to XON
1726 * Clearing this bit enables the next set of this bit to get
1727 * rising edge
1728 */
1729 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1730 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1731 (pfc_ctrl & ~(1<<1)));
1732 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1733 (pfc_ctrl | (1<<1)));
1734 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1735 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1736 if (en)
1737 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1738 else
1739 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1740 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1741 }
1742 }
1743
bnx2x_xmac_enable(struct link_params * params,struct link_vars * vars,u8 lb)1744 static int bnx2x_xmac_enable(struct link_params *params,
1745 struct link_vars *vars, u8 lb)
1746 {
1747 u32 val, xmac_base;
1748 struct bnx2x *bp = params->bp;
1749 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1750
1751 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1752
1753 bnx2x_xmac_init(params, vars->line_speed);
1754
1755 /* This register determines on which events the MAC will assert
1756 * error on the i/f to the NIG along w/ EOP.
1757 */
1758
1759 /* This register tells the NIG whether to send traffic to UMAC
1760 * or XMAC
1761 */
1762 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1763
1764 /* When XMAC is in XLGMII mode, disable sending idles for fault
1765 * detection.
1766 */
1767 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1768 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1769 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1770 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1771 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1772 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1773 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1774 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1775 }
1776 /* Set Max packet size */
1777 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1778
1779 /* CRC append for Tx packets */
1780 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1781
1782 /* update PFC */
1783 bnx2x_update_pfc_xmac(params, vars, 0);
1784
1785 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1786 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1787 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1788 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1789 } else {
1790 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1791 }
1792
1793 /* Enable TX and RX */
1794 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1795
1796 /* Set MAC in XLGMII mode for dual-mode */
1797 if ((vars->line_speed == SPEED_20000) &&
1798 (params->phy[INT_PHY].supported &
1799 SUPPORTED_20000baseKR2_Full))
1800 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1801
1802 /* Check loopback mode */
1803 if (lb)
1804 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1805 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1806 bnx2x_set_xumac_nig(params,
1807 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1808
1809 vars->mac_type = MAC_TYPE_XMAC;
1810
1811 return 0;
1812 }
1813
bnx2x_emac_enable(struct link_params * params,struct link_vars * vars,u8 lb)1814 static int bnx2x_emac_enable(struct link_params *params,
1815 struct link_vars *vars, u8 lb)
1816 {
1817 struct bnx2x *bp = params->bp;
1818 u8 port = params->port;
1819 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1820 u32 val;
1821
1822 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1823
1824 /* Disable BMAC */
1825 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1826 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1827
1828 /* enable emac and not bmac */
1829 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1830
1831 /* ASIC */
1832 if (vars->phy_flags & PHY_XGXS_FLAG) {
1833 u32 ser_lane = ((params->lane_config &
1834 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1835 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1836
1837 DP(NETIF_MSG_LINK, "XGXS\n");
1838 /* select the master lanes (out of 0-3) */
1839 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1840 /* select XGXS */
1841 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1842
1843 } else { /* SerDes */
1844 DP(NETIF_MSG_LINK, "SerDes\n");
1845 /* select SerDes */
1846 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1847 }
1848
1849 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1850 EMAC_RX_MODE_RESET);
1851 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1852 EMAC_TX_MODE_RESET);
1853
1854 /* pause enable/disable */
1855 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1856 EMAC_RX_MODE_FLOW_EN);
1857
1858 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1859 (EMAC_TX_MODE_EXT_PAUSE_EN |
1860 EMAC_TX_MODE_FLOW_EN));
1861 if (!(params->feature_config_flags &
1862 FEATURE_CONFIG_PFC_ENABLED)) {
1863 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1864 bnx2x_bits_en(bp, emac_base +
1865 EMAC_REG_EMAC_RX_MODE,
1866 EMAC_RX_MODE_FLOW_EN);
1867
1868 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1869 bnx2x_bits_en(bp, emac_base +
1870 EMAC_REG_EMAC_TX_MODE,
1871 (EMAC_TX_MODE_EXT_PAUSE_EN |
1872 EMAC_TX_MODE_FLOW_EN));
1873 } else
1874 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1875 EMAC_TX_MODE_FLOW_EN);
1876
1877 /* KEEP_VLAN_TAG, promiscuous */
1878 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1879 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1880
1881 /* Setting this bit causes MAC control frames (except for pause
1882 * frames) to be passed on for processing. This setting has no
1883 * affect on the operation of the pause frames. This bit effects
1884 * all packets regardless of RX Parser packet sorting logic.
1885 * Turn the PFC off to make sure we are in Xon state before
1886 * enabling it.
1887 */
1888 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1889 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1890 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1891 /* Enable PFC again */
1892 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1893 EMAC_REG_RX_PFC_MODE_RX_EN |
1894 EMAC_REG_RX_PFC_MODE_TX_EN |
1895 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1896
1897 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1898 ((0x0101 <<
1899 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1900 (0x00ff <<
1901 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1902 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1903 }
1904 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1905
1906 /* Set Loopback */
1907 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1908 if (lb)
1909 val |= 0x810;
1910 else
1911 val &= ~0x810;
1912 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1913
1914 /* Enable emac */
1915 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1916
1917 /* Enable emac for jumbo packets */
1918 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1919 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1920 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1921
1922 /* Strip CRC */
1923 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1924
1925 /* Disable the NIG in/out to the bmac */
1926 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1927 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1928 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1929
1930 /* Enable the NIG in/out to the emac */
1931 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1932 val = 0;
1933 if ((params->feature_config_flags &
1934 FEATURE_CONFIG_PFC_ENABLED) ||
1935 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1936 val = 1;
1937
1938 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1939 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1940
1941 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1942
1943 vars->mac_type = MAC_TYPE_EMAC;
1944 return 0;
1945 }
1946
bnx2x_update_pfc_bmac1(struct link_params * params,struct link_vars * vars)1947 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1948 struct link_vars *vars)
1949 {
1950 u32 wb_data[2];
1951 struct bnx2x *bp = params->bp;
1952 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1953 NIG_REG_INGRESS_BMAC0_MEM;
1954
1955 u32 val = 0x14;
1956 if ((!(params->feature_config_flags &
1957 FEATURE_CONFIG_PFC_ENABLED)) &&
1958 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1959 /* Enable BigMAC to react on received Pause packets */
1960 val |= (1<<5);
1961 wb_data[0] = val;
1962 wb_data[1] = 0;
1963 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1964
1965 /* TX control */
1966 val = 0xc0;
1967 if (!(params->feature_config_flags &
1968 FEATURE_CONFIG_PFC_ENABLED) &&
1969 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1970 val |= 0x800000;
1971 wb_data[0] = val;
1972 wb_data[1] = 0;
1973 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1974 }
1975
bnx2x_update_pfc_bmac2(struct link_params * params,struct link_vars * vars,u8 is_lb)1976 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1977 struct link_vars *vars,
1978 u8 is_lb)
1979 {
1980 /* Set rx control: Strip CRC and enable BigMAC to relay
1981 * control packets to the system as well
1982 */
1983 u32 wb_data[2];
1984 struct bnx2x *bp = params->bp;
1985 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1986 NIG_REG_INGRESS_BMAC0_MEM;
1987 u32 val = 0x14;
1988
1989 if ((!(params->feature_config_flags &
1990 FEATURE_CONFIG_PFC_ENABLED)) &&
1991 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1992 /* Enable BigMAC to react on received Pause packets */
1993 val |= (1<<5);
1994 wb_data[0] = val;
1995 wb_data[1] = 0;
1996 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1997 udelay(30);
1998
1999 /* Tx control */
2000 val = 0xc0;
2001 if (!(params->feature_config_flags &
2002 FEATURE_CONFIG_PFC_ENABLED) &&
2003 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2004 val |= 0x800000;
2005 wb_data[0] = val;
2006 wb_data[1] = 0;
2007 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2008
2009 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2010 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2011 /* Enable PFC RX & TX & STATS and set 8 COS */
2012 wb_data[0] = 0x0;
2013 wb_data[0] |= (1<<0); /* RX */
2014 wb_data[0] |= (1<<1); /* TX */
2015 wb_data[0] |= (1<<2); /* Force initial Xon */
2016 wb_data[0] |= (1<<3); /* 8 cos */
2017 wb_data[0] |= (1<<5); /* STATS */
2018 wb_data[1] = 0;
2019 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2020 wb_data, 2);
2021 /* Clear the force Xon */
2022 wb_data[0] &= ~(1<<2);
2023 } else {
2024 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2025 /* Disable PFC RX & TX & STATS and set 8 COS */
2026 wb_data[0] = 0x8;
2027 wb_data[1] = 0;
2028 }
2029
2030 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2031
2032 /* Set Time (based unit is 512 bit time) between automatic
2033 * re-sending of PP packets amd enable automatic re-send of
2034 * Per-Priroity Packet as long as pp_gen is asserted and
2035 * pp_disable is low.
2036 */
2037 val = 0x8000;
2038 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2039 val |= (1<<16); /* enable automatic re-send */
2040
2041 wb_data[0] = val;
2042 wb_data[1] = 0;
2043 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2044 wb_data, 2);
2045
2046 /* mac control */
2047 val = 0x3; /* Enable RX and TX */
2048 if (is_lb) {
2049 val |= 0x4; /* Local loopback */
2050 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2051 }
2052 /* When PFC enabled, Pass pause frames towards the NIG. */
2053 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2054 val |= ((1<<6)|(1<<5));
2055
2056 wb_data[0] = val;
2057 wb_data[1] = 0;
2058 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2059 }
2060
2061 /******************************************************************************
2062 * Description:
2063 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2064 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2065 ******************************************************************************/
bnx2x_pfc_nig_rx_priority_mask(struct bnx2x * bp,u8 cos_entry,u32 priority_mask,u8 port)2066 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2067 u8 cos_entry,
2068 u32 priority_mask, u8 port)
2069 {
2070 u32 nig_reg_rx_priority_mask_add = 0;
2071
2072 switch (cos_entry) {
2073 case 0:
2074 nig_reg_rx_priority_mask_add = (port) ?
2075 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2076 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2077 break;
2078 case 1:
2079 nig_reg_rx_priority_mask_add = (port) ?
2080 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2081 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2082 break;
2083 case 2:
2084 nig_reg_rx_priority_mask_add = (port) ?
2085 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2086 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2087 break;
2088 case 3:
2089 if (port)
2090 return -EINVAL;
2091 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2092 break;
2093 case 4:
2094 if (port)
2095 return -EINVAL;
2096 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2097 break;
2098 case 5:
2099 if (port)
2100 return -EINVAL;
2101 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2102 break;
2103 }
2104
2105 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2106
2107 return 0;
2108 }
bnx2x_update_mng(struct link_params * params,u32 link_status)2109 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2110 {
2111 struct bnx2x *bp = params->bp;
2112
2113 REG_WR(bp, params->shmem_base +
2114 offsetof(struct shmem_region,
2115 port_mb[params->port].link_status), link_status);
2116 }
2117
bnx2x_update_link_attr(struct link_params * params,u32 link_attr)2118 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2119 {
2120 struct bnx2x *bp = params->bp;
2121
2122 if (SHMEM2_HAS(bp, link_attr_sync))
2123 REG_WR(bp, params->shmem2_base +
2124 offsetof(struct shmem2_region,
2125 link_attr_sync[params->port]), link_attr);
2126 }
2127
bnx2x_update_pfc_nig(struct link_params * params,struct link_vars * vars,struct bnx2x_nig_brb_pfc_port_params * nig_params)2128 static void bnx2x_update_pfc_nig(struct link_params *params,
2129 struct link_vars *vars,
2130 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2131 {
2132 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2133 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2134 u32 pkt_priority_to_cos = 0;
2135 struct bnx2x *bp = params->bp;
2136 u8 port = params->port;
2137
2138 int set_pfc = params->feature_config_flags &
2139 FEATURE_CONFIG_PFC_ENABLED;
2140 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2141
2142 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2143 * MAC control frames (that are not pause packets)
2144 * will be forwarded to the XCM.
2145 */
2146 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2147 NIG_REG_LLH0_XCM_MASK);
2148 /* NIG params will override non PFC params, since it's possible to
2149 * do transition from PFC to SAFC
2150 */
2151 if (set_pfc) {
2152 pause_enable = 0;
2153 llfc_out_en = 0;
2154 llfc_enable = 0;
2155 if (CHIP_IS_E3(bp))
2156 ppp_enable = 0;
2157 else
2158 ppp_enable = 1;
2159 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2160 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2161 xcm_out_en = 0;
2162 hwpfc_enable = 1;
2163 } else {
2164 if (nig_params) {
2165 llfc_out_en = nig_params->llfc_out_en;
2166 llfc_enable = nig_params->llfc_enable;
2167 pause_enable = nig_params->pause_enable;
2168 } else /* Default non PFC mode - PAUSE */
2169 pause_enable = 1;
2170
2171 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2172 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2173 xcm_out_en = 1;
2174 }
2175
2176 if (CHIP_IS_E3(bp))
2177 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2178 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2179 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2180 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2181 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2182 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2183 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2184 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2185
2186 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2187 NIG_REG_PPP_ENABLE_0, ppp_enable);
2188
2189 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2190 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2191
2192 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2193 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2194
2195 /* Output enable for RX_XCM # IF */
2196 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2197 NIG_REG_XCM0_OUT_EN, xcm_out_en);
2198
2199 /* HW PFC TX enable */
2200 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2201 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2202
2203 if (nig_params) {
2204 u8 i = 0;
2205 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2206
2207 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2208 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2209 nig_params->rx_cos_priority_mask[i], port);
2210
2211 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2212 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2213 nig_params->llfc_high_priority_classes);
2214
2215 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2216 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2217 nig_params->llfc_low_priority_classes);
2218 }
2219 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2220 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2221 pkt_priority_to_cos);
2222 }
2223
bnx2x_update_pfc(struct link_params * params,struct link_vars * vars,struct bnx2x_nig_brb_pfc_port_params * pfc_params)2224 int bnx2x_update_pfc(struct link_params *params,
2225 struct link_vars *vars,
2226 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2227 {
2228 /* The PFC and pause are orthogonal to one another, meaning when
2229 * PFC is enabled, the pause are disabled, and when PFC is
2230 * disabled, pause are set according to the pause result.
2231 */
2232 u32 val;
2233 struct bnx2x *bp = params->bp;
2234 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2235
2236 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2237 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2238 else
2239 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2240
2241 bnx2x_update_mng(params, vars->link_status);
2242
2243 /* Update NIG params */
2244 bnx2x_update_pfc_nig(params, vars, pfc_params);
2245
2246 if (!vars->link_up)
2247 return 0;
2248
2249 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2250
2251 if (CHIP_IS_E3(bp)) {
2252 if (vars->mac_type == MAC_TYPE_XMAC)
2253 bnx2x_update_pfc_xmac(params, vars, 0);
2254 } else {
2255 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2256 if ((val &
2257 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2258 == 0) {
2259 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2260 bnx2x_emac_enable(params, vars, 0);
2261 return 0;
2262 }
2263 if (CHIP_IS_E2(bp))
2264 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2265 else
2266 bnx2x_update_pfc_bmac1(params, vars);
2267
2268 val = 0;
2269 if ((params->feature_config_flags &
2270 FEATURE_CONFIG_PFC_ENABLED) ||
2271 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2272 val = 1;
2273 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2274 }
2275 return 0;
2276 }
2277
bnx2x_bmac1_enable(struct link_params * params,struct link_vars * vars,u8 is_lb)2278 static int bnx2x_bmac1_enable(struct link_params *params,
2279 struct link_vars *vars,
2280 u8 is_lb)
2281 {
2282 struct bnx2x *bp = params->bp;
2283 u8 port = params->port;
2284 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2285 NIG_REG_INGRESS_BMAC0_MEM;
2286 u32 wb_data[2];
2287 u32 val;
2288
2289 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2290
2291 /* XGXS control */
2292 wb_data[0] = 0x3c;
2293 wb_data[1] = 0;
2294 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2295 wb_data, 2);
2296
2297 /* TX MAC SA */
2298 wb_data[0] = ((params->mac_addr[2] << 24) |
2299 (params->mac_addr[3] << 16) |
2300 (params->mac_addr[4] << 8) |
2301 params->mac_addr[5]);
2302 wb_data[1] = ((params->mac_addr[0] << 8) |
2303 params->mac_addr[1]);
2304 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2305
2306 /* MAC control */
2307 val = 0x3;
2308 if (is_lb) {
2309 val |= 0x4;
2310 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2311 }
2312 wb_data[0] = val;
2313 wb_data[1] = 0;
2314 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2315
2316 /* Set rx mtu */
2317 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2318 wb_data[1] = 0;
2319 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2320
2321 bnx2x_update_pfc_bmac1(params, vars);
2322
2323 /* Set tx mtu */
2324 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2325 wb_data[1] = 0;
2326 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2327
2328 /* Set cnt max size */
2329 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2330 wb_data[1] = 0;
2331 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2332
2333 /* Configure SAFC */
2334 wb_data[0] = 0x1000200;
2335 wb_data[1] = 0;
2336 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2337 wb_data, 2);
2338
2339 return 0;
2340 }
2341
bnx2x_bmac2_enable(struct link_params * params,struct link_vars * vars,u8 is_lb)2342 static int bnx2x_bmac2_enable(struct link_params *params,
2343 struct link_vars *vars,
2344 u8 is_lb)
2345 {
2346 struct bnx2x *bp = params->bp;
2347 u8 port = params->port;
2348 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2349 NIG_REG_INGRESS_BMAC0_MEM;
2350 u32 wb_data[2];
2351
2352 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2353
2354 wb_data[0] = 0;
2355 wb_data[1] = 0;
2356 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2357 udelay(30);
2358
2359 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2360 wb_data[0] = 0x3c;
2361 wb_data[1] = 0;
2362 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2363 wb_data, 2);
2364
2365 udelay(30);
2366
2367 /* TX MAC SA */
2368 wb_data[0] = ((params->mac_addr[2] << 24) |
2369 (params->mac_addr[3] << 16) |
2370 (params->mac_addr[4] << 8) |
2371 params->mac_addr[5]);
2372 wb_data[1] = ((params->mac_addr[0] << 8) |
2373 params->mac_addr[1]);
2374 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2375 wb_data, 2);
2376
2377 udelay(30);
2378
2379 /* Configure SAFC */
2380 wb_data[0] = 0x1000200;
2381 wb_data[1] = 0;
2382 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2383 wb_data, 2);
2384 udelay(30);
2385
2386 /* Set RX MTU */
2387 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2388 wb_data[1] = 0;
2389 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2390 udelay(30);
2391
2392 /* Set TX MTU */
2393 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2394 wb_data[1] = 0;
2395 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2396 udelay(30);
2397 /* Set cnt max size */
2398 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2399 wb_data[1] = 0;
2400 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2401 udelay(30);
2402 bnx2x_update_pfc_bmac2(params, vars, is_lb);
2403
2404 return 0;
2405 }
2406
bnx2x_bmac_enable(struct link_params * params,struct link_vars * vars,u8 is_lb,u8 reset_bmac)2407 static int bnx2x_bmac_enable(struct link_params *params,
2408 struct link_vars *vars,
2409 u8 is_lb, u8 reset_bmac)
2410 {
2411 int rc = 0;
2412 u8 port = params->port;
2413 struct bnx2x *bp = params->bp;
2414 u32 val;
2415 /* Reset and unreset the BigMac */
2416 if (reset_bmac) {
2417 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2418 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2419 usleep_range(1000, 2000);
2420 }
2421
2422 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2423 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2424
2425 /* Enable access for bmac registers */
2426 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2427
2428 /* Enable BMAC according to BMAC type*/
2429 if (CHIP_IS_E2(bp))
2430 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2431 else
2432 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2433 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2434 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2435 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2436 val = 0;
2437 if ((params->feature_config_flags &
2438 FEATURE_CONFIG_PFC_ENABLED) ||
2439 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2440 val = 1;
2441 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2442 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2443 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2444 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2445 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2446 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2447
2448 vars->mac_type = MAC_TYPE_BMAC;
2449 return rc;
2450 }
2451
bnx2x_set_bmac_rx(struct bnx2x * bp,u32 chip_id,u8 port,u8 en)2452 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2453 {
2454 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2455 NIG_REG_INGRESS_BMAC0_MEM;
2456 u32 wb_data[2];
2457 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2458
2459 if (CHIP_IS_E2(bp))
2460 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2461 else
2462 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2463 /* Only if the bmac is out of reset */
2464 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2465 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2466 nig_bmac_enable) {
2467 /* Clear Rx Enable bit in BMAC_CONTROL register */
2468 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2469 if (en)
2470 wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2471 else
2472 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2473 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2474 usleep_range(1000, 2000);
2475 }
2476 }
2477
bnx2x_pbf_update(struct link_params * params,u32 flow_ctrl,u32 line_speed)2478 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2479 u32 line_speed)
2480 {
2481 struct bnx2x *bp = params->bp;
2482 u8 port = params->port;
2483 u32 init_crd, crd;
2484 u32 count = 1000;
2485
2486 /* Disable port */
2487 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2488
2489 /* Wait for init credit */
2490 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2491 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2492 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2493
2494 while ((init_crd != crd) && count) {
2495 usleep_range(5000, 10000);
2496 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2497 count--;
2498 }
2499 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2500 if (init_crd != crd) {
2501 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2502 init_crd, crd);
2503 return -EINVAL;
2504 }
2505
2506 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2507 line_speed == SPEED_10 ||
2508 line_speed == SPEED_100 ||
2509 line_speed == SPEED_1000 ||
2510 line_speed == SPEED_2500) {
2511 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2512 /* Update threshold */
2513 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2514 /* Update init credit */
2515 init_crd = 778; /* (800-18-4) */
2516
2517 } else {
2518 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2519 ETH_OVREHEAD)/16;
2520 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2521 /* Update threshold */
2522 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2523 /* Update init credit */
2524 switch (line_speed) {
2525 case SPEED_10000:
2526 init_crd = thresh + 553 - 22;
2527 break;
2528 default:
2529 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2530 line_speed);
2531 return -EINVAL;
2532 }
2533 }
2534 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2535 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2536 line_speed, init_crd);
2537
2538 /* Probe the credit changes */
2539 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2540 usleep_range(5000, 10000);
2541 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2542
2543 /* Enable port */
2544 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2545 return 0;
2546 }
2547
2548 /**
2549 * bnx2x_get_emac_base - retrive emac base address
2550 *
2551 * @bp: driver handle
2552 * @mdc_mdio_access: access type
2553 * @port: port id
2554 *
2555 * This function selects the MDC/MDIO access (through emac0 or
2556 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2557 * phy has a default access mode, which could also be overridden
2558 * by nvram configuration. This parameter, whether this is the
2559 * default phy configuration, or the nvram overrun
2560 * configuration, is passed here as mdc_mdio_access and selects
2561 * the emac_base for the CL45 read/writes operations
2562 */
bnx2x_get_emac_base(struct bnx2x * bp,u32 mdc_mdio_access,u8 port)2563 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2564 u32 mdc_mdio_access, u8 port)
2565 {
2566 u32 emac_base = 0;
2567 switch (mdc_mdio_access) {
2568 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2569 break;
2570 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2571 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2572 emac_base = GRCBASE_EMAC1;
2573 else
2574 emac_base = GRCBASE_EMAC0;
2575 break;
2576 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2577 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2578 emac_base = GRCBASE_EMAC0;
2579 else
2580 emac_base = GRCBASE_EMAC1;
2581 break;
2582 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2583 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2584 break;
2585 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2586 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2587 break;
2588 default:
2589 break;
2590 }
2591 return emac_base;
2592
2593 }
2594
2595 /******************************************************************/
2596 /* CL22 access functions */
2597 /******************************************************************/
bnx2x_cl22_write(struct bnx2x * bp,struct bnx2x_phy * phy,u16 reg,u16 val)2598 static int bnx2x_cl22_write(struct bnx2x *bp,
2599 struct bnx2x_phy *phy,
2600 u16 reg, u16 val)
2601 {
2602 u32 tmp, mode;
2603 u8 i;
2604 int rc = 0;
2605 /* Switch to CL22 */
2606 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2607 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2608 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2609
2610 /* Address */
2611 tmp = ((phy->addr << 21) | (reg << 16) | val |
2612 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2613 EMAC_MDIO_COMM_START_BUSY);
2614 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2615
2616 for (i = 0; i < 50; i++) {
2617 udelay(10);
2618
2619 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2620 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2621 udelay(5);
2622 break;
2623 }
2624 }
2625 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2626 DP(NETIF_MSG_LINK, "write phy register failed\n");
2627 rc = -EFAULT;
2628 }
2629 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2630 return rc;
2631 }
2632
bnx2x_cl22_read(struct bnx2x * bp,struct bnx2x_phy * phy,u16 reg,u16 * ret_val)2633 static int bnx2x_cl22_read(struct bnx2x *bp,
2634 struct bnx2x_phy *phy,
2635 u16 reg, u16 *ret_val)
2636 {
2637 u32 val, mode;
2638 u16 i;
2639 int rc = 0;
2640
2641 /* Switch to CL22 */
2642 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2643 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2644 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2645
2646 /* Address */
2647 val = ((phy->addr << 21) | (reg << 16) |
2648 EMAC_MDIO_COMM_COMMAND_READ_22 |
2649 EMAC_MDIO_COMM_START_BUSY);
2650 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2651
2652 for (i = 0; i < 50; i++) {
2653 udelay(10);
2654
2655 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2656 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2657 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2658 udelay(5);
2659 break;
2660 }
2661 }
2662 if (val & EMAC_MDIO_COMM_START_BUSY) {
2663 DP(NETIF_MSG_LINK, "read phy register failed\n");
2664
2665 *ret_val = 0;
2666 rc = -EFAULT;
2667 }
2668 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2669 return rc;
2670 }
2671
2672 /******************************************************************/
2673 /* CL45 access functions */
2674 /******************************************************************/
bnx2x_cl45_read(struct bnx2x * bp,struct bnx2x_phy * phy,u8 devad,u16 reg,u16 * ret_val)2675 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2676 u8 devad, u16 reg, u16 *ret_val)
2677 {
2678 u32 val;
2679 u16 i;
2680 int rc = 0;
2681 u32 chip_id;
2682 if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2683 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2684 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2685 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2686 }
2687
2688 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2689 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2690 EMAC_MDIO_STATUS_10MB);
2691 /* Address */
2692 val = ((phy->addr << 21) | (devad << 16) | reg |
2693 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2694 EMAC_MDIO_COMM_START_BUSY);
2695 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2696
2697 for (i = 0; i < 50; i++) {
2698 udelay(10);
2699
2700 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2701 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2702 udelay(5);
2703 break;
2704 }
2705 }
2706 if (val & EMAC_MDIO_COMM_START_BUSY) {
2707 DP(NETIF_MSG_LINK, "read phy register failed\n");
2708 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2709 *ret_val = 0;
2710 rc = -EFAULT;
2711 } else {
2712 /* Data */
2713 val = ((phy->addr << 21) | (devad << 16) |
2714 EMAC_MDIO_COMM_COMMAND_READ_45 |
2715 EMAC_MDIO_COMM_START_BUSY);
2716 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2717
2718 for (i = 0; i < 50; i++) {
2719 udelay(10);
2720
2721 val = REG_RD(bp, phy->mdio_ctrl +
2722 EMAC_REG_EMAC_MDIO_COMM);
2723 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2724 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2725 break;
2726 }
2727 }
2728 if (val & EMAC_MDIO_COMM_START_BUSY) {
2729 DP(NETIF_MSG_LINK, "read phy register failed\n");
2730 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2731 *ret_val = 0;
2732 rc = -EFAULT;
2733 }
2734 }
2735 /* Work around for E3 A0 */
2736 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2737 phy->flags ^= FLAGS_DUMMY_READ;
2738 if (phy->flags & FLAGS_DUMMY_READ) {
2739 u16 temp_val;
2740 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2741 }
2742 }
2743
2744 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2745 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2746 EMAC_MDIO_STATUS_10MB);
2747 return rc;
2748 }
2749
bnx2x_cl45_write(struct bnx2x * bp,struct bnx2x_phy * phy,u8 devad,u16 reg,u16 val)2750 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2751 u8 devad, u16 reg, u16 val)
2752 {
2753 u32 tmp;
2754 u8 i;
2755 int rc = 0;
2756 u32 chip_id;
2757 if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2758 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2759 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2760 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2761 }
2762
2763 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2764 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2765 EMAC_MDIO_STATUS_10MB);
2766
2767 /* Address */
2768 tmp = ((phy->addr << 21) | (devad << 16) | reg |
2769 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2770 EMAC_MDIO_COMM_START_BUSY);
2771 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2772
2773 for (i = 0; i < 50; i++) {
2774 udelay(10);
2775
2776 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2777 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2778 udelay(5);
2779 break;
2780 }
2781 }
2782 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2783 DP(NETIF_MSG_LINK, "write phy register failed\n");
2784 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2785 rc = -EFAULT;
2786 } else {
2787 /* Data */
2788 tmp = ((phy->addr << 21) | (devad << 16) | val |
2789 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2790 EMAC_MDIO_COMM_START_BUSY);
2791 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2792
2793 for (i = 0; i < 50; i++) {
2794 udelay(10);
2795
2796 tmp = REG_RD(bp, phy->mdio_ctrl +
2797 EMAC_REG_EMAC_MDIO_COMM);
2798 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2799 udelay(5);
2800 break;
2801 }
2802 }
2803 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2804 DP(NETIF_MSG_LINK, "write phy register failed\n");
2805 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2806 rc = -EFAULT;
2807 }
2808 }
2809 /* Work around for E3 A0 */
2810 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2811 phy->flags ^= FLAGS_DUMMY_READ;
2812 if (phy->flags & FLAGS_DUMMY_READ) {
2813 u16 temp_val;
2814 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2815 }
2816 }
2817 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2818 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2819 EMAC_MDIO_STATUS_10MB);
2820 return rc;
2821 }
2822
2823 /******************************************************************/
2824 /* EEE section */
2825 /******************************************************************/
bnx2x_eee_has_cap(struct link_params * params)2826 static u8 bnx2x_eee_has_cap(struct link_params *params)
2827 {
2828 struct bnx2x *bp = params->bp;
2829
2830 if (REG_RD(bp, params->shmem2_base) <=
2831 offsetof(struct shmem2_region, eee_status[params->port]))
2832 return 0;
2833
2834 return 1;
2835 }
2836
bnx2x_eee_nvram_to_time(u32 nvram_mode,u32 * idle_timer)2837 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2838 {
2839 switch (nvram_mode) {
2840 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2841 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2842 break;
2843 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2844 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2845 break;
2846 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2847 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2848 break;
2849 default:
2850 *idle_timer = 0;
2851 break;
2852 }
2853
2854 return 0;
2855 }
2856
bnx2x_eee_time_to_nvram(u32 idle_timer,u32 * nvram_mode)2857 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2858 {
2859 switch (idle_timer) {
2860 case EEE_MODE_NVRAM_BALANCED_TIME:
2861 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2862 break;
2863 case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2864 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2865 break;
2866 case EEE_MODE_NVRAM_LATENCY_TIME:
2867 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2868 break;
2869 default:
2870 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2871 break;
2872 }
2873
2874 return 0;
2875 }
2876
bnx2x_eee_calc_timer(struct link_params * params)2877 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2878 {
2879 u32 eee_mode, eee_idle;
2880 struct bnx2x *bp = params->bp;
2881
2882 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2883 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2884 /* time value in eee_mode --> used directly*/
2885 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2886 } else {
2887 /* hsi value in eee_mode --> time */
2888 if (bnx2x_eee_nvram_to_time(params->eee_mode &
2889 EEE_MODE_NVRAM_MASK,
2890 &eee_idle))
2891 return 0;
2892 }
2893 } else {
2894 /* hsi values in nvram --> time*/
2895 eee_mode = ((REG_RD(bp, params->shmem_base +
2896 offsetof(struct shmem_region, dev_info.
2897 port_feature_config[params->port].
2898 eee_power_mode)) &
2899 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2900 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2901
2902 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2903 return 0;
2904 }
2905
2906 return eee_idle;
2907 }
2908
bnx2x_eee_set_timers(struct link_params * params,struct link_vars * vars)2909 static int bnx2x_eee_set_timers(struct link_params *params,
2910 struct link_vars *vars)
2911 {
2912 u32 eee_idle = 0, eee_mode;
2913 struct bnx2x *bp = params->bp;
2914
2915 eee_idle = bnx2x_eee_calc_timer(params);
2916
2917 if (eee_idle) {
2918 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2919 eee_idle);
2920 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2921 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2922 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2923 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2924 return -EINVAL;
2925 }
2926
2927 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2928 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2929 /* eee_idle in 1u --> eee_status in 16u */
2930 eee_idle >>= 4;
2931 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2932 SHMEM_EEE_TIME_OUTPUT_BIT;
2933 } else {
2934 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2935 return -EINVAL;
2936 vars->eee_status |= eee_mode;
2937 }
2938
2939 return 0;
2940 }
2941
bnx2x_eee_initial_config(struct link_params * params,struct link_vars * vars,u8 mode)2942 static int bnx2x_eee_initial_config(struct link_params *params,
2943 struct link_vars *vars, u8 mode)
2944 {
2945 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2946
2947 /* Propagate params' bits --> vars (for migration exposure) */
2948 if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2949 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2950 else
2951 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2952
2953 if (params->eee_mode & EEE_MODE_ADV_LPI)
2954 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2955 else
2956 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2957
2958 return bnx2x_eee_set_timers(params, vars);
2959 }
2960
bnx2x_eee_disable(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)2961 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2962 struct link_params *params,
2963 struct link_vars *vars)
2964 {
2965 struct bnx2x *bp = params->bp;
2966
2967 /* Make Certain LPI is disabled */
2968 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2969
2970 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
2971
2972 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2973
2974 return 0;
2975 }
2976
bnx2x_eee_advertise(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars,u8 modes)2977 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
2978 struct link_params *params,
2979 struct link_vars *vars, u8 modes)
2980 {
2981 struct bnx2x *bp = params->bp;
2982 u16 val = 0;
2983
2984 /* Mask events preventing LPI generation */
2985 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
2986
2987 if (modes & SHMEM_EEE_10G_ADV) {
2988 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
2989 val |= 0x8;
2990 }
2991 if (modes & SHMEM_EEE_1G_ADV) {
2992 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
2993 val |= 0x4;
2994 }
2995
2996 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
2997
2998 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2999 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3000
3001 return 0;
3002 }
3003
bnx2x_update_mng_eee(struct link_params * params,u32 eee_status)3004 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
3005 {
3006 struct bnx2x *bp = params->bp;
3007
3008 if (bnx2x_eee_has_cap(params))
3009 REG_WR(bp, params->shmem2_base +
3010 offsetof(struct shmem2_region,
3011 eee_status[params->port]), eee_status);
3012 }
3013
bnx2x_eee_an_resolve(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)3014 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3015 struct link_params *params,
3016 struct link_vars *vars)
3017 {
3018 struct bnx2x *bp = params->bp;
3019 u16 adv = 0, lp = 0;
3020 u32 lp_adv = 0;
3021 u8 neg = 0;
3022
3023 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3024 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3025
3026 if (lp & 0x2) {
3027 lp_adv |= SHMEM_EEE_100M_ADV;
3028 if (adv & 0x2) {
3029 if (vars->line_speed == SPEED_100)
3030 neg = 1;
3031 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3032 }
3033 }
3034 if (lp & 0x14) {
3035 lp_adv |= SHMEM_EEE_1G_ADV;
3036 if (adv & 0x14) {
3037 if (vars->line_speed == SPEED_1000)
3038 neg = 1;
3039 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3040 }
3041 }
3042 if (lp & 0x68) {
3043 lp_adv |= SHMEM_EEE_10G_ADV;
3044 if (adv & 0x68) {
3045 if (vars->line_speed == SPEED_10000)
3046 neg = 1;
3047 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3048 }
3049 }
3050
3051 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3052 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3053
3054 if (neg) {
3055 DP(NETIF_MSG_LINK, "EEE is active\n");
3056 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3057 }
3058
3059 }
3060
3061 /******************************************************************/
3062 /* BSC access functions from E3 */
3063 /******************************************************************/
bnx2x_bsc_module_sel(struct link_params * params)3064 static void bnx2x_bsc_module_sel(struct link_params *params)
3065 {
3066 int idx;
3067 u32 board_cfg, sfp_ctrl;
3068 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3069 struct bnx2x *bp = params->bp;
3070 u8 port = params->port;
3071 /* Read I2C output PINs */
3072 board_cfg = REG_RD(bp, params->shmem_base +
3073 offsetof(struct shmem_region,
3074 dev_info.shared_hw_config.board));
3075 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3076 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3077 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3078
3079 /* Read I2C output value */
3080 sfp_ctrl = REG_RD(bp, params->shmem_base +
3081 offsetof(struct shmem_region,
3082 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3083 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3084 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3085 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3086 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3087 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3088 }
3089
bnx2x_bsc_read(struct link_params * params,struct bnx2x * bp,u8 sl_devid,u16 sl_addr,u8 lc_addr,u8 xfer_cnt,u32 * data_array)3090 static int bnx2x_bsc_read(struct link_params *params,
3091 struct bnx2x *bp,
3092 u8 sl_devid,
3093 u16 sl_addr,
3094 u8 lc_addr,
3095 u8 xfer_cnt,
3096 u32 *data_array)
3097 {
3098 u32 val, i;
3099 int rc = 0;
3100
3101 if (xfer_cnt > 16) {
3102 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3103 xfer_cnt);
3104 return -EINVAL;
3105 }
3106 bnx2x_bsc_module_sel(params);
3107
3108 xfer_cnt = 16 - lc_addr;
3109
3110 /* Enable the engine */
3111 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3112 val |= MCPR_IMC_COMMAND_ENABLE;
3113 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3114
3115 /* Program slave device ID */
3116 val = (sl_devid << 16) | sl_addr;
3117 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3118
3119 /* Start xfer with 0 byte to update the address pointer ???*/
3120 val = (MCPR_IMC_COMMAND_ENABLE) |
3121 (MCPR_IMC_COMMAND_WRITE_OP <<
3122 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3123 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3124 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3125
3126 /* Poll for completion */
3127 i = 0;
3128 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3129 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3130 udelay(10);
3131 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3132 if (i++ > 1000) {
3133 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3134 i);
3135 rc = -EFAULT;
3136 break;
3137 }
3138 }
3139 if (rc == -EFAULT)
3140 return rc;
3141
3142 /* Start xfer with read op */
3143 val = (MCPR_IMC_COMMAND_ENABLE) |
3144 (MCPR_IMC_COMMAND_READ_OP <<
3145 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3146 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3147 (xfer_cnt);
3148 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3149
3150 /* Poll for completion */
3151 i = 0;
3152 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3153 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3154 udelay(10);
3155 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3156 if (i++ > 1000) {
3157 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3158 rc = -EFAULT;
3159 break;
3160 }
3161 }
3162 if (rc == -EFAULT)
3163 return rc;
3164
3165 for (i = (lc_addr >> 2); i < 4; i++) {
3166 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3167 #ifdef __BIG_ENDIAN
3168 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3169 ((data_array[i] & 0x0000ff00) << 8) |
3170 ((data_array[i] & 0x00ff0000) >> 8) |
3171 ((data_array[i] & 0xff000000) >> 24);
3172 #endif
3173 }
3174 return rc;
3175 }
3176
bnx2x_cl45_read_or_write(struct bnx2x * bp,struct bnx2x_phy * phy,u8 devad,u16 reg,u16 or_val)3177 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3178 u8 devad, u16 reg, u16 or_val)
3179 {
3180 u16 val;
3181 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3182 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3183 }
3184
bnx2x_cl45_read_and_write(struct bnx2x * bp,struct bnx2x_phy * phy,u8 devad,u16 reg,u16 and_val)3185 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3186 struct bnx2x_phy *phy,
3187 u8 devad, u16 reg, u16 and_val)
3188 {
3189 u16 val;
3190 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3191 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3192 }
3193
bnx2x_phy_read(struct link_params * params,u8 phy_addr,u8 devad,u16 reg,u16 * ret_val)3194 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3195 u8 devad, u16 reg, u16 *ret_val)
3196 {
3197 u8 phy_index;
3198 /* Probe for the phy according to the given phy_addr, and execute
3199 * the read request on it
3200 */
3201 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3202 if (params->phy[phy_index].addr == phy_addr) {
3203 return bnx2x_cl45_read(params->bp,
3204 ¶ms->phy[phy_index], devad,
3205 reg, ret_val);
3206 }
3207 }
3208 return -EINVAL;
3209 }
3210
bnx2x_phy_write(struct link_params * params,u8 phy_addr,u8 devad,u16 reg,u16 val)3211 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3212 u8 devad, u16 reg, u16 val)
3213 {
3214 u8 phy_index;
3215 /* Probe for the phy according to the given phy_addr, and execute
3216 * the write request on it
3217 */
3218 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3219 if (params->phy[phy_index].addr == phy_addr) {
3220 return bnx2x_cl45_write(params->bp,
3221 ¶ms->phy[phy_index], devad,
3222 reg, val);
3223 }
3224 }
3225 return -EINVAL;
3226 }
bnx2x_get_warpcore_lane(struct bnx2x_phy * phy,struct link_params * params)3227 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3228 struct link_params *params)
3229 {
3230 u8 lane = 0;
3231 struct bnx2x *bp = params->bp;
3232 u32 path_swap, path_swap_ovr;
3233 u8 path, port;
3234
3235 path = BP_PATH(bp);
3236 port = params->port;
3237
3238 if (bnx2x_is_4_port_mode(bp)) {
3239 u32 port_swap, port_swap_ovr;
3240
3241 /* Figure out path swap value */
3242 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3243 if (path_swap_ovr & 0x1)
3244 path_swap = (path_swap_ovr & 0x2);
3245 else
3246 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3247
3248 if (path_swap)
3249 path = path ^ 1;
3250
3251 /* Figure out port swap value */
3252 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3253 if (port_swap_ovr & 0x1)
3254 port_swap = (port_swap_ovr & 0x2);
3255 else
3256 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3257
3258 if (port_swap)
3259 port = port ^ 1;
3260
3261 lane = (port<<1) + path;
3262 } else { /* Two port mode - no port swap */
3263
3264 /* Figure out path swap value */
3265 path_swap_ovr =
3266 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3267 if (path_swap_ovr & 0x1) {
3268 path_swap = (path_swap_ovr & 0x2);
3269 } else {
3270 path_swap =
3271 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3272 }
3273 if (path_swap)
3274 path = path ^ 1;
3275
3276 lane = path << 1 ;
3277 }
3278 return lane;
3279 }
3280
bnx2x_set_aer_mmd(struct link_params * params,struct bnx2x_phy * phy)3281 static void bnx2x_set_aer_mmd(struct link_params *params,
3282 struct bnx2x_phy *phy)
3283 {
3284 u32 ser_lane;
3285 u16 offset, aer_val;
3286 struct bnx2x *bp = params->bp;
3287 ser_lane = ((params->lane_config &
3288 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3289 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3290
3291 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3292 (phy->addr + ser_lane) : 0;
3293
3294 if (USES_WARPCORE(bp)) {
3295 aer_val = bnx2x_get_warpcore_lane(phy, params);
3296 /* In Dual-lane mode, two lanes are joined together,
3297 * so in order to configure them, the AER broadcast method is
3298 * used here.
3299 * 0x200 is the broadcast address for lanes 0,1
3300 * 0x201 is the broadcast address for lanes 2,3
3301 */
3302 if (phy->flags & FLAGS_WC_DUAL_MODE)
3303 aer_val = (aer_val >> 1) | 0x200;
3304 } else if (CHIP_IS_E2(bp))
3305 aer_val = 0x3800 + offset - 1;
3306 else
3307 aer_val = 0x3800 + offset;
3308
3309 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3310 MDIO_AER_BLOCK_AER_REG, aer_val);
3311
3312 }
3313
3314 /******************************************************************/
3315 /* Internal phy section */
3316 /******************************************************************/
3317
bnx2x_set_serdes_access(struct bnx2x * bp,u8 port)3318 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3319 {
3320 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3321
3322 /* Set Clause 22 */
3323 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3324 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3325 udelay(500);
3326 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3327 udelay(500);
3328 /* Set Clause 45 */
3329 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3330 }
3331
bnx2x_serdes_deassert(struct bnx2x * bp,u8 port)3332 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3333 {
3334 u32 val;
3335
3336 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3337
3338 val = SERDES_RESET_BITS << (port*16);
3339
3340 /* Reset and unreset the SerDes/XGXS */
3341 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3342 udelay(500);
3343 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3344
3345 bnx2x_set_serdes_access(bp, port);
3346
3347 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3348 DEFAULT_PHY_DEV_ADDR);
3349 }
3350
bnx2x_xgxs_specific_func(struct bnx2x_phy * phy,struct link_params * params,u32 action)3351 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3352 struct link_params *params,
3353 u32 action)
3354 {
3355 struct bnx2x *bp = params->bp;
3356 switch (action) {
3357 case PHY_INIT:
3358 /* Set correct devad */
3359 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3360 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3361 phy->def_md_devad);
3362 break;
3363 }
3364 }
3365
bnx2x_xgxs_deassert(struct link_params * params)3366 static void bnx2x_xgxs_deassert(struct link_params *params)
3367 {
3368 struct bnx2x *bp = params->bp;
3369 u8 port;
3370 u32 val;
3371 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3372 port = params->port;
3373
3374 val = XGXS_RESET_BITS << (port*16);
3375
3376 /* Reset and unreset the SerDes/XGXS */
3377 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3378 udelay(500);
3379 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3380 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params,
3381 PHY_INIT);
3382 }
3383
bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy * phy,struct link_params * params,u16 * ieee_fc)3384 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3385 struct link_params *params, u16 *ieee_fc)
3386 {
3387 struct bnx2x *bp = params->bp;
3388 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3389 /* Resolve pause mode and advertisement Please refer to Table
3390 * 28B-3 of the 802.3ab-1999 spec
3391 */
3392
3393 switch (phy->req_flow_ctrl) {
3394 case BNX2X_FLOW_CTRL_AUTO:
3395 switch (params->req_fc_auto_adv) {
3396 case BNX2X_FLOW_CTRL_BOTH:
3397 case BNX2X_FLOW_CTRL_RX:
3398 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3399 break;
3400 case BNX2X_FLOW_CTRL_TX:
3401 *ieee_fc |=
3402 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3403 break;
3404 default:
3405 break;
3406 }
3407 break;
3408 case BNX2X_FLOW_CTRL_TX:
3409 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3410 break;
3411
3412 case BNX2X_FLOW_CTRL_RX:
3413 case BNX2X_FLOW_CTRL_BOTH:
3414 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3415 break;
3416
3417 case BNX2X_FLOW_CTRL_NONE:
3418 default:
3419 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3420 break;
3421 }
3422 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3423 }
3424
set_phy_vars(struct link_params * params,struct link_vars * vars)3425 static void set_phy_vars(struct link_params *params,
3426 struct link_vars *vars)
3427 {
3428 struct bnx2x *bp = params->bp;
3429 u8 actual_phy_idx, phy_index, link_cfg_idx;
3430 u8 phy_config_swapped = params->multi_phy_config &
3431 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3432 for (phy_index = INT_PHY; phy_index < params->num_phys;
3433 phy_index++) {
3434 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3435 actual_phy_idx = phy_index;
3436 if (phy_config_swapped) {
3437 if (phy_index == EXT_PHY1)
3438 actual_phy_idx = EXT_PHY2;
3439 else if (phy_index == EXT_PHY2)
3440 actual_phy_idx = EXT_PHY1;
3441 }
3442 params->phy[actual_phy_idx].req_flow_ctrl =
3443 params->req_flow_ctrl[link_cfg_idx];
3444
3445 params->phy[actual_phy_idx].req_line_speed =
3446 params->req_line_speed[link_cfg_idx];
3447
3448 params->phy[actual_phy_idx].speed_cap_mask =
3449 params->speed_cap_mask[link_cfg_idx];
3450
3451 params->phy[actual_phy_idx].req_duplex =
3452 params->req_duplex[link_cfg_idx];
3453
3454 if (params->req_line_speed[link_cfg_idx] ==
3455 SPEED_AUTO_NEG)
3456 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3457
3458 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3459 " speed_cap_mask %x\n",
3460 params->phy[actual_phy_idx].req_flow_ctrl,
3461 params->phy[actual_phy_idx].req_line_speed,
3462 params->phy[actual_phy_idx].speed_cap_mask);
3463 }
3464 }
3465
bnx2x_ext_phy_set_pause(struct link_params * params,struct bnx2x_phy * phy,struct link_vars * vars)3466 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3467 struct bnx2x_phy *phy,
3468 struct link_vars *vars)
3469 {
3470 u16 val;
3471 struct bnx2x *bp = params->bp;
3472 /* Read modify write pause advertizing */
3473 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3474
3475 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3476
3477 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3478 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3479 if ((vars->ieee_fc &
3480 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3481 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3482 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3483 }
3484 if ((vars->ieee_fc &
3485 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3486 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3487 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3488 }
3489 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3490 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3491 }
3492
bnx2x_pause_resolve(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars,u32 pause_result)3493 static void bnx2x_pause_resolve(struct bnx2x_phy *phy,
3494 struct link_params *params,
3495 struct link_vars *vars,
3496 u32 pause_result)
3497 {
3498 struct bnx2x *bp = params->bp;
3499 /* LD LP */
3500 switch (pause_result) { /* ASYM P ASYM P */
3501 case 0xb: /* 1 0 1 1 */
3502 DP(NETIF_MSG_LINK, "Flow Control: TX only\n");
3503 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3504 break;
3505
3506 case 0xe: /* 1 1 1 0 */
3507 DP(NETIF_MSG_LINK, "Flow Control: RX only\n");
3508 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3509 break;
3510
3511 case 0x5: /* 0 1 0 1 */
3512 case 0x7: /* 0 1 1 1 */
3513 case 0xd: /* 1 1 0 1 */
3514 case 0xf: /* 1 1 1 1 */
3515 /* If the user selected to advertise RX ONLY,
3516 * although we advertised both, need to enable
3517 * RX only.
3518 */
3519 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
3520 DP(NETIF_MSG_LINK, "Flow Control: RX & TX\n");
3521 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3522 } else {
3523 DP(NETIF_MSG_LINK, "Flow Control: RX only\n");
3524 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3525 }
3526 break;
3527
3528 default:
3529 DP(NETIF_MSG_LINK, "Flow Control: None\n");
3530 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3531 break;
3532 }
3533 if (pause_result & (1<<0))
3534 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3535 if (pause_result & (1<<1))
3536 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3537
3538 }
3539
bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)3540 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3541 struct link_params *params,
3542 struct link_vars *vars)
3543 {
3544 u16 ld_pause; /* local */
3545 u16 lp_pause; /* link partner */
3546 u16 pause_result;
3547 struct bnx2x *bp = params->bp;
3548 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3549 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3550 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3551 } else if (CHIP_IS_E3(bp) &&
3552 SINGLE_MEDIA_DIRECT(params)) {
3553 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3554 u16 gp_status, gp_mask;
3555 bnx2x_cl45_read(bp, phy,
3556 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3557 &gp_status);
3558 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3559 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3560 lane;
3561 if ((gp_status & gp_mask) == gp_mask) {
3562 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3563 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3564 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3565 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3566 } else {
3567 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3568 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3569 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3570 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3571 ld_pause = ((ld_pause &
3572 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3573 << 3);
3574 lp_pause = ((lp_pause &
3575 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3576 << 3);
3577 }
3578 } else {
3579 bnx2x_cl45_read(bp, phy,
3580 MDIO_AN_DEVAD,
3581 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3582 bnx2x_cl45_read(bp, phy,
3583 MDIO_AN_DEVAD,
3584 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3585 }
3586 pause_result = (ld_pause &
3587 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3588 pause_result |= (lp_pause &
3589 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3590 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3591 bnx2x_pause_resolve(phy, params, vars, pause_result);
3592
3593 }
3594
bnx2x_ext_phy_resolve_fc(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)3595 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3596 struct link_params *params,
3597 struct link_vars *vars)
3598 {
3599 u8 ret = 0;
3600 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3601 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3602 /* Update the advertised flow-controled of LD/LP in AN */
3603 if (phy->req_line_speed == SPEED_AUTO_NEG)
3604 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3605 /* But set the flow-control result as the requested one */
3606 vars->flow_ctrl = phy->req_flow_ctrl;
3607 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3608 vars->flow_ctrl = params->req_fc_auto_adv;
3609 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3610 ret = 1;
3611 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3612 }
3613 return ret;
3614 }
3615 /******************************************************************/
3616 /* Warpcore section */
3617 /******************************************************************/
3618 /* The init_internal_warpcore should mirror the xgxs,
3619 * i.e. reset the lane (if needed), set aer for the
3620 * init configuration, and set/clear SGMII flag. Internal
3621 * phy init is done purely in phy_init stage.
3622 */
3623 #define WC_TX_DRIVER(post2, idriver, ipre, ifir) \
3624 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3625 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3626 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET) | \
3627 (ifir << MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET))
3628
3629 #define WC_TX_FIR(post, main, pre) \
3630 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3631 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3632 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3633
bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)3634 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3635 struct link_params *params,
3636 struct link_vars *vars)
3637 {
3638 struct bnx2x *bp = params->bp;
3639 u16 i;
3640 static struct bnx2x_reg_set reg_set[] = {
3641 /* Step 1 - Program the TX/RX alignment markers */
3642 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3643 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3644 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3645 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3646 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3647 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3648 /* Step 2 - Configure the NP registers */
3649 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3650 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3651 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3652 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3653 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3654 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3655 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3656 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3657 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3658 };
3659 DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3660
3661 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3662 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3663
3664 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3665 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3666 reg_set[i].val);
3667
3668 /* Start KR2 work-around timer which handles BCM8073 link-parner */
3669 params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3670 bnx2x_update_link_attr(params, params->link_attr_sync);
3671 }
3672
bnx2x_disable_kr2(struct link_params * params,struct link_vars * vars,struct bnx2x_phy * phy)3673 static void bnx2x_disable_kr2(struct link_params *params,
3674 struct link_vars *vars,
3675 struct bnx2x_phy *phy)
3676 {
3677 struct bnx2x *bp = params->bp;
3678 int i;
3679 static struct bnx2x_reg_set reg_set[] = {
3680 /* Step 1 - Program the TX/RX alignment markers */
3681 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3682 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3683 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3684 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3685 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3686 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3687 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3688 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3689 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3690 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3691 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3692 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3693 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3694 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3695 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3696 };
3697 DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
3698
3699 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3700 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3701 reg_set[i].val);
3702 params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3703 bnx2x_update_link_attr(params, params->link_attr_sync);
3704
3705 vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
3706 }
3707
bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy * phy,struct link_params * params)3708 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3709 struct link_params *params)
3710 {
3711 struct bnx2x *bp = params->bp;
3712
3713 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3714 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3715 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3716 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3717 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3718 }
3719
bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy * phy,struct link_params * params)3720 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3721 struct link_params *params)
3722 {
3723 /* Restart autoneg on the leading lane only */
3724 struct bnx2x *bp = params->bp;
3725 u16 lane = bnx2x_get_warpcore_lane(phy, params);
3726 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3727 MDIO_AER_BLOCK_AER_REG, lane);
3728 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3729 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3730
3731 /* Restore AER */
3732 bnx2x_set_aer_mmd(params, phy);
3733 }
3734
bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)3735 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3736 struct link_params *params,
3737 struct link_vars *vars) {
3738 u16 lane, i, cl72_ctrl, an_adv = 0, val;
3739 u32 wc_lane_config;
3740 struct bnx2x *bp = params->bp;
3741 static struct bnx2x_reg_set reg_set[] = {
3742 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3743 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3744 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3745 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3746 /* Disable Autoneg: re-enable it after adv is done. */
3747 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3748 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3749 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3750 };
3751 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3752 /* Set to default registers that may be overriden by 10G force */
3753 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3754 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3755 reg_set[i].val);
3756
3757 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3758 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3759 cl72_ctrl &= 0x08ff;
3760 cl72_ctrl |= 0x3800;
3761 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3762 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3763
3764 /* Check adding advertisement for 1G KX */
3765 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3766 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3767 (vars->line_speed == SPEED_1000)) {
3768 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3769 an_adv |= (1<<5);
3770
3771 /* Enable CL37 1G Parallel Detect */
3772 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3773 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3774 }
3775 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3776 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3777 (vars->line_speed == SPEED_10000)) {
3778 /* Check adding advertisement for 10G KR */
3779 an_adv |= (1<<7);
3780 /* Enable 10G Parallel Detect */
3781 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3782 MDIO_AER_BLOCK_AER_REG, 0);
3783
3784 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3785 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3786 bnx2x_set_aer_mmd(params, phy);
3787 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3788 }
3789
3790 /* Set Transmit PMD settings */
3791 lane = bnx2x_get_warpcore_lane(phy, params);
3792 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3793 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3794 WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
3795 /* Configure the next lane if dual mode */
3796 if (phy->flags & FLAGS_WC_DUAL_MODE)
3797 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3798 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3799 WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
3800 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3801 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3802 0x03f0);
3803 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3804 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3805 0x03f0);
3806
3807 /* Advertised speeds */
3808 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3809 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3810
3811 /* Advertised and set FEC (Forward Error Correction) */
3812 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3813 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3814 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3815 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3816
3817 /* Enable CL37 BAM */
3818 if (REG_RD(bp, params->shmem_base +
3819 offsetof(struct shmem_region, dev_info.
3820 port_hw_config[params->port].default_cfg)) &
3821 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3822 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3823 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3824 1);
3825 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3826 }
3827
3828 /* Advertise pause */
3829 bnx2x_ext_phy_set_pause(params, phy, vars);
3830 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3831 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3832 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3833
3834 /* Over 1G - AN local device user page 1 */
3835 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3836 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3837
3838 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3839 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3840 (phy->req_line_speed == SPEED_20000)) {
3841
3842 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3843 MDIO_AER_BLOCK_AER_REG, lane);
3844
3845 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3846 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3847 (1<<11));
3848
3849 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3850 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3851 bnx2x_set_aer_mmd(params, phy);
3852
3853 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3854 } else {
3855 /* Enable Auto-Detect to support 1G over CL37 as well */
3856 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3857 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
3858 wc_lane_config = REG_RD(bp, params->shmem_base +
3859 offsetof(struct shmem_region, dev_info.
3860 shared_hw_config.wc_lane_config));
3861 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3862 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
3863 /* Force cl48 sync_status LOW to avoid getting stuck in CL73
3864 * parallel-detect loop when CL73 and CL37 are enabled.
3865 */
3866 val |= 1 << 11;
3867
3868 /* Restore Polarity settings in case it was run over by
3869 * previous link owner
3870 */
3871 if (wc_lane_config &
3872 (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
3873 val |= 3 << 2;
3874 else
3875 val &= ~(3 << 2);
3876 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3877 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),
3878 val);
3879
3880 bnx2x_disable_kr2(params, vars, phy);
3881 }
3882
3883 /* Enable Autoneg: only on the main lane */
3884 bnx2x_warpcore_restart_AN_KR(phy, params);
3885 }
3886
bnx2x_warpcore_set_10G_KR(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)3887 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3888 struct link_params *params,
3889 struct link_vars *vars)
3890 {
3891 struct bnx2x *bp = params->bp;
3892 u16 val16, i, lane;
3893 static struct bnx2x_reg_set reg_set[] = {
3894 /* Disable Autoneg */
3895 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3896 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3897 0x3f00},
3898 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3899 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3900 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3901 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3902 /* Leave cl72 training enable, needed for KR */
3903 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3904 };
3905
3906 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3907 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3908 reg_set[i].val);
3909
3910 lane = bnx2x_get_warpcore_lane(phy, params);
3911 /* Global registers */
3912 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3913 MDIO_AER_BLOCK_AER_REG, 0);
3914 /* Disable CL36 PCS Tx */
3915 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3916 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3917 val16 &= ~(0x0011 << lane);
3918 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3919 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3920
3921 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3922 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3923 val16 |= (0x0303 << (lane << 1));
3924 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3925 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3926 /* Restore AER */
3927 bnx2x_set_aer_mmd(params, phy);
3928 /* Set speed via PMA/PMD register */
3929 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3930 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3931
3932 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3933 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3934
3935 /* Enable encoded forced speed */
3936 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3937 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3938
3939 /* Turn TX scramble payload only the 64/66 scrambler */
3940 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3941 MDIO_WC_REG_TX66_CONTROL, 0x9);
3942
3943 /* Turn RX scramble payload only the 64/66 scrambler */
3944 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3945 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3946
3947 /* Set and clear loopback to cause a reset to 64/66 decoder */
3948 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3949 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3950 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3951 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3952
3953 }
3954
bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy * phy,struct link_params * params,u8 is_xfi)3955 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3956 struct link_params *params,
3957 u8 is_xfi)
3958 {
3959 struct bnx2x *bp = params->bp;
3960 u16 misc1_val, tap_val, tx_driver_val, lane, val;
3961 u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3962 u32 ifir_val, ipost2_val, ipre_driver_val;
3963
3964 /* Hold rxSeqStart */
3965 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3966 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3967
3968 /* Hold tx_fifo_reset */
3969 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3970 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3971
3972 /* Disable CL73 AN */
3973 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3974
3975 /* Disable 100FX Enable and Auto-Detect */
3976 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3977 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3978
3979 /* Disable 100FX Idle detect */
3980 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3981 MDIO_WC_REG_FX100_CTRL3, 0x0080);
3982
3983 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3984 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3985 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3986
3987 /* Turn off auto-detect & fiber mode */
3988 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3989 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3990 0xFFEE);
3991
3992 /* Set filter_force_link, disable_false_link and parallel_detect */
3993 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3994 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3995 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3996 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3997 ((val | 0x0006) & 0xFFFE));
3998
3999 /* Set XFI / SFI */
4000 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4001 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
4002
4003 misc1_val &= ~(0x1f);
4004
4005 if (is_xfi) {
4006 misc1_val |= 0x5;
4007 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
4008 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0);
4009 } else {
4010 cfg_tap_val = REG_RD(bp, params->shmem_base +
4011 offsetof(struct shmem_region, dev_info.
4012 port_hw_config[params->port].
4013 sfi_tap_values));
4014
4015 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
4016
4017 misc1_val |= 0x9;
4018
4019 /* TAP values are controlled by nvram, if value there isn't 0 */
4020 if (tx_equal)
4021 tap_val = (u16)tx_equal;
4022 else
4023 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
4024
4025 ifir_val = DEFAULT_TX_DRV_IFIR;
4026 ipost2_val = DEFAULT_TX_DRV_POST2;
4027 ipre_driver_val = DEFAULT_TX_DRV_IPRE_DRIVER;
4028 tx_drv_brdct = DEFAULT_TX_DRV_BRDCT;
4029
4030 /* If any of the IFIR/IPRE_DRIVER/POST@ is set, apply all
4031 * configuration.
4032 */
4033 if (cfg_tap_val & (PORT_HW_CFG_TX_DRV_IFIR_MASK |
4034 PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK |
4035 PORT_HW_CFG_TX_DRV_POST2_MASK)) {
4036 ifir_val = (cfg_tap_val &
4037 PORT_HW_CFG_TX_DRV_IFIR_MASK) >>
4038 PORT_HW_CFG_TX_DRV_IFIR_SHIFT;
4039 ipre_driver_val = (cfg_tap_val &
4040 PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK)
4041 >> PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT;
4042 ipost2_val = (cfg_tap_val &
4043 PORT_HW_CFG_TX_DRV_POST2_MASK) >>
4044 PORT_HW_CFG_TX_DRV_POST2_SHIFT;
4045 }
4046
4047 if (cfg_tap_val & PORT_HW_CFG_TX_DRV_BROADCAST_MASK) {
4048 tx_drv_brdct = (cfg_tap_val &
4049 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
4050 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
4051 }
4052
4053 tx_driver_val = WC_TX_DRIVER(ipost2_val, tx_drv_brdct,
4054 ipre_driver_val, ifir_val);
4055 }
4056 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4057 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4058
4059 /* Set Transmit PMD settings */
4060 lane = bnx2x_get_warpcore_lane(phy, params);
4061 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4062 MDIO_WC_REG_TX_FIR_TAP,
4063 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4064 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4065 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4066 tx_driver_val);
4067
4068 /* Enable fiber mode, enable and invert sig_det */
4069 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4070 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4071
4072 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4073 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4074 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4075
4076 bnx2x_warpcore_set_lpi_passthrough(phy, params);
4077
4078 /* 10G XFI Full Duplex */
4079 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4080 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4081
4082 /* Release tx_fifo_reset */
4083 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4084 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4085 0xFFFE);
4086 /* Release rxSeqStart */
4087 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4088 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4089 }
4090
bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy * phy,struct link_params * params)4091 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4092 struct link_params *params)
4093 {
4094 u16 val;
4095 struct bnx2x *bp = params->bp;
4096 /* Set global registers, so set AER lane to 0 */
4097 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4098 MDIO_AER_BLOCK_AER_REG, 0);
4099
4100 /* Disable sequencer */
4101 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4102 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4103
4104 bnx2x_set_aer_mmd(params, phy);
4105
4106 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4107 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4108 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4109 MDIO_AN_REG_CTRL, 0);
4110 /* Turn off CL73 */
4111 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4112 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4113 val &= ~(1<<5);
4114 val |= (1<<6);
4115 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4116 MDIO_WC_REG_CL73_USERB0_CTRL, val);
4117
4118 /* Set 20G KR2 force speed */
4119 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4120 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4121
4122 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4123 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4124
4125 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4126 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4127 val &= ~(3<<14);
4128 val |= (1<<15);
4129 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4130 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4131 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4132 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4133
4134 /* Enable sequencer (over lane 0) */
4135 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4136 MDIO_AER_BLOCK_AER_REG, 0);
4137
4138 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4139 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4140
4141 bnx2x_set_aer_mmd(params, phy);
4142 }
4143
bnx2x_warpcore_set_20G_DXGXS(struct bnx2x * bp,struct bnx2x_phy * phy,u16 lane)4144 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4145 struct bnx2x_phy *phy,
4146 u16 lane)
4147 {
4148 /* Rx0 anaRxControl1G */
4149 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4150 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4151
4152 /* Rx2 anaRxControl1G */
4153 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4154 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4155
4156 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4157 MDIO_WC_REG_RX66_SCW0, 0xE070);
4158
4159 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4160 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4161
4162 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4163 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4164
4165 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4166 MDIO_WC_REG_RX66_SCW3, 0x8090);
4167
4168 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4169 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4170
4171 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4172 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4173
4174 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4175 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4176
4177 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4178 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4179
4180 /* Serdes Digital Misc1 */
4181 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4182 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4183
4184 /* Serdes Digital4 Misc3 */
4185 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4186 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4187
4188 /* Set Transmit PMD settings */
4189 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4190 MDIO_WC_REG_TX_FIR_TAP,
4191 (WC_TX_FIR(0x12, 0x2d, 0x00) |
4192 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4193 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4194 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4195 WC_TX_DRIVER(0x02, 0x02, 0x02, 0));
4196 }
4197
bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy * phy,struct link_params * params,u8 fiber_mode,u8 always_autoneg)4198 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4199 struct link_params *params,
4200 u8 fiber_mode,
4201 u8 always_autoneg)
4202 {
4203 struct bnx2x *bp = params->bp;
4204 u16 val16, digctrl_kx1, digctrl_kx2;
4205
4206 /* Clear XFI clock comp in non-10G single lane mode. */
4207 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4208 MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4209
4210 bnx2x_warpcore_set_lpi_passthrough(phy, params);
4211
4212 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4213 /* SGMII Autoneg */
4214 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4215 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4216 0x1000);
4217 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4218 } else {
4219 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4220 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4221 val16 &= 0xcebf;
4222 switch (phy->req_line_speed) {
4223 case SPEED_10:
4224 break;
4225 case SPEED_100:
4226 val16 |= 0x2000;
4227 break;
4228 case SPEED_1000:
4229 val16 |= 0x0040;
4230 break;
4231 default:
4232 DP(NETIF_MSG_LINK,
4233 "Speed not supported: 0x%x\n", phy->req_line_speed);
4234 return;
4235 }
4236
4237 if (phy->req_duplex == DUPLEX_FULL)
4238 val16 |= 0x0100;
4239
4240 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4241 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4242
4243 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4244 phy->req_line_speed);
4245 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4246 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4247 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
4248 }
4249
4250 /* SGMII Slave mode and disable signal detect */
4251 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4252 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4253 if (fiber_mode)
4254 digctrl_kx1 = 1;
4255 else
4256 digctrl_kx1 &= 0xff4a;
4257
4258 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4259 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4260 digctrl_kx1);
4261
4262 /* Turn off parallel detect */
4263 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4264 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4265 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4266 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4267 (digctrl_kx2 & ~(1<<2)));
4268
4269 /* Re-enable parallel detect */
4270 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4271 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4272 (digctrl_kx2 | (1<<2)));
4273
4274 /* Enable autodet */
4275 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4276 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4277 (digctrl_kx1 | 0x10));
4278 }
4279
bnx2x_warpcore_reset_lane(struct bnx2x * bp,struct bnx2x_phy * phy,u8 reset)4280 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4281 struct bnx2x_phy *phy,
4282 u8 reset)
4283 {
4284 u16 val;
4285 /* Take lane out of reset after configuration is finished */
4286 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4287 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4288 if (reset)
4289 val |= 0xC000;
4290 else
4291 val &= 0x3FFF;
4292 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4293 MDIO_WC_REG_DIGITAL5_MISC6, val);
4294 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4295 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4296 }
4297 /* Clear SFI/XFI link settings registers */
bnx2x_warpcore_clear_regs(struct bnx2x_phy * phy,struct link_params * params,u16 lane)4298 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4299 struct link_params *params,
4300 u16 lane)
4301 {
4302 struct bnx2x *bp = params->bp;
4303 u16 i;
4304 static struct bnx2x_reg_set wc_regs[] = {
4305 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4306 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4307 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4308 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4309 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4310 0x0195},
4311 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4312 0x0007},
4313 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4314 0x0002},
4315 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4316 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4317 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4318 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4319 };
4320 /* Set XFI clock comp as default. */
4321 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4322 MDIO_WC_REG_RX66_CONTROL, (3<<13));
4323
4324 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4325 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4326 wc_regs[i].val);
4327
4328 lane = bnx2x_get_warpcore_lane(phy, params);
4329 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4330 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4331
4332 }
4333
bnx2x_get_mod_abs_int_cfg(struct bnx2x * bp,u32 chip_id,u32 shmem_base,u8 port,u8 * gpio_num,u8 * gpio_port)4334 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4335 u32 chip_id,
4336 u32 shmem_base, u8 port,
4337 u8 *gpio_num, u8 *gpio_port)
4338 {
4339 u32 cfg_pin;
4340 *gpio_num = 0;
4341 *gpio_port = 0;
4342 if (CHIP_IS_E3(bp)) {
4343 cfg_pin = (REG_RD(bp, shmem_base +
4344 offsetof(struct shmem_region,
4345 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4346 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4347 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4348
4349 /* Should not happen. This function called upon interrupt
4350 * triggered by GPIO ( since EPIO can only generate interrupts
4351 * to MCP).
4352 * So if this function was called and none of the GPIOs was set,
4353 * it means the shit hit the fan.
4354 */
4355 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4356 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4357 DP(NETIF_MSG_LINK,
4358 "No cfg pin %x for module detect indication\n",
4359 cfg_pin);
4360 return -EINVAL;
4361 }
4362
4363 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4364 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4365 } else {
4366 *gpio_num = MISC_REGISTERS_GPIO_3;
4367 *gpio_port = port;
4368 }
4369
4370 return 0;
4371 }
4372
bnx2x_is_sfp_module_plugged(struct bnx2x_phy * phy,struct link_params * params)4373 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4374 struct link_params *params)
4375 {
4376 struct bnx2x *bp = params->bp;
4377 u8 gpio_num, gpio_port;
4378 u32 gpio_val;
4379 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4380 params->shmem_base, params->port,
4381 &gpio_num, &gpio_port) != 0)
4382 return 0;
4383 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4384
4385 /* Call the handling function in case module is detected */
4386 if (gpio_val == 0)
4387 return 1;
4388 else
4389 return 0;
4390 }
bnx2x_warpcore_get_sigdet(struct bnx2x_phy * phy,struct link_params * params)4391 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4392 struct link_params *params)
4393 {
4394 u16 gp2_status_reg0, lane;
4395 struct bnx2x *bp = params->bp;
4396
4397 lane = bnx2x_get_warpcore_lane(phy, params);
4398
4399 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4400 &gp2_status_reg0);
4401
4402 return (gp2_status_reg0 >> (8+lane)) & 0x1;
4403 }
4404
bnx2x_warpcore_config_runtime(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)4405 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4406 struct link_params *params,
4407 struct link_vars *vars)
4408 {
4409 struct bnx2x *bp = params->bp;
4410 u32 serdes_net_if;
4411 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4412
4413 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4414
4415 if (!vars->turn_to_run_wc_rt)
4416 return;
4417
4418 if (vars->rx_tx_asic_rst) {
4419 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4420 serdes_net_if = (REG_RD(bp, params->shmem_base +
4421 offsetof(struct shmem_region, dev_info.
4422 port_hw_config[params->port].default_cfg)) &
4423 PORT_HW_CFG_NET_SERDES_IF_MASK);
4424
4425 switch (serdes_net_if) {
4426 case PORT_HW_CFG_NET_SERDES_IF_KR:
4427 /* Do we get link yet? */
4428 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4429 &gp_status1);
4430 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4431 /*10G KR*/
4432 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4433
4434 if (lnkup_kr || lnkup) {
4435 vars->rx_tx_asic_rst = 0;
4436 } else {
4437 /* Reset the lane to see if link comes up.*/
4438 bnx2x_warpcore_reset_lane(bp, phy, 1);
4439 bnx2x_warpcore_reset_lane(bp, phy, 0);
4440
4441 /* Restart Autoneg */
4442 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4443 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4444
4445 vars->rx_tx_asic_rst--;
4446 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4447 vars->rx_tx_asic_rst);
4448 }
4449 break;
4450
4451 default:
4452 break;
4453 }
4454
4455 } /*params->rx_tx_asic_rst*/
4456
4457 }
bnx2x_warpcore_config_sfi(struct bnx2x_phy * phy,struct link_params * params)4458 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4459 struct link_params *params)
4460 {
4461 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4462 struct bnx2x *bp = params->bp;
4463 bnx2x_warpcore_clear_regs(phy, params, lane);
4464 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4465 SPEED_10000) &&
4466 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4467 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4468 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4469 } else {
4470 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4471 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4472 }
4473 }
4474
bnx2x_sfp_e3_set_transmitter(struct link_params * params,struct bnx2x_phy * phy,u8 tx_en)4475 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4476 struct bnx2x_phy *phy,
4477 u8 tx_en)
4478 {
4479 struct bnx2x *bp = params->bp;
4480 u32 cfg_pin;
4481 u8 port = params->port;
4482
4483 cfg_pin = REG_RD(bp, params->shmem_base +
4484 offsetof(struct shmem_region,
4485 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4486 PORT_HW_CFG_E3_TX_LASER_MASK;
4487 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4488 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4489
4490 /* For 20G, the expected pin to be used is 3 pins after the current */
4491 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4492 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4493 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4494 }
4495
bnx2x_warpcore_config_init(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)4496 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4497 struct link_params *params,
4498 struct link_vars *vars)
4499 {
4500 struct bnx2x *bp = params->bp;
4501 u32 serdes_net_if;
4502 u8 fiber_mode;
4503 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4504 serdes_net_if = (REG_RD(bp, params->shmem_base +
4505 offsetof(struct shmem_region, dev_info.
4506 port_hw_config[params->port].default_cfg)) &
4507 PORT_HW_CFG_NET_SERDES_IF_MASK);
4508 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4509 "serdes_net_if = 0x%x\n",
4510 vars->line_speed, serdes_net_if);
4511 bnx2x_set_aer_mmd(params, phy);
4512 bnx2x_warpcore_reset_lane(bp, phy, 1);
4513 vars->phy_flags |= PHY_XGXS_FLAG;
4514 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4515 (phy->req_line_speed &&
4516 ((phy->req_line_speed == SPEED_100) ||
4517 (phy->req_line_speed == SPEED_10)))) {
4518 vars->phy_flags |= PHY_SGMII_FLAG;
4519 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4520 bnx2x_warpcore_clear_regs(phy, params, lane);
4521 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4522 } else {
4523 switch (serdes_net_if) {
4524 case PORT_HW_CFG_NET_SERDES_IF_KR:
4525 /* Enable KR Auto Neg */
4526 if (params->loopback_mode != LOOPBACK_EXT)
4527 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4528 else {
4529 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4530 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4531 }
4532 break;
4533
4534 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4535 bnx2x_warpcore_clear_regs(phy, params, lane);
4536 if (vars->line_speed == SPEED_10000) {
4537 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4538 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4539 } else {
4540 if (SINGLE_MEDIA_DIRECT(params)) {
4541 DP(NETIF_MSG_LINK, "1G Fiber\n");
4542 fiber_mode = 1;
4543 } else {
4544 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4545 fiber_mode = 0;
4546 }
4547 bnx2x_warpcore_set_sgmii_speed(phy,
4548 params,
4549 fiber_mode,
4550 0);
4551 }
4552
4553 break;
4554
4555 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4556 /* Issue Module detection if module is plugged, or
4557 * enabled transmitter to avoid current leakage in case
4558 * no module is connected
4559 */
4560 if ((params->loopback_mode == LOOPBACK_NONE) ||
4561 (params->loopback_mode == LOOPBACK_EXT)) {
4562 if (bnx2x_is_sfp_module_plugged(phy, params))
4563 bnx2x_sfp_module_detection(phy, params);
4564 else
4565 bnx2x_sfp_e3_set_transmitter(params,
4566 phy, 1);
4567 }
4568
4569 bnx2x_warpcore_config_sfi(phy, params);
4570 break;
4571
4572 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4573 if (vars->line_speed != SPEED_20000) {
4574 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4575 return;
4576 }
4577 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4578 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4579 /* Issue Module detection */
4580
4581 bnx2x_sfp_module_detection(phy, params);
4582 break;
4583 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4584 if (!params->loopback_mode) {
4585 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4586 } else {
4587 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4588 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4589 }
4590 break;
4591 default:
4592 DP(NETIF_MSG_LINK,
4593 "Unsupported Serdes Net Interface 0x%x\n",
4594 serdes_net_if);
4595 return;
4596 }
4597 }
4598
4599 /* Take lane out of reset after configuration is finished */
4600 bnx2x_warpcore_reset_lane(bp, phy, 0);
4601 DP(NETIF_MSG_LINK, "Exit config init\n");
4602 }
4603
bnx2x_warpcore_link_reset(struct bnx2x_phy * phy,struct link_params * params)4604 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4605 struct link_params *params)
4606 {
4607 struct bnx2x *bp = params->bp;
4608 u16 val16, lane;
4609 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4610 bnx2x_set_mdio_emac_per_phy(bp, params);
4611 bnx2x_set_aer_mmd(params, phy);
4612 /* Global register */
4613 bnx2x_warpcore_reset_lane(bp, phy, 1);
4614
4615 /* Clear loopback settings (if any) */
4616 /* 10G & 20G */
4617 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4618 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4619
4620 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4621 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4622
4623 /* Update those 1-copy registers */
4624 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4625 MDIO_AER_BLOCK_AER_REG, 0);
4626 /* Enable 1G MDIO (1-copy) */
4627 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4628 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4629 ~0x10);
4630
4631 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4632 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4633 lane = bnx2x_get_warpcore_lane(phy, params);
4634 /* Disable CL36 PCS Tx */
4635 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4636 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4637 val16 |= (0x11 << lane);
4638 if (phy->flags & FLAGS_WC_DUAL_MODE)
4639 val16 |= (0x22 << lane);
4640 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4641 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4642
4643 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4644 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4645 val16 &= ~(0x0303 << (lane << 1));
4646 val16 |= (0x0101 << (lane << 1));
4647 if (phy->flags & FLAGS_WC_DUAL_MODE) {
4648 val16 &= ~(0x0c0c << (lane << 1));
4649 val16 |= (0x0404 << (lane << 1));
4650 }
4651
4652 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4653 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4654 /* Restore AER */
4655 bnx2x_set_aer_mmd(params, phy);
4656
4657 }
4658
bnx2x_set_warpcore_loopback(struct bnx2x_phy * phy,struct link_params * params)4659 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4660 struct link_params *params)
4661 {
4662 struct bnx2x *bp = params->bp;
4663 u16 val16;
4664 u32 lane;
4665 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4666 params->loopback_mode, phy->req_line_speed);
4667
4668 if (phy->req_line_speed < SPEED_10000 ||
4669 phy->supported & SUPPORTED_20000baseKR2_Full) {
4670 /* 10/100/1000/20G-KR2 */
4671
4672 /* Update those 1-copy registers */
4673 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4674 MDIO_AER_BLOCK_AER_REG, 0);
4675 /* Enable 1G MDIO (1-copy) */
4676 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4677 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4678 0x10);
4679 /* Set 1G loopback based on lane (1-copy) */
4680 lane = bnx2x_get_warpcore_lane(phy, params);
4681 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4682 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4683 val16 |= (1<<lane);
4684 if (phy->flags & FLAGS_WC_DUAL_MODE)
4685 val16 |= (2<<lane);
4686 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4687 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4688 val16);
4689
4690 /* Switch back to 4-copy registers */
4691 bnx2x_set_aer_mmd(params, phy);
4692 } else {
4693 /* 10G / 20G-DXGXS */
4694 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4695 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4696 0x4000);
4697 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4698 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4699 }
4700 }
4701
4702
4703
bnx2x_sync_link(struct link_params * params,struct link_vars * vars)4704 static void bnx2x_sync_link(struct link_params *params,
4705 struct link_vars *vars)
4706 {
4707 struct bnx2x *bp = params->bp;
4708 u8 link_10g_plus;
4709 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4710 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4711 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4712 if (vars->link_up) {
4713 DP(NETIF_MSG_LINK, "phy link up\n");
4714
4715 vars->phy_link_up = 1;
4716 vars->duplex = DUPLEX_FULL;
4717 switch (vars->link_status &
4718 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4719 case LINK_10THD:
4720 vars->duplex = DUPLEX_HALF;
4721 /* Fall thru */
4722 case LINK_10TFD:
4723 vars->line_speed = SPEED_10;
4724 break;
4725
4726 case LINK_100TXHD:
4727 vars->duplex = DUPLEX_HALF;
4728 /* Fall thru */
4729 case LINK_100T4:
4730 case LINK_100TXFD:
4731 vars->line_speed = SPEED_100;
4732 break;
4733
4734 case LINK_1000THD:
4735 vars->duplex = DUPLEX_HALF;
4736 /* Fall thru */
4737 case LINK_1000TFD:
4738 vars->line_speed = SPEED_1000;
4739 break;
4740
4741 case LINK_2500THD:
4742 vars->duplex = DUPLEX_HALF;
4743 /* Fall thru */
4744 case LINK_2500TFD:
4745 vars->line_speed = SPEED_2500;
4746 break;
4747
4748 case LINK_10GTFD:
4749 vars->line_speed = SPEED_10000;
4750 break;
4751 case LINK_20GTFD:
4752 vars->line_speed = SPEED_20000;
4753 break;
4754 default:
4755 break;
4756 }
4757 vars->flow_ctrl = 0;
4758 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4759 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4760
4761 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4762 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4763
4764 if (!vars->flow_ctrl)
4765 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4766
4767 if (vars->line_speed &&
4768 ((vars->line_speed == SPEED_10) ||
4769 (vars->line_speed == SPEED_100))) {
4770 vars->phy_flags |= PHY_SGMII_FLAG;
4771 } else {
4772 vars->phy_flags &= ~PHY_SGMII_FLAG;
4773 }
4774 if (vars->line_speed &&
4775 USES_WARPCORE(bp) &&
4776 (vars->line_speed == SPEED_1000))
4777 vars->phy_flags |= PHY_SGMII_FLAG;
4778 /* Anything 10 and over uses the bmac */
4779 link_10g_plus = (vars->line_speed >= SPEED_10000);
4780
4781 if (link_10g_plus) {
4782 if (USES_WARPCORE(bp))
4783 vars->mac_type = MAC_TYPE_XMAC;
4784 else
4785 vars->mac_type = MAC_TYPE_BMAC;
4786 } else {
4787 if (USES_WARPCORE(bp))
4788 vars->mac_type = MAC_TYPE_UMAC;
4789 else
4790 vars->mac_type = MAC_TYPE_EMAC;
4791 }
4792 } else { /* Link down */
4793 DP(NETIF_MSG_LINK, "phy link down\n");
4794
4795 vars->phy_link_up = 0;
4796
4797 vars->line_speed = 0;
4798 vars->duplex = DUPLEX_FULL;
4799 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4800
4801 /* Indicate no mac active */
4802 vars->mac_type = MAC_TYPE_NONE;
4803 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4804 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4805 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4806 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4807 }
4808 }
4809
bnx2x_link_status_update(struct link_params * params,struct link_vars * vars)4810 void bnx2x_link_status_update(struct link_params *params,
4811 struct link_vars *vars)
4812 {
4813 struct bnx2x *bp = params->bp;
4814 u8 port = params->port;
4815 u32 sync_offset, media_types;
4816 /* Update PHY configuration */
4817 set_phy_vars(params, vars);
4818
4819 vars->link_status = REG_RD(bp, params->shmem_base +
4820 offsetof(struct shmem_region,
4821 port_mb[port].link_status));
4822
4823 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4824 if (params->loopback_mode != LOOPBACK_NONE &&
4825 params->loopback_mode != LOOPBACK_EXT)
4826 vars->link_status |= LINK_STATUS_LINK_UP;
4827
4828 if (bnx2x_eee_has_cap(params))
4829 vars->eee_status = REG_RD(bp, params->shmem2_base +
4830 offsetof(struct shmem2_region,
4831 eee_status[params->port]));
4832
4833 vars->phy_flags = PHY_XGXS_FLAG;
4834 bnx2x_sync_link(params, vars);
4835 /* Sync media type */
4836 sync_offset = params->shmem_base +
4837 offsetof(struct shmem_region,
4838 dev_info.port_hw_config[port].media_type);
4839 media_types = REG_RD(bp, sync_offset);
4840
4841 params->phy[INT_PHY].media_type =
4842 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4843 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4844 params->phy[EXT_PHY1].media_type =
4845 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4846 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4847 params->phy[EXT_PHY2].media_type =
4848 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4849 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4850 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4851
4852 /* Sync AEU offset */
4853 sync_offset = params->shmem_base +
4854 offsetof(struct shmem_region,
4855 dev_info.port_hw_config[port].aeu_int_mask);
4856
4857 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4858
4859 /* Sync PFC status */
4860 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4861 params->feature_config_flags |=
4862 FEATURE_CONFIG_PFC_ENABLED;
4863 else
4864 params->feature_config_flags &=
4865 ~FEATURE_CONFIG_PFC_ENABLED;
4866
4867 if (SHMEM2_HAS(bp, link_attr_sync))
4868 params->link_attr_sync = SHMEM2_RD(bp,
4869 link_attr_sync[params->port]);
4870
4871 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4872 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4873 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4874 vars->line_speed, vars->duplex, vars->flow_ctrl);
4875 }
4876
bnx2x_set_master_ln(struct link_params * params,struct bnx2x_phy * phy)4877 static void bnx2x_set_master_ln(struct link_params *params,
4878 struct bnx2x_phy *phy)
4879 {
4880 struct bnx2x *bp = params->bp;
4881 u16 new_master_ln, ser_lane;
4882 ser_lane = ((params->lane_config &
4883 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4884 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4885
4886 /* Set the master_ln for AN */
4887 CL22_RD_OVER_CL45(bp, phy,
4888 MDIO_REG_BANK_XGXS_BLOCK2,
4889 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4890 &new_master_ln);
4891
4892 CL22_WR_OVER_CL45(bp, phy,
4893 MDIO_REG_BANK_XGXS_BLOCK2 ,
4894 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4895 (new_master_ln | ser_lane));
4896 }
4897
bnx2x_reset_unicore(struct link_params * params,struct bnx2x_phy * phy,u8 set_serdes)4898 static int bnx2x_reset_unicore(struct link_params *params,
4899 struct bnx2x_phy *phy,
4900 u8 set_serdes)
4901 {
4902 struct bnx2x *bp = params->bp;
4903 u16 mii_control;
4904 u16 i;
4905 CL22_RD_OVER_CL45(bp, phy,
4906 MDIO_REG_BANK_COMBO_IEEE0,
4907 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4908
4909 /* Reset the unicore */
4910 CL22_WR_OVER_CL45(bp, phy,
4911 MDIO_REG_BANK_COMBO_IEEE0,
4912 MDIO_COMBO_IEEE0_MII_CONTROL,
4913 (mii_control |
4914 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4915 if (set_serdes)
4916 bnx2x_set_serdes_access(bp, params->port);
4917
4918 /* Wait for the reset to self clear */
4919 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4920 udelay(5);
4921
4922 /* The reset erased the previous bank value */
4923 CL22_RD_OVER_CL45(bp, phy,
4924 MDIO_REG_BANK_COMBO_IEEE0,
4925 MDIO_COMBO_IEEE0_MII_CONTROL,
4926 &mii_control);
4927
4928 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4929 udelay(5);
4930 return 0;
4931 }
4932 }
4933
4934 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4935 " Port %d\n",
4936 params->port);
4937 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4938 return -EINVAL;
4939
4940 }
4941
bnx2x_set_swap_lanes(struct link_params * params,struct bnx2x_phy * phy)4942 static void bnx2x_set_swap_lanes(struct link_params *params,
4943 struct bnx2x_phy *phy)
4944 {
4945 struct bnx2x *bp = params->bp;
4946 /* Each two bits represents a lane number:
4947 * No swap is 0123 => 0x1b no need to enable the swap
4948 */
4949 u16 rx_lane_swap, tx_lane_swap;
4950
4951 rx_lane_swap = ((params->lane_config &
4952 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4953 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4954 tx_lane_swap = ((params->lane_config &
4955 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4956 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4957
4958 if (rx_lane_swap != 0x1b) {
4959 CL22_WR_OVER_CL45(bp, phy,
4960 MDIO_REG_BANK_XGXS_BLOCK2,
4961 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4962 (rx_lane_swap |
4963 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4964 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4965 } else {
4966 CL22_WR_OVER_CL45(bp, phy,
4967 MDIO_REG_BANK_XGXS_BLOCK2,
4968 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4969 }
4970
4971 if (tx_lane_swap != 0x1b) {
4972 CL22_WR_OVER_CL45(bp, phy,
4973 MDIO_REG_BANK_XGXS_BLOCK2,
4974 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4975 (tx_lane_swap |
4976 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4977 } else {
4978 CL22_WR_OVER_CL45(bp, phy,
4979 MDIO_REG_BANK_XGXS_BLOCK2,
4980 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4981 }
4982 }
4983
bnx2x_set_parallel_detection(struct bnx2x_phy * phy,struct link_params * params)4984 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4985 struct link_params *params)
4986 {
4987 struct bnx2x *bp = params->bp;
4988 u16 control2;
4989 CL22_RD_OVER_CL45(bp, phy,
4990 MDIO_REG_BANK_SERDES_DIGITAL,
4991 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4992 &control2);
4993 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4994 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4995 else
4996 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4997 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4998 phy->speed_cap_mask, control2);
4999 CL22_WR_OVER_CL45(bp, phy,
5000 MDIO_REG_BANK_SERDES_DIGITAL,
5001 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
5002 control2);
5003
5004 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
5005 (phy->speed_cap_mask &
5006 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5007 DP(NETIF_MSG_LINK, "XGXS\n");
5008
5009 CL22_WR_OVER_CL45(bp, phy,
5010 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5011 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
5012 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
5013
5014 CL22_RD_OVER_CL45(bp, phy,
5015 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5016 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5017 &control2);
5018
5019
5020 control2 |=
5021 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
5022
5023 CL22_WR_OVER_CL45(bp, phy,
5024 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5025 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5026 control2);
5027
5028 /* Disable parallel detection of HiG */
5029 CL22_WR_OVER_CL45(bp, phy,
5030 MDIO_REG_BANK_XGXS_BLOCK2,
5031 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
5032 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
5033 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
5034 }
5035 }
5036
bnx2x_set_autoneg(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars,u8 enable_cl73)5037 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
5038 struct link_params *params,
5039 struct link_vars *vars,
5040 u8 enable_cl73)
5041 {
5042 struct bnx2x *bp = params->bp;
5043 u16 reg_val;
5044
5045 /* CL37 Autoneg */
5046 CL22_RD_OVER_CL45(bp, phy,
5047 MDIO_REG_BANK_COMBO_IEEE0,
5048 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5049
5050 /* CL37 Autoneg Enabled */
5051 if (vars->line_speed == SPEED_AUTO_NEG)
5052 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5053 else /* CL37 Autoneg Disabled */
5054 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5055 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5056
5057 CL22_WR_OVER_CL45(bp, phy,
5058 MDIO_REG_BANK_COMBO_IEEE0,
5059 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5060
5061 /* Enable/Disable Autodetection */
5062
5063 CL22_RD_OVER_CL45(bp, phy,
5064 MDIO_REG_BANK_SERDES_DIGITAL,
5065 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
5066 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5067 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5068 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5069 if (vars->line_speed == SPEED_AUTO_NEG)
5070 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5071 else
5072 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5073
5074 CL22_WR_OVER_CL45(bp, phy,
5075 MDIO_REG_BANK_SERDES_DIGITAL,
5076 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5077
5078 /* Enable TetonII and BAM autoneg */
5079 CL22_RD_OVER_CL45(bp, phy,
5080 MDIO_REG_BANK_BAM_NEXT_PAGE,
5081 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5082 ®_val);
5083 if (vars->line_speed == SPEED_AUTO_NEG) {
5084 /* Enable BAM aneg Mode and TetonII aneg Mode */
5085 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5086 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5087 } else {
5088 /* TetonII and BAM Autoneg Disabled */
5089 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5090 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5091 }
5092 CL22_WR_OVER_CL45(bp, phy,
5093 MDIO_REG_BANK_BAM_NEXT_PAGE,
5094 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5095 reg_val);
5096
5097 if (enable_cl73) {
5098 /* Enable Cl73 FSM status bits */
5099 CL22_WR_OVER_CL45(bp, phy,
5100 MDIO_REG_BANK_CL73_USERB0,
5101 MDIO_CL73_USERB0_CL73_UCTRL,
5102 0xe);
5103
5104 /* Enable BAM Station Manager*/
5105 CL22_WR_OVER_CL45(bp, phy,
5106 MDIO_REG_BANK_CL73_USERB0,
5107 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5108 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5109 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5110 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5111
5112 /* Advertise CL73 link speeds */
5113 CL22_RD_OVER_CL45(bp, phy,
5114 MDIO_REG_BANK_CL73_IEEEB1,
5115 MDIO_CL73_IEEEB1_AN_ADV2,
5116 ®_val);
5117 if (phy->speed_cap_mask &
5118 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5119 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5120 if (phy->speed_cap_mask &
5121 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5122 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5123
5124 CL22_WR_OVER_CL45(bp, phy,
5125 MDIO_REG_BANK_CL73_IEEEB1,
5126 MDIO_CL73_IEEEB1_AN_ADV2,
5127 reg_val);
5128
5129 /* CL73 Autoneg Enabled */
5130 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5131
5132 } else /* CL73 Autoneg Disabled */
5133 reg_val = 0;
5134
5135 CL22_WR_OVER_CL45(bp, phy,
5136 MDIO_REG_BANK_CL73_IEEEB0,
5137 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5138 }
5139
5140 /* Program SerDes, forced speed */
bnx2x_program_serdes(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)5141 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5142 struct link_params *params,
5143 struct link_vars *vars)
5144 {
5145 struct bnx2x *bp = params->bp;
5146 u16 reg_val;
5147
5148 /* Program duplex, disable autoneg and sgmii*/
5149 CL22_RD_OVER_CL45(bp, phy,
5150 MDIO_REG_BANK_COMBO_IEEE0,
5151 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5152 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5153 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5154 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5155 if (phy->req_duplex == DUPLEX_FULL)
5156 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5157 CL22_WR_OVER_CL45(bp, phy,
5158 MDIO_REG_BANK_COMBO_IEEE0,
5159 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5160
5161 /* Program speed
5162 * - needed only if the speed is greater than 1G (2.5G or 10G)
5163 */
5164 CL22_RD_OVER_CL45(bp, phy,
5165 MDIO_REG_BANK_SERDES_DIGITAL,
5166 MDIO_SERDES_DIGITAL_MISC1, ®_val);
5167 /* Clearing the speed value before setting the right speed */
5168 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5169
5170 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5171 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5172
5173 if (!((vars->line_speed == SPEED_1000) ||
5174 (vars->line_speed == SPEED_100) ||
5175 (vars->line_speed == SPEED_10))) {
5176
5177 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5178 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5179 if (vars->line_speed == SPEED_10000)
5180 reg_val |=
5181 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5182 }
5183
5184 CL22_WR_OVER_CL45(bp, phy,
5185 MDIO_REG_BANK_SERDES_DIGITAL,
5186 MDIO_SERDES_DIGITAL_MISC1, reg_val);
5187
5188 }
5189
bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy * phy,struct link_params * params)5190 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5191 struct link_params *params)
5192 {
5193 struct bnx2x *bp = params->bp;
5194 u16 val = 0;
5195
5196 /* Set extended capabilities */
5197 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5198 val |= MDIO_OVER_1G_UP1_2_5G;
5199 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5200 val |= MDIO_OVER_1G_UP1_10G;
5201 CL22_WR_OVER_CL45(bp, phy,
5202 MDIO_REG_BANK_OVER_1G,
5203 MDIO_OVER_1G_UP1, val);
5204
5205 CL22_WR_OVER_CL45(bp, phy,
5206 MDIO_REG_BANK_OVER_1G,
5207 MDIO_OVER_1G_UP3, 0x400);
5208 }
5209
bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy * phy,struct link_params * params,u16 ieee_fc)5210 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5211 struct link_params *params,
5212 u16 ieee_fc)
5213 {
5214 struct bnx2x *bp = params->bp;
5215 u16 val;
5216 /* For AN, we are always publishing full duplex */
5217
5218 CL22_WR_OVER_CL45(bp, phy,
5219 MDIO_REG_BANK_COMBO_IEEE0,
5220 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5221 CL22_RD_OVER_CL45(bp, phy,
5222 MDIO_REG_BANK_CL73_IEEEB1,
5223 MDIO_CL73_IEEEB1_AN_ADV1, &val);
5224 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5225 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5226 CL22_WR_OVER_CL45(bp, phy,
5227 MDIO_REG_BANK_CL73_IEEEB1,
5228 MDIO_CL73_IEEEB1_AN_ADV1, val);
5229 }
5230
bnx2x_restart_autoneg(struct bnx2x_phy * phy,struct link_params * params,u8 enable_cl73)5231 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5232 struct link_params *params,
5233 u8 enable_cl73)
5234 {
5235 struct bnx2x *bp = params->bp;
5236 u16 mii_control;
5237
5238 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5239 /* Enable and restart BAM/CL37 aneg */
5240
5241 if (enable_cl73) {
5242 CL22_RD_OVER_CL45(bp, phy,
5243 MDIO_REG_BANK_CL73_IEEEB0,
5244 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5245 &mii_control);
5246
5247 CL22_WR_OVER_CL45(bp, phy,
5248 MDIO_REG_BANK_CL73_IEEEB0,
5249 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5250 (mii_control |
5251 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5252 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5253 } else {
5254
5255 CL22_RD_OVER_CL45(bp, phy,
5256 MDIO_REG_BANK_COMBO_IEEE0,
5257 MDIO_COMBO_IEEE0_MII_CONTROL,
5258 &mii_control);
5259 DP(NETIF_MSG_LINK,
5260 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5261 mii_control);
5262 CL22_WR_OVER_CL45(bp, phy,
5263 MDIO_REG_BANK_COMBO_IEEE0,
5264 MDIO_COMBO_IEEE0_MII_CONTROL,
5265 (mii_control |
5266 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5267 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5268 }
5269 }
5270
bnx2x_initialize_sgmii_process(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)5271 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5272 struct link_params *params,
5273 struct link_vars *vars)
5274 {
5275 struct bnx2x *bp = params->bp;
5276 u16 control1;
5277
5278 /* In SGMII mode, the unicore is always slave */
5279
5280 CL22_RD_OVER_CL45(bp, phy,
5281 MDIO_REG_BANK_SERDES_DIGITAL,
5282 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5283 &control1);
5284 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5285 /* Set sgmii mode (and not fiber) */
5286 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5287 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5288 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5289 CL22_WR_OVER_CL45(bp, phy,
5290 MDIO_REG_BANK_SERDES_DIGITAL,
5291 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5292 control1);
5293
5294 /* If forced speed */
5295 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5296 /* Set speed, disable autoneg */
5297 u16 mii_control;
5298
5299 CL22_RD_OVER_CL45(bp, phy,
5300 MDIO_REG_BANK_COMBO_IEEE0,
5301 MDIO_COMBO_IEEE0_MII_CONTROL,
5302 &mii_control);
5303 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5304 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5305 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5306
5307 switch (vars->line_speed) {
5308 case SPEED_100:
5309 mii_control |=
5310 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5311 break;
5312 case SPEED_1000:
5313 mii_control |=
5314 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5315 break;
5316 case SPEED_10:
5317 /* There is nothing to set for 10M */
5318 break;
5319 default:
5320 /* Invalid speed for SGMII */
5321 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5322 vars->line_speed);
5323 break;
5324 }
5325
5326 /* Setting the full duplex */
5327 if (phy->req_duplex == DUPLEX_FULL)
5328 mii_control |=
5329 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5330 CL22_WR_OVER_CL45(bp, phy,
5331 MDIO_REG_BANK_COMBO_IEEE0,
5332 MDIO_COMBO_IEEE0_MII_CONTROL,
5333 mii_control);
5334
5335 } else { /* AN mode */
5336 /* Enable and restart AN */
5337 bnx2x_restart_autoneg(phy, params, 0);
5338 }
5339 }
5340
5341 /* Link management
5342 */
bnx2x_direct_parallel_detect_used(struct bnx2x_phy * phy,struct link_params * params)5343 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5344 struct link_params *params)
5345 {
5346 struct bnx2x *bp = params->bp;
5347 u16 pd_10g, status2_1000x;
5348 if (phy->req_line_speed != SPEED_AUTO_NEG)
5349 return 0;
5350 CL22_RD_OVER_CL45(bp, phy,
5351 MDIO_REG_BANK_SERDES_DIGITAL,
5352 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5353 &status2_1000x);
5354 CL22_RD_OVER_CL45(bp, phy,
5355 MDIO_REG_BANK_SERDES_DIGITAL,
5356 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5357 &status2_1000x);
5358 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5359 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5360 params->port);
5361 return 1;
5362 }
5363
5364 CL22_RD_OVER_CL45(bp, phy,
5365 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5366 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5367 &pd_10g);
5368
5369 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5370 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5371 params->port);
5372 return 1;
5373 }
5374 return 0;
5375 }
5376
bnx2x_update_adv_fc(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars,u32 gp_status)5377 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5378 struct link_params *params,
5379 struct link_vars *vars,
5380 u32 gp_status)
5381 {
5382 u16 ld_pause; /* local driver */
5383 u16 lp_pause; /* link partner */
5384 u16 pause_result;
5385 struct bnx2x *bp = params->bp;
5386 if ((gp_status &
5387 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5388 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5389 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5390 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5391
5392 CL22_RD_OVER_CL45(bp, phy,
5393 MDIO_REG_BANK_CL73_IEEEB1,
5394 MDIO_CL73_IEEEB1_AN_ADV1,
5395 &ld_pause);
5396 CL22_RD_OVER_CL45(bp, phy,
5397 MDIO_REG_BANK_CL73_IEEEB1,
5398 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5399 &lp_pause);
5400 pause_result = (ld_pause &
5401 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5402 pause_result |= (lp_pause &
5403 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5404 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5405 } else {
5406 CL22_RD_OVER_CL45(bp, phy,
5407 MDIO_REG_BANK_COMBO_IEEE0,
5408 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5409 &ld_pause);
5410 CL22_RD_OVER_CL45(bp, phy,
5411 MDIO_REG_BANK_COMBO_IEEE0,
5412 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5413 &lp_pause);
5414 pause_result = (ld_pause &
5415 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5416 pause_result |= (lp_pause &
5417 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5418 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5419 }
5420 bnx2x_pause_resolve(phy, params, vars, pause_result);
5421
5422 }
5423
bnx2x_flow_ctrl_resolve(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars,u32 gp_status)5424 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5425 struct link_params *params,
5426 struct link_vars *vars,
5427 u32 gp_status)
5428 {
5429 struct bnx2x *bp = params->bp;
5430 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5431
5432 /* Resolve from gp_status in case of AN complete and not sgmii */
5433 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5434 /* Update the advertised flow-controled of LD/LP in AN */
5435 if (phy->req_line_speed == SPEED_AUTO_NEG)
5436 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5437 /* But set the flow-control result as the requested one */
5438 vars->flow_ctrl = phy->req_flow_ctrl;
5439 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5440 vars->flow_ctrl = params->req_fc_auto_adv;
5441 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5442 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5443 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5444 vars->flow_ctrl = params->req_fc_auto_adv;
5445 return;
5446 }
5447 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5448 }
5449 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5450 }
5451
bnx2x_check_fallback_to_cl37(struct bnx2x_phy * phy,struct link_params * params)5452 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5453 struct link_params *params)
5454 {
5455 struct bnx2x *bp = params->bp;
5456 u16 rx_status, ustat_val, cl37_fsm_received;
5457 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5458 /* Step 1: Make sure signal is detected */
5459 CL22_RD_OVER_CL45(bp, phy,
5460 MDIO_REG_BANK_RX0,
5461 MDIO_RX0_RX_STATUS,
5462 &rx_status);
5463 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5464 (MDIO_RX0_RX_STATUS_SIGDET)) {
5465 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5466 "rx_status(0x80b0) = 0x%x\n", rx_status);
5467 CL22_WR_OVER_CL45(bp, phy,
5468 MDIO_REG_BANK_CL73_IEEEB0,
5469 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5470 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5471 return;
5472 }
5473 /* Step 2: Check CL73 state machine */
5474 CL22_RD_OVER_CL45(bp, phy,
5475 MDIO_REG_BANK_CL73_USERB0,
5476 MDIO_CL73_USERB0_CL73_USTAT1,
5477 &ustat_val);
5478 if ((ustat_val &
5479 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5480 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5481 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5482 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5483 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5484 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5485 return;
5486 }
5487 /* Step 3: Check CL37 Message Pages received to indicate LP
5488 * supports only CL37
5489 */
5490 CL22_RD_OVER_CL45(bp, phy,
5491 MDIO_REG_BANK_REMOTE_PHY,
5492 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5493 &cl37_fsm_received);
5494 if ((cl37_fsm_received &
5495 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5496 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5497 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5498 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5499 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5500 "misc_rx_status(0x8330) = 0x%x\n",
5501 cl37_fsm_received);
5502 return;
5503 }
5504 /* The combined cl37/cl73 fsm state information indicating that
5505 * we are connected to a device which does not support cl73, but
5506 * does support cl37 BAM. In this case we disable cl73 and
5507 * restart cl37 auto-neg
5508 */
5509
5510 /* Disable CL73 */
5511 CL22_WR_OVER_CL45(bp, phy,
5512 MDIO_REG_BANK_CL73_IEEEB0,
5513 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5514 0);
5515 /* Restart CL37 autoneg */
5516 bnx2x_restart_autoneg(phy, params, 0);
5517 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5518 }
5519
bnx2x_xgxs_an_resolve(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars,u32 gp_status)5520 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5521 struct link_params *params,
5522 struct link_vars *vars,
5523 u32 gp_status)
5524 {
5525 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5526 vars->link_status |=
5527 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5528
5529 if (bnx2x_direct_parallel_detect_used(phy, params))
5530 vars->link_status |=
5531 LINK_STATUS_PARALLEL_DETECTION_USED;
5532 }
bnx2x_get_link_speed_duplex(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars,u16 is_link_up,u16 speed_mask,u16 is_duplex)5533 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5534 struct link_params *params,
5535 struct link_vars *vars,
5536 u16 is_link_up,
5537 u16 speed_mask,
5538 u16 is_duplex)
5539 {
5540 struct bnx2x *bp = params->bp;
5541 if (phy->req_line_speed == SPEED_AUTO_NEG)
5542 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5543 if (is_link_up) {
5544 DP(NETIF_MSG_LINK, "phy link up\n");
5545
5546 vars->phy_link_up = 1;
5547 vars->link_status |= LINK_STATUS_LINK_UP;
5548
5549 switch (speed_mask) {
5550 case GP_STATUS_10M:
5551 vars->line_speed = SPEED_10;
5552 if (is_duplex == DUPLEX_FULL)
5553 vars->link_status |= LINK_10TFD;
5554 else
5555 vars->link_status |= LINK_10THD;
5556 break;
5557
5558 case GP_STATUS_100M:
5559 vars->line_speed = SPEED_100;
5560 if (is_duplex == DUPLEX_FULL)
5561 vars->link_status |= LINK_100TXFD;
5562 else
5563 vars->link_status |= LINK_100TXHD;
5564 break;
5565
5566 case GP_STATUS_1G:
5567 case GP_STATUS_1G_KX:
5568 vars->line_speed = SPEED_1000;
5569 if (is_duplex == DUPLEX_FULL)
5570 vars->link_status |= LINK_1000TFD;
5571 else
5572 vars->link_status |= LINK_1000THD;
5573 break;
5574
5575 case GP_STATUS_2_5G:
5576 vars->line_speed = SPEED_2500;
5577 if (is_duplex == DUPLEX_FULL)
5578 vars->link_status |= LINK_2500TFD;
5579 else
5580 vars->link_status |= LINK_2500THD;
5581 break;
5582
5583 case GP_STATUS_5G:
5584 case GP_STATUS_6G:
5585 DP(NETIF_MSG_LINK,
5586 "link speed unsupported gp_status 0x%x\n",
5587 speed_mask);
5588 return -EINVAL;
5589
5590 case GP_STATUS_10G_KX4:
5591 case GP_STATUS_10G_HIG:
5592 case GP_STATUS_10G_CX4:
5593 case GP_STATUS_10G_KR:
5594 case GP_STATUS_10G_SFI:
5595 case GP_STATUS_10G_XFI:
5596 vars->line_speed = SPEED_10000;
5597 vars->link_status |= LINK_10GTFD;
5598 break;
5599 case GP_STATUS_20G_DXGXS:
5600 case GP_STATUS_20G_KR2:
5601 vars->line_speed = SPEED_20000;
5602 vars->link_status |= LINK_20GTFD;
5603 break;
5604 default:
5605 DP(NETIF_MSG_LINK,
5606 "link speed unsupported gp_status 0x%x\n",
5607 speed_mask);
5608 return -EINVAL;
5609 }
5610 } else { /* link_down */
5611 DP(NETIF_MSG_LINK, "phy link down\n");
5612
5613 vars->phy_link_up = 0;
5614
5615 vars->duplex = DUPLEX_FULL;
5616 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5617 vars->mac_type = MAC_TYPE_NONE;
5618 }
5619 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5620 vars->phy_link_up, vars->line_speed);
5621 return 0;
5622 }
5623
bnx2x_link_settings_status(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)5624 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5625 struct link_params *params,
5626 struct link_vars *vars)
5627 {
5628 struct bnx2x *bp = params->bp;
5629
5630 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5631 int rc = 0;
5632
5633 /* Read gp_status */
5634 CL22_RD_OVER_CL45(bp, phy,
5635 MDIO_REG_BANK_GP_STATUS,
5636 MDIO_GP_STATUS_TOP_AN_STATUS1,
5637 &gp_status);
5638 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5639 duplex = DUPLEX_FULL;
5640 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5641 link_up = 1;
5642 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5643 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5644 gp_status, link_up, speed_mask);
5645 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5646 duplex);
5647 if (rc == -EINVAL)
5648 return rc;
5649
5650 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5651 if (SINGLE_MEDIA_DIRECT(params)) {
5652 vars->duplex = duplex;
5653 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5654 if (phy->req_line_speed == SPEED_AUTO_NEG)
5655 bnx2x_xgxs_an_resolve(phy, params, vars,
5656 gp_status);
5657 }
5658 } else { /* Link_down */
5659 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5660 SINGLE_MEDIA_DIRECT(params)) {
5661 /* Check signal is detected */
5662 bnx2x_check_fallback_to_cl37(phy, params);
5663 }
5664 }
5665
5666 /* Read LP advertised speeds*/
5667 if (SINGLE_MEDIA_DIRECT(params) &&
5668 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5669 u16 val;
5670
5671 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5672 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5673
5674 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5675 vars->link_status |=
5676 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5677 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5678 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5679 vars->link_status |=
5680 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5681
5682 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5683 MDIO_OVER_1G_LP_UP1, &val);
5684
5685 if (val & MDIO_OVER_1G_UP1_2_5G)
5686 vars->link_status |=
5687 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5688 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5689 vars->link_status |=
5690 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5691 }
5692
5693 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5694 vars->duplex, vars->flow_ctrl, vars->link_status);
5695 return rc;
5696 }
5697
bnx2x_warpcore_read_status(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)5698 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5699 struct link_params *params,
5700 struct link_vars *vars)
5701 {
5702 struct bnx2x *bp = params->bp;
5703 u8 lane;
5704 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5705 int rc = 0;
5706 lane = bnx2x_get_warpcore_lane(phy, params);
5707 /* Read gp_status */
5708 if ((params->loopback_mode) &&
5709 (phy->flags & FLAGS_WC_DUAL_MODE)) {
5710 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5711 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5712 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5713 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5714 link_up &= 0x1;
5715 } else if ((phy->req_line_speed > SPEED_10000) &&
5716 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5717 u16 temp_link_up;
5718 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5719 1, &temp_link_up);
5720 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5721 1, &link_up);
5722 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5723 temp_link_up, link_up);
5724 link_up &= (1<<2);
5725 if (link_up)
5726 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5727 } else {
5728 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5729 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5730 &gp_status1);
5731 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5732 /* Check for either KR, 1G, or AN up. */
5733 link_up = ((gp_status1 >> 8) |
5734 (gp_status1 >> 12) |
5735 (gp_status1)) &
5736 (1 << lane);
5737 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5738 u16 an_link;
5739 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5740 MDIO_AN_REG_STATUS, &an_link);
5741 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5742 MDIO_AN_REG_STATUS, &an_link);
5743 link_up |= (an_link & (1<<2));
5744 }
5745 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5746 u16 pd, gp_status4;
5747 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5748 /* Check Autoneg complete */
5749 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5750 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5751 &gp_status4);
5752 if (gp_status4 & ((1<<12)<<lane))
5753 vars->link_status |=
5754 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5755
5756 /* Check parallel detect used */
5757 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5758 MDIO_WC_REG_PAR_DET_10G_STATUS,
5759 &pd);
5760 if (pd & (1<<15))
5761 vars->link_status |=
5762 LINK_STATUS_PARALLEL_DETECTION_USED;
5763 }
5764 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5765 vars->duplex = duplex;
5766 }
5767 }
5768
5769 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5770 SINGLE_MEDIA_DIRECT(params)) {
5771 u16 val;
5772
5773 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5774 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5775
5776 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5777 vars->link_status |=
5778 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5779 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5780 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5781 vars->link_status |=
5782 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5783
5784 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5785 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5786
5787 if (val & MDIO_OVER_1G_UP1_2_5G)
5788 vars->link_status |=
5789 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5790 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5791 vars->link_status |=
5792 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5793
5794 }
5795
5796
5797 if (lane < 2) {
5798 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5799 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5800 } else {
5801 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5802 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5803 }
5804 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5805
5806 if ((lane & 1) == 0)
5807 gp_speed <<= 8;
5808 gp_speed &= 0x3f00;
5809 link_up = !!link_up;
5810
5811 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5812 duplex);
5813
5814 /* In case of KR link down, start up the recovering procedure */
5815 if ((!link_up) && (phy->media_type == ETH_PHY_KR) &&
5816 (!(phy->flags & FLAGS_WC_DUAL_MODE)))
5817 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5818
5819 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5820 vars->duplex, vars->flow_ctrl, vars->link_status);
5821 return rc;
5822 }
bnx2x_set_gmii_tx_driver(struct link_params * params)5823 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5824 {
5825 struct bnx2x *bp = params->bp;
5826 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
5827 u16 lp_up2;
5828 u16 tx_driver;
5829 u16 bank;
5830
5831 /* Read precomp */
5832 CL22_RD_OVER_CL45(bp, phy,
5833 MDIO_REG_BANK_OVER_1G,
5834 MDIO_OVER_1G_LP_UP2, &lp_up2);
5835
5836 /* Bits [10:7] at lp_up2, positioned at [15:12] */
5837 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5838 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5839 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5840
5841 if (lp_up2 == 0)
5842 return;
5843
5844 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5845 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5846 CL22_RD_OVER_CL45(bp, phy,
5847 bank,
5848 MDIO_TX0_TX_DRIVER, &tx_driver);
5849
5850 /* Replace tx_driver bits [15:12] */
5851 if (lp_up2 !=
5852 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5853 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5854 tx_driver |= lp_up2;
5855 CL22_WR_OVER_CL45(bp, phy,
5856 bank,
5857 MDIO_TX0_TX_DRIVER, tx_driver);
5858 }
5859 }
5860 }
5861
bnx2x_emac_program(struct link_params * params,struct link_vars * vars)5862 static int bnx2x_emac_program(struct link_params *params,
5863 struct link_vars *vars)
5864 {
5865 struct bnx2x *bp = params->bp;
5866 u8 port = params->port;
5867 u16 mode = 0;
5868
5869 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5870 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5871 EMAC_REG_EMAC_MODE,
5872 (EMAC_MODE_25G_MODE |
5873 EMAC_MODE_PORT_MII_10M |
5874 EMAC_MODE_HALF_DUPLEX));
5875 switch (vars->line_speed) {
5876 case SPEED_10:
5877 mode |= EMAC_MODE_PORT_MII_10M;
5878 break;
5879
5880 case SPEED_100:
5881 mode |= EMAC_MODE_PORT_MII;
5882 break;
5883
5884 case SPEED_1000:
5885 mode |= EMAC_MODE_PORT_GMII;
5886 break;
5887
5888 case SPEED_2500:
5889 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5890 break;
5891
5892 default:
5893 /* 10G not valid for EMAC */
5894 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5895 vars->line_speed);
5896 return -EINVAL;
5897 }
5898
5899 if (vars->duplex == DUPLEX_HALF)
5900 mode |= EMAC_MODE_HALF_DUPLEX;
5901 bnx2x_bits_en(bp,
5902 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5903 mode);
5904
5905 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5906 return 0;
5907 }
5908
bnx2x_set_preemphasis(struct bnx2x_phy * phy,struct link_params * params)5909 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5910 struct link_params *params)
5911 {
5912
5913 u16 bank, i = 0;
5914 struct bnx2x *bp = params->bp;
5915
5916 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5917 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5918 CL22_WR_OVER_CL45(bp, phy,
5919 bank,
5920 MDIO_RX0_RX_EQ_BOOST,
5921 phy->rx_preemphasis[i]);
5922 }
5923
5924 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5925 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5926 CL22_WR_OVER_CL45(bp, phy,
5927 bank,
5928 MDIO_TX0_TX_DRIVER,
5929 phy->tx_preemphasis[i]);
5930 }
5931 }
5932
bnx2x_xgxs_config_init(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)5933 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5934 struct link_params *params,
5935 struct link_vars *vars)
5936 {
5937 struct bnx2x *bp = params->bp;
5938 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5939 (params->loopback_mode == LOOPBACK_XGXS));
5940 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5941 if (SINGLE_MEDIA_DIRECT(params) &&
5942 (params->feature_config_flags &
5943 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5944 bnx2x_set_preemphasis(phy, params);
5945
5946 /* Forced speed requested? */
5947 if (vars->line_speed != SPEED_AUTO_NEG ||
5948 (SINGLE_MEDIA_DIRECT(params) &&
5949 params->loopback_mode == LOOPBACK_EXT)) {
5950 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5951
5952 /* Disable autoneg */
5953 bnx2x_set_autoneg(phy, params, vars, 0);
5954
5955 /* Program speed and duplex */
5956 bnx2x_program_serdes(phy, params, vars);
5957
5958 } else { /* AN_mode */
5959 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5960
5961 /* AN enabled */
5962 bnx2x_set_brcm_cl37_advertisement(phy, params);
5963
5964 /* Program duplex & pause advertisement (for aneg) */
5965 bnx2x_set_ieee_aneg_advertisement(phy, params,
5966 vars->ieee_fc);
5967
5968 /* Enable autoneg */
5969 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5970
5971 /* Enable and restart AN */
5972 bnx2x_restart_autoneg(phy, params, enable_cl73);
5973 }
5974
5975 } else { /* SGMII mode */
5976 DP(NETIF_MSG_LINK, "SGMII\n");
5977
5978 bnx2x_initialize_sgmii_process(phy, params, vars);
5979 }
5980 }
5981
bnx2x_prepare_xgxs(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)5982 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5983 struct link_params *params,
5984 struct link_vars *vars)
5985 {
5986 int rc;
5987 vars->phy_flags |= PHY_XGXS_FLAG;
5988 if ((phy->req_line_speed &&
5989 ((phy->req_line_speed == SPEED_100) ||
5990 (phy->req_line_speed == SPEED_10))) ||
5991 (!phy->req_line_speed &&
5992 (phy->speed_cap_mask >=
5993 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5994 (phy->speed_cap_mask <
5995 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5996 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5997 vars->phy_flags |= PHY_SGMII_FLAG;
5998 else
5999 vars->phy_flags &= ~PHY_SGMII_FLAG;
6000
6001 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6002 bnx2x_set_aer_mmd(params, phy);
6003 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
6004 bnx2x_set_master_ln(params, phy);
6005
6006 rc = bnx2x_reset_unicore(params, phy, 0);
6007 /* Reset the SerDes and wait for reset bit return low */
6008 if (rc)
6009 return rc;
6010
6011 bnx2x_set_aer_mmd(params, phy);
6012 /* Setting the masterLn_def again after the reset */
6013 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
6014 bnx2x_set_master_ln(params, phy);
6015 bnx2x_set_swap_lanes(params, phy);
6016 }
6017
6018 return rc;
6019 }
6020
bnx2x_wait_reset_complete(struct bnx2x * bp,struct bnx2x_phy * phy,struct link_params * params)6021 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
6022 struct bnx2x_phy *phy,
6023 struct link_params *params)
6024 {
6025 u16 cnt, ctrl;
6026 /* Wait for soft reset to get cleared up to 1 sec */
6027 for (cnt = 0; cnt < 1000; cnt++) {
6028 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6029 bnx2x_cl22_read(bp, phy,
6030 MDIO_PMA_REG_CTRL, &ctrl);
6031 else
6032 bnx2x_cl45_read(bp, phy,
6033 MDIO_PMA_DEVAD,
6034 MDIO_PMA_REG_CTRL, &ctrl);
6035 if (!(ctrl & (1<<15)))
6036 break;
6037 usleep_range(1000, 2000);
6038 }
6039
6040 if (cnt == 1000)
6041 netdev_err(bp->dev, "Warning: PHY was not initialized,"
6042 " Port %d\n",
6043 params->port);
6044 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6045 return cnt;
6046 }
6047
bnx2x_link_int_enable(struct link_params * params)6048 static void bnx2x_link_int_enable(struct link_params *params)
6049 {
6050 u8 port = params->port;
6051 u32 mask;
6052 struct bnx2x *bp = params->bp;
6053
6054 /* Setting the status to report on link up for either XGXS or SerDes */
6055 if (CHIP_IS_E3(bp)) {
6056 mask = NIG_MASK_XGXS0_LINK_STATUS;
6057 if (!(SINGLE_MEDIA_DIRECT(params)))
6058 mask |= NIG_MASK_MI_INT;
6059 } else if (params->switch_cfg == SWITCH_CFG_10G) {
6060 mask = (NIG_MASK_XGXS0_LINK10G |
6061 NIG_MASK_XGXS0_LINK_STATUS);
6062 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
6063 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6064 params->phy[INT_PHY].type !=
6065 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6066 mask |= NIG_MASK_MI_INT;
6067 DP(NETIF_MSG_LINK, "enabled external phy int\n");
6068 }
6069
6070 } else { /* SerDes */
6071 mask = NIG_MASK_SERDES0_LINK_STATUS;
6072 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6073 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6074 params->phy[INT_PHY].type !=
6075 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6076 mask |= NIG_MASK_MI_INT;
6077 DP(NETIF_MSG_LINK, "enabled external phy int\n");
6078 }
6079 }
6080 bnx2x_bits_en(bp,
6081 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6082 mask);
6083
6084 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6085 (params->switch_cfg == SWITCH_CFG_10G),
6086 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6087 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6088 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6089 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6090 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6091 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6092 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6093 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6094 }
6095
bnx2x_rearm_latch_signal(struct bnx2x * bp,u8 port,u8 exp_mi_int)6096 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6097 u8 exp_mi_int)
6098 {
6099 u32 latch_status = 0;
6100
6101 /* Disable the MI INT ( external phy int ) by writing 1 to the
6102 * status register. Link down indication is high-active-signal,
6103 * so in this case we need to write the status to clear the XOR
6104 */
6105 /* Read Latched signals */
6106 latch_status = REG_RD(bp,
6107 NIG_REG_LATCH_STATUS_0 + port*8);
6108 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6109 /* Handle only those with latched-signal=up.*/
6110 if (exp_mi_int)
6111 bnx2x_bits_en(bp,
6112 NIG_REG_STATUS_INTERRUPT_PORT0
6113 + port*4,
6114 NIG_STATUS_EMAC0_MI_INT);
6115 else
6116 bnx2x_bits_dis(bp,
6117 NIG_REG_STATUS_INTERRUPT_PORT0
6118 + port*4,
6119 NIG_STATUS_EMAC0_MI_INT);
6120
6121 if (latch_status & 1) {
6122
6123 /* For all latched-signal=up : Re-Arm Latch signals */
6124 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6125 (latch_status & 0xfffe) | (latch_status & 1));
6126 }
6127 /* For all latched-signal=up,Write original_signal to status */
6128 }
6129
bnx2x_link_int_ack(struct link_params * params,struct link_vars * vars,u8 is_10g_plus)6130 static void bnx2x_link_int_ack(struct link_params *params,
6131 struct link_vars *vars, u8 is_10g_plus)
6132 {
6133 struct bnx2x *bp = params->bp;
6134 u8 port = params->port;
6135 u32 mask;
6136 /* First reset all status we assume only one line will be
6137 * change at a time
6138 */
6139 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6140 (NIG_STATUS_XGXS0_LINK10G |
6141 NIG_STATUS_XGXS0_LINK_STATUS |
6142 NIG_STATUS_SERDES0_LINK_STATUS));
6143 if (vars->phy_link_up) {
6144 if (USES_WARPCORE(bp))
6145 mask = NIG_STATUS_XGXS0_LINK_STATUS;
6146 else {
6147 if (is_10g_plus)
6148 mask = NIG_STATUS_XGXS0_LINK10G;
6149 else if (params->switch_cfg == SWITCH_CFG_10G) {
6150 /* Disable the link interrupt by writing 1 to
6151 * the relevant lane in the status register
6152 */
6153 u32 ser_lane =
6154 ((params->lane_config &
6155 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6156 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6157 mask = ((1 << ser_lane) <<
6158 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6159 } else
6160 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6161 }
6162 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6163 mask);
6164 bnx2x_bits_en(bp,
6165 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6166 mask);
6167 }
6168 }
6169
bnx2x_format_ver(u32 num,u8 * str,u16 * len)6170 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6171 {
6172 u8 *str_ptr = str;
6173 u32 mask = 0xf0000000;
6174 u8 shift = 8*4;
6175 u8 digit;
6176 u8 remove_leading_zeros = 1;
6177 if (*len < 10) {
6178 /* Need more than 10chars for this format */
6179 *str_ptr = '\0';
6180 (*len)--;
6181 return -EINVAL;
6182 }
6183 while (shift > 0) {
6184
6185 shift -= 4;
6186 digit = ((num & mask) >> shift);
6187 if (digit == 0 && remove_leading_zeros) {
6188 mask = mask >> 4;
6189 continue;
6190 } else if (digit < 0xa)
6191 *str_ptr = digit + '0';
6192 else
6193 *str_ptr = digit - 0xa + 'a';
6194 remove_leading_zeros = 0;
6195 str_ptr++;
6196 (*len)--;
6197 mask = mask >> 4;
6198 if (shift == 4*4) {
6199 *str_ptr = '.';
6200 str_ptr++;
6201 (*len)--;
6202 remove_leading_zeros = 1;
6203 }
6204 }
6205 return 0;
6206 }
6207
6208
bnx2x_null_format_ver(u32 spirom_ver,u8 * str,u16 * len)6209 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6210 {
6211 str[0] = '\0';
6212 (*len)--;
6213 return 0;
6214 }
6215
bnx2x_get_ext_phy_fw_version(struct link_params * params,u8 * version,u16 len)6216 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6217 u16 len)
6218 {
6219 struct bnx2x *bp;
6220 u32 spirom_ver = 0;
6221 int status = 0;
6222 u8 *ver_p = version;
6223 u16 remain_len = len;
6224 if (version == NULL || params == NULL)
6225 return -EINVAL;
6226 bp = params->bp;
6227
6228 /* Extract first external phy*/
6229 version[0] = '\0';
6230 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6231
6232 if (params->phy[EXT_PHY1].format_fw_ver) {
6233 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6234 ver_p,
6235 &remain_len);
6236 ver_p += (len - remain_len);
6237 }
6238 if ((params->num_phys == MAX_PHYS) &&
6239 (params->phy[EXT_PHY2].ver_addr != 0)) {
6240 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6241 if (params->phy[EXT_PHY2].format_fw_ver) {
6242 *ver_p = '/';
6243 ver_p++;
6244 remain_len--;
6245 status |= params->phy[EXT_PHY2].format_fw_ver(
6246 spirom_ver,
6247 ver_p,
6248 &remain_len);
6249 ver_p = version + (len - remain_len);
6250 }
6251 }
6252 *ver_p = '\0';
6253 return status;
6254 }
6255
bnx2x_set_xgxs_loopback(struct bnx2x_phy * phy,struct link_params * params)6256 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6257 struct link_params *params)
6258 {
6259 u8 port = params->port;
6260 struct bnx2x *bp = params->bp;
6261
6262 if (phy->req_line_speed != SPEED_1000) {
6263 u32 md_devad = 0;
6264
6265 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6266
6267 if (!CHIP_IS_E3(bp)) {
6268 /* Change the uni_phy_addr in the nig */
6269 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6270 port*0x18));
6271
6272 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6273 0x5);
6274 }
6275
6276 bnx2x_cl45_write(bp, phy,
6277 5,
6278 (MDIO_REG_BANK_AER_BLOCK +
6279 (MDIO_AER_BLOCK_AER_REG & 0xf)),
6280 0x2800);
6281
6282 bnx2x_cl45_write(bp, phy,
6283 5,
6284 (MDIO_REG_BANK_CL73_IEEEB0 +
6285 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6286 0x6041);
6287 msleep(200);
6288 /* Set aer mmd back */
6289 bnx2x_set_aer_mmd(params, phy);
6290
6291 if (!CHIP_IS_E3(bp)) {
6292 /* And md_devad */
6293 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6294 md_devad);
6295 }
6296 } else {
6297 u16 mii_ctrl;
6298 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6299 bnx2x_cl45_read(bp, phy, 5,
6300 (MDIO_REG_BANK_COMBO_IEEE0 +
6301 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6302 &mii_ctrl);
6303 bnx2x_cl45_write(bp, phy, 5,
6304 (MDIO_REG_BANK_COMBO_IEEE0 +
6305 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6306 mii_ctrl |
6307 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6308 }
6309 }
6310
bnx2x_set_led(struct link_params * params,struct link_vars * vars,u8 mode,u32 speed)6311 int bnx2x_set_led(struct link_params *params,
6312 struct link_vars *vars, u8 mode, u32 speed)
6313 {
6314 u8 port = params->port;
6315 u16 hw_led_mode = params->hw_led_mode;
6316 int rc = 0;
6317 u8 phy_idx;
6318 u32 tmp;
6319 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6320 struct bnx2x *bp = params->bp;
6321 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6322 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6323 speed, hw_led_mode);
6324 /* In case */
6325 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6326 if (params->phy[phy_idx].set_link_led) {
6327 params->phy[phy_idx].set_link_led(
6328 ¶ms->phy[phy_idx], params, mode);
6329 }
6330 }
6331
6332 switch (mode) {
6333 case LED_MODE_FRONT_PANEL_OFF:
6334 case LED_MODE_OFF:
6335 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6336 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6337 SHARED_HW_CFG_LED_MAC1);
6338
6339 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6340 if (params->phy[EXT_PHY1].type ==
6341 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6342 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6343 EMAC_LED_100MB_OVERRIDE |
6344 EMAC_LED_10MB_OVERRIDE);
6345 else
6346 tmp |= EMAC_LED_OVERRIDE;
6347
6348 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6349 break;
6350
6351 case LED_MODE_OPER:
6352 /* For all other phys, OPER mode is same as ON, so in case
6353 * link is down, do nothing
6354 */
6355 if (!vars->link_up)
6356 break;
6357 case LED_MODE_ON:
6358 if (((params->phy[EXT_PHY1].type ==
6359 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6360 (params->phy[EXT_PHY1].type ==
6361 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6362 CHIP_IS_E2(bp) && params->num_phys == 2) {
6363 /* This is a work-around for E2+8727 Configurations */
6364 if (mode == LED_MODE_ON ||
6365 speed == SPEED_10000){
6366 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6367 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6368
6369 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6370 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6371 (tmp | EMAC_LED_OVERRIDE));
6372 /* Return here without enabling traffic
6373 * LED blink and setting rate in ON mode.
6374 * In oper mode, enabling LED blink
6375 * and setting rate is needed.
6376 */
6377 if (mode == LED_MODE_ON)
6378 return rc;
6379 }
6380 } else if (SINGLE_MEDIA_DIRECT(params)) {
6381 /* This is a work-around for HW issue found when link
6382 * is up in CL73
6383 */
6384 if ((!CHIP_IS_E3(bp)) ||
6385 (CHIP_IS_E3(bp) &&
6386 mode == LED_MODE_ON))
6387 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6388
6389 if (CHIP_IS_E1x(bp) ||
6390 CHIP_IS_E2(bp) ||
6391 (mode == LED_MODE_ON))
6392 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6393 else
6394 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6395 hw_led_mode);
6396 } else if ((params->phy[EXT_PHY1].type ==
6397 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6398 (mode == LED_MODE_ON)) {
6399 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6400 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6401 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6402 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6403 /* Break here; otherwise, it'll disable the
6404 * intended override.
6405 */
6406 break;
6407 } else {
6408 u32 nig_led_mode = ((params->hw_led_mode <<
6409 SHARED_HW_CFG_LED_MODE_SHIFT) ==
6410 SHARED_HW_CFG_LED_EXTPHY2) ?
6411 (SHARED_HW_CFG_LED_PHY1 >>
6412 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
6413 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6414 nig_led_mode);
6415 }
6416
6417 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6418 /* Set blinking rate to ~15.9Hz */
6419 if (CHIP_IS_E3(bp))
6420 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6421 LED_BLINK_RATE_VAL_E3);
6422 else
6423 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6424 LED_BLINK_RATE_VAL_E1X_E2);
6425 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6426 port*4, 1);
6427 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6428 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6429 (tmp & (~EMAC_LED_OVERRIDE)));
6430
6431 if (CHIP_IS_E1(bp) &&
6432 ((speed == SPEED_2500) ||
6433 (speed == SPEED_1000) ||
6434 (speed == SPEED_100) ||
6435 (speed == SPEED_10))) {
6436 /* For speeds less than 10G LED scheme is different */
6437 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6438 + port*4, 1);
6439 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6440 port*4, 0);
6441 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6442 port*4, 1);
6443 }
6444 break;
6445
6446 default:
6447 rc = -EINVAL;
6448 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6449 mode);
6450 break;
6451 }
6452 return rc;
6453
6454 }
6455
6456 /* This function comes to reflect the actual link state read DIRECTLY from the
6457 * HW
6458 */
bnx2x_test_link(struct link_params * params,struct link_vars * vars,u8 is_serdes)6459 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6460 u8 is_serdes)
6461 {
6462 struct bnx2x *bp = params->bp;
6463 u16 gp_status = 0, phy_index = 0;
6464 u8 ext_phy_link_up = 0, serdes_phy_type;
6465 struct link_vars temp_vars;
6466 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
6467
6468 if (CHIP_IS_E3(bp)) {
6469 u16 link_up;
6470 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6471 > SPEED_10000) {
6472 /* Check 20G link */
6473 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6474 1, &link_up);
6475 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6476 1, &link_up);
6477 link_up &= (1<<2);
6478 } else {
6479 /* Check 10G link and below*/
6480 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6481 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6482 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6483 &gp_status);
6484 gp_status = ((gp_status >> 8) & 0xf) |
6485 ((gp_status >> 12) & 0xf);
6486 link_up = gp_status & (1 << lane);
6487 }
6488 if (!link_up)
6489 return -ESRCH;
6490 } else {
6491 CL22_RD_OVER_CL45(bp, int_phy,
6492 MDIO_REG_BANK_GP_STATUS,
6493 MDIO_GP_STATUS_TOP_AN_STATUS1,
6494 &gp_status);
6495 /* Link is up only if both local phy and external phy are up */
6496 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6497 return -ESRCH;
6498 }
6499 /* In XGXS loopback mode, do not check external PHY */
6500 if (params->loopback_mode == LOOPBACK_XGXS)
6501 return 0;
6502
6503 switch (params->num_phys) {
6504 case 1:
6505 /* No external PHY */
6506 return 0;
6507 case 2:
6508 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6509 ¶ms->phy[EXT_PHY1],
6510 params, &temp_vars);
6511 break;
6512 case 3: /* Dual Media */
6513 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6514 phy_index++) {
6515 serdes_phy_type = ((params->phy[phy_index].media_type ==
6516 ETH_PHY_SFPP_10G_FIBER) ||
6517 (params->phy[phy_index].media_type ==
6518 ETH_PHY_SFP_1G_FIBER) ||
6519 (params->phy[phy_index].media_type ==
6520 ETH_PHY_XFP_FIBER) ||
6521 (params->phy[phy_index].media_type ==
6522 ETH_PHY_DA_TWINAX));
6523
6524 if (is_serdes != serdes_phy_type)
6525 continue;
6526 if (params->phy[phy_index].read_status) {
6527 ext_phy_link_up |=
6528 params->phy[phy_index].read_status(
6529 ¶ms->phy[phy_index],
6530 params, &temp_vars);
6531 }
6532 }
6533 break;
6534 }
6535 if (ext_phy_link_up)
6536 return 0;
6537 return -ESRCH;
6538 }
6539
bnx2x_link_initialize(struct link_params * params,struct link_vars * vars)6540 static int bnx2x_link_initialize(struct link_params *params,
6541 struct link_vars *vars)
6542 {
6543 u8 phy_index, non_ext_phy;
6544 struct bnx2x *bp = params->bp;
6545 /* In case of external phy existence, the line speed would be the
6546 * line speed linked up by the external phy. In case it is direct
6547 * only, then the line_speed during initialization will be
6548 * equal to the req_line_speed
6549 */
6550 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6551
6552 /* Initialize the internal phy in case this is a direct board
6553 * (no external phys), or this board has external phy which requires
6554 * to first.
6555 */
6556 if (!USES_WARPCORE(bp))
6557 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars);
6558 /* init ext phy and enable link state int */
6559 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6560 (params->loopback_mode == LOOPBACK_XGXS));
6561
6562 if (non_ext_phy ||
6563 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6564 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6565 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
6566 if (vars->line_speed == SPEED_AUTO_NEG &&
6567 (CHIP_IS_E1x(bp) ||
6568 CHIP_IS_E2(bp)))
6569 bnx2x_set_parallel_detection(phy, params);
6570 if (params->phy[INT_PHY].config_init)
6571 params->phy[INT_PHY].config_init(phy, params, vars);
6572 }
6573
6574 /* Re-read this value in case it was changed inside config_init due to
6575 * limitations of optic module
6576 */
6577 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6578
6579 /* Init external phy*/
6580 if (non_ext_phy) {
6581 if (params->phy[INT_PHY].supported &
6582 SUPPORTED_FIBRE)
6583 vars->link_status |= LINK_STATUS_SERDES_LINK;
6584 } else {
6585 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6586 phy_index++) {
6587 /* No need to initialize second phy in case of first
6588 * phy only selection. In case of second phy, we do
6589 * need to initialize the first phy, since they are
6590 * connected.
6591 */
6592 if (params->phy[phy_index].supported &
6593 SUPPORTED_FIBRE)
6594 vars->link_status |= LINK_STATUS_SERDES_LINK;
6595
6596 if (phy_index == EXT_PHY2 &&
6597 (bnx2x_phy_selection(params) ==
6598 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6599 DP(NETIF_MSG_LINK,
6600 "Not initializing second phy\n");
6601 continue;
6602 }
6603 params->phy[phy_index].config_init(
6604 ¶ms->phy[phy_index],
6605 params, vars);
6606 }
6607 }
6608 /* Reset the interrupt indication after phy was initialized */
6609 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6610 params->port*4,
6611 (NIG_STATUS_XGXS0_LINK10G |
6612 NIG_STATUS_XGXS0_LINK_STATUS |
6613 NIG_STATUS_SERDES0_LINK_STATUS |
6614 NIG_MASK_MI_INT));
6615 return 0;
6616 }
6617
bnx2x_int_link_reset(struct bnx2x_phy * phy,struct link_params * params)6618 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6619 struct link_params *params)
6620 {
6621 /* Reset the SerDes/XGXS */
6622 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6623 (0x1ff << (params->port*16)));
6624 }
6625
bnx2x_common_ext_link_reset(struct bnx2x_phy * phy,struct link_params * params)6626 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6627 struct link_params *params)
6628 {
6629 struct bnx2x *bp = params->bp;
6630 u8 gpio_port;
6631 /* HW reset */
6632 if (CHIP_IS_E2(bp))
6633 gpio_port = BP_PATH(bp);
6634 else
6635 gpio_port = params->port;
6636 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6637 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6638 gpio_port);
6639 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6640 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6641 gpio_port);
6642 DP(NETIF_MSG_LINK, "reset external PHY\n");
6643 }
6644
bnx2x_update_link_down(struct link_params * params,struct link_vars * vars)6645 static int bnx2x_update_link_down(struct link_params *params,
6646 struct link_vars *vars)
6647 {
6648 struct bnx2x *bp = params->bp;
6649 u8 port = params->port;
6650
6651 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6652 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6653 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6654 /* Indicate no mac active */
6655 vars->mac_type = MAC_TYPE_NONE;
6656
6657 /* Update shared memory */
6658 vars->link_status &= ~LINK_UPDATE_MASK;
6659 vars->line_speed = 0;
6660 bnx2x_update_mng(params, vars->link_status);
6661
6662 /* Activate nig drain */
6663 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6664
6665 /* Disable emac */
6666 if (!CHIP_IS_E3(bp))
6667 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6668
6669 usleep_range(10000, 20000);
6670 /* Reset BigMac/Xmac */
6671 if (CHIP_IS_E1x(bp) ||
6672 CHIP_IS_E2(bp))
6673 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6674
6675 if (CHIP_IS_E3(bp)) {
6676 /* Prevent LPI Generation by chip */
6677 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6678 0);
6679 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6680 0);
6681 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6682 SHMEM_EEE_ACTIVE_BIT);
6683
6684 bnx2x_update_mng_eee(params, vars->eee_status);
6685 bnx2x_set_xmac_rxtx(params, 0);
6686 bnx2x_set_umac_rxtx(params, 0);
6687 }
6688
6689 return 0;
6690 }
6691
bnx2x_update_link_up(struct link_params * params,struct link_vars * vars,u8 link_10g)6692 static int bnx2x_update_link_up(struct link_params *params,
6693 struct link_vars *vars,
6694 u8 link_10g)
6695 {
6696 struct bnx2x *bp = params->bp;
6697 u8 phy_idx, port = params->port;
6698 int rc = 0;
6699
6700 vars->link_status |= (LINK_STATUS_LINK_UP |
6701 LINK_STATUS_PHYSICAL_LINK_FLAG);
6702 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6703
6704 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6705 vars->link_status |=
6706 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6707
6708 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6709 vars->link_status |=
6710 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6711 if (USES_WARPCORE(bp)) {
6712 if (link_10g) {
6713 if (bnx2x_xmac_enable(params, vars, 0) ==
6714 -ESRCH) {
6715 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6716 vars->link_up = 0;
6717 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6718 vars->link_status &= ~LINK_STATUS_LINK_UP;
6719 }
6720 } else
6721 bnx2x_umac_enable(params, vars, 0);
6722 bnx2x_set_led(params, vars,
6723 LED_MODE_OPER, vars->line_speed);
6724
6725 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6726 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6727 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6728 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6729 (params->port << 2), 1);
6730 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6731 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6732 (params->port << 2), 0xfc20);
6733 }
6734 }
6735 if ((CHIP_IS_E1x(bp) ||
6736 CHIP_IS_E2(bp))) {
6737 if (link_10g) {
6738 if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6739 -ESRCH) {
6740 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6741 vars->link_up = 0;
6742 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6743 vars->link_status &= ~LINK_STATUS_LINK_UP;
6744 }
6745
6746 bnx2x_set_led(params, vars,
6747 LED_MODE_OPER, SPEED_10000);
6748 } else {
6749 rc = bnx2x_emac_program(params, vars);
6750 bnx2x_emac_enable(params, vars, 0);
6751
6752 /* AN complete? */
6753 if ((vars->link_status &
6754 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6755 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6756 SINGLE_MEDIA_DIRECT(params))
6757 bnx2x_set_gmii_tx_driver(params);
6758 }
6759 }
6760
6761 /* PBF - link up */
6762 if (CHIP_IS_E1x(bp))
6763 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6764 vars->line_speed);
6765
6766 /* Disable drain */
6767 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6768
6769 /* Update shared memory */
6770 bnx2x_update_mng(params, vars->link_status);
6771 bnx2x_update_mng_eee(params, vars->eee_status);
6772 /* Check remote fault */
6773 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6774 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6775 bnx2x_check_half_open_conn(params, vars, 0);
6776 break;
6777 }
6778 }
6779 msleep(20);
6780 return rc;
6781 }
6782
bnx2x_chng_link_count(struct link_params * params,bool clear)6783 static void bnx2x_chng_link_count(struct link_params *params, bool clear)
6784 {
6785 struct bnx2x *bp = params->bp;
6786 u32 addr, val;
6787
6788 /* Verify the link_change_count is supported by the MFW */
6789 if (!(SHMEM2_HAS(bp, link_change_count)))
6790 return;
6791
6792 addr = params->shmem2_base +
6793 offsetof(struct shmem2_region, link_change_count[params->port]);
6794 if (clear)
6795 val = 0;
6796 else
6797 val = REG_RD(bp, addr) + 1;
6798 REG_WR(bp, addr, val);
6799 }
6800
6801 /* The bnx2x_link_update function should be called upon link
6802 * interrupt.
6803 * Link is considered up as follows:
6804 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6805 * to be up
6806 * - SINGLE_MEDIA - The link between the 577xx and the external
6807 * phy (XGXS) need to up as well as the external link of the
6808 * phy (PHY_EXT1)
6809 * - DUAL_MEDIA - The link between the 577xx and the first
6810 * external phy needs to be up, and at least one of the 2
6811 * external phy link must be up.
6812 */
bnx2x_link_update(struct link_params * params,struct link_vars * vars)6813 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6814 {
6815 struct bnx2x *bp = params->bp;
6816 struct link_vars phy_vars[MAX_PHYS];
6817 u8 port = params->port;
6818 u8 link_10g_plus, phy_index;
6819 u32 prev_link_status = vars->link_status;
6820 u8 ext_phy_link_up = 0, cur_link_up;
6821 int rc = 0;
6822 u8 is_mi_int = 0;
6823 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6824 u8 active_external_phy = INT_PHY;
6825 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6826 vars->link_status &= ~LINK_UPDATE_MASK;
6827 for (phy_index = INT_PHY; phy_index < params->num_phys;
6828 phy_index++) {
6829 phy_vars[phy_index].flow_ctrl = 0;
6830 phy_vars[phy_index].link_status = 0;
6831 phy_vars[phy_index].line_speed = 0;
6832 phy_vars[phy_index].duplex = DUPLEX_FULL;
6833 phy_vars[phy_index].phy_link_up = 0;
6834 phy_vars[phy_index].link_up = 0;
6835 phy_vars[phy_index].fault_detected = 0;
6836 /* different consideration, since vars holds inner state */
6837 phy_vars[phy_index].eee_status = vars->eee_status;
6838 }
6839
6840 if (USES_WARPCORE(bp))
6841 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]);
6842
6843 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6844 port, (vars->phy_flags & PHY_XGXS_FLAG),
6845 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6846
6847 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6848 port*0x18) > 0);
6849 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6850 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6851 is_mi_int,
6852 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6853
6854 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6855 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6856 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6857
6858 /* Disable emac */
6859 if (!CHIP_IS_E3(bp))
6860 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6861
6862 /* Step 1:
6863 * Check external link change only for external phys, and apply
6864 * priority selection between them in case the link on both phys
6865 * is up. Note that instead of the common vars, a temporary
6866 * vars argument is used since each phy may have different link/
6867 * speed/duplex result
6868 */
6869 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6870 phy_index++) {
6871 struct bnx2x_phy *phy = ¶ms->phy[phy_index];
6872 if (!phy->read_status)
6873 continue;
6874 /* Read link status and params of this ext phy */
6875 cur_link_up = phy->read_status(phy, params,
6876 &phy_vars[phy_index]);
6877 if (cur_link_up) {
6878 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6879 phy_index);
6880 } else {
6881 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6882 phy_index);
6883 continue;
6884 }
6885
6886 if (!ext_phy_link_up) {
6887 ext_phy_link_up = 1;
6888 active_external_phy = phy_index;
6889 } else {
6890 switch (bnx2x_phy_selection(params)) {
6891 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6892 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6893 /* In this option, the first PHY makes sure to pass the
6894 * traffic through itself only.
6895 * Its not clear how to reset the link on the second phy
6896 */
6897 active_external_phy = EXT_PHY1;
6898 break;
6899 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6900 /* In this option, the first PHY makes sure to pass the
6901 * traffic through the second PHY.
6902 */
6903 active_external_phy = EXT_PHY2;
6904 break;
6905 default:
6906 /* Link indication on both PHYs with the following cases
6907 * is invalid:
6908 * - FIRST_PHY means that second phy wasn't initialized,
6909 * hence its link is expected to be down
6910 * - SECOND_PHY means that first phy should not be able
6911 * to link up by itself (using configuration)
6912 * - DEFAULT should be overriden during initialiazation
6913 */
6914 DP(NETIF_MSG_LINK, "Invalid link indication"
6915 "mpc=0x%x. DISABLING LINK !!!\n",
6916 params->multi_phy_config);
6917 ext_phy_link_up = 0;
6918 break;
6919 }
6920 }
6921 }
6922 prev_line_speed = vars->line_speed;
6923 /* Step 2:
6924 * Read the status of the internal phy. In case of
6925 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6926 * otherwise this is the link between the 577xx and the first
6927 * external phy
6928 */
6929 if (params->phy[INT_PHY].read_status)
6930 params->phy[INT_PHY].read_status(
6931 ¶ms->phy[INT_PHY],
6932 params, vars);
6933 /* The INT_PHY flow control reside in the vars. This include the
6934 * case where the speed or flow control are not set to AUTO.
6935 * Otherwise, the active external phy flow control result is set
6936 * to the vars. The ext_phy_line_speed is needed to check if the
6937 * speed is different between the internal phy and external phy.
6938 * This case may be result of intermediate link speed change.
6939 */
6940 if (active_external_phy > INT_PHY) {
6941 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6942 /* Link speed is taken from the XGXS. AN and FC result from
6943 * the external phy.
6944 */
6945 vars->link_status |= phy_vars[active_external_phy].link_status;
6946
6947 /* if active_external_phy is first PHY and link is up - disable
6948 * disable TX on second external PHY
6949 */
6950 if (active_external_phy == EXT_PHY1) {
6951 if (params->phy[EXT_PHY2].phy_specific_func) {
6952 DP(NETIF_MSG_LINK,
6953 "Disabling TX on EXT_PHY2\n");
6954 params->phy[EXT_PHY2].phy_specific_func(
6955 ¶ms->phy[EXT_PHY2],
6956 params, DISABLE_TX);
6957 }
6958 }
6959
6960 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6961 vars->duplex = phy_vars[active_external_phy].duplex;
6962 if (params->phy[active_external_phy].supported &
6963 SUPPORTED_FIBRE)
6964 vars->link_status |= LINK_STATUS_SERDES_LINK;
6965 else
6966 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6967
6968 vars->eee_status = phy_vars[active_external_phy].eee_status;
6969
6970 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6971 active_external_phy);
6972 }
6973
6974 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6975 phy_index++) {
6976 if (params->phy[phy_index].flags &
6977 FLAGS_REARM_LATCH_SIGNAL) {
6978 bnx2x_rearm_latch_signal(bp, port,
6979 phy_index ==
6980 active_external_phy);
6981 break;
6982 }
6983 }
6984 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6985 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6986 vars->link_status, ext_phy_line_speed);
6987 /* Upon link speed change set the NIG into drain mode. Comes to
6988 * deals with possible FIFO glitch due to clk change when speed
6989 * is decreased without link down indicator
6990 */
6991
6992 if (vars->phy_link_up) {
6993 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6994 (ext_phy_line_speed != vars->line_speed)) {
6995 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6996 " different than the external"
6997 " link speed %d\n", vars->line_speed,
6998 ext_phy_line_speed);
6999 vars->phy_link_up = 0;
7000 } else if (prev_line_speed != vars->line_speed) {
7001 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
7002 0);
7003 usleep_range(1000, 2000);
7004 }
7005 }
7006
7007 /* Anything 10 and over uses the bmac */
7008 link_10g_plus = (vars->line_speed >= SPEED_10000);
7009
7010 bnx2x_link_int_ack(params, vars, link_10g_plus);
7011
7012 /* In case external phy link is up, and internal link is down
7013 * (not initialized yet probably after link initialization, it
7014 * needs to be initialized.
7015 * Note that after link down-up as result of cable plug, the xgxs
7016 * link would probably become up again without the need
7017 * initialize it
7018 */
7019 if (!(SINGLE_MEDIA_DIRECT(params))) {
7020 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
7021 " init_preceding = %d\n", ext_phy_link_up,
7022 vars->phy_link_up,
7023 params->phy[EXT_PHY1].flags &
7024 FLAGS_INIT_XGXS_FIRST);
7025 if (!(params->phy[EXT_PHY1].flags &
7026 FLAGS_INIT_XGXS_FIRST)
7027 && ext_phy_link_up && !vars->phy_link_up) {
7028 vars->line_speed = ext_phy_line_speed;
7029 if (vars->line_speed < SPEED_1000)
7030 vars->phy_flags |= PHY_SGMII_FLAG;
7031 else
7032 vars->phy_flags &= ~PHY_SGMII_FLAG;
7033
7034 if (params->phy[INT_PHY].config_init)
7035 params->phy[INT_PHY].config_init(
7036 ¶ms->phy[INT_PHY], params,
7037 vars);
7038 }
7039 }
7040 /* Link is up only if both local phy and external phy (in case of
7041 * non-direct board) are up and no fault detected on active PHY.
7042 */
7043 vars->link_up = (vars->phy_link_up &&
7044 (ext_phy_link_up ||
7045 SINGLE_MEDIA_DIRECT(params)) &&
7046 (phy_vars[active_external_phy].fault_detected == 0));
7047
7048 /* Update the PFC configuration in case it was changed */
7049 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
7050 vars->link_status |= LINK_STATUS_PFC_ENABLED;
7051 else
7052 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
7053
7054 if (vars->link_up)
7055 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
7056 else
7057 rc = bnx2x_update_link_down(params, vars);
7058
7059 if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP)
7060 bnx2x_chng_link_count(params, false);
7061
7062 /* Update MCP link status was changed */
7063 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7064 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7065
7066 return rc;
7067 }
7068
7069 /*****************************************************************************/
7070 /* External Phy section */
7071 /*****************************************************************************/
bnx2x_ext_phy_hw_reset(struct bnx2x * bp,u8 port)7072 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
7073 {
7074 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7075 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7076 usleep_range(1000, 2000);
7077 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7078 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7079 }
7080
bnx2x_save_spirom_version(struct bnx2x * bp,u8 port,u32 spirom_ver,u32 ver_addr)7081 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
7082 u32 spirom_ver, u32 ver_addr)
7083 {
7084 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
7085 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
7086
7087 if (ver_addr)
7088 REG_WR(bp, ver_addr, spirom_ver);
7089 }
7090
bnx2x_save_bcm_spirom_ver(struct bnx2x * bp,struct bnx2x_phy * phy,u8 port)7091 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
7092 struct bnx2x_phy *phy,
7093 u8 port)
7094 {
7095 u16 fw_ver1, fw_ver2;
7096
7097 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7098 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7099 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7100 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7101 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7102 phy->ver_addr);
7103 }
7104
bnx2x_ext_phy_10G_an_resolve(struct bnx2x * bp,struct bnx2x_phy * phy,struct link_vars * vars)7105 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7106 struct bnx2x_phy *phy,
7107 struct link_vars *vars)
7108 {
7109 u16 val;
7110 bnx2x_cl45_read(bp, phy,
7111 MDIO_AN_DEVAD,
7112 MDIO_AN_REG_STATUS, &val);
7113 bnx2x_cl45_read(bp, phy,
7114 MDIO_AN_DEVAD,
7115 MDIO_AN_REG_STATUS, &val);
7116 if (val & (1<<5))
7117 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7118 if ((val & (1<<0)) == 0)
7119 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7120 }
7121
7122 /******************************************************************/
7123 /* common BCM8073/BCM8727 PHY SECTION */
7124 /******************************************************************/
bnx2x_8073_resolve_fc(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)7125 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7126 struct link_params *params,
7127 struct link_vars *vars)
7128 {
7129 struct bnx2x *bp = params->bp;
7130 if (phy->req_line_speed == SPEED_10 ||
7131 phy->req_line_speed == SPEED_100) {
7132 vars->flow_ctrl = phy->req_flow_ctrl;
7133 return;
7134 }
7135
7136 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7137 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7138 u16 pause_result;
7139 u16 ld_pause; /* local */
7140 u16 lp_pause; /* link partner */
7141 bnx2x_cl45_read(bp, phy,
7142 MDIO_AN_DEVAD,
7143 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7144
7145 bnx2x_cl45_read(bp, phy,
7146 MDIO_AN_DEVAD,
7147 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7148 pause_result = (ld_pause &
7149 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7150 pause_result |= (lp_pause &
7151 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7152
7153 bnx2x_pause_resolve(phy, params, vars, pause_result);
7154 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7155 pause_result);
7156 }
7157 }
bnx2x_8073_8727_external_rom_boot(struct bnx2x * bp,struct bnx2x_phy * phy,u8 port)7158 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7159 struct bnx2x_phy *phy,
7160 u8 port)
7161 {
7162 u32 count = 0;
7163 u16 fw_ver1, fw_msgout;
7164 int rc = 0;
7165
7166 /* Boot port from external ROM */
7167 /* EDC grst */
7168 bnx2x_cl45_write(bp, phy,
7169 MDIO_PMA_DEVAD,
7170 MDIO_PMA_REG_GEN_CTRL,
7171 0x0001);
7172
7173 /* Ucode reboot and rst */
7174 bnx2x_cl45_write(bp, phy,
7175 MDIO_PMA_DEVAD,
7176 MDIO_PMA_REG_GEN_CTRL,
7177 0x008c);
7178
7179 bnx2x_cl45_write(bp, phy,
7180 MDIO_PMA_DEVAD,
7181 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7182
7183 /* Reset internal microprocessor */
7184 bnx2x_cl45_write(bp, phy,
7185 MDIO_PMA_DEVAD,
7186 MDIO_PMA_REG_GEN_CTRL,
7187 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7188
7189 /* Release srst bit */
7190 bnx2x_cl45_write(bp, phy,
7191 MDIO_PMA_DEVAD,
7192 MDIO_PMA_REG_GEN_CTRL,
7193 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7194
7195 /* Delay 100ms per the PHY specifications */
7196 msleep(100);
7197
7198 /* 8073 sometimes taking longer to download */
7199 do {
7200 count++;
7201 if (count > 300) {
7202 DP(NETIF_MSG_LINK,
7203 "bnx2x_8073_8727_external_rom_boot port %x:"
7204 "Download failed. fw version = 0x%x\n",
7205 port, fw_ver1);
7206 rc = -EINVAL;
7207 break;
7208 }
7209
7210 bnx2x_cl45_read(bp, phy,
7211 MDIO_PMA_DEVAD,
7212 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7213 bnx2x_cl45_read(bp, phy,
7214 MDIO_PMA_DEVAD,
7215 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7216
7217 usleep_range(1000, 2000);
7218 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7219 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7220 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7221
7222 /* Clear ser_boot_ctl bit */
7223 bnx2x_cl45_write(bp, phy,
7224 MDIO_PMA_DEVAD,
7225 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7226 bnx2x_save_bcm_spirom_ver(bp, phy, port);
7227
7228 DP(NETIF_MSG_LINK,
7229 "bnx2x_8073_8727_external_rom_boot port %x:"
7230 "Download complete. fw version = 0x%x\n",
7231 port, fw_ver1);
7232
7233 return rc;
7234 }
7235
7236 /******************************************************************/
7237 /* BCM8073 PHY SECTION */
7238 /******************************************************************/
bnx2x_8073_is_snr_needed(struct bnx2x * bp,struct bnx2x_phy * phy)7239 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7240 {
7241 /* This is only required for 8073A1, version 102 only */
7242 u16 val;
7243
7244 /* Read 8073 HW revision*/
7245 bnx2x_cl45_read(bp, phy,
7246 MDIO_PMA_DEVAD,
7247 MDIO_PMA_REG_8073_CHIP_REV, &val);
7248
7249 if (val != 1) {
7250 /* No need to workaround in 8073 A1 */
7251 return 0;
7252 }
7253
7254 bnx2x_cl45_read(bp, phy,
7255 MDIO_PMA_DEVAD,
7256 MDIO_PMA_REG_ROM_VER2, &val);
7257
7258 /* SNR should be applied only for version 0x102 */
7259 if (val != 0x102)
7260 return 0;
7261
7262 return 1;
7263 }
7264
bnx2x_8073_xaui_wa(struct bnx2x * bp,struct bnx2x_phy * phy)7265 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7266 {
7267 u16 val, cnt, cnt1 ;
7268
7269 bnx2x_cl45_read(bp, phy,
7270 MDIO_PMA_DEVAD,
7271 MDIO_PMA_REG_8073_CHIP_REV, &val);
7272
7273 if (val > 0) {
7274 /* No need to workaround in 8073 A1 */
7275 return 0;
7276 }
7277 /* XAUI workaround in 8073 A0: */
7278
7279 /* After loading the boot ROM and restarting Autoneg, poll
7280 * Dev1, Reg $C820:
7281 */
7282
7283 for (cnt = 0; cnt < 1000; cnt++) {
7284 bnx2x_cl45_read(bp, phy,
7285 MDIO_PMA_DEVAD,
7286 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7287 &val);
7288 /* If bit [14] = 0 or bit [13] = 0, continue on with
7289 * system initialization (XAUI work-around not required, as
7290 * these bits indicate 2.5G or 1G link up).
7291 */
7292 if (!(val & (1<<14)) || !(val & (1<<13))) {
7293 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7294 return 0;
7295 } else if (!(val & (1<<15))) {
7296 DP(NETIF_MSG_LINK, "bit 15 went off\n");
7297 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7298 * MSB (bit15) goes to 1 (indicating that the XAUI
7299 * workaround has completed), then continue on with
7300 * system initialization.
7301 */
7302 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7303 bnx2x_cl45_read(bp, phy,
7304 MDIO_PMA_DEVAD,
7305 MDIO_PMA_REG_8073_XAUI_WA, &val);
7306 if (val & (1<<15)) {
7307 DP(NETIF_MSG_LINK,
7308 "XAUI workaround has completed\n");
7309 return 0;
7310 }
7311 usleep_range(3000, 6000);
7312 }
7313 break;
7314 }
7315 usleep_range(3000, 6000);
7316 }
7317 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7318 return -EINVAL;
7319 }
7320
bnx2x_807x_force_10G(struct bnx2x * bp,struct bnx2x_phy * phy)7321 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7322 {
7323 /* Force KR or KX */
7324 bnx2x_cl45_write(bp, phy,
7325 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7326 bnx2x_cl45_write(bp, phy,
7327 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7328 bnx2x_cl45_write(bp, phy,
7329 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7330 bnx2x_cl45_write(bp, phy,
7331 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7332 }
7333
bnx2x_8073_set_pause_cl37(struct link_params * params,struct bnx2x_phy * phy,struct link_vars * vars)7334 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7335 struct bnx2x_phy *phy,
7336 struct link_vars *vars)
7337 {
7338 u16 cl37_val;
7339 struct bnx2x *bp = params->bp;
7340 bnx2x_cl45_read(bp, phy,
7341 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7342
7343 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7344 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7345 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7346 if ((vars->ieee_fc &
7347 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7348 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7349 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7350 }
7351 if ((vars->ieee_fc &
7352 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7353 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7354 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7355 }
7356 if ((vars->ieee_fc &
7357 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7358 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7359 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7360 }
7361 DP(NETIF_MSG_LINK,
7362 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7363
7364 bnx2x_cl45_write(bp, phy,
7365 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7366 msleep(500);
7367 }
7368
bnx2x_8073_specific_func(struct bnx2x_phy * phy,struct link_params * params,u32 action)7369 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7370 struct link_params *params,
7371 u32 action)
7372 {
7373 struct bnx2x *bp = params->bp;
7374 switch (action) {
7375 case PHY_INIT:
7376 /* Enable LASI */
7377 bnx2x_cl45_write(bp, phy,
7378 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7379 bnx2x_cl45_write(bp, phy,
7380 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
7381 break;
7382 }
7383 }
7384
bnx2x_8073_config_init(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)7385 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7386 struct link_params *params,
7387 struct link_vars *vars)
7388 {
7389 struct bnx2x *bp = params->bp;
7390 u16 val = 0, tmp1;
7391 u8 gpio_port;
7392 DP(NETIF_MSG_LINK, "Init 8073\n");
7393
7394 if (CHIP_IS_E2(bp))
7395 gpio_port = BP_PATH(bp);
7396 else
7397 gpio_port = params->port;
7398 /* Restore normal power mode*/
7399 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7400 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7401
7402 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7403 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7404
7405 bnx2x_8073_specific_func(phy, params, PHY_INIT);
7406 bnx2x_8073_set_pause_cl37(params, phy, vars);
7407
7408 bnx2x_cl45_read(bp, phy,
7409 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7410
7411 bnx2x_cl45_read(bp, phy,
7412 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7413
7414 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7415
7416 /* Swap polarity if required - Must be done only in non-1G mode */
7417 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7418 /* Configure the 8073 to swap _P and _N of the KR lines */
7419 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7420 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7421 bnx2x_cl45_read(bp, phy,
7422 MDIO_PMA_DEVAD,
7423 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7424 bnx2x_cl45_write(bp, phy,
7425 MDIO_PMA_DEVAD,
7426 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7427 (val | (3<<9)));
7428 }
7429
7430
7431 /* Enable CL37 BAM */
7432 if (REG_RD(bp, params->shmem_base +
7433 offsetof(struct shmem_region, dev_info.
7434 port_hw_config[params->port].default_cfg)) &
7435 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7436
7437 bnx2x_cl45_read(bp, phy,
7438 MDIO_AN_DEVAD,
7439 MDIO_AN_REG_8073_BAM, &val);
7440 bnx2x_cl45_write(bp, phy,
7441 MDIO_AN_DEVAD,
7442 MDIO_AN_REG_8073_BAM, val | 1);
7443 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7444 }
7445 if (params->loopback_mode == LOOPBACK_EXT) {
7446 bnx2x_807x_force_10G(bp, phy);
7447 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7448 return 0;
7449 } else {
7450 bnx2x_cl45_write(bp, phy,
7451 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7452 }
7453 if (phy->req_line_speed != SPEED_AUTO_NEG) {
7454 if (phy->req_line_speed == SPEED_10000) {
7455 val = (1<<7);
7456 } else if (phy->req_line_speed == SPEED_2500) {
7457 val = (1<<5);
7458 /* Note that 2.5G works only when used with 1G
7459 * advertisement
7460 */
7461 } else
7462 val = (1<<5);
7463 } else {
7464 val = 0;
7465 if (phy->speed_cap_mask &
7466 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7467 val |= (1<<7);
7468
7469 /* Note that 2.5G works only when used with 1G advertisement */
7470 if (phy->speed_cap_mask &
7471 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7472 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7473 val |= (1<<5);
7474 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7475 }
7476
7477 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7478 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7479
7480 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7481 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7482 (phy->req_line_speed == SPEED_2500)) {
7483 u16 phy_ver;
7484 /* Allow 2.5G for A1 and above */
7485 bnx2x_cl45_read(bp, phy,
7486 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7487 &phy_ver);
7488 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7489 if (phy_ver > 0)
7490 tmp1 |= 1;
7491 else
7492 tmp1 &= 0xfffe;
7493 } else {
7494 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7495 tmp1 &= 0xfffe;
7496 }
7497
7498 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7499 /* Add support for CL37 (passive mode) II */
7500
7501 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7502 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7503 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7504 0x20 : 0x40)));
7505
7506 /* Add support for CL37 (passive mode) III */
7507 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7508
7509 /* The SNR will improve about 2db by changing BW and FEE main
7510 * tap. Rest commands are executed after link is up
7511 * Change FFE main cursor to 5 in EDC register
7512 */
7513 if (bnx2x_8073_is_snr_needed(bp, phy))
7514 bnx2x_cl45_write(bp, phy,
7515 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7516 0xFB0C);
7517
7518 /* Enable FEC (Forware Error Correction) Request in the AN */
7519 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7520 tmp1 |= (1<<15);
7521 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7522
7523 bnx2x_ext_phy_set_pause(params, phy, vars);
7524
7525 /* Restart autoneg */
7526 msleep(500);
7527 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7528 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7529 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7530 return 0;
7531 }
7532
bnx2x_8073_read_status(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)7533 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7534 struct link_params *params,
7535 struct link_vars *vars)
7536 {
7537 struct bnx2x *bp = params->bp;
7538 u8 link_up = 0;
7539 u16 val1, val2;
7540 u16 link_status = 0;
7541 u16 an1000_status = 0;
7542
7543 bnx2x_cl45_read(bp, phy,
7544 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7545
7546 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7547
7548 /* Clear the interrupt LASI status register */
7549 bnx2x_cl45_read(bp, phy,
7550 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7551 bnx2x_cl45_read(bp, phy,
7552 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7553 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7554 /* Clear MSG-OUT */
7555 bnx2x_cl45_read(bp, phy,
7556 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7557
7558 /* Check the LASI */
7559 bnx2x_cl45_read(bp, phy,
7560 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7561
7562 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7563
7564 /* Check the link status */
7565 bnx2x_cl45_read(bp, phy,
7566 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7567 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7568
7569 bnx2x_cl45_read(bp, phy,
7570 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7571 bnx2x_cl45_read(bp, phy,
7572 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7573 link_up = ((val1 & 4) == 4);
7574 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7575
7576 if (link_up &&
7577 ((phy->req_line_speed != SPEED_10000))) {
7578 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7579 return 0;
7580 }
7581 bnx2x_cl45_read(bp, phy,
7582 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7583 bnx2x_cl45_read(bp, phy,
7584 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7585
7586 /* Check the link status on 1.1.2 */
7587 bnx2x_cl45_read(bp, phy,
7588 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7589 bnx2x_cl45_read(bp, phy,
7590 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7591 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7592 "an_link_status=0x%x\n", val2, val1, an1000_status);
7593
7594 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7595 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7596 /* The SNR will improve about 2dbby changing the BW and FEE main
7597 * tap. The 1st write to change FFE main tap is set before
7598 * restart AN. Change PLL Bandwidth in EDC register
7599 */
7600 bnx2x_cl45_write(bp, phy,
7601 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7602 0x26BC);
7603
7604 /* Change CDR Bandwidth in EDC register */
7605 bnx2x_cl45_write(bp, phy,
7606 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7607 0x0333);
7608 }
7609 bnx2x_cl45_read(bp, phy,
7610 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7611 &link_status);
7612
7613 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7614 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7615 link_up = 1;
7616 vars->line_speed = SPEED_10000;
7617 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7618 params->port);
7619 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7620 link_up = 1;
7621 vars->line_speed = SPEED_2500;
7622 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7623 params->port);
7624 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7625 link_up = 1;
7626 vars->line_speed = SPEED_1000;
7627 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7628 params->port);
7629 } else {
7630 link_up = 0;
7631 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7632 params->port);
7633 }
7634
7635 if (link_up) {
7636 /* Swap polarity if required */
7637 if (params->lane_config &
7638 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7639 /* Configure the 8073 to swap P and N of the KR lines */
7640 bnx2x_cl45_read(bp, phy,
7641 MDIO_XS_DEVAD,
7642 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7643 /* Set bit 3 to invert Rx in 1G mode and clear this bit
7644 * when it`s in 10G mode.
7645 */
7646 if (vars->line_speed == SPEED_1000) {
7647 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7648 "the 8073\n");
7649 val1 |= (1<<3);
7650 } else
7651 val1 &= ~(1<<3);
7652
7653 bnx2x_cl45_write(bp, phy,
7654 MDIO_XS_DEVAD,
7655 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7656 val1);
7657 }
7658 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7659 bnx2x_8073_resolve_fc(phy, params, vars);
7660 vars->duplex = DUPLEX_FULL;
7661 }
7662
7663 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7664 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7665 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7666
7667 if (val1 & (1<<5))
7668 vars->link_status |=
7669 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7670 if (val1 & (1<<7))
7671 vars->link_status |=
7672 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7673 }
7674
7675 return link_up;
7676 }
7677
bnx2x_8073_link_reset(struct bnx2x_phy * phy,struct link_params * params)7678 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7679 struct link_params *params)
7680 {
7681 struct bnx2x *bp = params->bp;
7682 u8 gpio_port;
7683 if (CHIP_IS_E2(bp))
7684 gpio_port = BP_PATH(bp);
7685 else
7686 gpio_port = params->port;
7687 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7688 gpio_port);
7689 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7690 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7691 gpio_port);
7692 }
7693
7694 /******************************************************************/
7695 /* BCM8705 PHY SECTION */
7696 /******************************************************************/
bnx2x_8705_config_init(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)7697 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7698 struct link_params *params,
7699 struct link_vars *vars)
7700 {
7701 struct bnx2x *bp = params->bp;
7702 DP(NETIF_MSG_LINK, "init 8705\n");
7703 /* Restore normal power mode*/
7704 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7705 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7706 /* HW reset */
7707 bnx2x_ext_phy_hw_reset(bp, params->port);
7708 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7709 bnx2x_wait_reset_complete(bp, phy, params);
7710
7711 bnx2x_cl45_write(bp, phy,
7712 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7713 bnx2x_cl45_write(bp, phy,
7714 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7715 bnx2x_cl45_write(bp, phy,
7716 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7717 bnx2x_cl45_write(bp, phy,
7718 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7719 /* BCM8705 doesn't have microcode, hence the 0 */
7720 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7721 return 0;
7722 }
7723
bnx2x_8705_read_status(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)7724 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7725 struct link_params *params,
7726 struct link_vars *vars)
7727 {
7728 u8 link_up = 0;
7729 u16 val1, rx_sd;
7730 struct bnx2x *bp = params->bp;
7731 DP(NETIF_MSG_LINK, "read status 8705\n");
7732 bnx2x_cl45_read(bp, phy,
7733 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7734 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7735
7736 bnx2x_cl45_read(bp, phy,
7737 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7738 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7739
7740 bnx2x_cl45_read(bp, phy,
7741 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7742
7743 bnx2x_cl45_read(bp, phy,
7744 MDIO_PMA_DEVAD, 0xc809, &val1);
7745 bnx2x_cl45_read(bp, phy,
7746 MDIO_PMA_DEVAD, 0xc809, &val1);
7747
7748 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7749 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7750 if (link_up) {
7751 vars->line_speed = SPEED_10000;
7752 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7753 }
7754 return link_up;
7755 }
7756
7757 /******************************************************************/
7758 /* SFP+ module Section */
7759 /******************************************************************/
bnx2x_set_disable_pmd_transmit(struct link_params * params,struct bnx2x_phy * phy,u8 pmd_dis)7760 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7761 struct bnx2x_phy *phy,
7762 u8 pmd_dis)
7763 {
7764 struct bnx2x *bp = params->bp;
7765 /* Disable transmitter only for bootcodes which can enable it afterwards
7766 * (for D3 link)
7767 */
7768 if (pmd_dis) {
7769 if (params->feature_config_flags &
7770 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7771 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7772 else {
7773 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7774 return;
7775 }
7776 } else
7777 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7778 bnx2x_cl45_write(bp, phy,
7779 MDIO_PMA_DEVAD,
7780 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7781 }
7782
bnx2x_get_gpio_port(struct link_params * params)7783 static u8 bnx2x_get_gpio_port(struct link_params *params)
7784 {
7785 u8 gpio_port;
7786 u32 swap_val, swap_override;
7787 struct bnx2x *bp = params->bp;
7788 if (CHIP_IS_E2(bp))
7789 gpio_port = BP_PATH(bp);
7790 else
7791 gpio_port = params->port;
7792 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7793 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7794 return gpio_port ^ (swap_val && swap_override);
7795 }
7796
bnx2x_sfp_e1e2_set_transmitter(struct link_params * params,struct bnx2x_phy * phy,u8 tx_en)7797 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7798 struct bnx2x_phy *phy,
7799 u8 tx_en)
7800 {
7801 u16 val;
7802 u8 port = params->port;
7803 struct bnx2x *bp = params->bp;
7804 u32 tx_en_mode;
7805
7806 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7807 tx_en_mode = REG_RD(bp, params->shmem_base +
7808 offsetof(struct shmem_region,
7809 dev_info.port_hw_config[port].sfp_ctrl)) &
7810 PORT_HW_CFG_TX_LASER_MASK;
7811 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7812 "mode = %x\n", tx_en, port, tx_en_mode);
7813 switch (tx_en_mode) {
7814 case PORT_HW_CFG_TX_LASER_MDIO:
7815
7816 bnx2x_cl45_read(bp, phy,
7817 MDIO_PMA_DEVAD,
7818 MDIO_PMA_REG_PHY_IDENTIFIER,
7819 &val);
7820
7821 if (tx_en)
7822 val &= ~(1<<15);
7823 else
7824 val |= (1<<15);
7825
7826 bnx2x_cl45_write(bp, phy,
7827 MDIO_PMA_DEVAD,
7828 MDIO_PMA_REG_PHY_IDENTIFIER,
7829 val);
7830 break;
7831 case PORT_HW_CFG_TX_LASER_GPIO0:
7832 case PORT_HW_CFG_TX_LASER_GPIO1:
7833 case PORT_HW_CFG_TX_LASER_GPIO2:
7834 case PORT_HW_CFG_TX_LASER_GPIO3:
7835 {
7836 u16 gpio_pin;
7837 u8 gpio_port, gpio_mode;
7838 if (tx_en)
7839 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7840 else
7841 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7842
7843 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7844 gpio_port = bnx2x_get_gpio_port(params);
7845 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7846 break;
7847 }
7848 default:
7849 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7850 break;
7851 }
7852 }
7853
bnx2x_sfp_set_transmitter(struct link_params * params,struct bnx2x_phy * phy,u8 tx_en)7854 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7855 struct bnx2x_phy *phy,
7856 u8 tx_en)
7857 {
7858 struct bnx2x *bp = params->bp;
7859 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7860 if (CHIP_IS_E3(bp))
7861 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7862 else
7863 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7864 }
7865
bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy * phy,struct link_params * params,u8 dev_addr,u16 addr,u8 byte_cnt,u8 * o_buf,u8 is_init)7866 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7867 struct link_params *params,
7868 u8 dev_addr, u16 addr, u8 byte_cnt,
7869 u8 *o_buf, u8 is_init)
7870 {
7871 struct bnx2x *bp = params->bp;
7872 u16 val = 0;
7873 u16 i;
7874 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7875 DP(NETIF_MSG_LINK,
7876 "Reading from eeprom is limited to 0xf\n");
7877 return -EINVAL;
7878 }
7879 /* Set the read command byte count */
7880 bnx2x_cl45_write(bp, phy,
7881 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7882 (byte_cnt | (dev_addr << 8)));
7883
7884 /* Set the read command address */
7885 bnx2x_cl45_write(bp, phy,
7886 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7887 addr);
7888
7889 /* Activate read command */
7890 bnx2x_cl45_write(bp, phy,
7891 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7892 0x2c0f);
7893
7894 /* Wait up to 500us for command complete status */
7895 for (i = 0; i < 100; i++) {
7896 bnx2x_cl45_read(bp, phy,
7897 MDIO_PMA_DEVAD,
7898 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7899 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7900 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7901 break;
7902 udelay(5);
7903 }
7904
7905 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7906 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7907 DP(NETIF_MSG_LINK,
7908 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7909 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7910 return -EINVAL;
7911 }
7912
7913 /* Read the buffer */
7914 for (i = 0; i < byte_cnt; i++) {
7915 bnx2x_cl45_read(bp, phy,
7916 MDIO_PMA_DEVAD,
7917 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7918 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7919 }
7920
7921 for (i = 0; i < 100; i++) {
7922 bnx2x_cl45_read(bp, phy,
7923 MDIO_PMA_DEVAD,
7924 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7925 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7926 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7927 return 0;
7928 usleep_range(1000, 2000);
7929 }
7930 return -EINVAL;
7931 }
7932
bnx2x_warpcore_power_module(struct link_params * params,u8 power)7933 static void bnx2x_warpcore_power_module(struct link_params *params,
7934 u8 power)
7935 {
7936 u32 pin_cfg;
7937 struct bnx2x *bp = params->bp;
7938
7939 pin_cfg = (REG_RD(bp, params->shmem_base +
7940 offsetof(struct shmem_region,
7941 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7942 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7943 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7944
7945 if (pin_cfg == PIN_CFG_NA)
7946 return;
7947 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7948 power, pin_cfg);
7949 /* Low ==> corresponding SFP+ module is powered
7950 * high ==> the SFP+ module is powered down
7951 */
7952 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7953 }
bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy * phy,struct link_params * params,u8 dev_addr,u16 addr,u8 byte_cnt,u8 * o_buf,u8 is_init)7954 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7955 struct link_params *params,
7956 u8 dev_addr,
7957 u16 addr, u8 byte_cnt,
7958 u8 *o_buf, u8 is_init)
7959 {
7960 int rc = 0;
7961 u8 i, j = 0, cnt = 0;
7962 u32 data_array[4];
7963 u16 addr32;
7964 struct bnx2x *bp = params->bp;
7965
7966 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7967 DP(NETIF_MSG_LINK,
7968 "Reading from eeprom is limited to 16 bytes\n");
7969 return -EINVAL;
7970 }
7971
7972 /* 4 byte aligned address */
7973 addr32 = addr & (~0x3);
7974 do {
7975 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7976 bnx2x_warpcore_power_module(params, 0);
7977 /* Note that 100us are not enough here */
7978 usleep_range(1000, 2000);
7979 bnx2x_warpcore_power_module(params, 1);
7980 }
7981 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt,
7982 data_array);
7983 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7984
7985 if (rc == 0) {
7986 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7987 o_buf[j] = *((u8 *)data_array + i);
7988 j++;
7989 }
7990 }
7991
7992 return rc;
7993 }
7994
bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy * phy,struct link_params * params,u8 dev_addr,u16 addr,u8 byte_cnt,u8 * o_buf,u8 is_init)7995 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7996 struct link_params *params,
7997 u8 dev_addr, u16 addr, u8 byte_cnt,
7998 u8 *o_buf, u8 is_init)
7999 {
8000 struct bnx2x *bp = params->bp;
8001 u16 val, i;
8002
8003 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
8004 DP(NETIF_MSG_LINK,
8005 "Reading from eeprom is limited to 0xf\n");
8006 return -EINVAL;
8007 }
8008
8009 /* Set 2-wire transfer rate of SFP+ module EEPROM
8010 * to 100Khz since some DACs(direct attached cables) do
8011 * not work at 400Khz.
8012 */
8013 bnx2x_cl45_write(bp, phy,
8014 MDIO_PMA_DEVAD,
8015 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8016 ((dev_addr << 8) | 1));
8017
8018 /* Need to read from 1.8000 to clear it */
8019 bnx2x_cl45_read(bp, phy,
8020 MDIO_PMA_DEVAD,
8021 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8022 &val);
8023
8024 /* Set the read command byte count */
8025 bnx2x_cl45_write(bp, phy,
8026 MDIO_PMA_DEVAD,
8027 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8028 ((byte_cnt < 2) ? 2 : byte_cnt));
8029
8030 /* Set the read command address */
8031 bnx2x_cl45_write(bp, phy,
8032 MDIO_PMA_DEVAD,
8033 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8034 addr);
8035 /* Set the destination address */
8036 bnx2x_cl45_write(bp, phy,
8037 MDIO_PMA_DEVAD,
8038 0x8004,
8039 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
8040
8041 /* Activate read command */
8042 bnx2x_cl45_write(bp, phy,
8043 MDIO_PMA_DEVAD,
8044 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8045 0x8002);
8046 /* Wait appropriate time for two-wire command to finish before
8047 * polling the status register
8048 */
8049 usleep_range(1000, 2000);
8050
8051 /* Wait up to 500us for command complete status */
8052 for (i = 0; i < 100; i++) {
8053 bnx2x_cl45_read(bp, phy,
8054 MDIO_PMA_DEVAD,
8055 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8056 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8057 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8058 break;
8059 udelay(5);
8060 }
8061
8062 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8063 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8064 DP(NETIF_MSG_LINK,
8065 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8066 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8067 return -EFAULT;
8068 }
8069
8070 /* Read the buffer */
8071 for (i = 0; i < byte_cnt; i++) {
8072 bnx2x_cl45_read(bp, phy,
8073 MDIO_PMA_DEVAD,
8074 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8075 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8076 }
8077
8078 for (i = 0; i < 100; i++) {
8079 bnx2x_cl45_read(bp, phy,
8080 MDIO_PMA_DEVAD,
8081 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8082 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8083 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8084 return 0;
8085 usleep_range(1000, 2000);
8086 }
8087
8088 return -EINVAL;
8089 }
bnx2x_read_sfp_module_eeprom(struct bnx2x_phy * phy,struct link_params * params,u8 dev_addr,u16 addr,u16 byte_cnt,u8 * o_buf)8090 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
8091 struct link_params *params, u8 dev_addr,
8092 u16 addr, u16 byte_cnt, u8 *o_buf)
8093 {
8094 int rc = 0;
8095 struct bnx2x *bp = params->bp;
8096 u8 xfer_size;
8097 u8 *user_data = o_buf;
8098 read_sfp_module_eeprom_func_p read_func;
8099
8100 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8101 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
8102 return -EINVAL;
8103 }
8104
8105 switch (phy->type) {
8106 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8107 read_func = bnx2x_8726_read_sfp_module_eeprom;
8108 break;
8109 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8110 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8111 read_func = bnx2x_8727_read_sfp_module_eeprom;
8112 break;
8113 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8114 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8115 break;
8116 default:
8117 return -EOPNOTSUPP;
8118 }
8119
8120 while (!rc && (byte_cnt > 0)) {
8121 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8122 SFP_EEPROM_PAGE_SIZE : byte_cnt;
8123 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8124 user_data, 0);
8125 byte_cnt -= xfer_size;
8126 user_data += xfer_size;
8127 addr += xfer_size;
8128 }
8129 return rc;
8130 }
8131
bnx2x_get_edc_mode(struct bnx2x_phy * phy,struct link_params * params,u16 * edc_mode)8132 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8133 struct link_params *params,
8134 u16 *edc_mode)
8135 {
8136 struct bnx2x *bp = params->bp;
8137 u32 sync_offset = 0, phy_idx, media_types;
8138 u8 val[SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0;
8139 *edc_mode = EDC_MODE_LIMITING;
8140 phy->media_type = ETH_PHY_UNSPECIFIED;
8141 /* First check for copper cable */
8142 if (bnx2x_read_sfp_module_eeprom(phy,
8143 params,
8144 I2C_DEV_ADDR_A0,
8145 0,
8146 SFP_EEPROM_FC_TX_TECH_ADDR + 1,
8147 (u8 *)val) != 0) {
8148 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8149 return -EINVAL;
8150 }
8151 params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK;
8152 params->link_attr_sync |= val[SFP_EEPROM_10G_COMP_CODE_ADDR] <<
8153 LINK_SFP_EEPROM_COMP_CODE_SHIFT;
8154 bnx2x_update_link_attr(params, params->link_attr_sync);
8155 switch (val[SFP_EEPROM_CON_TYPE_ADDR]) {
8156 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8157 {
8158 u8 copper_module_type;
8159 phy->media_type = ETH_PHY_DA_TWINAX;
8160 /* Check if its active cable (includes SFP+ module)
8161 * of passive cable
8162 */
8163 copper_module_type = val[SFP_EEPROM_FC_TX_TECH_ADDR];
8164
8165 if (copper_module_type &
8166 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8167 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8168 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8169 *edc_mode = EDC_MODE_ACTIVE_DAC;
8170 else
8171 check_limiting_mode = 1;
8172 } else {
8173 *edc_mode = EDC_MODE_PASSIVE_DAC;
8174 /* Even in case PASSIVE_DAC indication is not set,
8175 * treat it as a passive DAC cable, since some cables
8176 * don't have this indication.
8177 */
8178 if (copper_module_type &
8179 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8180 DP(NETIF_MSG_LINK,
8181 "Passive Copper cable detected\n");
8182 } else {
8183 DP(NETIF_MSG_LINK,
8184 "Unknown copper-cable-type\n");
8185 }
8186 }
8187 break;
8188 }
8189 case SFP_EEPROM_CON_TYPE_VAL_UNKNOWN:
8190 case SFP_EEPROM_CON_TYPE_VAL_LC:
8191 case SFP_EEPROM_CON_TYPE_VAL_RJ45:
8192 check_limiting_mode = 1;
8193 if (((val[SFP_EEPROM_10G_COMP_CODE_ADDR] &
8194 (SFP_EEPROM_10G_COMP_CODE_SR_MASK |
8195 SFP_EEPROM_10G_COMP_CODE_LR_MASK |
8196 SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) &&
8197 (val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) {
8198 DP(NETIF_MSG_LINK, "1G SFP module detected\n");
8199 phy->media_type = ETH_PHY_SFP_1G_FIBER;
8200 if (phy->req_line_speed != SPEED_1000) {
8201 u8 gport = params->port;
8202 phy->req_line_speed = SPEED_1000;
8203 if (!CHIP_IS_E1x(bp)) {
8204 gport = BP_PATH(bp) +
8205 (params->port << 1);
8206 }
8207 netdev_err(bp->dev,
8208 "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8209 gport);
8210 }
8211 if (val[SFP_EEPROM_1G_COMP_CODE_ADDR] &
8212 SFP_EEPROM_1G_COMP_CODE_BASE_T) {
8213 bnx2x_sfp_set_transmitter(params, phy, 0);
8214 msleep(40);
8215 bnx2x_sfp_set_transmitter(params, phy, 1);
8216 }
8217 } else {
8218 int idx, cfg_idx = 0;
8219 DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8220 for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8221 if (params->phy[idx].type == phy->type) {
8222 cfg_idx = LINK_CONFIG_IDX(idx);
8223 break;
8224 }
8225 }
8226 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8227 phy->req_line_speed = params->req_line_speed[cfg_idx];
8228 }
8229 break;
8230 default:
8231 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8232 val[SFP_EEPROM_CON_TYPE_ADDR]);
8233 return -EINVAL;
8234 }
8235 sync_offset = params->shmem_base +
8236 offsetof(struct shmem_region,
8237 dev_info.port_hw_config[params->port].media_type);
8238 media_types = REG_RD(bp, sync_offset);
8239 /* Update media type for non-PMF sync */
8240 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8241 if (&(params->phy[phy_idx]) == phy) {
8242 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8243 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8244 media_types |= ((phy->media_type &
8245 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8246 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8247 break;
8248 }
8249 }
8250 REG_WR(bp, sync_offset, media_types);
8251 if (check_limiting_mode) {
8252 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8253 if (bnx2x_read_sfp_module_eeprom(phy,
8254 params,
8255 I2C_DEV_ADDR_A0,
8256 SFP_EEPROM_OPTIONS_ADDR,
8257 SFP_EEPROM_OPTIONS_SIZE,
8258 options) != 0) {
8259 DP(NETIF_MSG_LINK,
8260 "Failed to read Option field from module EEPROM\n");
8261 return -EINVAL;
8262 }
8263 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8264 *edc_mode = EDC_MODE_LINEAR;
8265 else
8266 *edc_mode = EDC_MODE_LIMITING;
8267 }
8268 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8269 return 0;
8270 }
8271 /* This function read the relevant field from the module (SFP+), and verify it
8272 * is compliant with this board
8273 */
bnx2x_verify_sfp_module(struct bnx2x_phy * phy,struct link_params * params)8274 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8275 struct link_params *params)
8276 {
8277 struct bnx2x *bp = params->bp;
8278 u32 val, cmd;
8279 u32 fw_resp, fw_cmd_param;
8280 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8281 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8282 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8283 val = REG_RD(bp, params->shmem_base +
8284 offsetof(struct shmem_region, dev_info.
8285 port_feature_config[params->port].config));
8286 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8287 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8288 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8289 return 0;
8290 }
8291
8292 if (params->feature_config_flags &
8293 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8294 /* Use specific phy request */
8295 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8296 } else if (params->feature_config_flags &
8297 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8298 /* Use first phy request only in case of non-dual media*/
8299 if (DUAL_MEDIA(params)) {
8300 DP(NETIF_MSG_LINK,
8301 "FW does not support OPT MDL verification\n");
8302 return -EINVAL;
8303 }
8304 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8305 } else {
8306 /* No support in OPT MDL detection */
8307 DP(NETIF_MSG_LINK,
8308 "FW does not support OPT MDL verification\n");
8309 return -EINVAL;
8310 }
8311
8312 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8313 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8314 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8315 DP(NETIF_MSG_LINK, "Approved module\n");
8316 return 0;
8317 }
8318
8319 /* Format the warning message */
8320 if (bnx2x_read_sfp_module_eeprom(phy,
8321 params,
8322 I2C_DEV_ADDR_A0,
8323 SFP_EEPROM_VENDOR_NAME_ADDR,
8324 SFP_EEPROM_VENDOR_NAME_SIZE,
8325 (u8 *)vendor_name))
8326 vendor_name[0] = '\0';
8327 else
8328 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8329 if (bnx2x_read_sfp_module_eeprom(phy,
8330 params,
8331 I2C_DEV_ADDR_A0,
8332 SFP_EEPROM_PART_NO_ADDR,
8333 SFP_EEPROM_PART_NO_SIZE,
8334 (u8 *)vendor_pn))
8335 vendor_pn[0] = '\0';
8336 else
8337 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8338
8339 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
8340 " Port %d from %s part number %s\n",
8341 params->port, vendor_name, vendor_pn);
8342 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8343 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8344 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8345 return -EINVAL;
8346 }
8347
bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy * phy,struct link_params * params)8348 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8349 struct link_params *params)
8350
8351 {
8352 u8 val;
8353 int rc;
8354 struct bnx2x *bp = params->bp;
8355 u16 timeout;
8356 /* Initialization time after hot-plug may take up to 300ms for
8357 * some phys type ( e.g. JDSU )
8358 */
8359
8360 for (timeout = 0; timeout < 60; timeout++) {
8361 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8362 rc = bnx2x_warpcore_read_sfp_module_eeprom(
8363 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8364 1);
8365 else
8366 rc = bnx2x_read_sfp_module_eeprom(phy, params,
8367 I2C_DEV_ADDR_A0,
8368 1, 1, &val);
8369 if (rc == 0) {
8370 DP(NETIF_MSG_LINK,
8371 "SFP+ module initialization took %d ms\n",
8372 timeout * 5);
8373 return 0;
8374 }
8375 usleep_range(5000, 10000);
8376 }
8377 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8378 1, 1, &val);
8379 return rc;
8380 }
8381
bnx2x_8727_power_module(struct bnx2x * bp,struct bnx2x_phy * phy,u8 is_power_up)8382 static void bnx2x_8727_power_module(struct bnx2x *bp,
8383 struct bnx2x_phy *phy,
8384 u8 is_power_up) {
8385 /* Make sure GPIOs are not using for LED mode */
8386 u16 val;
8387 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8388 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8389 * output
8390 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8391 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8392 * where the 1st bit is the over-current(only input), and 2nd bit is
8393 * for power( only output )
8394 *
8395 * In case of NOC feature is disabled and power is up, set GPIO control
8396 * as input to enable listening of over-current indication
8397 */
8398 if (phy->flags & FLAGS_NOC)
8399 return;
8400 if (is_power_up)
8401 val = (1<<4);
8402 else
8403 /* Set GPIO control to OUTPUT, and set the power bit
8404 * to according to the is_power_up
8405 */
8406 val = (1<<1);
8407
8408 bnx2x_cl45_write(bp, phy,
8409 MDIO_PMA_DEVAD,
8410 MDIO_PMA_REG_8727_GPIO_CTRL,
8411 val);
8412 }
8413
bnx2x_8726_set_limiting_mode(struct bnx2x * bp,struct bnx2x_phy * phy,u16 edc_mode)8414 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8415 struct bnx2x_phy *phy,
8416 u16 edc_mode)
8417 {
8418 u16 cur_limiting_mode;
8419
8420 bnx2x_cl45_read(bp, phy,
8421 MDIO_PMA_DEVAD,
8422 MDIO_PMA_REG_ROM_VER2,
8423 &cur_limiting_mode);
8424 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8425 cur_limiting_mode);
8426
8427 if (edc_mode == EDC_MODE_LIMITING) {
8428 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8429 bnx2x_cl45_write(bp, phy,
8430 MDIO_PMA_DEVAD,
8431 MDIO_PMA_REG_ROM_VER2,
8432 EDC_MODE_LIMITING);
8433 } else { /* LRM mode ( default )*/
8434
8435 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8436
8437 /* Changing to LRM mode takes quite few seconds. So do it only
8438 * if current mode is limiting (default is LRM)
8439 */
8440 if (cur_limiting_mode != EDC_MODE_LIMITING)
8441 return 0;
8442
8443 bnx2x_cl45_write(bp, phy,
8444 MDIO_PMA_DEVAD,
8445 MDIO_PMA_REG_LRM_MODE,
8446 0);
8447 bnx2x_cl45_write(bp, phy,
8448 MDIO_PMA_DEVAD,
8449 MDIO_PMA_REG_ROM_VER2,
8450 0x128);
8451 bnx2x_cl45_write(bp, phy,
8452 MDIO_PMA_DEVAD,
8453 MDIO_PMA_REG_MISC_CTRL0,
8454 0x4008);
8455 bnx2x_cl45_write(bp, phy,
8456 MDIO_PMA_DEVAD,
8457 MDIO_PMA_REG_LRM_MODE,
8458 0xaaaa);
8459 }
8460 return 0;
8461 }
8462
bnx2x_8727_set_limiting_mode(struct bnx2x * bp,struct bnx2x_phy * phy,u16 edc_mode)8463 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8464 struct bnx2x_phy *phy,
8465 u16 edc_mode)
8466 {
8467 u16 phy_identifier;
8468 u16 rom_ver2_val;
8469 bnx2x_cl45_read(bp, phy,
8470 MDIO_PMA_DEVAD,
8471 MDIO_PMA_REG_PHY_IDENTIFIER,
8472 &phy_identifier);
8473
8474 bnx2x_cl45_write(bp, phy,
8475 MDIO_PMA_DEVAD,
8476 MDIO_PMA_REG_PHY_IDENTIFIER,
8477 (phy_identifier & ~(1<<9)));
8478
8479 bnx2x_cl45_read(bp, phy,
8480 MDIO_PMA_DEVAD,
8481 MDIO_PMA_REG_ROM_VER2,
8482 &rom_ver2_val);
8483 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8484 bnx2x_cl45_write(bp, phy,
8485 MDIO_PMA_DEVAD,
8486 MDIO_PMA_REG_ROM_VER2,
8487 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8488
8489 bnx2x_cl45_write(bp, phy,
8490 MDIO_PMA_DEVAD,
8491 MDIO_PMA_REG_PHY_IDENTIFIER,
8492 (phy_identifier | (1<<9)));
8493
8494 return 0;
8495 }
8496
bnx2x_8727_specific_func(struct bnx2x_phy * phy,struct link_params * params,u32 action)8497 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8498 struct link_params *params,
8499 u32 action)
8500 {
8501 struct bnx2x *bp = params->bp;
8502 u16 val;
8503 switch (action) {
8504 case DISABLE_TX:
8505 bnx2x_sfp_set_transmitter(params, phy, 0);
8506 break;
8507 case ENABLE_TX:
8508 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8509 bnx2x_sfp_set_transmitter(params, phy, 1);
8510 break;
8511 case PHY_INIT:
8512 bnx2x_cl45_write(bp, phy,
8513 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8514 (1<<2) | (1<<5));
8515 bnx2x_cl45_write(bp, phy,
8516 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8517 0);
8518 bnx2x_cl45_write(bp, phy,
8519 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8520 /* Make MOD_ABS give interrupt on change */
8521 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8522 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8523 &val);
8524 val |= (1<<12);
8525 if (phy->flags & FLAGS_NOC)
8526 val |= (3<<5);
8527 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8528 * status which reflect SFP+ module over-current
8529 */
8530 if (!(phy->flags & FLAGS_NOC))
8531 val &= 0xff8f; /* Reset bits 4-6 */
8532 bnx2x_cl45_write(bp, phy,
8533 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8534 val);
8535 break;
8536 default:
8537 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8538 action);
8539 return;
8540 }
8541 }
8542
bnx2x_set_e1e2_module_fault_led(struct link_params * params,u8 gpio_mode)8543 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8544 u8 gpio_mode)
8545 {
8546 struct bnx2x *bp = params->bp;
8547
8548 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8549 offsetof(struct shmem_region,
8550 dev_info.port_hw_config[params->port].sfp_ctrl)) &
8551 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8552 switch (fault_led_gpio) {
8553 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8554 return;
8555 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8556 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8557 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8558 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8559 {
8560 u8 gpio_port = bnx2x_get_gpio_port(params);
8561 u16 gpio_pin = fault_led_gpio -
8562 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8563 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8564 "pin %x port %x mode %x\n",
8565 gpio_pin, gpio_port, gpio_mode);
8566 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8567 }
8568 break;
8569 default:
8570 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8571 fault_led_gpio);
8572 }
8573 }
8574
bnx2x_set_e3_module_fault_led(struct link_params * params,u8 gpio_mode)8575 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8576 u8 gpio_mode)
8577 {
8578 u32 pin_cfg;
8579 u8 port = params->port;
8580 struct bnx2x *bp = params->bp;
8581 pin_cfg = (REG_RD(bp, params->shmem_base +
8582 offsetof(struct shmem_region,
8583 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8584 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8585 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8586 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8587 gpio_mode, pin_cfg);
8588 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8589 }
8590
bnx2x_set_sfp_module_fault_led(struct link_params * params,u8 gpio_mode)8591 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8592 u8 gpio_mode)
8593 {
8594 struct bnx2x *bp = params->bp;
8595 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8596 if (CHIP_IS_E3(bp)) {
8597 /* Low ==> if SFP+ module is supported otherwise
8598 * High ==> if SFP+ module is not on the approved vendor list
8599 */
8600 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8601 } else
8602 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8603 }
8604
bnx2x_warpcore_hw_reset(struct bnx2x_phy * phy,struct link_params * params)8605 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8606 struct link_params *params)
8607 {
8608 struct bnx2x *bp = params->bp;
8609 bnx2x_warpcore_power_module(params, 0);
8610 /* Put Warpcore in low power mode */
8611 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8612
8613 /* Put LCPLL in low power mode */
8614 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8615 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8616 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8617 }
8618
bnx2x_power_sfp_module(struct link_params * params,struct bnx2x_phy * phy,u8 power)8619 static void bnx2x_power_sfp_module(struct link_params *params,
8620 struct bnx2x_phy *phy,
8621 u8 power)
8622 {
8623 struct bnx2x *bp = params->bp;
8624 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8625
8626 switch (phy->type) {
8627 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8628 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8629 bnx2x_8727_power_module(params->bp, phy, power);
8630 break;
8631 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8632 bnx2x_warpcore_power_module(params, power);
8633 break;
8634 default:
8635 break;
8636 }
8637 }
bnx2x_warpcore_set_limiting_mode(struct link_params * params,struct bnx2x_phy * phy,u16 edc_mode)8638 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8639 struct bnx2x_phy *phy,
8640 u16 edc_mode)
8641 {
8642 u16 val = 0;
8643 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8644 struct bnx2x *bp = params->bp;
8645
8646 u8 lane = bnx2x_get_warpcore_lane(phy, params);
8647 /* This is a global register which controls all lanes */
8648 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8649 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8650 val &= ~(0xf << (lane << 2));
8651
8652 switch (edc_mode) {
8653 case EDC_MODE_LINEAR:
8654 case EDC_MODE_LIMITING:
8655 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8656 break;
8657 case EDC_MODE_PASSIVE_DAC:
8658 case EDC_MODE_ACTIVE_DAC:
8659 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8660 break;
8661 default:
8662 break;
8663 }
8664
8665 val |= (mode << (lane << 2));
8666 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8667 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8668 /* A must read */
8669 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8670 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8671
8672 /* Restart microcode to re-read the new mode */
8673 bnx2x_warpcore_reset_lane(bp, phy, 1);
8674 bnx2x_warpcore_reset_lane(bp, phy, 0);
8675
8676 }
8677
bnx2x_set_limiting_mode(struct link_params * params,struct bnx2x_phy * phy,u16 edc_mode)8678 static void bnx2x_set_limiting_mode(struct link_params *params,
8679 struct bnx2x_phy *phy,
8680 u16 edc_mode)
8681 {
8682 switch (phy->type) {
8683 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8684 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8685 break;
8686 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8687 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8688 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8689 break;
8690 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8691 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8692 break;
8693 }
8694 }
8695
bnx2x_sfp_module_detection(struct bnx2x_phy * phy,struct link_params * params)8696 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8697 struct link_params *params)
8698 {
8699 struct bnx2x *bp = params->bp;
8700 u16 edc_mode;
8701 int rc = 0;
8702
8703 u32 val = REG_RD(bp, params->shmem_base +
8704 offsetof(struct shmem_region, dev_info.
8705 port_feature_config[params->port].config));
8706 /* Enabled transmitter by default */
8707 bnx2x_sfp_set_transmitter(params, phy, 1);
8708 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8709 params->port);
8710 /* Power up module */
8711 bnx2x_power_sfp_module(params, phy, 1);
8712 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8713 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8714 return -EINVAL;
8715 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8716 /* Check SFP+ module compatibility */
8717 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8718 rc = -EINVAL;
8719 /* Turn on fault module-detected led */
8720 bnx2x_set_sfp_module_fault_led(params,
8721 MISC_REGISTERS_GPIO_HIGH);
8722
8723 /* Check if need to power down the SFP+ module */
8724 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8725 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8726 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8727 bnx2x_power_sfp_module(params, phy, 0);
8728 return rc;
8729 }
8730 } else {
8731 /* Turn off fault module-detected led */
8732 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8733 }
8734
8735 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8736 * is done automatically
8737 */
8738 bnx2x_set_limiting_mode(params, phy, edc_mode);
8739
8740 /* Disable transmit for this module if the module is not approved, and
8741 * laser needs to be disabled.
8742 */
8743 if ((rc) &&
8744 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8745 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8746 bnx2x_sfp_set_transmitter(params, phy, 0);
8747
8748 return rc;
8749 }
8750
bnx2x_handle_module_detect_int(struct link_params * params)8751 void bnx2x_handle_module_detect_int(struct link_params *params)
8752 {
8753 struct bnx2x *bp = params->bp;
8754 struct bnx2x_phy *phy;
8755 u32 gpio_val;
8756 u8 gpio_num, gpio_port;
8757 if (CHIP_IS_E3(bp)) {
8758 phy = ¶ms->phy[INT_PHY];
8759 /* Always enable TX laser,will be disabled in case of fault */
8760 bnx2x_sfp_set_transmitter(params, phy, 1);
8761 } else {
8762 phy = ¶ms->phy[EXT_PHY1];
8763 }
8764 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8765 params->port, &gpio_num, &gpio_port) ==
8766 -EINVAL) {
8767 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8768 return;
8769 }
8770
8771 /* Set valid module led off */
8772 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8773
8774 /* Get current gpio val reflecting module plugged in / out*/
8775 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8776
8777 /* Call the handling function in case module is detected */
8778 if (gpio_val == 0) {
8779 bnx2x_set_mdio_emac_per_phy(bp, params);
8780 bnx2x_set_aer_mmd(params, phy);
8781
8782 bnx2x_power_sfp_module(params, phy, 1);
8783 bnx2x_set_gpio_int(bp, gpio_num,
8784 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8785 gpio_port);
8786 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8787 bnx2x_sfp_module_detection(phy, params);
8788 if (CHIP_IS_E3(bp)) {
8789 u16 rx_tx_in_reset;
8790 /* In case WC is out of reset, reconfigure the
8791 * link speed while taking into account 1G
8792 * module limitation.
8793 */
8794 bnx2x_cl45_read(bp, phy,
8795 MDIO_WC_DEVAD,
8796 MDIO_WC_REG_DIGITAL5_MISC6,
8797 &rx_tx_in_reset);
8798 if ((!rx_tx_in_reset) &&
8799 (params->link_flags &
8800 PHY_INITIALIZED)) {
8801 bnx2x_warpcore_reset_lane(bp, phy, 1);
8802 bnx2x_warpcore_config_sfi(phy, params);
8803 bnx2x_warpcore_reset_lane(bp, phy, 0);
8804 }
8805 }
8806 } else {
8807 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8808 }
8809 } else {
8810 bnx2x_set_gpio_int(bp, gpio_num,
8811 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8812 gpio_port);
8813 /* Module was plugged out.
8814 * Disable transmit for this module
8815 */
8816 phy->media_type = ETH_PHY_NOT_PRESENT;
8817 }
8818 }
8819
8820 /******************************************************************/
8821 /* Used by 8706 and 8727 */
8822 /******************************************************************/
bnx2x_sfp_mask_fault(struct bnx2x * bp,struct bnx2x_phy * phy,u16 alarm_status_offset,u16 alarm_ctrl_offset)8823 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8824 struct bnx2x_phy *phy,
8825 u16 alarm_status_offset,
8826 u16 alarm_ctrl_offset)
8827 {
8828 u16 alarm_status, val;
8829 bnx2x_cl45_read(bp, phy,
8830 MDIO_PMA_DEVAD, alarm_status_offset,
8831 &alarm_status);
8832 bnx2x_cl45_read(bp, phy,
8833 MDIO_PMA_DEVAD, alarm_status_offset,
8834 &alarm_status);
8835 /* Mask or enable the fault event. */
8836 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8837 if (alarm_status & (1<<0))
8838 val &= ~(1<<0);
8839 else
8840 val |= (1<<0);
8841 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8842 }
8843 /******************************************************************/
8844 /* common BCM8706/BCM8726 PHY SECTION */
8845 /******************************************************************/
bnx2x_8706_8726_read_status(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)8846 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8847 struct link_params *params,
8848 struct link_vars *vars)
8849 {
8850 u8 link_up = 0;
8851 u16 val1, val2, rx_sd, pcs_status;
8852 struct bnx2x *bp = params->bp;
8853 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8854 /* Clear RX Alarm*/
8855 bnx2x_cl45_read(bp, phy,
8856 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8857
8858 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8859 MDIO_PMA_LASI_TXCTRL);
8860
8861 /* Clear LASI indication*/
8862 bnx2x_cl45_read(bp, phy,
8863 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8864 bnx2x_cl45_read(bp, phy,
8865 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8866 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8867
8868 bnx2x_cl45_read(bp, phy,
8869 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8870 bnx2x_cl45_read(bp, phy,
8871 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8872 bnx2x_cl45_read(bp, phy,
8873 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8874 bnx2x_cl45_read(bp, phy,
8875 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8876
8877 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8878 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8879 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8880 * are set, or if the autoneg bit 1 is set
8881 */
8882 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8883 if (link_up) {
8884 if (val2 & (1<<1))
8885 vars->line_speed = SPEED_1000;
8886 else
8887 vars->line_speed = SPEED_10000;
8888 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8889 vars->duplex = DUPLEX_FULL;
8890 }
8891
8892 /* Capture 10G link fault. Read twice to clear stale value. */
8893 if (vars->line_speed == SPEED_10000) {
8894 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8895 MDIO_PMA_LASI_TXSTAT, &val1);
8896 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8897 MDIO_PMA_LASI_TXSTAT, &val1);
8898 if (val1 & (1<<0))
8899 vars->fault_detected = 1;
8900 }
8901
8902 return link_up;
8903 }
8904
8905 /******************************************************************/
8906 /* BCM8706 PHY SECTION */
8907 /******************************************************************/
bnx2x_8706_config_init(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)8908 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8909 struct link_params *params,
8910 struct link_vars *vars)
8911 {
8912 u32 tx_en_mode;
8913 u16 cnt, val, tmp1;
8914 struct bnx2x *bp = params->bp;
8915
8916 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8917 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8918 /* HW reset */
8919 bnx2x_ext_phy_hw_reset(bp, params->port);
8920 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8921 bnx2x_wait_reset_complete(bp, phy, params);
8922
8923 /* Wait until fw is loaded */
8924 for (cnt = 0; cnt < 100; cnt++) {
8925 bnx2x_cl45_read(bp, phy,
8926 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8927 if (val)
8928 break;
8929 usleep_range(10000, 20000);
8930 }
8931 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8932 if ((params->feature_config_flags &
8933 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8934 u8 i;
8935 u16 reg;
8936 for (i = 0; i < 4; i++) {
8937 reg = MDIO_XS_8706_REG_BANK_RX0 +
8938 i*(MDIO_XS_8706_REG_BANK_RX1 -
8939 MDIO_XS_8706_REG_BANK_RX0);
8940 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8941 /* Clear first 3 bits of the control */
8942 val &= ~0x7;
8943 /* Set control bits according to configuration */
8944 val |= (phy->rx_preemphasis[i] & 0x7);
8945 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8946 " reg 0x%x <-- val 0x%x\n", reg, val);
8947 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8948 }
8949 }
8950 /* Force speed */
8951 if (phy->req_line_speed == SPEED_10000) {
8952 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8953
8954 bnx2x_cl45_write(bp, phy,
8955 MDIO_PMA_DEVAD,
8956 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8957 bnx2x_cl45_write(bp, phy,
8958 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8959 0);
8960 /* Arm LASI for link and Tx fault. */
8961 bnx2x_cl45_write(bp, phy,
8962 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8963 } else {
8964 /* Force 1Gbps using autoneg with 1G advertisement */
8965
8966 /* Allow CL37 through CL73 */
8967 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8968 bnx2x_cl45_write(bp, phy,
8969 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8970
8971 /* Enable Full-Duplex advertisement on CL37 */
8972 bnx2x_cl45_write(bp, phy,
8973 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8974 /* Enable CL37 AN */
8975 bnx2x_cl45_write(bp, phy,
8976 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8977 /* 1G support */
8978 bnx2x_cl45_write(bp, phy,
8979 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8980
8981 /* Enable clause 73 AN */
8982 bnx2x_cl45_write(bp, phy,
8983 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8984 bnx2x_cl45_write(bp, phy,
8985 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8986 0x0400);
8987 bnx2x_cl45_write(bp, phy,
8988 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8989 0x0004);
8990 }
8991 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8992
8993 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8994 * power mode, if TX Laser is disabled
8995 */
8996
8997 tx_en_mode = REG_RD(bp, params->shmem_base +
8998 offsetof(struct shmem_region,
8999 dev_info.port_hw_config[params->port].sfp_ctrl))
9000 & PORT_HW_CFG_TX_LASER_MASK;
9001
9002 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9003 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9004 bnx2x_cl45_read(bp, phy,
9005 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
9006 tmp1 |= 0x1;
9007 bnx2x_cl45_write(bp, phy,
9008 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
9009 }
9010
9011 return 0;
9012 }
9013
bnx2x_8706_read_status(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)9014 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
9015 struct link_params *params,
9016 struct link_vars *vars)
9017 {
9018 return bnx2x_8706_8726_read_status(phy, params, vars);
9019 }
9020
9021 /******************************************************************/
9022 /* BCM8726 PHY SECTION */
9023 /******************************************************************/
bnx2x_8726_config_loopback(struct bnx2x_phy * phy,struct link_params * params)9024 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
9025 struct link_params *params)
9026 {
9027 struct bnx2x *bp = params->bp;
9028 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
9029 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
9030 }
9031
bnx2x_8726_external_rom_boot(struct bnx2x_phy * phy,struct link_params * params)9032 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
9033 struct link_params *params)
9034 {
9035 struct bnx2x *bp = params->bp;
9036 /* Need to wait 100ms after reset */
9037 msleep(100);
9038
9039 /* Micro controller re-boot */
9040 bnx2x_cl45_write(bp, phy,
9041 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
9042
9043 /* Set soft reset */
9044 bnx2x_cl45_write(bp, phy,
9045 MDIO_PMA_DEVAD,
9046 MDIO_PMA_REG_GEN_CTRL,
9047 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
9048
9049 bnx2x_cl45_write(bp, phy,
9050 MDIO_PMA_DEVAD,
9051 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
9052
9053 bnx2x_cl45_write(bp, phy,
9054 MDIO_PMA_DEVAD,
9055 MDIO_PMA_REG_GEN_CTRL,
9056 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
9057
9058 /* Wait for 150ms for microcode load */
9059 msleep(150);
9060
9061 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
9062 bnx2x_cl45_write(bp, phy,
9063 MDIO_PMA_DEVAD,
9064 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
9065
9066 msleep(200);
9067 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
9068 }
9069
bnx2x_8726_read_status(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)9070 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
9071 struct link_params *params,
9072 struct link_vars *vars)
9073 {
9074 struct bnx2x *bp = params->bp;
9075 u16 val1;
9076 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
9077 if (link_up) {
9078 bnx2x_cl45_read(bp, phy,
9079 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9080 &val1);
9081 if (val1 & (1<<15)) {
9082 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9083 link_up = 0;
9084 vars->line_speed = 0;
9085 }
9086 }
9087 return link_up;
9088 }
9089
9090
bnx2x_8726_config_init(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)9091 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
9092 struct link_params *params,
9093 struct link_vars *vars)
9094 {
9095 struct bnx2x *bp = params->bp;
9096 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
9097
9098 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9099 bnx2x_wait_reset_complete(bp, phy, params);
9100
9101 bnx2x_8726_external_rom_boot(phy, params);
9102
9103 /* Need to call module detected on initialization since the module
9104 * detection triggered by actual module insertion might occur before
9105 * driver is loaded, and when driver is loaded, it reset all
9106 * registers, including the transmitter
9107 */
9108 bnx2x_sfp_module_detection(phy, params);
9109
9110 if (phy->req_line_speed == SPEED_1000) {
9111 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9112 bnx2x_cl45_write(bp, phy,
9113 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9114 bnx2x_cl45_write(bp, phy,
9115 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9116 bnx2x_cl45_write(bp, phy,
9117 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9118 bnx2x_cl45_write(bp, phy,
9119 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9120 0x400);
9121 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9122 (phy->speed_cap_mask &
9123 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9124 ((phy->speed_cap_mask &
9125 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9126 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9127 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9128 /* Set Flow control */
9129 bnx2x_ext_phy_set_pause(params, phy, vars);
9130 bnx2x_cl45_write(bp, phy,
9131 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9132 bnx2x_cl45_write(bp, phy,
9133 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9134 bnx2x_cl45_write(bp, phy,
9135 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9136 bnx2x_cl45_write(bp, phy,
9137 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9138 bnx2x_cl45_write(bp, phy,
9139 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9140 /* Enable RX-ALARM control to receive interrupt for 1G speed
9141 * change
9142 */
9143 bnx2x_cl45_write(bp, phy,
9144 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9145 bnx2x_cl45_write(bp, phy,
9146 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9147 0x400);
9148
9149 } else { /* Default 10G. Set only LASI control */
9150 bnx2x_cl45_write(bp, phy,
9151 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9152 }
9153
9154 /* Set TX PreEmphasis if needed */
9155 if ((params->feature_config_flags &
9156 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9157 DP(NETIF_MSG_LINK,
9158 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9159 phy->tx_preemphasis[0],
9160 phy->tx_preemphasis[1]);
9161 bnx2x_cl45_write(bp, phy,
9162 MDIO_PMA_DEVAD,
9163 MDIO_PMA_REG_8726_TX_CTRL1,
9164 phy->tx_preemphasis[0]);
9165
9166 bnx2x_cl45_write(bp, phy,
9167 MDIO_PMA_DEVAD,
9168 MDIO_PMA_REG_8726_TX_CTRL2,
9169 phy->tx_preemphasis[1]);
9170 }
9171
9172 return 0;
9173
9174 }
9175
bnx2x_8726_link_reset(struct bnx2x_phy * phy,struct link_params * params)9176 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9177 struct link_params *params)
9178 {
9179 struct bnx2x *bp = params->bp;
9180 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9181 /* Set serial boot control for external load */
9182 bnx2x_cl45_write(bp, phy,
9183 MDIO_PMA_DEVAD,
9184 MDIO_PMA_REG_GEN_CTRL, 0x0001);
9185 }
9186
9187 /******************************************************************/
9188 /* BCM8727 PHY SECTION */
9189 /******************************************************************/
9190
bnx2x_8727_set_link_led(struct bnx2x_phy * phy,struct link_params * params,u8 mode)9191 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9192 struct link_params *params, u8 mode)
9193 {
9194 struct bnx2x *bp = params->bp;
9195 u16 led_mode_bitmask = 0;
9196 u16 gpio_pins_bitmask = 0;
9197 u16 val;
9198 /* Only NOC flavor requires to set the LED specifically */
9199 if (!(phy->flags & FLAGS_NOC))
9200 return;
9201 switch (mode) {
9202 case LED_MODE_FRONT_PANEL_OFF:
9203 case LED_MODE_OFF:
9204 led_mode_bitmask = 0;
9205 gpio_pins_bitmask = 0x03;
9206 break;
9207 case LED_MODE_ON:
9208 led_mode_bitmask = 0;
9209 gpio_pins_bitmask = 0x02;
9210 break;
9211 case LED_MODE_OPER:
9212 led_mode_bitmask = 0x60;
9213 gpio_pins_bitmask = 0x11;
9214 break;
9215 }
9216 bnx2x_cl45_read(bp, phy,
9217 MDIO_PMA_DEVAD,
9218 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9219 &val);
9220 val &= 0xff8f;
9221 val |= led_mode_bitmask;
9222 bnx2x_cl45_write(bp, phy,
9223 MDIO_PMA_DEVAD,
9224 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9225 val);
9226 bnx2x_cl45_read(bp, phy,
9227 MDIO_PMA_DEVAD,
9228 MDIO_PMA_REG_8727_GPIO_CTRL,
9229 &val);
9230 val &= 0xffe0;
9231 val |= gpio_pins_bitmask;
9232 bnx2x_cl45_write(bp, phy,
9233 MDIO_PMA_DEVAD,
9234 MDIO_PMA_REG_8727_GPIO_CTRL,
9235 val);
9236 }
bnx2x_8727_hw_reset(struct bnx2x_phy * phy,struct link_params * params)9237 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9238 struct link_params *params) {
9239 u32 swap_val, swap_override;
9240 u8 port;
9241 /* The PHY reset is controlled by GPIO 1. Fake the port number
9242 * to cancel the swap done in set_gpio()
9243 */
9244 struct bnx2x *bp = params->bp;
9245 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9246 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9247 port = (swap_val && swap_override) ^ 1;
9248 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9249 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9250 }
9251
bnx2x_8727_config_speed(struct bnx2x_phy * phy,struct link_params * params)9252 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9253 struct link_params *params)
9254 {
9255 struct bnx2x *bp = params->bp;
9256 u16 tmp1, val;
9257 /* Set option 1G speed */
9258 if ((phy->req_line_speed == SPEED_1000) ||
9259 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9260 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9261 bnx2x_cl45_write(bp, phy,
9262 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9263 bnx2x_cl45_write(bp, phy,
9264 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9265 bnx2x_cl45_read(bp, phy,
9266 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9267 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9268 /* Power down the XAUI until link is up in case of dual-media
9269 * and 1G
9270 */
9271 if (DUAL_MEDIA(params)) {
9272 bnx2x_cl45_read(bp, phy,
9273 MDIO_PMA_DEVAD,
9274 MDIO_PMA_REG_8727_PCS_GP, &val);
9275 val |= (3<<10);
9276 bnx2x_cl45_write(bp, phy,
9277 MDIO_PMA_DEVAD,
9278 MDIO_PMA_REG_8727_PCS_GP, val);
9279 }
9280 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9281 ((phy->speed_cap_mask &
9282 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9283 ((phy->speed_cap_mask &
9284 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9285 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9286
9287 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9288 bnx2x_cl45_write(bp, phy,
9289 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9290 bnx2x_cl45_write(bp, phy,
9291 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9292 } else {
9293 /* Since the 8727 has only single reset pin, need to set the 10G
9294 * registers although it is default
9295 */
9296 bnx2x_cl45_write(bp, phy,
9297 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9298 0x0020);
9299 bnx2x_cl45_write(bp, phy,
9300 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9301 bnx2x_cl45_write(bp, phy,
9302 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9303 bnx2x_cl45_write(bp, phy,
9304 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9305 0x0008);
9306 }
9307 }
9308
bnx2x_8727_config_init(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)9309 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9310 struct link_params *params,
9311 struct link_vars *vars)
9312 {
9313 u32 tx_en_mode;
9314 u16 tmp1, mod_abs, tmp2;
9315 struct bnx2x *bp = params->bp;
9316 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9317
9318 bnx2x_wait_reset_complete(bp, phy, params);
9319
9320 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9321
9322 bnx2x_8727_specific_func(phy, params, PHY_INIT);
9323 /* Initially configure MOD_ABS to interrupt when module is
9324 * presence( bit 8)
9325 */
9326 bnx2x_cl45_read(bp, phy,
9327 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9328 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9329 * When the EDC is off it locks onto a reference clock and avoids
9330 * becoming 'lost'
9331 */
9332 mod_abs &= ~(1<<8);
9333 if (!(phy->flags & FLAGS_NOC))
9334 mod_abs &= ~(1<<9);
9335 bnx2x_cl45_write(bp, phy,
9336 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9337
9338 /* Enable/Disable PHY transmitter output */
9339 bnx2x_set_disable_pmd_transmit(params, phy, 0);
9340
9341 bnx2x_8727_power_module(bp, phy, 1);
9342
9343 bnx2x_cl45_read(bp, phy,
9344 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9345
9346 bnx2x_cl45_read(bp, phy,
9347 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9348
9349 bnx2x_8727_config_speed(phy, params);
9350
9351
9352 /* Set TX PreEmphasis if needed */
9353 if ((params->feature_config_flags &
9354 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9355 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9356 phy->tx_preemphasis[0],
9357 phy->tx_preemphasis[1]);
9358 bnx2x_cl45_write(bp, phy,
9359 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9360 phy->tx_preemphasis[0]);
9361
9362 bnx2x_cl45_write(bp, phy,
9363 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9364 phy->tx_preemphasis[1]);
9365 }
9366
9367 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9368 * power mode, if TX Laser is disabled
9369 */
9370 tx_en_mode = REG_RD(bp, params->shmem_base +
9371 offsetof(struct shmem_region,
9372 dev_info.port_hw_config[params->port].sfp_ctrl))
9373 & PORT_HW_CFG_TX_LASER_MASK;
9374
9375 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9376
9377 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9378 bnx2x_cl45_read(bp, phy,
9379 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9380 tmp2 |= 0x1000;
9381 tmp2 &= 0xFFEF;
9382 bnx2x_cl45_write(bp, phy,
9383 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9384 bnx2x_cl45_read(bp, phy,
9385 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9386 &tmp2);
9387 bnx2x_cl45_write(bp, phy,
9388 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9389 (tmp2 & 0x7fff));
9390 }
9391
9392 return 0;
9393 }
9394
bnx2x_8727_handle_mod_abs(struct bnx2x_phy * phy,struct link_params * params)9395 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9396 struct link_params *params)
9397 {
9398 struct bnx2x *bp = params->bp;
9399 u16 mod_abs, rx_alarm_status;
9400 u32 val = REG_RD(bp, params->shmem_base +
9401 offsetof(struct shmem_region, dev_info.
9402 port_feature_config[params->port].
9403 config));
9404 bnx2x_cl45_read(bp, phy,
9405 MDIO_PMA_DEVAD,
9406 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9407 if (mod_abs & (1<<8)) {
9408
9409 /* Module is absent */
9410 DP(NETIF_MSG_LINK,
9411 "MOD_ABS indication show module is absent\n");
9412 phy->media_type = ETH_PHY_NOT_PRESENT;
9413 /* 1. Set mod_abs to detect next module
9414 * presence event
9415 * 2. Set EDC off by setting OPTXLOS signal input to low
9416 * (bit 9).
9417 * When the EDC is off it locks onto a reference clock and
9418 * avoids becoming 'lost'.
9419 */
9420 mod_abs &= ~(1<<8);
9421 if (!(phy->flags & FLAGS_NOC))
9422 mod_abs &= ~(1<<9);
9423 bnx2x_cl45_write(bp, phy,
9424 MDIO_PMA_DEVAD,
9425 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9426
9427 /* Clear RX alarm since it stays up as long as
9428 * the mod_abs wasn't changed
9429 */
9430 bnx2x_cl45_read(bp, phy,
9431 MDIO_PMA_DEVAD,
9432 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9433
9434 } else {
9435 /* Module is present */
9436 DP(NETIF_MSG_LINK,
9437 "MOD_ABS indication show module is present\n");
9438 /* First disable transmitter, and if the module is ok, the
9439 * module_detection will enable it
9440 * 1. Set mod_abs to detect next module absent event ( bit 8)
9441 * 2. Restore the default polarity of the OPRXLOS signal and
9442 * this signal will then correctly indicate the presence or
9443 * absence of the Rx signal. (bit 9)
9444 */
9445 mod_abs |= (1<<8);
9446 if (!(phy->flags & FLAGS_NOC))
9447 mod_abs |= (1<<9);
9448 bnx2x_cl45_write(bp, phy,
9449 MDIO_PMA_DEVAD,
9450 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9451
9452 /* Clear RX alarm since it stays up as long as the mod_abs
9453 * wasn't changed. This is need to be done before calling the
9454 * module detection, otherwise it will clear* the link update
9455 * alarm
9456 */
9457 bnx2x_cl45_read(bp, phy,
9458 MDIO_PMA_DEVAD,
9459 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9460
9461
9462 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9463 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9464 bnx2x_sfp_set_transmitter(params, phy, 0);
9465
9466 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9467 bnx2x_sfp_module_detection(phy, params);
9468 else
9469 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9470
9471 /* Reconfigure link speed based on module type limitations */
9472 bnx2x_8727_config_speed(phy, params);
9473 }
9474
9475 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9476 rx_alarm_status);
9477 /* No need to check link status in case of module plugged in/out */
9478 }
9479
bnx2x_8727_read_status(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)9480 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9481 struct link_params *params,
9482 struct link_vars *vars)
9483
9484 {
9485 struct bnx2x *bp = params->bp;
9486 u8 link_up = 0, oc_port = params->port;
9487 u16 link_status = 0;
9488 u16 rx_alarm_status, lasi_ctrl, val1;
9489
9490 /* If PHY is not initialized, do not check link status */
9491 bnx2x_cl45_read(bp, phy,
9492 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9493 &lasi_ctrl);
9494 if (!lasi_ctrl)
9495 return 0;
9496
9497 /* Check the LASI on Rx */
9498 bnx2x_cl45_read(bp, phy,
9499 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9500 &rx_alarm_status);
9501 vars->line_speed = 0;
9502 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
9503
9504 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9505 MDIO_PMA_LASI_TXCTRL);
9506
9507 bnx2x_cl45_read(bp, phy,
9508 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9509
9510 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9511
9512 /* Clear MSG-OUT */
9513 bnx2x_cl45_read(bp, phy,
9514 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9515
9516 /* If a module is present and there is need to check
9517 * for over current
9518 */
9519 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9520 /* Check over-current using 8727 GPIO0 input*/
9521 bnx2x_cl45_read(bp, phy,
9522 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9523 &val1);
9524
9525 if ((val1 & (1<<8)) == 0) {
9526 if (!CHIP_IS_E1x(bp))
9527 oc_port = BP_PATH(bp) + (params->port << 1);
9528 DP(NETIF_MSG_LINK,
9529 "8727 Power fault has been detected on port %d\n",
9530 oc_port);
9531 netdev_err(bp->dev, "Error: Power fault on Port %d has "
9532 "been detected and the power to "
9533 "that SFP+ module has been removed "
9534 "to prevent failure of the card. "
9535 "Please remove the SFP+ module and "
9536 "restart the system to clear this "
9537 "error.\n",
9538 oc_port);
9539 /* Disable all RX_ALARMs except for mod_abs */
9540 bnx2x_cl45_write(bp, phy,
9541 MDIO_PMA_DEVAD,
9542 MDIO_PMA_LASI_RXCTRL, (1<<5));
9543
9544 bnx2x_cl45_read(bp, phy,
9545 MDIO_PMA_DEVAD,
9546 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9547 /* Wait for module_absent_event */
9548 val1 |= (1<<8);
9549 bnx2x_cl45_write(bp, phy,
9550 MDIO_PMA_DEVAD,
9551 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9552 /* Clear RX alarm */
9553 bnx2x_cl45_read(bp, phy,
9554 MDIO_PMA_DEVAD,
9555 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9556 bnx2x_8727_power_module(params->bp, phy, 0);
9557 return 0;
9558 }
9559 } /* Over current check */
9560
9561 /* When module absent bit is set, check module */
9562 if (rx_alarm_status & (1<<5)) {
9563 bnx2x_8727_handle_mod_abs(phy, params);
9564 /* Enable all mod_abs and link detection bits */
9565 bnx2x_cl45_write(bp, phy,
9566 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9567 ((1<<5) | (1<<2)));
9568 }
9569
9570 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9571 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9572 bnx2x_sfp_set_transmitter(params, phy, 1);
9573 } else {
9574 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9575 return 0;
9576 }
9577
9578 bnx2x_cl45_read(bp, phy,
9579 MDIO_PMA_DEVAD,
9580 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9581
9582 /* Bits 0..2 --> speed detected,
9583 * Bits 13..15--> link is down
9584 */
9585 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9586 link_up = 1;
9587 vars->line_speed = SPEED_10000;
9588 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9589 params->port);
9590 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9591 link_up = 1;
9592 vars->line_speed = SPEED_1000;
9593 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9594 params->port);
9595 } else {
9596 link_up = 0;
9597 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9598 params->port);
9599 }
9600
9601 /* Capture 10G link fault. */
9602 if (vars->line_speed == SPEED_10000) {
9603 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9604 MDIO_PMA_LASI_TXSTAT, &val1);
9605
9606 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9607 MDIO_PMA_LASI_TXSTAT, &val1);
9608
9609 if (val1 & (1<<0)) {
9610 vars->fault_detected = 1;
9611 }
9612 }
9613
9614 if (link_up) {
9615 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9616 vars->duplex = DUPLEX_FULL;
9617 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9618 }
9619
9620 if ((DUAL_MEDIA(params)) &&
9621 (phy->req_line_speed == SPEED_1000)) {
9622 bnx2x_cl45_read(bp, phy,
9623 MDIO_PMA_DEVAD,
9624 MDIO_PMA_REG_8727_PCS_GP, &val1);
9625 /* In case of dual-media board and 1G, power up the XAUI side,
9626 * otherwise power it down. For 10G it is done automatically
9627 */
9628 if (link_up)
9629 val1 &= ~(3<<10);
9630 else
9631 val1 |= (3<<10);
9632 bnx2x_cl45_write(bp, phy,
9633 MDIO_PMA_DEVAD,
9634 MDIO_PMA_REG_8727_PCS_GP, val1);
9635 }
9636 return link_up;
9637 }
9638
bnx2x_8727_link_reset(struct bnx2x_phy * phy,struct link_params * params)9639 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9640 struct link_params *params)
9641 {
9642 struct bnx2x *bp = params->bp;
9643
9644 /* Enable/Disable PHY transmitter output */
9645 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9646
9647 /* Disable Transmitter */
9648 bnx2x_sfp_set_transmitter(params, phy, 0);
9649 /* Clear LASI */
9650 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9651
9652 }
9653
9654 /******************************************************************/
9655 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9656 /******************************************************************/
bnx2x_is_8483x_8485x(struct bnx2x_phy * phy)9657 static int bnx2x_is_8483x_8485x(struct bnx2x_phy *phy)
9658 {
9659 return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9660 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) ||
9661 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858));
9662 }
9663
bnx2x_save_848xx_spirom_version(struct bnx2x_phy * phy,struct bnx2x * bp,u8 port)9664 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9665 struct bnx2x *bp,
9666 u8 port)
9667 {
9668 u16 val, fw_ver2, cnt, i;
9669 static struct bnx2x_reg_set reg_set[] = {
9670 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9671 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9672 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9673 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9674 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9675 };
9676 u16 fw_ver1;
9677
9678 if (bnx2x_is_8483x_8485x(phy)) {
9679 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9680 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9681 phy->ver_addr);
9682 } else {
9683 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9684 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9685 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9686 bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9687 reg_set[i].reg, reg_set[i].val);
9688
9689 for (cnt = 0; cnt < 100; cnt++) {
9690 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9691 if (val & 1)
9692 break;
9693 udelay(5);
9694 }
9695 if (cnt == 100) {
9696 DP(NETIF_MSG_LINK, "Unable to read 848xx "
9697 "phy fw version(1)\n");
9698 bnx2x_save_spirom_version(bp, port, 0,
9699 phy->ver_addr);
9700 return;
9701 }
9702
9703
9704 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9705 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9706 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9707 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9708 for (cnt = 0; cnt < 100; cnt++) {
9709 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9710 if (val & 1)
9711 break;
9712 udelay(5);
9713 }
9714 if (cnt == 100) {
9715 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9716 "version(2)\n");
9717 bnx2x_save_spirom_version(bp, port, 0,
9718 phy->ver_addr);
9719 return;
9720 }
9721
9722 /* lower 16 bits of the register SPI_FW_STATUS */
9723 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9724 /* upper 16 bits of register SPI_FW_STATUS */
9725 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9726
9727 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9728 phy->ver_addr);
9729 }
9730
9731 }
bnx2x_848xx_set_led(struct bnx2x * bp,struct bnx2x_phy * phy)9732 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9733 struct bnx2x_phy *phy)
9734 {
9735 u16 val, offset, i;
9736 static struct bnx2x_reg_set reg_set[] = {
9737 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9738 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9739 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9740 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9741 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9742 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9743 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9744 };
9745 /* PHYC_CTL_LED_CTL */
9746 bnx2x_cl45_read(bp, phy,
9747 MDIO_PMA_DEVAD,
9748 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9749 val &= 0xFE00;
9750 val |= 0x0092;
9751
9752 bnx2x_cl45_write(bp, phy,
9753 MDIO_PMA_DEVAD,
9754 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9755
9756 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9757 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9758 reg_set[i].val);
9759
9760 if (bnx2x_is_8483x_8485x(phy))
9761 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9762 else
9763 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9764
9765 /* stretch_en for LED3*/
9766 bnx2x_cl45_read_or_write(bp, phy,
9767 MDIO_PMA_DEVAD, offset,
9768 MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9769 }
9770
bnx2x_848xx_specific_func(struct bnx2x_phy * phy,struct link_params * params,u32 action)9771 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9772 struct link_params *params,
9773 u32 action)
9774 {
9775 struct bnx2x *bp = params->bp;
9776 switch (action) {
9777 case PHY_INIT:
9778 if (!bnx2x_is_8483x_8485x(phy)) {
9779 /* Save spirom version */
9780 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9781 }
9782 /* This phy uses the NIG latch mechanism since link indication
9783 * arrives through its LED4 and not via its LASI signal, so we
9784 * get steady signal instead of clear on read
9785 */
9786 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9787 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9788
9789 bnx2x_848xx_set_led(bp, phy);
9790 break;
9791 }
9792 }
9793
bnx2x_848xx_cmn_config_init(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)9794 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9795 struct link_params *params,
9796 struct link_vars *vars)
9797 {
9798 struct bnx2x *bp = params->bp;
9799 u16 autoneg_val, an_1000_val, an_10_100_val;
9800
9801 bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9802 bnx2x_cl45_write(bp, phy,
9803 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9804
9805 /* set 1000 speed advertisement */
9806 bnx2x_cl45_read(bp, phy,
9807 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9808 &an_1000_val);
9809
9810 bnx2x_ext_phy_set_pause(params, phy, vars);
9811 bnx2x_cl45_read(bp, phy,
9812 MDIO_AN_DEVAD,
9813 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9814 &an_10_100_val);
9815 bnx2x_cl45_read(bp, phy,
9816 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9817 &autoneg_val);
9818 /* Disable forced speed */
9819 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9820 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9821
9822 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9823 (phy->speed_cap_mask &
9824 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9825 (phy->req_line_speed == SPEED_1000)) {
9826 an_1000_val |= (1<<8);
9827 autoneg_val |= (1<<9 | 1<<12);
9828 if (phy->req_duplex == DUPLEX_FULL)
9829 an_1000_val |= (1<<9);
9830 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9831 } else
9832 an_1000_val &= ~((1<<8) | (1<<9));
9833
9834 bnx2x_cl45_write(bp, phy,
9835 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9836 an_1000_val);
9837
9838 /* Set 10/100 speed advertisement */
9839 if (phy->req_line_speed == SPEED_AUTO_NEG) {
9840 if (phy->speed_cap_mask &
9841 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9842 /* Enable autoneg and restart autoneg for legacy speeds
9843 */
9844 autoneg_val |= (1<<9 | 1<<12);
9845 an_10_100_val |= (1<<8);
9846 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
9847 }
9848
9849 if (phy->speed_cap_mask &
9850 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9851 /* Enable autoneg and restart autoneg for legacy speeds
9852 */
9853 autoneg_val |= (1<<9 | 1<<12);
9854 an_10_100_val |= (1<<7);
9855 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
9856 }
9857
9858 if ((phy->speed_cap_mask &
9859 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9860 (phy->supported & SUPPORTED_10baseT_Full)) {
9861 an_10_100_val |= (1<<6);
9862 autoneg_val |= (1<<9 | 1<<12);
9863 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
9864 }
9865
9866 if ((phy->speed_cap_mask &
9867 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9868 (phy->supported & SUPPORTED_10baseT_Half)) {
9869 an_10_100_val |= (1<<5);
9870 autoneg_val |= (1<<9 | 1<<12);
9871 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
9872 }
9873 }
9874
9875 /* Only 10/100 are allowed to work in FORCE mode */
9876 if ((phy->req_line_speed == SPEED_100) &&
9877 (phy->supported &
9878 (SUPPORTED_100baseT_Half |
9879 SUPPORTED_100baseT_Full))) {
9880 autoneg_val |= (1<<13);
9881 /* Enabled AUTO-MDIX when autoneg is disabled */
9882 bnx2x_cl45_write(bp, phy,
9883 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9884 (1<<15 | 1<<9 | 7<<0));
9885 /* The PHY needs this set even for forced link. */
9886 an_10_100_val |= (1<<8) | (1<<7);
9887 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9888 }
9889 if ((phy->req_line_speed == SPEED_10) &&
9890 (phy->supported &
9891 (SUPPORTED_10baseT_Half |
9892 SUPPORTED_10baseT_Full))) {
9893 /* Enabled AUTO-MDIX when autoneg is disabled */
9894 bnx2x_cl45_write(bp, phy,
9895 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9896 (1<<15 | 1<<9 | 7<<0));
9897 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9898 }
9899
9900 bnx2x_cl45_write(bp, phy,
9901 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9902 an_10_100_val);
9903
9904 if (phy->req_duplex == DUPLEX_FULL)
9905 autoneg_val |= (1<<8);
9906
9907 /* Always write this if this is not 84833/4.
9908 * For 84833/4, write it only when it's a forced speed.
9909 */
9910 if (!bnx2x_is_8483x_8485x(phy) ||
9911 ((autoneg_val & (1<<12)) == 0))
9912 bnx2x_cl45_write(bp, phy,
9913 MDIO_AN_DEVAD,
9914 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9915
9916 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9917 (phy->speed_cap_mask &
9918 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9919 (phy->req_line_speed == SPEED_10000)) {
9920 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9921 /* Restart autoneg for 10G*/
9922
9923 bnx2x_cl45_read_or_write(
9924 bp, phy,
9925 MDIO_AN_DEVAD,
9926 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9927 0x1000);
9928 bnx2x_cl45_write(bp, phy,
9929 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9930 0x3200);
9931 } else
9932 bnx2x_cl45_write(bp, phy,
9933 MDIO_AN_DEVAD,
9934 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9935 1);
9936
9937 return 0;
9938 }
9939
bnx2x_8481_config_init(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)9940 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9941 struct link_params *params,
9942 struct link_vars *vars)
9943 {
9944 struct bnx2x *bp = params->bp;
9945 /* Restore normal power mode*/
9946 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9947 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9948
9949 /* HW reset */
9950 bnx2x_ext_phy_hw_reset(bp, params->port);
9951 bnx2x_wait_reset_complete(bp, phy, params);
9952
9953 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9954 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9955 }
9956
9957 #define PHY848xx_CMDHDLR_WAIT 300
9958 #define PHY848xx_CMDHDLR_MAX_ARGS 5
9959
bnx2x_84858_cmd_hdlr(struct bnx2x_phy * phy,struct link_params * params,u16 fw_cmd,u16 cmd_args[],int argc)9960 static int bnx2x_84858_cmd_hdlr(struct bnx2x_phy *phy,
9961 struct link_params *params,
9962 u16 fw_cmd,
9963 u16 cmd_args[], int argc)
9964 {
9965 int idx;
9966 u16 val;
9967 struct bnx2x *bp = params->bp;
9968
9969 /* Step 1: Poll the STATUS register to see whether the previous command
9970 * is in progress or the system is busy (CMD_IN_PROGRESS or
9971 * SYSTEM_BUSY). If previous command is in progress or system is busy,
9972 * check again until the previous command finishes execution and the
9973 * system is available for taking command
9974 */
9975
9976 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
9977 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9978 MDIO_848xx_CMD_HDLR_STATUS, &val);
9979 if ((val != PHY84858_STATUS_CMD_IN_PROGRESS) &&
9980 (val != PHY84858_STATUS_CMD_SYSTEM_BUSY))
9981 break;
9982 usleep_range(1000, 2000);
9983 }
9984 if (idx >= PHY848xx_CMDHDLR_WAIT) {
9985 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9986 return -EINVAL;
9987 }
9988
9989 /* Step2: If any parameters are required for the function, write them
9990 * to the required DATA registers
9991 */
9992
9993 for (idx = 0; idx < argc; idx++) {
9994 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9995 MDIO_848xx_CMD_HDLR_DATA1 + idx,
9996 cmd_args[idx]);
9997 }
9998
9999 /* Step3: When the firmware is ready for commands, write the 'Command
10000 * code' to the CMD register
10001 */
10002 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10003 MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
10004
10005 /* Step4: Once the command has been written, poll the STATUS register
10006 * to check whether the command has completed (CMD_COMPLETED_PASS/
10007 * CMD_FOR_CMDS or CMD_COMPLETED_ERROR).
10008 */
10009
10010 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10011 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10012 MDIO_848xx_CMD_HDLR_STATUS, &val);
10013 if ((val == PHY84858_STATUS_CMD_COMPLETE_PASS) ||
10014 (val == PHY84858_STATUS_CMD_COMPLETE_ERROR))
10015 break;
10016 usleep_range(1000, 2000);
10017 }
10018 if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
10019 (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) {
10020 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
10021 return -EINVAL;
10022 }
10023 /* Step5: Once the command has completed, read the specficied DATA
10024 * registers for any saved results for the command, if applicable
10025 */
10026
10027 /* Gather returning data */
10028 for (idx = 0; idx < argc; idx++) {
10029 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10030 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10031 &cmd_args[idx]);
10032 }
10033
10034 return 0;
10035 }
10036
bnx2x_84833_cmd_hdlr(struct bnx2x_phy * phy,struct link_params * params,u16 fw_cmd,u16 cmd_args[],int argc)10037 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
10038 struct link_params *params, u16 fw_cmd,
10039 u16 cmd_args[], int argc)
10040 {
10041 int idx;
10042 u16 val;
10043 struct bnx2x *bp = params->bp;
10044 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
10045 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10046 MDIO_848xx_CMD_HDLR_STATUS,
10047 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
10048 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10049 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10050 MDIO_848xx_CMD_HDLR_STATUS, &val);
10051 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
10052 break;
10053 usleep_range(1000, 2000);
10054 }
10055 if (idx >= PHY848xx_CMDHDLR_WAIT) {
10056 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
10057 return -EINVAL;
10058 }
10059
10060 /* Prepare argument(s) and issue command */
10061 for (idx = 0; idx < argc; idx++) {
10062 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10063 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10064 cmd_args[idx]);
10065 }
10066 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10067 MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
10068 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10069 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10070 MDIO_848xx_CMD_HDLR_STATUS, &val);
10071 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
10072 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
10073 break;
10074 usleep_range(1000, 2000);
10075 }
10076 if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
10077 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
10078 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
10079 return -EINVAL;
10080 }
10081 /* Gather returning data */
10082 for (idx = 0; idx < argc; idx++) {
10083 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10084 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10085 &cmd_args[idx]);
10086 }
10087 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10088 MDIO_848xx_CMD_HDLR_STATUS,
10089 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
10090 return 0;
10091 }
10092
bnx2x_848xx_cmd_hdlr(struct bnx2x_phy * phy,struct link_params * params,u16 fw_cmd,u16 cmd_args[],int argc)10093 static int bnx2x_848xx_cmd_hdlr(struct bnx2x_phy *phy,
10094 struct link_params *params,
10095 u16 fw_cmd,
10096 u16 cmd_args[], int argc)
10097 {
10098 struct bnx2x *bp = params->bp;
10099
10100 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) ||
10101 (REG_RD(bp, params->shmem2_base +
10102 offsetof(struct shmem2_region,
10103 link_attr_sync[params->port])) &
10104 LINK_ATTR_84858)) {
10105 return bnx2x_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,
10106 argc);
10107 } else {
10108 return bnx2x_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,
10109 argc);
10110 }
10111 }
10112
bnx2x_848xx_pair_swap_cfg(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)10113 static int bnx2x_848xx_pair_swap_cfg(struct bnx2x_phy *phy,
10114 struct link_params *params,
10115 struct link_vars *vars)
10116 {
10117 u32 pair_swap;
10118 u16 data[PHY848xx_CMDHDLR_MAX_ARGS];
10119 int status;
10120 struct bnx2x *bp = params->bp;
10121
10122 /* Check for configuration. */
10123 pair_swap = REG_RD(bp, params->shmem_base +
10124 offsetof(struct shmem_region,
10125 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
10126 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
10127
10128 if (pair_swap == 0)
10129 return 0;
10130
10131 /* Only the second argument is used for this command */
10132 data[1] = (u16)pair_swap;
10133
10134 status = bnx2x_848xx_cmd_hdlr(phy, params,
10135 PHY848xx_CMD_SET_PAIR_SWAP, data,
10136 PHY848xx_CMDHDLR_MAX_ARGS);
10137 if (status == 0)
10138 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
10139
10140 return status;
10141 }
10142
bnx2x_84833_get_reset_gpios(struct bnx2x * bp,u32 shmem_base_path[],u32 chip_id)10143 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
10144 u32 shmem_base_path[],
10145 u32 chip_id)
10146 {
10147 u32 reset_pin[2];
10148 u32 idx;
10149 u8 reset_gpios;
10150 if (CHIP_IS_E3(bp)) {
10151 /* Assume that these will be GPIOs, not EPIOs. */
10152 for (idx = 0; idx < 2; idx++) {
10153 /* Map config param to register bit. */
10154 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10155 offsetof(struct shmem_region,
10156 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
10157 reset_pin[idx] = (reset_pin[idx] &
10158 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10159 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10160 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
10161 reset_pin[idx] = (1 << reset_pin[idx]);
10162 }
10163 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10164 } else {
10165 /* E2, look from diff place of shmem. */
10166 for (idx = 0; idx < 2; idx++) {
10167 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10168 offsetof(struct shmem_region,
10169 dev_info.port_hw_config[0].default_cfg));
10170 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
10171 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
10172 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
10173 reset_pin[idx] = (1 << reset_pin[idx]);
10174 }
10175 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10176 }
10177
10178 return reset_gpios;
10179 }
10180
bnx2x_84833_hw_reset_phy(struct bnx2x_phy * phy,struct link_params * params)10181 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
10182 struct link_params *params)
10183 {
10184 struct bnx2x *bp = params->bp;
10185 u8 reset_gpios;
10186 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
10187 offsetof(struct shmem2_region,
10188 other_shmem_base_addr));
10189
10190 u32 shmem_base_path[2];
10191
10192 /* Work around for 84833 LED failure inside RESET status */
10193 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10194 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10195 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10196 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10197 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10198 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10199
10200 shmem_base_path[0] = params->shmem_base;
10201 shmem_base_path[1] = other_shmem_base_addr;
10202
10203 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
10204 params->chip_id);
10205
10206 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10207 udelay(10);
10208 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
10209 reset_gpios);
10210
10211 return 0;
10212 }
10213
bnx2x_8483x_disable_eee(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)10214 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
10215 struct link_params *params,
10216 struct link_vars *vars)
10217 {
10218 int rc;
10219 struct bnx2x *bp = params->bp;
10220 u16 cmd_args = 0;
10221
10222 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10223
10224 /* Prevent Phy from working in EEE and advertising it */
10225 rc = bnx2x_848xx_cmd_hdlr(phy, params,
10226 PHY848xx_CMD_SET_EEE_MODE, &cmd_args, 1);
10227 if (rc) {
10228 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10229 return rc;
10230 }
10231
10232 return bnx2x_eee_disable(phy, params, vars);
10233 }
10234
bnx2x_8483x_enable_eee(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)10235 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10236 struct link_params *params,
10237 struct link_vars *vars)
10238 {
10239 int rc;
10240 struct bnx2x *bp = params->bp;
10241 u16 cmd_args = 1;
10242
10243 rc = bnx2x_848xx_cmd_hdlr(phy, params,
10244 PHY848xx_CMD_SET_EEE_MODE, &cmd_args, 1);
10245 if (rc) {
10246 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10247 return rc;
10248 }
10249
10250 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10251 }
10252
10253 #define PHY84833_CONSTANT_LATENCY 1193
bnx2x_848x3_config_init(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)10254 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10255 struct link_params *params,
10256 struct link_vars *vars)
10257 {
10258 struct bnx2x *bp = params->bp;
10259 u8 port, initialize = 1;
10260 u16 val;
10261 u32 actual_phy_selection;
10262 u16 cmd_args[PHY848xx_CMDHDLR_MAX_ARGS];
10263 int rc = 0;
10264
10265 usleep_range(1000, 2000);
10266
10267 if (!(CHIP_IS_E1x(bp)))
10268 port = BP_PATH(bp);
10269 else
10270 port = params->port;
10271
10272 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10273 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10274 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10275 port);
10276 } else {
10277 /* MDIO reset */
10278 bnx2x_cl45_write(bp, phy,
10279 MDIO_PMA_DEVAD,
10280 MDIO_PMA_REG_CTRL, 0x8000);
10281 }
10282
10283 bnx2x_wait_reset_complete(bp, phy, params);
10284
10285 /* Wait for GPHY to come out of reset */
10286 msleep(50);
10287 if (!bnx2x_is_8483x_8485x(phy)) {
10288 /* BCM84823 requires that XGXS links up first @ 10G for normal
10289 * behavior.
10290 */
10291 u16 temp;
10292 temp = vars->line_speed;
10293 vars->line_speed = SPEED_10000;
10294 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0);
10295 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars);
10296 vars->line_speed = temp;
10297 }
10298 /* Check if this is actually BCM84858 */
10299 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10300 u16 hw_rev;
10301
10302 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10303 MDIO_AN_REG_848xx_ID_MSB, &hw_rev);
10304 if (hw_rev == BCM84858_PHY_ID) {
10305 params->link_attr_sync |= LINK_ATTR_84858;
10306 bnx2x_update_link_attr(params, params->link_attr_sync);
10307 }
10308 }
10309
10310 /* Set dual-media configuration according to configuration */
10311 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10312 MDIO_CTL_REG_84823_MEDIA, &val);
10313 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10314 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10315 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10316 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10317 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10318
10319 if (CHIP_IS_E3(bp)) {
10320 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10321 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10322 } else {
10323 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10324 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10325 }
10326
10327 actual_phy_selection = bnx2x_phy_selection(params);
10328
10329 switch (actual_phy_selection) {
10330 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10331 /* Do nothing. Essentially this is like the priority copper */
10332 break;
10333 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10334 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10335 break;
10336 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10337 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10338 break;
10339 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10340 /* Do nothing here. The first PHY won't be initialized at all */
10341 break;
10342 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10343 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10344 initialize = 0;
10345 break;
10346 }
10347 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10348 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10349
10350 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10351 MDIO_CTL_REG_84823_MEDIA, val);
10352 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10353 params->multi_phy_config, val);
10354
10355 if (bnx2x_is_8483x_8485x(phy)) {
10356 bnx2x_848xx_pair_swap_cfg(phy, params, vars);
10357
10358 /* Keep AutogrEEEn disabled. */
10359 cmd_args[0] = 0x0;
10360 cmd_args[1] = 0x0;
10361 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10362 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10363 rc = bnx2x_848xx_cmd_hdlr(phy, params,
10364 PHY848xx_CMD_SET_EEE_MODE, cmd_args,
10365 PHY848xx_CMDHDLR_MAX_ARGS);
10366 if (rc)
10367 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10368 }
10369 if (initialize)
10370 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10371 else
10372 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10373 /* 84833 PHY has a better feature and doesn't need to support this. */
10374 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10375 u32 cms_enable = REG_RD(bp, params->shmem_base +
10376 offsetof(struct shmem_region,
10377 dev_info.port_hw_config[params->port].default_cfg)) &
10378 PORT_HW_CFG_ENABLE_CMS_MASK;
10379
10380 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10381 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10382 if (cms_enable)
10383 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10384 else
10385 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10386 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10387 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10388 }
10389
10390 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10391 MDIO_84833_TOP_CFG_FW_REV, &val);
10392
10393 /* Configure EEE support */
10394 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10395 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10396 bnx2x_eee_has_cap(params)) {
10397 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10398 if (rc) {
10399 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10400 bnx2x_8483x_disable_eee(phy, params, vars);
10401 return rc;
10402 }
10403
10404 if ((phy->req_duplex == DUPLEX_FULL) &&
10405 (params->eee_mode & EEE_MODE_ADV_LPI) &&
10406 (bnx2x_eee_calc_timer(params) ||
10407 !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10408 rc = bnx2x_8483x_enable_eee(phy, params, vars);
10409 else
10410 rc = bnx2x_8483x_disable_eee(phy, params, vars);
10411 if (rc) {
10412 DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10413 return rc;
10414 }
10415 } else {
10416 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10417 }
10418
10419 if (bnx2x_is_8483x_8485x(phy)) {
10420 /* Bring PHY out of super isolate mode as the final step. */
10421 bnx2x_cl45_read_and_write(bp, phy,
10422 MDIO_CTL_DEVAD,
10423 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10424 (u16)~MDIO_84833_SUPER_ISOLATE);
10425 }
10426 return rc;
10427 }
10428
bnx2x_848xx_read_status(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)10429 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10430 struct link_params *params,
10431 struct link_vars *vars)
10432 {
10433 struct bnx2x *bp = params->bp;
10434 u16 val, val1, val2;
10435 u8 link_up = 0;
10436
10437
10438 /* Check 10G-BaseT link status */
10439 /* Check PMD signal ok */
10440 bnx2x_cl45_read(bp, phy,
10441 MDIO_AN_DEVAD, 0xFFFA, &val1);
10442 bnx2x_cl45_read(bp, phy,
10443 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10444 &val2);
10445 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10446
10447 /* Check link 10G */
10448 if (val2 & (1<<11)) {
10449 vars->line_speed = SPEED_10000;
10450 vars->duplex = DUPLEX_FULL;
10451 link_up = 1;
10452 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10453 } else { /* Check Legacy speed link */
10454 u16 legacy_status, legacy_speed;
10455
10456 /* Enable expansion register 0x42 (Operation mode status) */
10457 bnx2x_cl45_write(bp, phy,
10458 MDIO_AN_DEVAD,
10459 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10460
10461 /* Get legacy speed operation status */
10462 bnx2x_cl45_read(bp, phy,
10463 MDIO_AN_DEVAD,
10464 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10465 &legacy_status);
10466
10467 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10468 legacy_status);
10469 link_up = ((legacy_status & (1<<11)) == (1<<11));
10470 legacy_speed = (legacy_status & (3<<9));
10471 if (legacy_speed == (0<<9))
10472 vars->line_speed = SPEED_10;
10473 else if (legacy_speed == (1<<9))
10474 vars->line_speed = SPEED_100;
10475 else if (legacy_speed == (2<<9))
10476 vars->line_speed = SPEED_1000;
10477 else { /* Should not happen: Treat as link down */
10478 vars->line_speed = 0;
10479 link_up = 0;
10480 }
10481
10482 if (link_up) {
10483 if (legacy_status & (1<<8))
10484 vars->duplex = DUPLEX_FULL;
10485 else
10486 vars->duplex = DUPLEX_HALF;
10487
10488 DP(NETIF_MSG_LINK,
10489 "Link is up in %dMbps, is_duplex_full= %d\n",
10490 vars->line_speed,
10491 (vars->duplex == DUPLEX_FULL));
10492 /* Check legacy speed AN resolution */
10493 bnx2x_cl45_read(bp, phy,
10494 MDIO_AN_DEVAD,
10495 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10496 &val);
10497 if (val & (1<<5))
10498 vars->link_status |=
10499 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10500 bnx2x_cl45_read(bp, phy,
10501 MDIO_AN_DEVAD,
10502 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10503 &val);
10504 if ((val & (1<<0)) == 0)
10505 vars->link_status |=
10506 LINK_STATUS_PARALLEL_DETECTION_USED;
10507 }
10508 }
10509 if (link_up) {
10510 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10511 vars->line_speed);
10512 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10513
10514 /* Read LP advertised speeds */
10515 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10516 MDIO_AN_REG_CL37_FC_LP, &val);
10517 if (val & (1<<5))
10518 vars->link_status |=
10519 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10520 if (val & (1<<6))
10521 vars->link_status |=
10522 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10523 if (val & (1<<7))
10524 vars->link_status |=
10525 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10526 if (val & (1<<8))
10527 vars->link_status |=
10528 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10529 if (val & (1<<9))
10530 vars->link_status |=
10531 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10532
10533 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10534 MDIO_AN_REG_1000T_STATUS, &val);
10535
10536 if (val & (1<<10))
10537 vars->link_status |=
10538 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10539 if (val & (1<<11))
10540 vars->link_status |=
10541 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10542
10543 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10544 MDIO_AN_REG_MASTER_STATUS, &val);
10545
10546 if (val & (1<<11))
10547 vars->link_status |=
10548 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10549
10550 /* Determine if EEE was negotiated */
10551 if (bnx2x_is_8483x_8485x(phy))
10552 bnx2x_eee_an_resolve(phy, params, vars);
10553 }
10554
10555 return link_up;
10556 }
10557
bnx2x_848xx_format_ver(u32 raw_ver,u8 * str,u16 * len)10558 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10559 {
10560 int status = 0;
10561 u32 spirom_ver;
10562 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10563 status = bnx2x_format_ver(spirom_ver, str, len);
10564 return status;
10565 }
10566
bnx2x_8481_hw_reset(struct bnx2x_phy * phy,struct link_params * params)10567 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10568 struct link_params *params)
10569 {
10570 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10571 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10572 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10573 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10574 }
10575
bnx2x_8481_link_reset(struct bnx2x_phy * phy,struct link_params * params)10576 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10577 struct link_params *params)
10578 {
10579 bnx2x_cl45_write(params->bp, phy,
10580 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10581 bnx2x_cl45_write(params->bp, phy,
10582 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10583 }
10584
bnx2x_848x3_link_reset(struct bnx2x_phy * phy,struct link_params * params)10585 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10586 struct link_params *params)
10587 {
10588 struct bnx2x *bp = params->bp;
10589 u8 port;
10590 u16 val16;
10591
10592 if (!(CHIP_IS_E1x(bp)))
10593 port = BP_PATH(bp);
10594 else
10595 port = params->port;
10596
10597 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10598 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10599 MISC_REGISTERS_GPIO_OUTPUT_LOW,
10600 port);
10601 } else {
10602 bnx2x_cl45_read(bp, phy,
10603 MDIO_CTL_DEVAD,
10604 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10605 val16 |= MDIO_84833_SUPER_ISOLATE;
10606 bnx2x_cl45_write(bp, phy,
10607 MDIO_CTL_DEVAD,
10608 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10609 }
10610 }
10611
bnx2x_848xx_set_link_led(struct bnx2x_phy * phy,struct link_params * params,u8 mode)10612 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10613 struct link_params *params, u8 mode)
10614 {
10615 struct bnx2x *bp = params->bp;
10616 u16 val;
10617 u8 port;
10618
10619 if (!(CHIP_IS_E1x(bp)))
10620 port = BP_PATH(bp);
10621 else
10622 port = params->port;
10623
10624 switch (mode) {
10625 case LED_MODE_OFF:
10626
10627 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10628
10629 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10630 SHARED_HW_CFG_LED_EXTPHY1) {
10631
10632 /* Set LED masks */
10633 bnx2x_cl45_write(bp, phy,
10634 MDIO_PMA_DEVAD,
10635 MDIO_PMA_REG_8481_LED1_MASK,
10636 0x0);
10637
10638 bnx2x_cl45_write(bp, phy,
10639 MDIO_PMA_DEVAD,
10640 MDIO_PMA_REG_8481_LED2_MASK,
10641 0x0);
10642
10643 bnx2x_cl45_write(bp, phy,
10644 MDIO_PMA_DEVAD,
10645 MDIO_PMA_REG_8481_LED3_MASK,
10646 0x0);
10647
10648 bnx2x_cl45_write(bp, phy,
10649 MDIO_PMA_DEVAD,
10650 MDIO_PMA_REG_8481_LED5_MASK,
10651 0x0);
10652
10653 } else {
10654 bnx2x_cl45_write(bp, phy,
10655 MDIO_PMA_DEVAD,
10656 MDIO_PMA_REG_8481_LED1_MASK,
10657 0x0);
10658 }
10659 break;
10660 case LED_MODE_FRONT_PANEL_OFF:
10661
10662 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10663 port);
10664
10665 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10666 SHARED_HW_CFG_LED_EXTPHY1) {
10667
10668 /* Set LED masks */
10669 bnx2x_cl45_write(bp, phy,
10670 MDIO_PMA_DEVAD,
10671 MDIO_PMA_REG_8481_LED1_MASK,
10672 0x0);
10673
10674 bnx2x_cl45_write(bp, phy,
10675 MDIO_PMA_DEVAD,
10676 MDIO_PMA_REG_8481_LED2_MASK,
10677 0x0);
10678
10679 bnx2x_cl45_write(bp, phy,
10680 MDIO_PMA_DEVAD,
10681 MDIO_PMA_REG_8481_LED3_MASK,
10682 0x0);
10683
10684 bnx2x_cl45_write(bp, phy,
10685 MDIO_PMA_DEVAD,
10686 MDIO_PMA_REG_8481_LED5_MASK,
10687 0x20);
10688
10689 } else {
10690 bnx2x_cl45_write(bp, phy,
10691 MDIO_PMA_DEVAD,
10692 MDIO_PMA_REG_8481_LED1_MASK,
10693 0x0);
10694 if (phy->type ==
10695 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10696 /* Disable MI_INT interrupt before setting LED4
10697 * source to constant off.
10698 */
10699 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10700 params->port*4) &
10701 NIG_MASK_MI_INT) {
10702 params->link_flags |=
10703 LINK_FLAGS_INT_DISABLED;
10704
10705 bnx2x_bits_dis(
10706 bp,
10707 NIG_REG_MASK_INTERRUPT_PORT0 +
10708 params->port*4,
10709 NIG_MASK_MI_INT);
10710 }
10711 bnx2x_cl45_write(bp, phy,
10712 MDIO_PMA_DEVAD,
10713 MDIO_PMA_REG_8481_SIGNAL_MASK,
10714 0x0);
10715 }
10716 }
10717 break;
10718 case LED_MODE_ON:
10719
10720 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10721
10722 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10723 SHARED_HW_CFG_LED_EXTPHY1) {
10724 /* Set control reg */
10725 bnx2x_cl45_read(bp, phy,
10726 MDIO_PMA_DEVAD,
10727 MDIO_PMA_REG_8481_LINK_SIGNAL,
10728 &val);
10729 val &= 0x8000;
10730 val |= 0x2492;
10731
10732 bnx2x_cl45_write(bp, phy,
10733 MDIO_PMA_DEVAD,
10734 MDIO_PMA_REG_8481_LINK_SIGNAL,
10735 val);
10736
10737 /* Set LED masks */
10738 bnx2x_cl45_write(bp, phy,
10739 MDIO_PMA_DEVAD,
10740 MDIO_PMA_REG_8481_LED1_MASK,
10741 0x0);
10742
10743 bnx2x_cl45_write(bp, phy,
10744 MDIO_PMA_DEVAD,
10745 MDIO_PMA_REG_8481_LED2_MASK,
10746 0x20);
10747
10748 bnx2x_cl45_write(bp, phy,
10749 MDIO_PMA_DEVAD,
10750 MDIO_PMA_REG_8481_LED3_MASK,
10751 0x20);
10752
10753 bnx2x_cl45_write(bp, phy,
10754 MDIO_PMA_DEVAD,
10755 MDIO_PMA_REG_8481_LED5_MASK,
10756 0x0);
10757 } else {
10758 bnx2x_cl45_write(bp, phy,
10759 MDIO_PMA_DEVAD,
10760 MDIO_PMA_REG_8481_LED1_MASK,
10761 0x20);
10762 if (phy->type ==
10763 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10764 /* Disable MI_INT interrupt before setting LED4
10765 * source to constant on.
10766 */
10767 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10768 params->port*4) &
10769 NIG_MASK_MI_INT) {
10770 params->link_flags |=
10771 LINK_FLAGS_INT_DISABLED;
10772
10773 bnx2x_bits_dis(
10774 bp,
10775 NIG_REG_MASK_INTERRUPT_PORT0 +
10776 params->port*4,
10777 NIG_MASK_MI_INT);
10778 }
10779 bnx2x_cl45_write(bp, phy,
10780 MDIO_PMA_DEVAD,
10781 MDIO_PMA_REG_8481_SIGNAL_MASK,
10782 0x20);
10783 }
10784 }
10785 break;
10786
10787 case LED_MODE_OPER:
10788
10789 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10790
10791 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10792 SHARED_HW_CFG_LED_EXTPHY1) {
10793
10794 /* Set control reg */
10795 bnx2x_cl45_read(bp, phy,
10796 MDIO_PMA_DEVAD,
10797 MDIO_PMA_REG_8481_LINK_SIGNAL,
10798 &val);
10799
10800 if (!((val &
10801 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10802 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10803 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10804 bnx2x_cl45_write(bp, phy,
10805 MDIO_PMA_DEVAD,
10806 MDIO_PMA_REG_8481_LINK_SIGNAL,
10807 0xa492);
10808 }
10809
10810 /* Set LED masks */
10811 bnx2x_cl45_write(bp, phy,
10812 MDIO_PMA_DEVAD,
10813 MDIO_PMA_REG_8481_LED1_MASK,
10814 0x10);
10815
10816 bnx2x_cl45_write(bp, phy,
10817 MDIO_PMA_DEVAD,
10818 MDIO_PMA_REG_8481_LED2_MASK,
10819 0x80);
10820
10821 bnx2x_cl45_write(bp, phy,
10822 MDIO_PMA_DEVAD,
10823 MDIO_PMA_REG_8481_LED3_MASK,
10824 0x98);
10825
10826 bnx2x_cl45_write(bp, phy,
10827 MDIO_PMA_DEVAD,
10828 MDIO_PMA_REG_8481_LED5_MASK,
10829 0x40);
10830
10831 } else {
10832 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
10833 * sources are all wired through LED1, rather than only
10834 * 10G in other modes.
10835 */
10836 val = ((params->hw_led_mode <<
10837 SHARED_HW_CFG_LED_MODE_SHIFT) ==
10838 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
10839
10840 bnx2x_cl45_write(bp, phy,
10841 MDIO_PMA_DEVAD,
10842 MDIO_PMA_REG_8481_LED1_MASK,
10843 val);
10844
10845 /* Tell LED3 to blink on source */
10846 bnx2x_cl45_read(bp, phy,
10847 MDIO_PMA_DEVAD,
10848 MDIO_PMA_REG_8481_LINK_SIGNAL,
10849 &val);
10850 val &= ~(7<<6);
10851 val |= (1<<6); /* A83B[8:6]= 1 */
10852 bnx2x_cl45_write(bp, phy,
10853 MDIO_PMA_DEVAD,
10854 MDIO_PMA_REG_8481_LINK_SIGNAL,
10855 val);
10856 if (phy->type ==
10857 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10858 /* Restore LED4 source to external link,
10859 * and re-enable interrupts.
10860 */
10861 bnx2x_cl45_write(bp, phy,
10862 MDIO_PMA_DEVAD,
10863 MDIO_PMA_REG_8481_SIGNAL_MASK,
10864 0x40);
10865 if (params->link_flags &
10866 LINK_FLAGS_INT_DISABLED) {
10867 bnx2x_link_int_enable(params);
10868 params->link_flags &=
10869 ~LINK_FLAGS_INT_DISABLED;
10870 }
10871 }
10872 }
10873 break;
10874 }
10875
10876 /* This is a workaround for E3+84833 until autoneg
10877 * restart is fixed in f/w
10878 */
10879 if (CHIP_IS_E3(bp)) {
10880 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10881 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10882 }
10883 }
10884
10885 /******************************************************************/
10886 /* 54618SE PHY SECTION */
10887 /******************************************************************/
bnx2x_54618se_specific_func(struct bnx2x_phy * phy,struct link_params * params,u32 action)10888 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
10889 struct link_params *params,
10890 u32 action)
10891 {
10892 struct bnx2x *bp = params->bp;
10893 u16 temp;
10894 switch (action) {
10895 case PHY_INIT:
10896 /* Configure LED4: set to INTR (0x6). */
10897 /* Accessing shadow register 0xe. */
10898 bnx2x_cl22_write(bp, phy,
10899 MDIO_REG_GPHY_SHADOW,
10900 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10901 bnx2x_cl22_read(bp, phy,
10902 MDIO_REG_GPHY_SHADOW,
10903 &temp);
10904 temp &= ~(0xf << 4);
10905 temp |= (0x6 << 4);
10906 bnx2x_cl22_write(bp, phy,
10907 MDIO_REG_GPHY_SHADOW,
10908 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10909 /* Configure INTR based on link status change. */
10910 bnx2x_cl22_write(bp, phy,
10911 MDIO_REG_INTR_MASK,
10912 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10913 break;
10914 }
10915 }
10916
bnx2x_54618se_config_init(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)10917 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10918 struct link_params *params,
10919 struct link_vars *vars)
10920 {
10921 struct bnx2x *bp = params->bp;
10922 u8 port;
10923 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10924 u32 cfg_pin;
10925
10926 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10927 usleep_range(1000, 2000);
10928
10929 /* This works with E3 only, no need to check the chip
10930 * before determining the port.
10931 */
10932 port = params->port;
10933
10934 cfg_pin = (REG_RD(bp, params->shmem_base +
10935 offsetof(struct shmem_region,
10936 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10937 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10938 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10939
10940 /* Drive pin high to bring the GPHY out of reset. */
10941 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10942
10943 /* wait for GPHY to reset */
10944 msleep(50);
10945
10946 /* reset phy */
10947 bnx2x_cl22_write(bp, phy,
10948 MDIO_PMA_REG_CTRL, 0x8000);
10949 bnx2x_wait_reset_complete(bp, phy, params);
10950
10951 /* Wait for GPHY to reset */
10952 msleep(50);
10953
10954
10955 bnx2x_54618se_specific_func(phy, params, PHY_INIT);
10956 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10957 bnx2x_cl22_write(bp, phy,
10958 MDIO_REG_GPHY_SHADOW,
10959 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10960 bnx2x_cl22_read(bp, phy,
10961 MDIO_REG_GPHY_SHADOW,
10962 &temp);
10963 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10964 bnx2x_cl22_write(bp, phy,
10965 MDIO_REG_GPHY_SHADOW,
10966 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10967
10968 /* Set up fc */
10969 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10970 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10971 fc_val = 0;
10972 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10973 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10974 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10975
10976 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10977 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10978 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10979
10980 /* Read all advertisement */
10981 bnx2x_cl22_read(bp, phy,
10982 0x09,
10983 &an_1000_val);
10984
10985 bnx2x_cl22_read(bp, phy,
10986 0x04,
10987 &an_10_100_val);
10988
10989 bnx2x_cl22_read(bp, phy,
10990 MDIO_PMA_REG_CTRL,
10991 &autoneg_val);
10992
10993 /* Disable forced speed */
10994 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10995 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10996 (1<<11));
10997
10998 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10999 (phy->speed_cap_mask &
11000 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
11001 (phy->req_line_speed == SPEED_1000)) {
11002 an_1000_val |= (1<<8);
11003 autoneg_val |= (1<<9 | 1<<12);
11004 if (phy->req_duplex == DUPLEX_FULL)
11005 an_1000_val |= (1<<9);
11006 DP(NETIF_MSG_LINK, "Advertising 1G\n");
11007 } else
11008 an_1000_val &= ~((1<<8) | (1<<9));
11009
11010 bnx2x_cl22_write(bp, phy,
11011 0x09,
11012 an_1000_val);
11013 bnx2x_cl22_read(bp, phy,
11014 0x09,
11015 &an_1000_val);
11016
11017 /* Advertise 10/100 link speed */
11018 if (phy->req_line_speed == SPEED_AUTO_NEG) {
11019 if (phy->speed_cap_mask &
11020 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
11021 an_10_100_val |= (1<<5);
11022 autoneg_val |= (1<<9 | 1<<12);
11023 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
11024 }
11025 if (phy->speed_cap_mask &
11026 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {
11027 an_10_100_val |= (1<<6);
11028 autoneg_val |= (1<<9 | 1<<12);
11029 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
11030 }
11031 if (phy->speed_cap_mask &
11032 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
11033 an_10_100_val |= (1<<7);
11034 autoneg_val |= (1<<9 | 1<<12);
11035 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
11036 }
11037 if (phy->speed_cap_mask &
11038 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
11039 an_10_100_val |= (1<<8);
11040 autoneg_val |= (1<<9 | 1<<12);
11041 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
11042 }
11043 }
11044
11045 /* Only 10/100 are allowed to work in FORCE mode */
11046 if (phy->req_line_speed == SPEED_100) {
11047 autoneg_val |= (1<<13);
11048 /* Enabled AUTO-MDIX when autoneg is disabled */
11049 bnx2x_cl22_write(bp, phy,
11050 0x18,
11051 (1<<15 | 1<<9 | 7<<0));
11052 DP(NETIF_MSG_LINK, "Setting 100M force\n");
11053 }
11054 if (phy->req_line_speed == SPEED_10) {
11055 /* Enabled AUTO-MDIX when autoneg is disabled */
11056 bnx2x_cl22_write(bp, phy,
11057 0x18,
11058 (1<<15 | 1<<9 | 7<<0));
11059 DP(NETIF_MSG_LINK, "Setting 10M force\n");
11060 }
11061
11062 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
11063 int rc;
11064
11065 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
11066 MDIO_REG_GPHY_EXP_ACCESS_TOP |
11067 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
11068 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
11069 temp &= 0xfffe;
11070 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
11071
11072 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
11073 if (rc) {
11074 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
11075 bnx2x_eee_disable(phy, params, vars);
11076 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
11077 (phy->req_duplex == DUPLEX_FULL) &&
11078 (bnx2x_eee_calc_timer(params) ||
11079 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
11080 /* Need to advertise EEE only when requested,
11081 * and either no LPI assertion was requested,
11082 * or it was requested and a valid timer was set.
11083 * Also notice full duplex is required for EEE.
11084 */
11085 bnx2x_eee_advertise(phy, params, vars,
11086 SHMEM_EEE_1G_ADV);
11087 } else {
11088 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
11089 bnx2x_eee_disable(phy, params, vars);
11090 }
11091 } else {
11092 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
11093 SHMEM_EEE_SUPPORTED_SHIFT;
11094
11095 if (phy->flags & FLAGS_EEE) {
11096 /* Handle legacy auto-grEEEn */
11097 if (params->feature_config_flags &
11098 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
11099 temp = 6;
11100 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
11101 } else {
11102 temp = 0;
11103 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
11104 }
11105 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
11106 MDIO_AN_REG_EEE_ADV, temp);
11107 }
11108 }
11109
11110 bnx2x_cl22_write(bp, phy,
11111 0x04,
11112 an_10_100_val | fc_val);
11113
11114 if (phy->req_duplex == DUPLEX_FULL)
11115 autoneg_val |= (1<<8);
11116
11117 bnx2x_cl22_write(bp, phy,
11118 MDIO_PMA_REG_CTRL, autoneg_val);
11119
11120 return 0;
11121 }
11122
11123
bnx2x_5461x_set_link_led(struct bnx2x_phy * phy,struct link_params * params,u8 mode)11124 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
11125 struct link_params *params, u8 mode)
11126 {
11127 struct bnx2x *bp = params->bp;
11128 u16 temp;
11129
11130 bnx2x_cl22_write(bp, phy,
11131 MDIO_REG_GPHY_SHADOW,
11132 MDIO_REG_GPHY_SHADOW_LED_SEL1);
11133 bnx2x_cl22_read(bp, phy,
11134 MDIO_REG_GPHY_SHADOW,
11135 &temp);
11136 temp &= 0xff00;
11137
11138 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
11139 switch (mode) {
11140 case LED_MODE_FRONT_PANEL_OFF:
11141 case LED_MODE_OFF:
11142 temp |= 0x00ee;
11143 break;
11144 case LED_MODE_OPER:
11145 temp |= 0x0001;
11146 break;
11147 case LED_MODE_ON:
11148 temp |= 0x00ff;
11149 break;
11150 default:
11151 break;
11152 }
11153 bnx2x_cl22_write(bp, phy,
11154 MDIO_REG_GPHY_SHADOW,
11155 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11156 return;
11157 }
11158
11159
bnx2x_54618se_link_reset(struct bnx2x_phy * phy,struct link_params * params)11160 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
11161 struct link_params *params)
11162 {
11163 struct bnx2x *bp = params->bp;
11164 u32 cfg_pin;
11165 u8 port;
11166
11167 /* In case of no EPIO routed to reset the GPHY, put it
11168 * in low power mode.
11169 */
11170 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
11171 /* This works with E3 only, no need to check the chip
11172 * before determining the port.
11173 */
11174 port = params->port;
11175 cfg_pin = (REG_RD(bp, params->shmem_base +
11176 offsetof(struct shmem_region,
11177 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11178 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11179 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11180
11181 /* Drive pin low to put GPHY in reset. */
11182 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
11183 }
11184
bnx2x_54618se_read_status(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)11185 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
11186 struct link_params *params,
11187 struct link_vars *vars)
11188 {
11189 struct bnx2x *bp = params->bp;
11190 u16 val;
11191 u8 link_up = 0;
11192 u16 legacy_status, legacy_speed;
11193
11194 /* Get speed operation status */
11195 bnx2x_cl22_read(bp, phy,
11196 MDIO_REG_GPHY_AUX_STATUS,
11197 &legacy_status);
11198 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
11199
11200 /* Read status to clear the PHY interrupt. */
11201 bnx2x_cl22_read(bp, phy,
11202 MDIO_REG_INTR_STATUS,
11203 &val);
11204
11205 link_up = ((legacy_status & (1<<2)) == (1<<2));
11206
11207 if (link_up) {
11208 legacy_speed = (legacy_status & (7<<8));
11209 if (legacy_speed == (7<<8)) {
11210 vars->line_speed = SPEED_1000;
11211 vars->duplex = DUPLEX_FULL;
11212 } else if (legacy_speed == (6<<8)) {
11213 vars->line_speed = SPEED_1000;
11214 vars->duplex = DUPLEX_HALF;
11215 } else if (legacy_speed == (5<<8)) {
11216 vars->line_speed = SPEED_100;
11217 vars->duplex = DUPLEX_FULL;
11218 }
11219 /* Omitting 100Base-T4 for now */
11220 else if (legacy_speed == (3<<8)) {
11221 vars->line_speed = SPEED_100;
11222 vars->duplex = DUPLEX_HALF;
11223 } else if (legacy_speed == (2<<8)) {
11224 vars->line_speed = SPEED_10;
11225 vars->duplex = DUPLEX_FULL;
11226 } else if (legacy_speed == (1<<8)) {
11227 vars->line_speed = SPEED_10;
11228 vars->duplex = DUPLEX_HALF;
11229 } else /* Should not happen */
11230 vars->line_speed = 0;
11231
11232 DP(NETIF_MSG_LINK,
11233 "Link is up in %dMbps, is_duplex_full= %d\n",
11234 vars->line_speed,
11235 (vars->duplex == DUPLEX_FULL));
11236
11237 /* Check legacy speed AN resolution */
11238 bnx2x_cl22_read(bp, phy,
11239 0x01,
11240 &val);
11241 if (val & (1<<5))
11242 vars->link_status |=
11243 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11244 bnx2x_cl22_read(bp, phy,
11245 0x06,
11246 &val);
11247 if ((val & (1<<0)) == 0)
11248 vars->link_status |=
11249 LINK_STATUS_PARALLEL_DETECTION_USED;
11250
11251 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
11252 vars->line_speed);
11253
11254 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11255
11256 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11257 /* Report LP advertised speeds */
11258 bnx2x_cl22_read(bp, phy, 0x5, &val);
11259
11260 if (val & (1<<5))
11261 vars->link_status |=
11262 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11263 if (val & (1<<6))
11264 vars->link_status |=
11265 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11266 if (val & (1<<7))
11267 vars->link_status |=
11268 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11269 if (val & (1<<8))
11270 vars->link_status |=
11271 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11272 if (val & (1<<9))
11273 vars->link_status |=
11274 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11275
11276 bnx2x_cl22_read(bp, phy, 0xa, &val);
11277 if (val & (1<<10))
11278 vars->link_status |=
11279 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11280 if (val & (1<<11))
11281 vars->link_status |=
11282 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11283
11284 if ((phy->flags & FLAGS_EEE) &&
11285 bnx2x_eee_has_cap(params))
11286 bnx2x_eee_an_resolve(phy, params, vars);
11287 }
11288 }
11289 return link_up;
11290 }
11291
bnx2x_54618se_config_loopback(struct bnx2x_phy * phy,struct link_params * params)11292 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11293 struct link_params *params)
11294 {
11295 struct bnx2x *bp = params->bp;
11296 u16 val;
11297 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11298
11299 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11300
11301 /* Enable master/slave manual mmode and set to master */
11302 /* mii write 9 [bits set 11 12] */
11303 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11304
11305 /* forced 1G and disable autoneg */
11306 /* set val [mii read 0] */
11307 /* set val [expr $val & [bits clear 6 12 13]] */
11308 /* set val [expr $val | [bits set 6 8]] */
11309 /* mii write 0 $val */
11310 bnx2x_cl22_read(bp, phy, 0x00, &val);
11311 val &= ~((1<<6) | (1<<12) | (1<<13));
11312 val |= (1<<6) | (1<<8);
11313 bnx2x_cl22_write(bp, phy, 0x00, val);
11314
11315 /* Set external loopback and Tx using 6dB coding */
11316 /* mii write 0x18 7 */
11317 /* set val [mii read 0x18] */
11318 /* mii write 0x18 [expr $val | [bits set 10 15]] */
11319 bnx2x_cl22_write(bp, phy, 0x18, 7);
11320 bnx2x_cl22_read(bp, phy, 0x18, &val);
11321 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11322
11323 /* This register opens the gate for the UMAC despite its name */
11324 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11325
11326 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11327 * length used by the MAC receive logic to check frames.
11328 */
11329 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11330 }
11331
11332 /******************************************************************/
11333 /* SFX7101 PHY SECTION */
11334 /******************************************************************/
bnx2x_7101_config_loopback(struct bnx2x_phy * phy,struct link_params * params)11335 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11336 struct link_params *params)
11337 {
11338 struct bnx2x *bp = params->bp;
11339 /* SFX7101_XGXS_TEST1 */
11340 bnx2x_cl45_write(bp, phy,
11341 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11342 }
11343
bnx2x_7101_config_init(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)11344 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11345 struct link_params *params,
11346 struct link_vars *vars)
11347 {
11348 u16 fw_ver1, fw_ver2, val;
11349 struct bnx2x *bp = params->bp;
11350 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11351
11352 /* Restore normal power mode*/
11353 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11354 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11355 /* HW reset */
11356 bnx2x_ext_phy_hw_reset(bp, params->port);
11357 bnx2x_wait_reset_complete(bp, phy, params);
11358
11359 bnx2x_cl45_write(bp, phy,
11360 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11361 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11362 bnx2x_cl45_write(bp, phy,
11363 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11364
11365 bnx2x_ext_phy_set_pause(params, phy, vars);
11366 /* Restart autoneg */
11367 bnx2x_cl45_read(bp, phy,
11368 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11369 val |= 0x200;
11370 bnx2x_cl45_write(bp, phy,
11371 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11372
11373 /* Save spirom version */
11374 bnx2x_cl45_read(bp, phy,
11375 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11376
11377 bnx2x_cl45_read(bp, phy,
11378 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11379 bnx2x_save_spirom_version(bp, params->port,
11380 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11381 return 0;
11382 }
11383
bnx2x_7101_read_status(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)11384 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11385 struct link_params *params,
11386 struct link_vars *vars)
11387 {
11388 struct bnx2x *bp = params->bp;
11389 u8 link_up;
11390 u16 val1, val2;
11391 bnx2x_cl45_read(bp, phy,
11392 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11393 bnx2x_cl45_read(bp, phy,
11394 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11395 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11396 val2, val1);
11397 bnx2x_cl45_read(bp, phy,
11398 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11399 bnx2x_cl45_read(bp, phy,
11400 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11401 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11402 val2, val1);
11403 link_up = ((val1 & 4) == 4);
11404 /* If link is up print the AN outcome of the SFX7101 PHY */
11405 if (link_up) {
11406 bnx2x_cl45_read(bp, phy,
11407 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11408 &val2);
11409 vars->line_speed = SPEED_10000;
11410 vars->duplex = DUPLEX_FULL;
11411 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11412 val2, (val2 & (1<<14)));
11413 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11414 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11415
11416 /* Read LP advertised speeds */
11417 if (val2 & (1<<11))
11418 vars->link_status |=
11419 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11420 }
11421 return link_up;
11422 }
11423
bnx2x_7101_format_ver(u32 spirom_ver,u8 * str,u16 * len)11424 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11425 {
11426 if (*len < 5)
11427 return -EINVAL;
11428 str[0] = (spirom_ver & 0xFF);
11429 str[1] = (spirom_ver & 0xFF00) >> 8;
11430 str[2] = (spirom_ver & 0xFF0000) >> 16;
11431 str[3] = (spirom_ver & 0xFF000000) >> 24;
11432 str[4] = '\0';
11433 *len -= 5;
11434 return 0;
11435 }
11436
bnx2x_sfx7101_sp_sw_reset(struct bnx2x * bp,struct bnx2x_phy * phy)11437 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11438 {
11439 u16 val, cnt;
11440
11441 bnx2x_cl45_read(bp, phy,
11442 MDIO_PMA_DEVAD,
11443 MDIO_PMA_REG_7101_RESET, &val);
11444
11445 for (cnt = 0; cnt < 10; cnt++) {
11446 msleep(50);
11447 /* Writes a self-clearing reset */
11448 bnx2x_cl45_write(bp, phy,
11449 MDIO_PMA_DEVAD,
11450 MDIO_PMA_REG_7101_RESET,
11451 (val | (1<<15)));
11452 /* Wait for clear */
11453 bnx2x_cl45_read(bp, phy,
11454 MDIO_PMA_DEVAD,
11455 MDIO_PMA_REG_7101_RESET, &val);
11456
11457 if ((val & (1<<15)) == 0)
11458 break;
11459 }
11460 }
11461
bnx2x_7101_hw_reset(struct bnx2x_phy * phy,struct link_params * params)11462 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11463 struct link_params *params) {
11464 /* Low power mode is controlled by GPIO 2 */
11465 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11466 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11467 /* The PHY reset is controlled by GPIO 1 */
11468 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11469 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11470 }
11471
bnx2x_7101_set_link_led(struct bnx2x_phy * phy,struct link_params * params,u8 mode)11472 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11473 struct link_params *params, u8 mode)
11474 {
11475 u16 val = 0;
11476 struct bnx2x *bp = params->bp;
11477 switch (mode) {
11478 case LED_MODE_FRONT_PANEL_OFF:
11479 case LED_MODE_OFF:
11480 val = 2;
11481 break;
11482 case LED_MODE_ON:
11483 val = 1;
11484 break;
11485 case LED_MODE_OPER:
11486 val = 0;
11487 break;
11488 }
11489 bnx2x_cl45_write(bp, phy,
11490 MDIO_PMA_DEVAD,
11491 MDIO_PMA_REG_7107_LINK_LED_CNTL,
11492 val);
11493 }
11494
11495 /******************************************************************/
11496 /* STATIC PHY DECLARATION */
11497 /******************************************************************/
11498
11499 static const struct bnx2x_phy phy_null = {
11500 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11501 .addr = 0,
11502 .def_md_devad = 0,
11503 .flags = FLAGS_INIT_XGXS_FIRST,
11504 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11505 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11506 .mdio_ctrl = 0,
11507 .supported = 0,
11508 .media_type = ETH_PHY_NOT_PRESENT,
11509 .ver_addr = 0,
11510 .req_flow_ctrl = 0,
11511 .req_line_speed = 0,
11512 .speed_cap_mask = 0,
11513 .req_duplex = 0,
11514 .rsrv = 0,
11515 .config_init = (config_init_t)NULL,
11516 .read_status = (read_status_t)NULL,
11517 .link_reset = (link_reset_t)NULL,
11518 .config_loopback = (config_loopback_t)NULL,
11519 .format_fw_ver = (format_fw_ver_t)NULL,
11520 .hw_reset = (hw_reset_t)NULL,
11521 .set_link_led = (set_link_led_t)NULL,
11522 .phy_specific_func = (phy_specific_func_t)NULL
11523 };
11524
11525 static const struct bnx2x_phy phy_serdes = {
11526 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11527 .addr = 0xff,
11528 .def_md_devad = 0,
11529 .flags = 0,
11530 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11531 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11532 .mdio_ctrl = 0,
11533 .supported = (SUPPORTED_10baseT_Half |
11534 SUPPORTED_10baseT_Full |
11535 SUPPORTED_100baseT_Half |
11536 SUPPORTED_100baseT_Full |
11537 SUPPORTED_1000baseT_Full |
11538 SUPPORTED_2500baseX_Full |
11539 SUPPORTED_TP |
11540 SUPPORTED_Autoneg |
11541 SUPPORTED_Pause |
11542 SUPPORTED_Asym_Pause),
11543 .media_type = ETH_PHY_BASE_T,
11544 .ver_addr = 0,
11545 .req_flow_ctrl = 0,
11546 .req_line_speed = 0,
11547 .speed_cap_mask = 0,
11548 .req_duplex = 0,
11549 .rsrv = 0,
11550 .config_init = (config_init_t)bnx2x_xgxs_config_init,
11551 .read_status = (read_status_t)bnx2x_link_settings_status,
11552 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11553 .config_loopback = (config_loopback_t)NULL,
11554 .format_fw_ver = (format_fw_ver_t)NULL,
11555 .hw_reset = (hw_reset_t)NULL,
11556 .set_link_led = (set_link_led_t)NULL,
11557 .phy_specific_func = (phy_specific_func_t)NULL
11558 };
11559
11560 static const struct bnx2x_phy phy_xgxs = {
11561 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11562 .addr = 0xff,
11563 .def_md_devad = 0,
11564 .flags = 0,
11565 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11566 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11567 .mdio_ctrl = 0,
11568 .supported = (SUPPORTED_10baseT_Half |
11569 SUPPORTED_10baseT_Full |
11570 SUPPORTED_100baseT_Half |
11571 SUPPORTED_100baseT_Full |
11572 SUPPORTED_1000baseT_Full |
11573 SUPPORTED_2500baseX_Full |
11574 SUPPORTED_10000baseT_Full |
11575 SUPPORTED_FIBRE |
11576 SUPPORTED_Autoneg |
11577 SUPPORTED_Pause |
11578 SUPPORTED_Asym_Pause),
11579 .media_type = ETH_PHY_CX4,
11580 .ver_addr = 0,
11581 .req_flow_ctrl = 0,
11582 .req_line_speed = 0,
11583 .speed_cap_mask = 0,
11584 .req_duplex = 0,
11585 .rsrv = 0,
11586 .config_init = (config_init_t)bnx2x_xgxs_config_init,
11587 .read_status = (read_status_t)bnx2x_link_settings_status,
11588 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11589 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11590 .format_fw_ver = (format_fw_ver_t)NULL,
11591 .hw_reset = (hw_reset_t)NULL,
11592 .set_link_led = (set_link_led_t)NULL,
11593 .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11594 };
11595 static const struct bnx2x_phy phy_warpcore = {
11596 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11597 .addr = 0xff,
11598 .def_md_devad = 0,
11599 .flags = FLAGS_TX_ERROR_CHECK,
11600 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11601 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11602 .mdio_ctrl = 0,
11603 .supported = (SUPPORTED_10baseT_Half |
11604 SUPPORTED_10baseT_Full |
11605 SUPPORTED_100baseT_Half |
11606 SUPPORTED_100baseT_Full |
11607 SUPPORTED_1000baseT_Full |
11608 SUPPORTED_1000baseKX_Full |
11609 SUPPORTED_10000baseT_Full |
11610 SUPPORTED_10000baseKR_Full |
11611 SUPPORTED_20000baseKR2_Full |
11612 SUPPORTED_20000baseMLD2_Full |
11613 SUPPORTED_FIBRE |
11614 SUPPORTED_Autoneg |
11615 SUPPORTED_Pause |
11616 SUPPORTED_Asym_Pause),
11617 .media_type = ETH_PHY_UNSPECIFIED,
11618 .ver_addr = 0,
11619 .req_flow_ctrl = 0,
11620 .req_line_speed = 0,
11621 .speed_cap_mask = 0,
11622 /* req_duplex = */0,
11623 /* rsrv = */0,
11624 .config_init = (config_init_t)bnx2x_warpcore_config_init,
11625 .read_status = (read_status_t)bnx2x_warpcore_read_status,
11626 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
11627 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11628 .format_fw_ver = (format_fw_ver_t)NULL,
11629 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset,
11630 .set_link_led = (set_link_led_t)NULL,
11631 .phy_specific_func = (phy_specific_func_t)NULL
11632 };
11633
11634
11635 static const struct bnx2x_phy phy_7101 = {
11636 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11637 .addr = 0xff,
11638 .def_md_devad = 0,
11639 .flags = FLAGS_FAN_FAILURE_DET_REQ,
11640 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11641 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11642 .mdio_ctrl = 0,
11643 .supported = (SUPPORTED_10000baseT_Full |
11644 SUPPORTED_TP |
11645 SUPPORTED_Autoneg |
11646 SUPPORTED_Pause |
11647 SUPPORTED_Asym_Pause),
11648 .media_type = ETH_PHY_BASE_T,
11649 .ver_addr = 0,
11650 .req_flow_ctrl = 0,
11651 .req_line_speed = 0,
11652 .speed_cap_mask = 0,
11653 .req_duplex = 0,
11654 .rsrv = 0,
11655 .config_init = (config_init_t)bnx2x_7101_config_init,
11656 .read_status = (read_status_t)bnx2x_7101_read_status,
11657 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11658 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11659 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
11660 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
11661 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
11662 .phy_specific_func = (phy_specific_func_t)NULL
11663 };
11664 static const struct bnx2x_phy phy_8073 = {
11665 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11666 .addr = 0xff,
11667 .def_md_devad = 0,
11668 .flags = 0,
11669 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11670 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11671 .mdio_ctrl = 0,
11672 .supported = (SUPPORTED_10000baseT_Full |
11673 SUPPORTED_2500baseX_Full |
11674 SUPPORTED_1000baseT_Full |
11675 SUPPORTED_FIBRE |
11676 SUPPORTED_Autoneg |
11677 SUPPORTED_Pause |
11678 SUPPORTED_Asym_Pause),
11679 .media_type = ETH_PHY_KR,
11680 .ver_addr = 0,
11681 .req_flow_ctrl = 0,
11682 .req_line_speed = 0,
11683 .speed_cap_mask = 0,
11684 .req_duplex = 0,
11685 .rsrv = 0,
11686 .config_init = (config_init_t)bnx2x_8073_config_init,
11687 .read_status = (read_status_t)bnx2x_8073_read_status,
11688 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
11689 .config_loopback = (config_loopback_t)NULL,
11690 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11691 .hw_reset = (hw_reset_t)NULL,
11692 .set_link_led = (set_link_led_t)NULL,
11693 .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11694 };
11695 static const struct bnx2x_phy phy_8705 = {
11696 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11697 .addr = 0xff,
11698 .def_md_devad = 0,
11699 .flags = FLAGS_INIT_XGXS_FIRST,
11700 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11701 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11702 .mdio_ctrl = 0,
11703 .supported = (SUPPORTED_10000baseT_Full |
11704 SUPPORTED_FIBRE |
11705 SUPPORTED_Pause |
11706 SUPPORTED_Asym_Pause),
11707 .media_type = ETH_PHY_XFP_FIBER,
11708 .ver_addr = 0,
11709 .req_flow_ctrl = 0,
11710 .req_line_speed = 0,
11711 .speed_cap_mask = 0,
11712 .req_duplex = 0,
11713 .rsrv = 0,
11714 .config_init = (config_init_t)bnx2x_8705_config_init,
11715 .read_status = (read_status_t)bnx2x_8705_read_status,
11716 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11717 .config_loopback = (config_loopback_t)NULL,
11718 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
11719 .hw_reset = (hw_reset_t)NULL,
11720 .set_link_led = (set_link_led_t)NULL,
11721 .phy_specific_func = (phy_specific_func_t)NULL
11722 };
11723 static const struct bnx2x_phy phy_8706 = {
11724 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11725 .addr = 0xff,
11726 .def_md_devad = 0,
11727 .flags = FLAGS_INIT_XGXS_FIRST,
11728 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11729 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11730 .mdio_ctrl = 0,
11731 .supported = (SUPPORTED_10000baseT_Full |
11732 SUPPORTED_1000baseT_Full |
11733 SUPPORTED_FIBRE |
11734 SUPPORTED_Pause |
11735 SUPPORTED_Asym_Pause),
11736 .media_type = ETH_PHY_SFPP_10G_FIBER,
11737 .ver_addr = 0,
11738 .req_flow_ctrl = 0,
11739 .req_line_speed = 0,
11740 .speed_cap_mask = 0,
11741 .req_duplex = 0,
11742 .rsrv = 0,
11743 .config_init = (config_init_t)bnx2x_8706_config_init,
11744 .read_status = (read_status_t)bnx2x_8706_read_status,
11745 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11746 .config_loopback = (config_loopback_t)NULL,
11747 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11748 .hw_reset = (hw_reset_t)NULL,
11749 .set_link_led = (set_link_led_t)NULL,
11750 .phy_specific_func = (phy_specific_func_t)NULL
11751 };
11752
11753 static const struct bnx2x_phy phy_8726 = {
11754 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11755 .addr = 0xff,
11756 .def_md_devad = 0,
11757 .flags = (FLAGS_INIT_XGXS_FIRST |
11758 FLAGS_TX_ERROR_CHECK),
11759 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11760 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11761 .mdio_ctrl = 0,
11762 .supported = (SUPPORTED_10000baseT_Full |
11763 SUPPORTED_1000baseT_Full |
11764 SUPPORTED_Autoneg |
11765 SUPPORTED_FIBRE |
11766 SUPPORTED_Pause |
11767 SUPPORTED_Asym_Pause),
11768 .media_type = ETH_PHY_NOT_PRESENT,
11769 .ver_addr = 0,
11770 .req_flow_ctrl = 0,
11771 .req_line_speed = 0,
11772 .speed_cap_mask = 0,
11773 .req_duplex = 0,
11774 .rsrv = 0,
11775 .config_init = (config_init_t)bnx2x_8726_config_init,
11776 .read_status = (read_status_t)bnx2x_8726_read_status,
11777 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
11778 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11779 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11780 .hw_reset = (hw_reset_t)NULL,
11781 .set_link_led = (set_link_led_t)NULL,
11782 .phy_specific_func = (phy_specific_func_t)NULL
11783 };
11784
11785 static const struct bnx2x_phy phy_8727 = {
11786 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11787 .addr = 0xff,
11788 .def_md_devad = 0,
11789 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11790 FLAGS_TX_ERROR_CHECK),
11791 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11792 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11793 .mdio_ctrl = 0,
11794 .supported = (SUPPORTED_10000baseT_Full |
11795 SUPPORTED_1000baseT_Full |
11796 SUPPORTED_FIBRE |
11797 SUPPORTED_Pause |
11798 SUPPORTED_Asym_Pause),
11799 .media_type = ETH_PHY_NOT_PRESENT,
11800 .ver_addr = 0,
11801 .req_flow_ctrl = 0,
11802 .req_line_speed = 0,
11803 .speed_cap_mask = 0,
11804 .req_duplex = 0,
11805 .rsrv = 0,
11806 .config_init = (config_init_t)bnx2x_8727_config_init,
11807 .read_status = (read_status_t)bnx2x_8727_read_status,
11808 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
11809 .config_loopback = (config_loopback_t)NULL,
11810 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11811 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
11812 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
11813 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11814 };
11815 static const struct bnx2x_phy phy_8481 = {
11816 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11817 .addr = 0xff,
11818 .def_md_devad = 0,
11819 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11820 FLAGS_REARM_LATCH_SIGNAL,
11821 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11822 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11823 .mdio_ctrl = 0,
11824 .supported = (SUPPORTED_10baseT_Half |
11825 SUPPORTED_10baseT_Full |
11826 SUPPORTED_100baseT_Half |
11827 SUPPORTED_100baseT_Full |
11828 SUPPORTED_1000baseT_Full |
11829 SUPPORTED_10000baseT_Full |
11830 SUPPORTED_TP |
11831 SUPPORTED_Autoneg |
11832 SUPPORTED_Pause |
11833 SUPPORTED_Asym_Pause),
11834 .media_type = ETH_PHY_BASE_T,
11835 .ver_addr = 0,
11836 .req_flow_ctrl = 0,
11837 .req_line_speed = 0,
11838 .speed_cap_mask = 0,
11839 .req_duplex = 0,
11840 .rsrv = 0,
11841 .config_init = (config_init_t)bnx2x_8481_config_init,
11842 .read_status = (read_status_t)bnx2x_848xx_read_status,
11843 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
11844 .config_loopback = (config_loopback_t)NULL,
11845 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11846 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
11847 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11848 .phy_specific_func = (phy_specific_func_t)NULL
11849 };
11850
11851 static const struct bnx2x_phy phy_84823 = {
11852 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11853 .addr = 0xff,
11854 .def_md_devad = 0,
11855 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11856 FLAGS_REARM_LATCH_SIGNAL |
11857 FLAGS_TX_ERROR_CHECK),
11858 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11859 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11860 .mdio_ctrl = 0,
11861 .supported = (SUPPORTED_10baseT_Half |
11862 SUPPORTED_10baseT_Full |
11863 SUPPORTED_100baseT_Half |
11864 SUPPORTED_100baseT_Full |
11865 SUPPORTED_1000baseT_Full |
11866 SUPPORTED_10000baseT_Full |
11867 SUPPORTED_TP |
11868 SUPPORTED_Autoneg |
11869 SUPPORTED_Pause |
11870 SUPPORTED_Asym_Pause),
11871 .media_type = ETH_PHY_BASE_T,
11872 .ver_addr = 0,
11873 .req_flow_ctrl = 0,
11874 .req_line_speed = 0,
11875 .speed_cap_mask = 0,
11876 .req_duplex = 0,
11877 .rsrv = 0,
11878 .config_init = (config_init_t)bnx2x_848x3_config_init,
11879 .read_status = (read_status_t)bnx2x_848xx_read_status,
11880 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11881 .config_loopback = (config_loopback_t)NULL,
11882 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11883 .hw_reset = (hw_reset_t)NULL,
11884 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11885 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11886 };
11887
11888 static const struct bnx2x_phy phy_84833 = {
11889 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11890 .addr = 0xff,
11891 .def_md_devad = 0,
11892 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11893 FLAGS_REARM_LATCH_SIGNAL |
11894 FLAGS_TX_ERROR_CHECK),
11895 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11896 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11897 .mdio_ctrl = 0,
11898 .supported = (SUPPORTED_100baseT_Half |
11899 SUPPORTED_100baseT_Full |
11900 SUPPORTED_1000baseT_Full |
11901 SUPPORTED_10000baseT_Full |
11902 SUPPORTED_TP |
11903 SUPPORTED_Autoneg |
11904 SUPPORTED_Pause |
11905 SUPPORTED_Asym_Pause),
11906 .media_type = ETH_PHY_BASE_T,
11907 .ver_addr = 0,
11908 .req_flow_ctrl = 0,
11909 .req_line_speed = 0,
11910 .speed_cap_mask = 0,
11911 .req_duplex = 0,
11912 .rsrv = 0,
11913 .config_init = (config_init_t)bnx2x_848x3_config_init,
11914 .read_status = (read_status_t)bnx2x_848xx_read_status,
11915 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11916 .config_loopback = (config_loopback_t)NULL,
11917 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11918 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11919 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11920 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11921 };
11922
11923 static const struct bnx2x_phy phy_84834 = {
11924 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
11925 .addr = 0xff,
11926 .def_md_devad = 0,
11927 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11928 FLAGS_REARM_LATCH_SIGNAL,
11929 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11930 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11931 .mdio_ctrl = 0,
11932 .supported = (SUPPORTED_100baseT_Half |
11933 SUPPORTED_100baseT_Full |
11934 SUPPORTED_1000baseT_Full |
11935 SUPPORTED_10000baseT_Full |
11936 SUPPORTED_TP |
11937 SUPPORTED_Autoneg |
11938 SUPPORTED_Pause |
11939 SUPPORTED_Asym_Pause),
11940 .media_type = ETH_PHY_BASE_T,
11941 .ver_addr = 0,
11942 .req_flow_ctrl = 0,
11943 .req_line_speed = 0,
11944 .speed_cap_mask = 0,
11945 .req_duplex = 0,
11946 .rsrv = 0,
11947 .config_init = (config_init_t)bnx2x_848x3_config_init,
11948 .read_status = (read_status_t)bnx2x_848xx_read_status,
11949 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11950 .config_loopback = (config_loopback_t)NULL,
11951 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11952 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11953 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11954 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11955 };
11956
11957 static const struct bnx2x_phy phy_84858 = {
11958 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858,
11959 .addr = 0xff,
11960 .def_md_devad = 0,
11961 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11962 FLAGS_REARM_LATCH_SIGNAL,
11963 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11964 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11965 .mdio_ctrl = 0,
11966 .supported = (SUPPORTED_100baseT_Half |
11967 SUPPORTED_100baseT_Full |
11968 SUPPORTED_1000baseT_Full |
11969 SUPPORTED_10000baseT_Full |
11970 SUPPORTED_TP |
11971 SUPPORTED_Autoneg |
11972 SUPPORTED_Pause |
11973 SUPPORTED_Asym_Pause),
11974 .media_type = ETH_PHY_BASE_T,
11975 .ver_addr = 0,
11976 .req_flow_ctrl = 0,
11977 .req_line_speed = 0,
11978 .speed_cap_mask = 0,
11979 .req_duplex = 0,
11980 .rsrv = 0,
11981 .config_init = (config_init_t)bnx2x_848x3_config_init,
11982 .read_status = (read_status_t)bnx2x_848xx_read_status,
11983 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11984 .config_loopback = (config_loopback_t)NULL,
11985 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11986 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11987 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11988 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11989 };
11990
11991 static const struct bnx2x_phy phy_54618se = {
11992 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11993 .addr = 0xff,
11994 .def_md_devad = 0,
11995 .flags = FLAGS_INIT_XGXS_FIRST,
11996 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11997 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11998 .mdio_ctrl = 0,
11999 .supported = (SUPPORTED_10baseT_Half |
12000 SUPPORTED_10baseT_Full |
12001 SUPPORTED_100baseT_Half |
12002 SUPPORTED_100baseT_Full |
12003 SUPPORTED_1000baseT_Full |
12004 SUPPORTED_TP |
12005 SUPPORTED_Autoneg |
12006 SUPPORTED_Pause |
12007 SUPPORTED_Asym_Pause),
12008 .media_type = ETH_PHY_BASE_T,
12009 .ver_addr = 0,
12010 .req_flow_ctrl = 0,
12011 .req_line_speed = 0,
12012 .speed_cap_mask = 0,
12013 /* req_duplex = */0,
12014 /* rsrv = */0,
12015 .config_init = (config_init_t)bnx2x_54618se_config_init,
12016 .read_status = (read_status_t)bnx2x_54618se_read_status,
12017 .link_reset = (link_reset_t)bnx2x_54618se_link_reset,
12018 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
12019 .format_fw_ver = (format_fw_ver_t)NULL,
12020 .hw_reset = (hw_reset_t)NULL,
12021 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led,
12022 .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
12023 };
12024 /*****************************************************************/
12025 /* */
12026 /* Populate the phy according. Main function: bnx2x_populate_phy */
12027 /* */
12028 /*****************************************************************/
12029
bnx2x_populate_preemphasis(struct bnx2x * bp,u32 shmem_base,struct bnx2x_phy * phy,u8 port,u8 phy_index)12030 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
12031 struct bnx2x_phy *phy, u8 port,
12032 u8 phy_index)
12033 {
12034 /* Get the 4 lanes xgxs config rx and tx */
12035 u32 rx = 0, tx = 0, i;
12036 for (i = 0; i < 2; i++) {
12037 /* INT_PHY and EXT_PHY1 share the same value location in
12038 * the shmem. When num_phys is greater than 1, than this value
12039 * applies only to EXT_PHY1
12040 */
12041 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
12042 rx = REG_RD(bp, shmem_base +
12043 offsetof(struct shmem_region,
12044 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
12045
12046 tx = REG_RD(bp, shmem_base +
12047 offsetof(struct shmem_region,
12048 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
12049 } else {
12050 rx = REG_RD(bp, shmem_base +
12051 offsetof(struct shmem_region,
12052 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12053
12054 tx = REG_RD(bp, shmem_base +
12055 offsetof(struct shmem_region,
12056 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12057 }
12058
12059 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
12060 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
12061
12062 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
12063 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
12064 }
12065 }
12066
bnx2x_get_ext_phy_config(struct bnx2x * bp,u32 shmem_base,u8 phy_index,u8 port)12067 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
12068 u8 phy_index, u8 port)
12069 {
12070 u32 ext_phy_config = 0;
12071 switch (phy_index) {
12072 case EXT_PHY1:
12073 ext_phy_config = REG_RD(bp, shmem_base +
12074 offsetof(struct shmem_region,
12075 dev_info.port_hw_config[port].external_phy_config));
12076 break;
12077 case EXT_PHY2:
12078 ext_phy_config = REG_RD(bp, shmem_base +
12079 offsetof(struct shmem_region,
12080 dev_info.port_hw_config[port].external_phy_config2));
12081 break;
12082 default:
12083 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
12084 return -EINVAL;
12085 }
12086
12087 return ext_phy_config;
12088 }
bnx2x_populate_int_phy(struct bnx2x * bp,u32 shmem_base,u8 port,struct bnx2x_phy * phy)12089 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
12090 struct bnx2x_phy *phy)
12091 {
12092 u32 phy_addr;
12093 u32 chip_id;
12094 u32 switch_cfg = (REG_RD(bp, shmem_base +
12095 offsetof(struct shmem_region,
12096 dev_info.port_feature_config[port].link_config)) &
12097 PORT_FEATURE_CONNECTED_SWITCH_MASK);
12098 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
12099 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
12100
12101 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
12102 if (USES_WARPCORE(bp)) {
12103 u32 serdes_net_if;
12104 phy_addr = REG_RD(bp,
12105 MISC_REG_WC0_CTRL_PHY_ADDR);
12106 *phy = phy_warpcore;
12107 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
12108 phy->flags |= FLAGS_4_PORT_MODE;
12109 else
12110 phy->flags &= ~FLAGS_4_PORT_MODE;
12111 /* Check Dual mode */
12112 serdes_net_if = (REG_RD(bp, shmem_base +
12113 offsetof(struct shmem_region, dev_info.
12114 port_hw_config[port].default_cfg)) &
12115 PORT_HW_CFG_NET_SERDES_IF_MASK);
12116 /* Set the appropriate supported and flags indications per
12117 * interface type of the chip
12118 */
12119 switch (serdes_net_if) {
12120 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
12121 phy->supported &= (SUPPORTED_10baseT_Half |
12122 SUPPORTED_10baseT_Full |
12123 SUPPORTED_100baseT_Half |
12124 SUPPORTED_100baseT_Full |
12125 SUPPORTED_1000baseT_Full |
12126 SUPPORTED_FIBRE |
12127 SUPPORTED_Autoneg |
12128 SUPPORTED_Pause |
12129 SUPPORTED_Asym_Pause);
12130 phy->media_type = ETH_PHY_BASE_T;
12131 break;
12132 case PORT_HW_CFG_NET_SERDES_IF_XFI:
12133 phy->supported &= (SUPPORTED_1000baseT_Full |
12134 SUPPORTED_10000baseT_Full |
12135 SUPPORTED_FIBRE |
12136 SUPPORTED_Pause |
12137 SUPPORTED_Asym_Pause);
12138 phy->media_type = ETH_PHY_XFP_FIBER;
12139 break;
12140 case PORT_HW_CFG_NET_SERDES_IF_SFI:
12141 phy->supported &= (SUPPORTED_1000baseT_Full |
12142 SUPPORTED_10000baseT_Full |
12143 SUPPORTED_FIBRE |
12144 SUPPORTED_Pause |
12145 SUPPORTED_Asym_Pause);
12146 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
12147 break;
12148 case PORT_HW_CFG_NET_SERDES_IF_KR:
12149 phy->media_type = ETH_PHY_KR;
12150 phy->supported &= (SUPPORTED_1000baseKX_Full |
12151 SUPPORTED_10000baseKR_Full |
12152 SUPPORTED_FIBRE |
12153 SUPPORTED_Autoneg |
12154 SUPPORTED_Pause |
12155 SUPPORTED_Asym_Pause);
12156 break;
12157 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
12158 phy->media_type = ETH_PHY_KR;
12159 phy->flags |= FLAGS_WC_DUAL_MODE;
12160 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
12161 SUPPORTED_FIBRE |
12162 SUPPORTED_Pause |
12163 SUPPORTED_Asym_Pause);
12164 break;
12165 case PORT_HW_CFG_NET_SERDES_IF_KR2:
12166 phy->media_type = ETH_PHY_KR;
12167 phy->flags |= FLAGS_WC_DUAL_MODE;
12168 phy->supported &= (SUPPORTED_20000baseKR2_Full |
12169 SUPPORTED_10000baseKR_Full |
12170 SUPPORTED_1000baseKX_Full |
12171 SUPPORTED_Autoneg |
12172 SUPPORTED_FIBRE |
12173 SUPPORTED_Pause |
12174 SUPPORTED_Asym_Pause);
12175 phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12176 break;
12177 default:
12178 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
12179 serdes_net_if);
12180 break;
12181 }
12182
12183 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
12184 * was not set as expected. For B0, ECO will be enabled so there
12185 * won't be an issue there
12186 */
12187 if (CHIP_REV(bp) == CHIP_REV_Ax)
12188 phy->flags |= FLAGS_MDC_MDIO_WA;
12189 else
12190 phy->flags |= FLAGS_MDC_MDIO_WA_B0;
12191 } else {
12192 switch (switch_cfg) {
12193 case SWITCH_CFG_1G:
12194 phy_addr = REG_RD(bp,
12195 NIG_REG_SERDES0_CTRL_PHY_ADDR +
12196 port * 0x10);
12197 *phy = phy_serdes;
12198 break;
12199 case SWITCH_CFG_10G:
12200 phy_addr = REG_RD(bp,
12201 NIG_REG_XGXS0_CTRL_PHY_ADDR +
12202 port * 0x18);
12203 *phy = phy_xgxs;
12204 break;
12205 default:
12206 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
12207 return -EINVAL;
12208 }
12209 }
12210 phy->addr = (u8)phy_addr;
12211 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
12212 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
12213 port);
12214 if (CHIP_IS_E2(bp))
12215 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
12216 else
12217 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
12218
12219 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
12220 port, phy->addr, phy->mdio_ctrl);
12221
12222 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
12223 return 0;
12224 }
12225
bnx2x_populate_ext_phy(struct bnx2x * bp,u8 phy_index,u32 shmem_base,u32 shmem2_base,u8 port,struct bnx2x_phy * phy)12226 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
12227 u8 phy_index,
12228 u32 shmem_base,
12229 u32 shmem2_base,
12230 u8 port,
12231 struct bnx2x_phy *phy)
12232 {
12233 u32 ext_phy_config, phy_type, config2;
12234 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
12235 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
12236 phy_index, port);
12237 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12238 /* Select the phy type */
12239 switch (phy_type) {
12240 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12241 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
12242 *phy = phy_8073;
12243 break;
12244 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
12245 *phy = phy_8705;
12246 break;
12247 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
12248 *phy = phy_8706;
12249 break;
12250 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12251 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12252 *phy = phy_8726;
12253 break;
12254 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12255 /* BCM8727_NOC => BCM8727 no over current */
12256 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12257 *phy = phy_8727;
12258 phy->flags |= FLAGS_NOC;
12259 break;
12260 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12261 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12262 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12263 *phy = phy_8727;
12264 break;
12265 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12266 *phy = phy_8481;
12267 break;
12268 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12269 *phy = phy_84823;
12270 break;
12271 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12272 *phy = phy_84833;
12273 break;
12274 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12275 *phy = phy_84834;
12276 break;
12277 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
12278 *phy = phy_84858;
12279 break;
12280 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12281 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12282 *phy = phy_54618se;
12283 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12284 phy->flags |= FLAGS_EEE;
12285 break;
12286 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12287 *phy = phy_7101;
12288 break;
12289 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12290 *phy = phy_null;
12291 return -EINVAL;
12292 default:
12293 *phy = phy_null;
12294 /* In case external PHY wasn't found */
12295 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12296 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12297 return -EINVAL;
12298 return 0;
12299 }
12300
12301 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12302 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12303
12304 /* The shmem address of the phy version is located on different
12305 * structures. In case this structure is too old, do not set
12306 * the address
12307 */
12308 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12309 dev_info.shared_hw_config.config2));
12310 if (phy_index == EXT_PHY1) {
12311 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12312 port_mb[port].ext_phy_fw_version);
12313
12314 /* Check specific mdc mdio settings */
12315 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12316 mdc_mdio_access = config2 &
12317 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12318 } else {
12319 u32 size = REG_RD(bp, shmem2_base);
12320
12321 if (size >
12322 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12323 phy->ver_addr = shmem2_base +
12324 offsetof(struct shmem2_region,
12325 ext_phy_fw_version2[port]);
12326 }
12327 /* Check specific mdc mdio settings */
12328 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12329 mdc_mdio_access = (config2 &
12330 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12331 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12332 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12333 }
12334 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12335
12336 if (bnx2x_is_8483x_8485x(phy) && (phy->ver_addr)) {
12337 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12338 * version lower than or equal to 1.39
12339 */
12340 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12341 if (((raw_ver & 0x7F) <= 39) &&
12342 (((raw_ver & 0xF80) >> 7) <= 1))
12343 phy->supported &= ~(SUPPORTED_100baseT_Half |
12344 SUPPORTED_100baseT_Full);
12345 }
12346
12347 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12348 phy_type, port, phy_index);
12349 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
12350 phy->addr, phy->mdio_ctrl);
12351 return 0;
12352 }
12353
bnx2x_populate_phy(struct bnx2x * bp,u8 phy_index,u32 shmem_base,u32 shmem2_base,u8 port,struct bnx2x_phy * phy)12354 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12355 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12356 {
12357 int status = 0;
12358 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12359 if (phy_index == INT_PHY)
12360 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12361 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12362 port, phy);
12363 return status;
12364 }
12365
bnx2x_phy_def_cfg(struct link_params * params,struct bnx2x_phy * phy,u8 phy_index)12366 static void bnx2x_phy_def_cfg(struct link_params *params,
12367 struct bnx2x_phy *phy,
12368 u8 phy_index)
12369 {
12370 struct bnx2x *bp = params->bp;
12371 u32 link_config;
12372 /* Populate the default phy configuration for MF mode */
12373 if (phy_index == EXT_PHY2) {
12374 link_config = REG_RD(bp, params->shmem_base +
12375 offsetof(struct shmem_region, dev_info.
12376 port_feature_config[params->port].link_config2));
12377 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12378 offsetof(struct shmem_region,
12379 dev_info.
12380 port_hw_config[params->port].speed_capability_mask2));
12381 } else {
12382 link_config = REG_RD(bp, params->shmem_base +
12383 offsetof(struct shmem_region, dev_info.
12384 port_feature_config[params->port].link_config));
12385 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12386 offsetof(struct shmem_region,
12387 dev_info.
12388 port_hw_config[params->port].speed_capability_mask));
12389 }
12390 DP(NETIF_MSG_LINK,
12391 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12392 phy_index, link_config, phy->speed_cap_mask);
12393
12394 phy->req_duplex = DUPLEX_FULL;
12395 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
12396 case PORT_FEATURE_LINK_SPEED_10M_HALF:
12397 phy->req_duplex = DUPLEX_HALF;
12398 case PORT_FEATURE_LINK_SPEED_10M_FULL:
12399 phy->req_line_speed = SPEED_10;
12400 break;
12401 case PORT_FEATURE_LINK_SPEED_100M_HALF:
12402 phy->req_duplex = DUPLEX_HALF;
12403 case PORT_FEATURE_LINK_SPEED_100M_FULL:
12404 phy->req_line_speed = SPEED_100;
12405 break;
12406 case PORT_FEATURE_LINK_SPEED_1G:
12407 phy->req_line_speed = SPEED_1000;
12408 break;
12409 case PORT_FEATURE_LINK_SPEED_2_5G:
12410 phy->req_line_speed = SPEED_2500;
12411 break;
12412 case PORT_FEATURE_LINK_SPEED_10G_CX4:
12413 phy->req_line_speed = SPEED_10000;
12414 break;
12415 default:
12416 phy->req_line_speed = SPEED_AUTO_NEG;
12417 break;
12418 }
12419
12420 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
12421 case PORT_FEATURE_FLOW_CONTROL_AUTO:
12422 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12423 break;
12424 case PORT_FEATURE_FLOW_CONTROL_TX:
12425 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12426 break;
12427 case PORT_FEATURE_FLOW_CONTROL_RX:
12428 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12429 break;
12430 case PORT_FEATURE_FLOW_CONTROL_BOTH:
12431 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12432 break;
12433 default:
12434 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12435 break;
12436 }
12437 }
12438
bnx2x_phy_selection(struct link_params * params)12439 u32 bnx2x_phy_selection(struct link_params *params)
12440 {
12441 u32 phy_config_swapped, prio_cfg;
12442 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12443
12444 phy_config_swapped = params->multi_phy_config &
12445 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12446
12447 prio_cfg = params->multi_phy_config &
12448 PORT_HW_CFG_PHY_SELECTION_MASK;
12449
12450 if (phy_config_swapped) {
12451 switch (prio_cfg) {
12452 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12453 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12454 break;
12455 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12456 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12457 break;
12458 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12459 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12460 break;
12461 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12462 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12463 break;
12464 }
12465 } else
12466 return_cfg = prio_cfg;
12467
12468 return return_cfg;
12469 }
12470
bnx2x_phy_probe(struct link_params * params)12471 int bnx2x_phy_probe(struct link_params *params)
12472 {
12473 u8 phy_index, actual_phy_idx;
12474 u32 phy_config_swapped, sync_offset, media_types;
12475 struct bnx2x *bp = params->bp;
12476 struct bnx2x_phy *phy;
12477 params->num_phys = 0;
12478 DP(NETIF_MSG_LINK, "Begin phy probe\n");
12479 phy_config_swapped = params->multi_phy_config &
12480 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12481
12482 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12483 phy_index++) {
12484 actual_phy_idx = phy_index;
12485 if (phy_config_swapped) {
12486 if (phy_index == EXT_PHY1)
12487 actual_phy_idx = EXT_PHY2;
12488 else if (phy_index == EXT_PHY2)
12489 actual_phy_idx = EXT_PHY1;
12490 }
12491 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12492 " actual_phy_idx %x\n", phy_config_swapped,
12493 phy_index, actual_phy_idx);
12494 phy = ¶ms->phy[actual_phy_idx];
12495 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12496 params->shmem2_base, params->port,
12497 phy) != 0) {
12498 params->num_phys = 0;
12499 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12500 phy_index);
12501 for (phy_index = INT_PHY;
12502 phy_index < MAX_PHYS;
12503 phy_index++)
12504 *phy = phy_null;
12505 return -EINVAL;
12506 }
12507 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12508 break;
12509
12510 if (params->feature_config_flags &
12511 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12512 phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12513
12514 if (!(params->feature_config_flags &
12515 FEATURE_CONFIG_MT_SUPPORT))
12516 phy->flags |= FLAGS_MDC_MDIO_WA_G;
12517
12518 sync_offset = params->shmem_base +
12519 offsetof(struct shmem_region,
12520 dev_info.port_hw_config[params->port].media_type);
12521 media_types = REG_RD(bp, sync_offset);
12522
12523 /* Update media type for non-PMF sync only for the first time
12524 * In case the media type changes afterwards, it will be updated
12525 * using the update_status function
12526 */
12527 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12528 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12529 actual_phy_idx))) == 0) {
12530 media_types |= ((phy->media_type &
12531 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12532 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12533 actual_phy_idx));
12534 }
12535 REG_WR(bp, sync_offset, media_types);
12536
12537 bnx2x_phy_def_cfg(params, phy, phy_index);
12538 params->num_phys++;
12539 }
12540
12541 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12542 return 0;
12543 }
12544
bnx2x_init_bmac_loopback(struct link_params * params,struct link_vars * vars)12545 static void bnx2x_init_bmac_loopback(struct link_params *params,
12546 struct link_vars *vars)
12547 {
12548 struct bnx2x *bp = params->bp;
12549 vars->link_up = 1;
12550 vars->line_speed = SPEED_10000;
12551 vars->duplex = DUPLEX_FULL;
12552 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12553 vars->mac_type = MAC_TYPE_BMAC;
12554
12555 vars->phy_flags = PHY_XGXS_FLAG;
12556
12557 bnx2x_xgxs_deassert(params);
12558
12559 /* Set bmac loopback */
12560 bnx2x_bmac_enable(params, vars, 1, 1);
12561
12562 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12563 }
12564
bnx2x_init_emac_loopback(struct link_params * params,struct link_vars * vars)12565 static void bnx2x_init_emac_loopback(struct link_params *params,
12566 struct link_vars *vars)
12567 {
12568 struct bnx2x *bp = params->bp;
12569 vars->link_up = 1;
12570 vars->line_speed = SPEED_1000;
12571 vars->duplex = DUPLEX_FULL;
12572 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12573 vars->mac_type = MAC_TYPE_EMAC;
12574
12575 vars->phy_flags = PHY_XGXS_FLAG;
12576
12577 bnx2x_xgxs_deassert(params);
12578 /* Set bmac loopback */
12579 bnx2x_emac_enable(params, vars, 1);
12580 bnx2x_emac_program(params, vars);
12581 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12582 }
12583
bnx2x_init_xmac_loopback(struct link_params * params,struct link_vars * vars)12584 static void bnx2x_init_xmac_loopback(struct link_params *params,
12585 struct link_vars *vars)
12586 {
12587 struct bnx2x *bp = params->bp;
12588 vars->link_up = 1;
12589 if (!params->req_line_speed[0])
12590 vars->line_speed = SPEED_10000;
12591 else
12592 vars->line_speed = params->req_line_speed[0];
12593 vars->duplex = DUPLEX_FULL;
12594 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12595 vars->mac_type = MAC_TYPE_XMAC;
12596 vars->phy_flags = PHY_XGXS_FLAG;
12597 /* Set WC to loopback mode since link is required to provide clock
12598 * to the XMAC in 20G mode
12599 */
12600 bnx2x_set_aer_mmd(params, ¶ms->phy[0]);
12601 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0);
12602 params->phy[INT_PHY].config_loopback(
12603 ¶ms->phy[INT_PHY],
12604 params);
12605
12606 bnx2x_xmac_enable(params, vars, 1);
12607 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12608 }
12609
bnx2x_init_umac_loopback(struct link_params * params,struct link_vars * vars)12610 static void bnx2x_init_umac_loopback(struct link_params *params,
12611 struct link_vars *vars)
12612 {
12613 struct bnx2x *bp = params->bp;
12614 vars->link_up = 1;
12615 vars->line_speed = SPEED_1000;
12616 vars->duplex = DUPLEX_FULL;
12617 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12618 vars->mac_type = MAC_TYPE_UMAC;
12619 vars->phy_flags = PHY_XGXS_FLAG;
12620 bnx2x_umac_enable(params, vars, 1);
12621
12622 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12623 }
12624
bnx2x_init_xgxs_loopback(struct link_params * params,struct link_vars * vars)12625 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12626 struct link_vars *vars)
12627 {
12628 struct bnx2x *bp = params->bp;
12629 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
12630 vars->link_up = 1;
12631 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12632 vars->duplex = DUPLEX_FULL;
12633 if (params->req_line_speed[0] == SPEED_1000)
12634 vars->line_speed = SPEED_1000;
12635 else if ((params->req_line_speed[0] == SPEED_20000) ||
12636 (int_phy->flags & FLAGS_WC_DUAL_MODE))
12637 vars->line_speed = SPEED_20000;
12638 else
12639 vars->line_speed = SPEED_10000;
12640
12641 if (!USES_WARPCORE(bp))
12642 bnx2x_xgxs_deassert(params);
12643 bnx2x_link_initialize(params, vars);
12644
12645 if (params->req_line_speed[0] == SPEED_1000) {
12646 if (USES_WARPCORE(bp))
12647 bnx2x_umac_enable(params, vars, 0);
12648 else {
12649 bnx2x_emac_program(params, vars);
12650 bnx2x_emac_enable(params, vars, 0);
12651 }
12652 } else {
12653 if (USES_WARPCORE(bp))
12654 bnx2x_xmac_enable(params, vars, 0);
12655 else
12656 bnx2x_bmac_enable(params, vars, 0, 1);
12657 }
12658
12659 if (params->loopback_mode == LOOPBACK_XGXS) {
12660 /* Set 10G XGXS loopback */
12661 int_phy->config_loopback(int_phy, params);
12662 } else {
12663 /* Set external phy loopback */
12664 u8 phy_index;
12665 for (phy_index = EXT_PHY1;
12666 phy_index < params->num_phys; phy_index++)
12667 if (params->phy[phy_index].config_loopback)
12668 params->phy[phy_index].config_loopback(
12669 ¶ms->phy[phy_index],
12670 params);
12671 }
12672 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12673
12674 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12675 }
12676
bnx2x_set_rx_filter(struct link_params * params,u8 en)12677 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12678 {
12679 struct bnx2x *bp = params->bp;
12680 u8 val = en * 0x1F;
12681
12682 /* Open / close the gate between the NIG and the BRB */
12683 if (!CHIP_IS_E1x(bp))
12684 val |= en * 0x20;
12685 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12686
12687 if (!CHIP_IS_E1(bp)) {
12688 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12689 en*0x3);
12690 }
12691
12692 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12693 NIG_REG_LLH0_BRB1_NOT_MCP), en);
12694 }
bnx2x_avoid_link_flap(struct link_params * params,struct link_vars * vars)12695 static int bnx2x_avoid_link_flap(struct link_params *params,
12696 struct link_vars *vars)
12697 {
12698 u32 phy_idx;
12699 u32 dont_clear_stat, lfa_sts;
12700 struct bnx2x *bp = params->bp;
12701
12702 bnx2x_set_mdio_emac_per_phy(bp, params);
12703 /* Sync the link parameters */
12704 bnx2x_link_status_update(params, vars);
12705
12706 /*
12707 * The module verification was already done by previous link owner,
12708 * so this call is meant only to get warning message
12709 */
12710
12711 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12712 struct bnx2x_phy *phy = ¶ms->phy[phy_idx];
12713 if (phy->phy_specific_func) {
12714 DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12715 phy->phy_specific_func(phy, params, PHY_INIT);
12716 }
12717 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12718 (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12719 (phy->media_type == ETH_PHY_DA_TWINAX))
12720 bnx2x_verify_sfp_module(phy, params);
12721 }
12722 lfa_sts = REG_RD(bp, params->lfa_base +
12723 offsetof(struct shmem_lfa,
12724 lfa_sts));
12725
12726 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12727
12728 /* Re-enable the NIG/MAC */
12729 if (CHIP_IS_E3(bp)) {
12730 if (!dont_clear_stat) {
12731 REG_WR(bp, GRCBASE_MISC +
12732 MISC_REGISTERS_RESET_REG_2_CLEAR,
12733 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12734 params->port));
12735 REG_WR(bp, GRCBASE_MISC +
12736 MISC_REGISTERS_RESET_REG_2_SET,
12737 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12738 params->port));
12739 }
12740 if (vars->line_speed < SPEED_10000)
12741 bnx2x_umac_enable(params, vars, 0);
12742 else
12743 bnx2x_xmac_enable(params, vars, 0);
12744 } else {
12745 if (vars->line_speed < SPEED_10000)
12746 bnx2x_emac_enable(params, vars, 0);
12747 else
12748 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12749 }
12750
12751 /* Increment LFA count */
12752 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12753 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12754 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12755 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12756 /* Clear link flap reason */
12757 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12758
12759 REG_WR(bp, params->lfa_base +
12760 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12761
12762 /* Disable NIG DRAIN */
12763 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12764
12765 /* Enable interrupts */
12766 bnx2x_link_int_enable(params);
12767 return 0;
12768 }
12769
bnx2x_cannot_avoid_link_flap(struct link_params * params,struct link_vars * vars,int lfa_status)12770 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12771 struct link_vars *vars,
12772 int lfa_status)
12773 {
12774 u32 lfa_sts, cfg_idx, tmp_val;
12775 struct bnx2x *bp = params->bp;
12776
12777 bnx2x_link_reset(params, vars, 1);
12778
12779 if (!params->lfa_base)
12780 return;
12781 /* Store the new link parameters */
12782 REG_WR(bp, params->lfa_base +
12783 offsetof(struct shmem_lfa, req_duplex),
12784 params->req_duplex[0] | (params->req_duplex[1] << 16));
12785
12786 REG_WR(bp, params->lfa_base +
12787 offsetof(struct shmem_lfa, req_flow_ctrl),
12788 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12789
12790 REG_WR(bp, params->lfa_base +
12791 offsetof(struct shmem_lfa, req_line_speed),
12792 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12793
12794 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12795 REG_WR(bp, params->lfa_base +
12796 offsetof(struct shmem_lfa,
12797 speed_cap_mask[cfg_idx]),
12798 params->speed_cap_mask[cfg_idx]);
12799 }
12800
12801 tmp_val = REG_RD(bp, params->lfa_base +
12802 offsetof(struct shmem_lfa, additional_config));
12803 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12804 tmp_val |= params->req_fc_auto_adv;
12805
12806 REG_WR(bp, params->lfa_base +
12807 offsetof(struct shmem_lfa, additional_config), tmp_val);
12808
12809 lfa_sts = REG_RD(bp, params->lfa_base +
12810 offsetof(struct shmem_lfa, lfa_sts));
12811
12812 /* Clear the "Don't Clear Statistics" bit, and set reason */
12813 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12814
12815 /* Set link flap reason */
12816 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12817 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12818 LFA_LINK_FLAP_REASON_OFFSET);
12819
12820 /* Increment link flap counter */
12821 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12822 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12823 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12824 << LINK_FLAP_COUNT_OFFSET));
12825 REG_WR(bp, params->lfa_base +
12826 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12827 /* Proceed with regular link initialization */
12828 }
12829
bnx2x_phy_init(struct link_params * params,struct link_vars * vars)12830 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12831 {
12832 int lfa_status;
12833 struct bnx2x *bp = params->bp;
12834 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12835 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12836 params->req_line_speed[0], params->req_flow_ctrl[0]);
12837 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12838 params->req_line_speed[1], params->req_flow_ctrl[1]);
12839 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
12840 vars->link_status = 0;
12841 vars->phy_link_up = 0;
12842 vars->link_up = 0;
12843 vars->line_speed = 0;
12844 vars->duplex = DUPLEX_FULL;
12845 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12846 vars->mac_type = MAC_TYPE_NONE;
12847 vars->phy_flags = 0;
12848 vars->check_kr2_recovery_cnt = 0;
12849 params->link_flags = PHY_INITIALIZED;
12850 /* Driver opens NIG-BRB filters */
12851 bnx2x_set_rx_filter(params, 1);
12852 bnx2x_chng_link_count(params, true);
12853 /* Check if link flap can be avoided */
12854 lfa_status = bnx2x_check_lfa(params);
12855
12856 if (lfa_status == 0) {
12857 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12858 return bnx2x_avoid_link_flap(params, vars);
12859 }
12860
12861 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12862 lfa_status);
12863 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12864
12865 /* Disable attentions */
12866 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12867 (NIG_MASK_XGXS0_LINK_STATUS |
12868 NIG_MASK_XGXS0_LINK10G |
12869 NIG_MASK_SERDES0_LINK_STATUS |
12870 NIG_MASK_MI_INT));
12871
12872 bnx2x_emac_init(params, vars);
12873
12874 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12875 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12876
12877 if (params->num_phys == 0) {
12878 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12879 return -EINVAL;
12880 }
12881 set_phy_vars(params, vars);
12882
12883 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12884 switch (params->loopback_mode) {
12885 case LOOPBACK_BMAC:
12886 bnx2x_init_bmac_loopback(params, vars);
12887 break;
12888 case LOOPBACK_EMAC:
12889 bnx2x_init_emac_loopback(params, vars);
12890 break;
12891 case LOOPBACK_XMAC:
12892 bnx2x_init_xmac_loopback(params, vars);
12893 break;
12894 case LOOPBACK_UMAC:
12895 bnx2x_init_umac_loopback(params, vars);
12896 break;
12897 case LOOPBACK_XGXS:
12898 case LOOPBACK_EXT_PHY:
12899 bnx2x_init_xgxs_loopback(params, vars);
12900 break;
12901 default:
12902 if (!CHIP_IS_E3(bp)) {
12903 if (params->switch_cfg == SWITCH_CFG_10G)
12904 bnx2x_xgxs_deassert(params);
12905 else
12906 bnx2x_serdes_deassert(bp, params->port);
12907 }
12908 bnx2x_link_initialize(params, vars);
12909 msleep(30);
12910 bnx2x_link_int_enable(params);
12911 break;
12912 }
12913 bnx2x_update_mng(params, vars->link_status);
12914
12915 bnx2x_update_mng_eee(params, vars->eee_status);
12916 return 0;
12917 }
12918
bnx2x_link_reset(struct link_params * params,struct link_vars * vars,u8 reset_ext_phy)12919 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12920 u8 reset_ext_phy)
12921 {
12922 struct bnx2x *bp = params->bp;
12923 u8 phy_index, port = params->port, clear_latch_ind = 0;
12924 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12925 /* Disable attentions */
12926 vars->link_status = 0;
12927 bnx2x_chng_link_count(params, true);
12928 bnx2x_update_mng(params, vars->link_status);
12929 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12930 SHMEM_EEE_ACTIVE_BIT);
12931 bnx2x_update_mng_eee(params, vars->eee_status);
12932 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12933 (NIG_MASK_XGXS0_LINK_STATUS |
12934 NIG_MASK_XGXS0_LINK10G |
12935 NIG_MASK_SERDES0_LINK_STATUS |
12936 NIG_MASK_MI_INT));
12937
12938 /* Activate nig drain */
12939 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12940
12941 /* Disable nig egress interface */
12942 if (!CHIP_IS_E3(bp)) {
12943 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12944 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12945 }
12946
12947 if (!CHIP_IS_E3(bp)) {
12948 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
12949 } else {
12950 bnx2x_set_xmac_rxtx(params, 0);
12951 bnx2x_set_umac_rxtx(params, 0);
12952 }
12953 /* Disable emac */
12954 if (!CHIP_IS_E3(bp))
12955 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12956
12957 usleep_range(10000, 20000);
12958 /* The PHY reset is controlled by GPIO 1
12959 * Hold it as vars low
12960 */
12961 /* Clear link led */
12962 bnx2x_set_mdio_emac_per_phy(bp, params);
12963 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12964
12965 if (reset_ext_phy) {
12966 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12967 phy_index++) {
12968 if (params->phy[phy_index].link_reset) {
12969 bnx2x_set_aer_mmd(params,
12970 ¶ms->phy[phy_index]);
12971 params->phy[phy_index].link_reset(
12972 ¶ms->phy[phy_index],
12973 params);
12974 }
12975 if (params->phy[phy_index].flags &
12976 FLAGS_REARM_LATCH_SIGNAL)
12977 clear_latch_ind = 1;
12978 }
12979 }
12980
12981 if (clear_latch_ind) {
12982 /* Clear latching indication */
12983 bnx2x_rearm_latch_signal(bp, port, 0);
12984 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12985 1 << NIG_LATCH_BC_ENABLE_MI_INT);
12986 }
12987 if (params->phy[INT_PHY].link_reset)
12988 params->phy[INT_PHY].link_reset(
12989 ¶ms->phy[INT_PHY], params);
12990
12991 /* Disable nig ingress interface */
12992 if (!CHIP_IS_E3(bp)) {
12993 /* Reset BigMac */
12994 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12995 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12996 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12997 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12998 } else {
12999 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13000 bnx2x_set_xumac_nig(params, 0, 0);
13001 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13002 MISC_REGISTERS_RESET_REG_2_XMAC)
13003 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
13004 XMAC_CTRL_REG_SOFT_RESET);
13005 }
13006 vars->link_up = 0;
13007 vars->phy_flags = 0;
13008 return 0;
13009 }
bnx2x_lfa_reset(struct link_params * params,struct link_vars * vars)13010 int bnx2x_lfa_reset(struct link_params *params,
13011 struct link_vars *vars)
13012 {
13013 struct bnx2x *bp = params->bp;
13014 vars->link_up = 0;
13015 vars->phy_flags = 0;
13016 params->link_flags &= ~PHY_INITIALIZED;
13017 if (!params->lfa_base)
13018 return bnx2x_link_reset(params, vars, 1);
13019 /*
13020 * Activate NIG drain so that during this time the device won't send
13021 * anything while it is unable to response.
13022 */
13023 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13024
13025 /*
13026 * Close gracefully the gate from BMAC to NIG such that no half packets
13027 * are passed.
13028 */
13029 if (!CHIP_IS_E3(bp))
13030 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
13031
13032 if (CHIP_IS_E3(bp)) {
13033 bnx2x_set_xmac_rxtx(params, 0);
13034 bnx2x_set_umac_rxtx(params, 0);
13035 }
13036 /* Wait 10ms for the pipe to clean up*/
13037 usleep_range(10000, 20000);
13038
13039 /* Clean the NIG-BRB using the network filters in a way that will
13040 * not cut a packet in the middle.
13041 */
13042 bnx2x_set_rx_filter(params, 0);
13043
13044 /*
13045 * Re-open the gate between the BMAC and the NIG, after verifying the
13046 * gate to the BRB is closed, otherwise packets may arrive to the
13047 * firmware before driver had initialized it. The target is to achieve
13048 * minimum management protocol down time.
13049 */
13050 if (!CHIP_IS_E3(bp))
13051 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
13052
13053 if (CHIP_IS_E3(bp)) {
13054 bnx2x_set_xmac_rxtx(params, 1);
13055 bnx2x_set_umac_rxtx(params, 1);
13056 }
13057 /* Disable NIG drain */
13058 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13059 return 0;
13060 }
13061
13062 /****************************************************************************/
13063 /* Common function */
13064 /****************************************************************************/
bnx2x_8073_common_init_phy(struct bnx2x * bp,u32 shmem_base_path[],u32 shmem2_base_path[],u8 phy_index,u32 chip_id)13065 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
13066 u32 shmem_base_path[],
13067 u32 shmem2_base_path[], u8 phy_index,
13068 u32 chip_id)
13069 {
13070 struct bnx2x_phy phy[PORT_MAX];
13071 struct bnx2x_phy *phy_blk[PORT_MAX];
13072 u16 val;
13073 s8 port = 0;
13074 s8 port_of_path = 0;
13075 u32 swap_val, swap_override;
13076 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13077 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13078 port ^= (swap_val && swap_override);
13079 bnx2x_ext_phy_hw_reset(bp, port);
13080 /* PART1 - Reset both phys */
13081 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13082 u32 shmem_base, shmem2_base;
13083 /* In E2, same phy is using for port0 of the two paths */
13084 if (CHIP_IS_E1x(bp)) {
13085 shmem_base = shmem_base_path[0];
13086 shmem2_base = shmem2_base_path[0];
13087 port_of_path = port;
13088 } else {
13089 shmem_base = shmem_base_path[port];
13090 shmem2_base = shmem2_base_path[port];
13091 port_of_path = 0;
13092 }
13093
13094 /* Extract the ext phy address for the port */
13095 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13096 port_of_path, &phy[port]) !=
13097 0) {
13098 DP(NETIF_MSG_LINK, "populate_phy failed\n");
13099 return -EINVAL;
13100 }
13101 /* Disable attentions */
13102 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13103 port_of_path*4,
13104 (NIG_MASK_XGXS0_LINK_STATUS |
13105 NIG_MASK_XGXS0_LINK10G |
13106 NIG_MASK_SERDES0_LINK_STATUS |
13107 NIG_MASK_MI_INT));
13108
13109 /* Need to take the phy out of low power mode in order
13110 * to write to access its registers
13111 */
13112 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
13113 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13114 port);
13115
13116 /* Reset the phy */
13117 bnx2x_cl45_write(bp, &phy[port],
13118 MDIO_PMA_DEVAD,
13119 MDIO_PMA_REG_CTRL,
13120 1<<15);
13121 }
13122
13123 /* Add delay of 150ms after reset */
13124 msleep(150);
13125
13126 if (phy[PORT_0].addr & 0x1) {
13127 phy_blk[PORT_0] = &(phy[PORT_1]);
13128 phy_blk[PORT_1] = &(phy[PORT_0]);
13129 } else {
13130 phy_blk[PORT_0] = &(phy[PORT_0]);
13131 phy_blk[PORT_1] = &(phy[PORT_1]);
13132 }
13133
13134 /* PART2 - Download firmware to both phys */
13135 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13136 if (CHIP_IS_E1x(bp))
13137 port_of_path = port;
13138 else
13139 port_of_path = 0;
13140
13141 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13142 phy_blk[port]->addr);
13143 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13144 port_of_path))
13145 return -EINVAL;
13146
13147 /* Only set bit 10 = 1 (Tx power down) */
13148 bnx2x_cl45_read(bp, phy_blk[port],
13149 MDIO_PMA_DEVAD,
13150 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13151
13152 /* Phase1 of TX_POWER_DOWN reset */
13153 bnx2x_cl45_write(bp, phy_blk[port],
13154 MDIO_PMA_DEVAD,
13155 MDIO_PMA_REG_TX_POWER_DOWN,
13156 (val | 1<<10));
13157 }
13158
13159 /* Toggle Transmitter: Power down and then up with 600ms delay
13160 * between
13161 */
13162 msleep(600);
13163
13164 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
13165 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13166 /* Phase2 of POWER_DOWN_RESET */
13167 /* Release bit 10 (Release Tx power down) */
13168 bnx2x_cl45_read(bp, phy_blk[port],
13169 MDIO_PMA_DEVAD,
13170 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13171
13172 bnx2x_cl45_write(bp, phy_blk[port],
13173 MDIO_PMA_DEVAD,
13174 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
13175 usleep_range(15000, 30000);
13176
13177 /* Read modify write the SPI-ROM version select register */
13178 bnx2x_cl45_read(bp, phy_blk[port],
13179 MDIO_PMA_DEVAD,
13180 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
13181 bnx2x_cl45_write(bp, phy_blk[port],
13182 MDIO_PMA_DEVAD,
13183 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
13184
13185 /* set GPIO2 back to LOW */
13186 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
13187 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
13188 }
13189 return 0;
13190 }
bnx2x_8726_common_init_phy(struct bnx2x * bp,u32 shmem_base_path[],u32 shmem2_base_path[],u8 phy_index,u32 chip_id)13191 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
13192 u32 shmem_base_path[],
13193 u32 shmem2_base_path[], u8 phy_index,
13194 u32 chip_id)
13195 {
13196 u32 val;
13197 s8 port;
13198 struct bnx2x_phy phy;
13199 /* Use port1 because of the static port-swap */
13200 /* Enable the module detection interrupt */
13201 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13202 val |= ((1<<MISC_REGISTERS_GPIO_3)|
13203 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
13204 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13205
13206 bnx2x_ext_phy_hw_reset(bp, 0);
13207 usleep_range(5000, 10000);
13208 for (port = 0; port < PORT_MAX; port++) {
13209 u32 shmem_base, shmem2_base;
13210
13211 /* In E2, same phy is using for port0 of the two paths */
13212 if (CHIP_IS_E1x(bp)) {
13213 shmem_base = shmem_base_path[0];
13214 shmem2_base = shmem2_base_path[0];
13215 } else {
13216 shmem_base = shmem_base_path[port];
13217 shmem2_base = shmem2_base_path[port];
13218 }
13219 /* Extract the ext phy address for the port */
13220 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13221 port, &phy) !=
13222 0) {
13223 DP(NETIF_MSG_LINK, "populate phy failed\n");
13224 return -EINVAL;
13225 }
13226
13227 /* Reset phy*/
13228 bnx2x_cl45_write(bp, &phy,
13229 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
13230
13231
13232 /* Set fault module detected LED on */
13233 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
13234 MISC_REGISTERS_GPIO_HIGH,
13235 port);
13236 }
13237
13238 return 0;
13239 }
bnx2x_get_ext_phy_reset_gpio(struct bnx2x * bp,u32 shmem_base,u8 * io_gpio,u8 * io_port)13240 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
13241 u8 *io_gpio, u8 *io_port)
13242 {
13243
13244 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
13245 offsetof(struct shmem_region,
13246 dev_info.port_hw_config[PORT_0].default_cfg));
13247 switch (phy_gpio_reset) {
13248 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
13249 *io_gpio = 0;
13250 *io_port = 0;
13251 break;
13252 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
13253 *io_gpio = 1;
13254 *io_port = 0;
13255 break;
13256 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
13257 *io_gpio = 2;
13258 *io_port = 0;
13259 break;
13260 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
13261 *io_gpio = 3;
13262 *io_port = 0;
13263 break;
13264 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
13265 *io_gpio = 0;
13266 *io_port = 1;
13267 break;
13268 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
13269 *io_gpio = 1;
13270 *io_port = 1;
13271 break;
13272 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
13273 *io_gpio = 2;
13274 *io_port = 1;
13275 break;
13276 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
13277 *io_gpio = 3;
13278 *io_port = 1;
13279 break;
13280 default:
13281 /* Don't override the io_gpio and io_port */
13282 break;
13283 }
13284 }
13285
bnx2x_8727_common_init_phy(struct bnx2x * bp,u32 shmem_base_path[],u32 shmem2_base_path[],u8 phy_index,u32 chip_id)13286 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13287 u32 shmem_base_path[],
13288 u32 shmem2_base_path[], u8 phy_index,
13289 u32 chip_id)
13290 {
13291 s8 port, reset_gpio;
13292 u32 swap_val, swap_override;
13293 struct bnx2x_phy phy[PORT_MAX];
13294 struct bnx2x_phy *phy_blk[PORT_MAX];
13295 s8 port_of_path;
13296 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13297 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13298
13299 reset_gpio = MISC_REGISTERS_GPIO_1;
13300 port = 1;
13301
13302 /* Retrieve the reset gpio/port which control the reset.
13303 * Default is GPIO1, PORT1
13304 */
13305 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13306 (u8 *)&reset_gpio, (u8 *)&port);
13307
13308 /* Calculate the port based on port swap */
13309 port ^= (swap_val && swap_override);
13310
13311 /* Initiate PHY reset*/
13312 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13313 port);
13314 usleep_range(1000, 2000);
13315 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13316 port);
13317
13318 usleep_range(5000, 10000);
13319
13320 /* PART1 - Reset both phys */
13321 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13322 u32 shmem_base, shmem2_base;
13323
13324 /* In E2, same phy is using for port0 of the two paths */
13325 if (CHIP_IS_E1x(bp)) {
13326 shmem_base = shmem_base_path[0];
13327 shmem2_base = shmem2_base_path[0];
13328 port_of_path = port;
13329 } else {
13330 shmem_base = shmem_base_path[port];
13331 shmem2_base = shmem2_base_path[port];
13332 port_of_path = 0;
13333 }
13334
13335 /* Extract the ext phy address for the port */
13336 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13337 port_of_path, &phy[port]) !=
13338 0) {
13339 DP(NETIF_MSG_LINK, "populate phy failed\n");
13340 return -EINVAL;
13341 }
13342 /* disable attentions */
13343 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13344 port_of_path*4,
13345 (NIG_MASK_XGXS0_LINK_STATUS |
13346 NIG_MASK_XGXS0_LINK10G |
13347 NIG_MASK_SERDES0_LINK_STATUS |
13348 NIG_MASK_MI_INT));
13349
13350
13351 /* Reset the phy */
13352 bnx2x_cl45_write(bp, &phy[port],
13353 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13354 }
13355
13356 /* Add delay of 150ms after reset */
13357 msleep(150);
13358 if (phy[PORT_0].addr & 0x1) {
13359 phy_blk[PORT_0] = &(phy[PORT_1]);
13360 phy_blk[PORT_1] = &(phy[PORT_0]);
13361 } else {
13362 phy_blk[PORT_0] = &(phy[PORT_0]);
13363 phy_blk[PORT_1] = &(phy[PORT_1]);
13364 }
13365 /* PART2 - Download firmware to both phys */
13366 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13367 if (CHIP_IS_E1x(bp))
13368 port_of_path = port;
13369 else
13370 port_of_path = 0;
13371 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13372 phy_blk[port]->addr);
13373 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13374 port_of_path))
13375 return -EINVAL;
13376 /* Disable PHY transmitter output */
13377 bnx2x_cl45_write(bp, phy_blk[port],
13378 MDIO_PMA_DEVAD,
13379 MDIO_PMA_REG_TX_DISABLE, 1);
13380
13381 }
13382 return 0;
13383 }
13384
bnx2x_84833_common_init_phy(struct bnx2x * bp,u32 shmem_base_path[],u32 shmem2_base_path[],u8 phy_index,u32 chip_id)13385 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13386 u32 shmem_base_path[],
13387 u32 shmem2_base_path[],
13388 u8 phy_index,
13389 u32 chip_id)
13390 {
13391 u8 reset_gpios;
13392 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13393 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13394 udelay(10);
13395 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13396 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13397 reset_gpios);
13398 return 0;
13399 }
13400
bnx2x_ext_phy_common_init(struct bnx2x * bp,u32 shmem_base_path[],u32 shmem2_base_path[],u8 phy_index,u32 ext_phy_type,u32 chip_id)13401 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13402 u32 shmem2_base_path[], u8 phy_index,
13403 u32 ext_phy_type, u32 chip_id)
13404 {
13405 int rc = 0;
13406
13407 switch (ext_phy_type) {
13408 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13409 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13410 shmem2_base_path,
13411 phy_index, chip_id);
13412 break;
13413 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13414 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13415 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13416 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13417 shmem2_base_path,
13418 phy_index, chip_id);
13419 break;
13420
13421 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13422 /* GPIO1 affects both ports, so there's need to pull
13423 * it for single port alone
13424 */
13425 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13426 shmem2_base_path,
13427 phy_index, chip_id);
13428 break;
13429 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13430 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13431 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
13432 /* GPIO3's are linked, and so both need to be toggled
13433 * to obtain required 2us pulse.
13434 */
13435 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13436 shmem2_base_path,
13437 phy_index, chip_id);
13438 break;
13439 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13440 rc = -EINVAL;
13441 break;
13442 default:
13443 DP(NETIF_MSG_LINK,
13444 "ext_phy 0x%x common init not required\n",
13445 ext_phy_type);
13446 break;
13447 }
13448
13449 if (rc)
13450 netdev_err(bp->dev, "Warning: PHY was not initialized,"
13451 " Port %d\n",
13452 0);
13453 return rc;
13454 }
13455
bnx2x_common_init_phy(struct bnx2x * bp,u32 shmem_base_path[],u32 shmem2_base_path[],u32 chip_id)13456 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13457 u32 shmem2_base_path[], u32 chip_id)
13458 {
13459 int rc = 0;
13460 u32 phy_ver, val;
13461 u8 phy_index = 0;
13462 u32 ext_phy_type, ext_phy_config;
13463
13464 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13465 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13466 DP(NETIF_MSG_LINK, "Begin common phy init\n");
13467 if (CHIP_IS_E3(bp)) {
13468 /* Enable EPIO */
13469 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13470 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13471 }
13472 /* Check if common init was already done */
13473 phy_ver = REG_RD(bp, shmem_base_path[0] +
13474 offsetof(struct shmem_region,
13475 port_mb[PORT_0].ext_phy_fw_version));
13476 if (phy_ver) {
13477 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13478 phy_ver);
13479 return 0;
13480 }
13481
13482 /* Read the ext_phy_type for arbitrary port(0) */
13483 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13484 phy_index++) {
13485 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13486 shmem_base_path[0],
13487 phy_index, 0);
13488 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13489 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13490 shmem2_base_path,
13491 phy_index, ext_phy_type,
13492 chip_id);
13493 }
13494 return rc;
13495 }
13496
bnx2x_check_over_curr(struct link_params * params,struct link_vars * vars)13497 static void bnx2x_check_over_curr(struct link_params *params,
13498 struct link_vars *vars)
13499 {
13500 struct bnx2x *bp = params->bp;
13501 u32 cfg_pin;
13502 u8 port = params->port;
13503 u32 pin_val;
13504
13505 cfg_pin = (REG_RD(bp, params->shmem_base +
13506 offsetof(struct shmem_region,
13507 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13508 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13509 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13510
13511 /* Ignore check if no external input PIN available */
13512 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13513 return;
13514
13515 if (!pin_val) {
13516 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13517 netdev_err(bp->dev, "Error: Power fault on Port %d has"
13518 " been detected and the power to "
13519 "that SFP+ module has been removed"
13520 " to prevent failure of the card."
13521 " Please remove the SFP+ module and"
13522 " restart the system to clear this"
13523 " error.\n",
13524 params->port);
13525 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13526 bnx2x_warpcore_power_module(params, 0);
13527 }
13528 } else
13529 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13530 }
13531
13532 /* Returns 0 if no change occurred since last check; 1 otherwise. */
bnx2x_analyze_link_error(struct link_params * params,struct link_vars * vars,u32 status,u32 phy_flag,u32 link_flag,u8 notify)13533 static u8 bnx2x_analyze_link_error(struct link_params *params,
13534 struct link_vars *vars, u32 status,
13535 u32 phy_flag, u32 link_flag, u8 notify)
13536 {
13537 struct bnx2x *bp = params->bp;
13538 /* Compare new value with previous value */
13539 u8 led_mode;
13540 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13541
13542 if ((status ^ old_status) == 0)
13543 return 0;
13544
13545 /* If values differ */
13546 switch (phy_flag) {
13547 case PHY_HALF_OPEN_CONN_FLAG:
13548 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13549 break;
13550 case PHY_SFP_TX_FAULT_FLAG:
13551 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13552 break;
13553 default:
13554 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13555 }
13556 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13557 old_status, status);
13558
13559 /* Do not touch the link in case physical link down */
13560 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
13561 return 1;
13562
13563 /* a. Update shmem->link_status accordingly
13564 * b. Update link_vars->link_up
13565 */
13566 if (status) {
13567 vars->link_status &= ~LINK_STATUS_LINK_UP;
13568 vars->link_status |= link_flag;
13569 vars->link_up = 0;
13570 vars->phy_flags |= phy_flag;
13571
13572 /* activate nig drain */
13573 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13574 /* Set LED mode to off since the PHY doesn't know about these
13575 * errors
13576 */
13577 led_mode = LED_MODE_OFF;
13578 } else {
13579 vars->link_status |= LINK_STATUS_LINK_UP;
13580 vars->link_status &= ~link_flag;
13581 vars->link_up = 1;
13582 vars->phy_flags &= ~phy_flag;
13583 led_mode = LED_MODE_OPER;
13584
13585 /* Clear nig drain */
13586 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13587 }
13588 bnx2x_sync_link(params, vars);
13589 /* Update the LED according to the link state */
13590 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13591
13592 /* Update link status in the shared memory */
13593 bnx2x_update_mng(params, vars->link_status);
13594
13595 /* C. Trigger General Attention */
13596 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13597 if (notify)
13598 bnx2x_notify_link_changed(bp);
13599
13600 return 1;
13601 }
13602
13603 /******************************************************************************
13604 * Description:
13605 * This function checks for half opened connection change indication.
13606 * When such change occurs, it calls the bnx2x_analyze_link_error
13607 * to check if Remote Fault is set or cleared. Reception of remote fault
13608 * status message in the MAC indicates that the peer's MAC has detected
13609 * a fault, for example, due to break in the TX side of fiber.
13610 *
13611 ******************************************************************************/
bnx2x_check_half_open_conn(struct link_params * params,struct link_vars * vars,u8 notify)13612 static int bnx2x_check_half_open_conn(struct link_params *params,
13613 struct link_vars *vars,
13614 u8 notify)
13615 {
13616 struct bnx2x *bp = params->bp;
13617 u32 lss_status = 0;
13618 u32 mac_base;
13619 /* In case link status is physically up @ 10G do */
13620 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13621 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13622 return 0;
13623
13624 if (CHIP_IS_E3(bp) &&
13625 (REG_RD(bp, MISC_REG_RESET_REG_2) &
13626 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13627 /* Check E3 XMAC */
13628 /* Note that link speed cannot be queried here, since it may be
13629 * zero while link is down. In case UMAC is active, LSS will
13630 * simply not be set
13631 */
13632 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13633
13634 /* Clear stick bits (Requires rising edge) */
13635 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13636 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13637 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13638 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13639 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13640 lss_status = 1;
13641
13642 bnx2x_analyze_link_error(params, vars, lss_status,
13643 PHY_HALF_OPEN_CONN_FLAG,
13644 LINK_STATUS_NONE, notify);
13645 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13646 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13647 /* Check E1X / E2 BMAC */
13648 u32 lss_status_reg;
13649 u32 wb_data[2];
13650 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13651 NIG_REG_INGRESS_BMAC0_MEM;
13652 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
13653 if (CHIP_IS_E2(bp))
13654 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13655 else
13656 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13657
13658 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13659 lss_status = (wb_data[0] > 0);
13660
13661 bnx2x_analyze_link_error(params, vars, lss_status,
13662 PHY_HALF_OPEN_CONN_FLAG,
13663 LINK_STATUS_NONE, notify);
13664 }
13665 return 0;
13666 }
bnx2x_sfp_tx_fault_detection(struct bnx2x_phy * phy,struct link_params * params,struct link_vars * vars)13667 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13668 struct link_params *params,
13669 struct link_vars *vars)
13670 {
13671 struct bnx2x *bp = params->bp;
13672 u32 cfg_pin, value = 0;
13673 u8 led_change, port = params->port;
13674
13675 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13676 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13677 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13678 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13679 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13680
13681 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13682 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13683 return;
13684 }
13685
13686 led_change = bnx2x_analyze_link_error(params, vars, value,
13687 PHY_SFP_TX_FAULT_FLAG,
13688 LINK_STATUS_SFP_TX_FAULT, 1);
13689
13690 if (led_change) {
13691 /* Change TX_Fault led, set link status for further syncs */
13692 u8 led_mode;
13693
13694 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13695 led_mode = MISC_REGISTERS_GPIO_HIGH;
13696 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13697 } else {
13698 led_mode = MISC_REGISTERS_GPIO_LOW;
13699 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13700 }
13701
13702 /* If module is unapproved, led should be on regardless */
13703 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13704 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13705 led_mode);
13706 bnx2x_set_e3_module_fault_led(params, led_mode);
13707 }
13708 }
13709 }
bnx2x_kr2_recovery(struct link_params * params,struct link_vars * vars,struct bnx2x_phy * phy)13710 static void bnx2x_kr2_recovery(struct link_params *params,
13711 struct link_vars *vars,
13712 struct bnx2x_phy *phy)
13713 {
13714 struct bnx2x *bp = params->bp;
13715 DP(NETIF_MSG_LINK, "KR2 recovery\n");
13716 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13717 bnx2x_warpcore_restart_AN_KR(phy, params);
13718 }
13719
bnx2x_check_kr2_wa(struct link_params * params,struct link_vars * vars,struct bnx2x_phy * phy)13720 static void bnx2x_check_kr2_wa(struct link_params *params,
13721 struct link_vars *vars,
13722 struct bnx2x_phy *phy)
13723 {
13724 struct bnx2x *bp = params->bp;
13725 u16 base_page, next_page, not_kr2_device, lane;
13726 int sigdet;
13727
13728 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13729 * Since some switches tend to reinit the AN process and clear the
13730 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13731 * and recovered many times
13732 */
13733 if (vars->check_kr2_recovery_cnt > 0) {
13734 vars->check_kr2_recovery_cnt--;
13735 return;
13736 }
13737
13738 sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13739 if (!sigdet) {
13740 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13741 bnx2x_kr2_recovery(params, vars, phy);
13742 DP(NETIF_MSG_LINK, "No sigdet\n");
13743 }
13744 return;
13745 }
13746
13747 lane = bnx2x_get_warpcore_lane(phy, params);
13748 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13749 MDIO_AER_BLOCK_AER_REG, lane);
13750 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13751 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13752 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13753 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13754 bnx2x_set_aer_mmd(params, phy);
13755
13756 /* CL73 has not begun yet */
13757 if (base_page == 0) {
13758 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13759 bnx2x_kr2_recovery(params, vars, phy);
13760 DP(NETIF_MSG_LINK, "No BP\n");
13761 }
13762 return;
13763 }
13764
13765 /* In case NP bit is not set in the BasePage, or it is set,
13766 * but only KX is advertised, declare this link partner as non-KR2
13767 * device.
13768 */
13769 not_kr2_device = (((base_page & 0x8000) == 0) ||
13770 (((base_page & 0x8000) &&
13771 ((next_page & 0xe0) == 0x20))));
13772
13773 /* In case KR2 is already disabled, check if we need to re-enable it */
13774 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13775 if (!not_kr2_device) {
13776 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13777 next_page);
13778 bnx2x_kr2_recovery(params, vars, phy);
13779 }
13780 return;
13781 }
13782 /* KR2 is enabled, but not KR2 device */
13783 if (not_kr2_device) {
13784 /* Disable KR2 on both lanes */
13785 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13786 bnx2x_disable_kr2(params, vars, phy);
13787 /* Restart AN on leading lane */
13788 bnx2x_warpcore_restart_AN_KR(phy, params);
13789 return;
13790 }
13791 }
13792
bnx2x_period_func(struct link_params * params,struct link_vars * vars)13793 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13794 {
13795 u16 phy_idx;
13796 struct bnx2x *bp = params->bp;
13797 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13798 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13799 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]);
13800 if (bnx2x_check_half_open_conn(params, vars, 1) !=
13801 0)
13802 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13803 break;
13804 }
13805 }
13806
13807 if (CHIP_IS_E3(bp)) {
13808 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
13809 bnx2x_set_aer_mmd(params, phy);
13810 if ((phy->supported & SUPPORTED_20000baseKR2_Full) &&
13811 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
13812 bnx2x_check_kr2_wa(params, vars, phy);
13813 bnx2x_check_over_curr(params, vars);
13814 if (vars->rx_tx_asic_rst)
13815 bnx2x_warpcore_config_runtime(phy, params, vars);
13816
13817 if ((REG_RD(bp, params->shmem_base +
13818 offsetof(struct shmem_region, dev_info.
13819 port_hw_config[params->port].default_cfg))
13820 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13821 PORT_HW_CFG_NET_SERDES_IF_SFI) {
13822 if (bnx2x_is_sfp_module_plugged(phy, params)) {
13823 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13824 } else if (vars->link_status &
13825 LINK_STATUS_SFP_TX_FAULT) {
13826 /* Clean trail, interrupt corrects the leds */
13827 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13828 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13829 /* Update link status in the shared memory */
13830 bnx2x_update_mng(params, vars->link_status);
13831 }
13832 }
13833 }
13834 }
13835
bnx2x_fan_failure_det_req(struct bnx2x * bp,u32 shmem_base,u32 shmem2_base,u8 port)13836 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13837 u32 shmem_base,
13838 u32 shmem2_base,
13839 u8 port)
13840 {
13841 u8 phy_index, fan_failure_det_req = 0;
13842 struct bnx2x_phy phy;
13843 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13844 phy_index++) {
13845 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13846 port, &phy)
13847 != 0) {
13848 DP(NETIF_MSG_LINK, "populate phy failed\n");
13849 return 0;
13850 }
13851 fan_failure_det_req |= (phy.flags &
13852 FLAGS_FAN_FAILURE_DET_REQ);
13853 }
13854 return fan_failure_det_req;
13855 }
13856
bnx2x_hw_reset_phy(struct link_params * params)13857 void bnx2x_hw_reset_phy(struct link_params *params)
13858 {
13859 u8 phy_index;
13860 struct bnx2x *bp = params->bp;
13861 bnx2x_update_mng(params, 0);
13862 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13863 (NIG_MASK_XGXS0_LINK_STATUS |
13864 NIG_MASK_XGXS0_LINK10G |
13865 NIG_MASK_SERDES0_LINK_STATUS |
13866 NIG_MASK_MI_INT));
13867
13868 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13869 phy_index++) {
13870 if (params->phy[phy_index].hw_reset) {
13871 params->phy[phy_index].hw_reset(
13872 ¶ms->phy[phy_index],
13873 params);
13874 params->phy[phy_index] = phy_null;
13875 }
13876 }
13877 }
13878
bnx2x_init_mod_abs_int(struct bnx2x * bp,struct link_vars * vars,u32 chip_id,u32 shmem_base,u32 shmem2_base,u8 port)13879 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13880 u32 chip_id, u32 shmem_base, u32 shmem2_base,
13881 u8 port)
13882 {
13883 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13884 u32 val;
13885 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
13886 if (CHIP_IS_E3(bp)) {
13887 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13888 shmem_base,
13889 port,
13890 &gpio_num,
13891 &gpio_port) != 0)
13892 return;
13893 } else {
13894 struct bnx2x_phy phy;
13895 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13896 phy_index++) {
13897 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13898 shmem2_base, port, &phy)
13899 != 0) {
13900 DP(NETIF_MSG_LINK, "populate phy failed\n");
13901 return;
13902 }
13903 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13904 gpio_num = MISC_REGISTERS_GPIO_3;
13905 gpio_port = port;
13906 break;
13907 }
13908 }
13909 }
13910
13911 if (gpio_num == 0xff)
13912 return;
13913
13914 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13915 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13916
13917 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13918 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13919 gpio_port ^= (swap_val && swap_override);
13920
13921 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13922 (gpio_num + (gpio_port << 2));
13923
13924 sync_offset = shmem_base +
13925 offsetof(struct shmem_region,
13926 dev_info.port_hw_config[port].aeu_int_mask);
13927 REG_WR(bp, sync_offset, vars->aeu_int_mask);
13928
13929 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13930 gpio_num, gpio_port, vars->aeu_int_mask);
13931
13932 if (port == 0)
13933 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13934 else
13935 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13936
13937 /* Open appropriate AEU for interrupts */
13938 aeu_mask = REG_RD(bp, offset);
13939 aeu_mask |= vars->aeu_int_mask;
13940 REG_WR(bp, offset, aeu_mask);
13941
13942 /* Enable the GPIO to trigger interrupt */
13943 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13944 val |= 1 << (gpio_num + (gpio_port << 2));
13945 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13946 }
13947