1 /*
2 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #ifndef FIMC_CORE_H_
10 #define FIMC_CORE_H_
11
12 /*#define DEBUG*/
13
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/sched.h>
17 #include <linux/spinlock.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/types.h>
20 #include <linux/videodev2.h>
21 #include <linux/io.h>
22 #include <linux/sizes.h>
23
24 #include <media/media-entity.h>
25 #include <media/videobuf2-v4l2.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-mem2mem.h>
29 #include <media/v4l2-mediabus.h>
30 #include <media/exynos-fimc.h>
31
32 #define dbg(fmt, args...) \
33 pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
34
35 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
36 #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
37 #define MAX_FIMC_CLOCKS 2
38 #define FIMC_DRIVER_NAME "exynos4-fimc"
39 #define FIMC_MAX_DEVS 4
40 #define FIMC_MAX_OUT_BUFS 4
41 #define SCALER_MAX_HRATIO 64
42 #define SCALER_MAX_VRATIO 64
43 #define DMA_MIN_SIZE 8
44 #define FIMC_CAMIF_MAX_HEIGHT 0x2000
45 #define FIMC_MAX_JPEG_BUF_SIZE (10 * SZ_1M)
46 #define FIMC_MAX_PLANES 3
47 #define FIMC_PIX_LIMITS_MAX 4
48 #define FIMC_DEF_MIN_SIZE 16
49 #define FIMC_DEF_HEIGHT_ALIGN 2
50 #define FIMC_DEF_HOR_OFFS_ALIGN 1
51 #define FIMC_DEFAULT_WIDTH 640
52 #define FIMC_DEFAULT_HEIGHT 480
53
54 /* indices to the clocks array */
55 enum {
56 CLK_BUS,
57 CLK_GATE,
58 };
59
60 enum fimc_dev_flags {
61 ST_LPM,
62 /* m2m node */
63 ST_M2M_RUN,
64 ST_M2M_PEND,
65 ST_M2M_SUSPENDING,
66 ST_M2M_SUSPENDED,
67 /* capture node */
68 ST_CAPT_PEND,
69 ST_CAPT_RUN,
70 ST_CAPT_STREAM,
71 ST_CAPT_ISP_STREAM,
72 ST_CAPT_SUSPENDED,
73 ST_CAPT_SHUT,
74 ST_CAPT_BUSY,
75 ST_CAPT_APPLY_CFG,
76 ST_CAPT_JPEG,
77 };
78
79 #define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
80 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
81
82 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
83 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
84 #define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
85
86 enum fimc_datapath {
87 FIMC_IO_NONE,
88 FIMC_IO_CAMERA,
89 FIMC_IO_DMA,
90 FIMC_IO_LCDFIFO,
91 FIMC_IO_WRITEBACK,
92 FIMC_IO_ISP,
93 };
94
95 enum fimc_color_fmt {
96 FIMC_FMT_RGB444 = 0x10,
97 FIMC_FMT_RGB555,
98 FIMC_FMT_RGB565,
99 FIMC_FMT_RGB666,
100 FIMC_FMT_RGB888,
101 FIMC_FMT_RGB30_LOCAL,
102 FIMC_FMT_YCBCR420 = 0x20,
103 FIMC_FMT_YCBYCR422,
104 FIMC_FMT_YCRYCB422,
105 FIMC_FMT_CBYCRY422,
106 FIMC_FMT_CRYCBY422,
107 FIMC_FMT_YCBCR444_LOCAL,
108 FIMC_FMT_RAW8 = 0x40,
109 FIMC_FMT_RAW10,
110 FIMC_FMT_RAW12,
111 FIMC_FMT_JPEG = 0x80,
112 FIMC_FMT_YUYV_JPEG = 0x100,
113 };
114
115 #define fimc_fmt_is_user_defined(x) (!!((x) & 0x180))
116 #define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
117
118 #define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \
119 __strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
120
121 /* The hardware context state. */
122 #define FIMC_PARAMS (1 << 0)
123 #define FIMC_COMPOSE (1 << 1)
124 #define FIMC_CTX_M2M (1 << 16)
125 #define FIMC_CTX_CAP (1 << 17)
126 #define FIMC_CTX_SHUT (1 << 18)
127
128 /* Image conversion flags */
129 #define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
130 #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
131 #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
132 #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
133 #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
134 #define FIMC_SCAN_MODE_INTERLACED (1 << 2)
135 /*
136 * YCbCr data dynamic range for RGB-YUV color conversion.
137 * Y/Cb/Cr: (0 ~ 255) */
138 #define FIMC_COLOR_RANGE_WIDE (0 << 3)
139 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
140 #define FIMC_COLOR_RANGE_NARROW (1 << 3)
141
142 /**
143 * struct fimc_dma_offset - pixel offset information for DMA
144 * @y_h: y value horizontal offset
145 * @y_v: y value vertical offset
146 * @cb_h: cb value horizontal offset
147 * @cb_v: cb value vertical offset
148 * @cr_h: cr value horizontal offset
149 * @cr_v: cr value vertical offset
150 */
151 struct fimc_dma_offset {
152 int y_h;
153 int y_v;
154 int cb_h;
155 int cb_v;
156 int cr_h;
157 int cr_v;
158 };
159
160 /**
161 * struct fimc_effect - color effect information
162 * @type: effect type
163 * @pat_cb: cr value when type is "arbitrary"
164 * @pat_cr: cr value when type is "arbitrary"
165 */
166 struct fimc_effect {
167 u32 type;
168 u8 pat_cb;
169 u8 pat_cr;
170 };
171
172 /**
173 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
174 * @scaleup_h: flag indicating scaling up horizontally
175 * @scaleup_v: flag indicating scaling up vertically
176 * @copy_mode: flag indicating transparent DMA transfer (no scaling
177 * and color format conversion)
178 * @enabled: flag indicating if the scaler is used
179 * @hfactor: horizontal shift factor
180 * @vfactor: vertical shift factor
181 * @pre_hratio: horizontal ratio of the prescaler
182 * @pre_vratio: vertical ratio of the prescaler
183 * @pre_dst_width: the prescaler's destination width
184 * @pre_dst_height: the prescaler's destination height
185 * @main_hratio: the main scaler's horizontal ratio
186 * @main_vratio: the main scaler's vertical ratio
187 * @real_width: source pixel (width - offset)
188 * @real_height: source pixel (height - offset)
189 */
190 struct fimc_scaler {
191 unsigned int scaleup_h:1;
192 unsigned int scaleup_v:1;
193 unsigned int copy_mode:1;
194 unsigned int enabled:1;
195 u32 hfactor;
196 u32 vfactor;
197 u32 pre_hratio;
198 u32 pre_vratio;
199 u32 pre_dst_width;
200 u32 pre_dst_height;
201 u32 main_hratio;
202 u32 main_vratio;
203 u32 real_width;
204 u32 real_height;
205 };
206
207 /**
208 * struct fimc_addr - the FIMC physical address set for DMA
209 * @y: luminance plane physical address
210 * @cb: Cb plane physical address
211 * @cr: Cr plane physical address
212 */
213 struct fimc_addr {
214 u32 y;
215 u32 cb;
216 u32 cr;
217 };
218
219 /**
220 * struct fimc_vid_buffer - the driver's video buffer
221 * @vb: v4l videobuf buffer
222 * @list: linked list structure for buffer queue
223 * @paddr: precalculated physical address set
224 * @index: buffer index for the output DMA engine
225 */
226 struct fimc_vid_buffer {
227 struct vb2_v4l2_buffer vb;
228 struct list_head list;
229 struct fimc_addr paddr;
230 int index;
231 };
232
233 /**
234 * struct fimc_frame - source/target frame properties
235 * @f_width: image full width (virtual screen size)
236 * @f_height: image full height (virtual screen size)
237 * @o_width: original image width as set by S_FMT
238 * @o_height: original image height as set by S_FMT
239 * @offs_h: image horizontal pixel offset
240 * @offs_v: image vertical pixel offset
241 * @width: image pixel width
242 * @height: image pixel weight
243 * @payload: image size in bytes (w x h x bpp)
244 * @bytesperline: bytesperline value for each plane
245 * @paddr: image frame buffer physical addresses
246 * @dma_offset: DMA offset in bytes
247 * @fmt: fimc color format pointer
248 */
249 struct fimc_frame {
250 u32 f_width;
251 u32 f_height;
252 u32 o_width;
253 u32 o_height;
254 u32 offs_h;
255 u32 offs_v;
256 u32 width;
257 u32 height;
258 unsigned int payload[VIDEO_MAX_PLANES];
259 unsigned int bytesperline[VIDEO_MAX_PLANES];
260 struct fimc_addr paddr;
261 struct fimc_dma_offset dma_offset;
262 struct fimc_fmt *fmt;
263 u8 alpha;
264 };
265
266 /**
267 * struct fimc_m2m_device - v4l2 memory-to-memory device data
268 * @vfd: the video device node for v4l2 m2m mode
269 * @m2m_dev: v4l2 memory-to-memory device data
270 * @ctx: hardware context data
271 * @refcnt: the reference counter
272 */
273 struct fimc_m2m_device {
274 struct video_device vfd;
275 struct v4l2_m2m_dev *m2m_dev;
276 struct fimc_ctx *ctx;
277 int refcnt;
278 };
279
280 #define FIMC_SD_PAD_SINK_CAM 0
281 #define FIMC_SD_PAD_SINK_FIFO 1
282 #define FIMC_SD_PAD_SOURCE 2
283 #define FIMC_SD_PADS_NUM 3
284
285 /**
286 * struct fimc_vid_cap - camera capture device information
287 * @ctx: hardware context data
288 * @subdev: subdev exposing the FIMC processing block
289 * @ve: exynos video device entity structure
290 * @vd_pad: fimc video capture node pad
291 * @sd_pads: fimc video processing block pads
292 * @ci_fmt: image format at the FIMC camera input (and the scaler output)
293 * @wb_fmt: image format at the FIMC ISP Writeback input
294 * @source_config: external image source related configuration structure
295 * @pending_buf_q: the pending buffer queue head
296 * @active_buf_q: the queue head of buffers scheduled in hardware
297 * @vbq: the capture am video buffer queue
298 * @active_buf_cnt: number of video buffers scheduled in hardware
299 * @buf_index: index for managing the output DMA buffers
300 * @frame_count: the frame counter for statistics
301 * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
302 * @input_index: input (camera sensor) index
303 * @input: capture input type, grp_id of the attached subdev
304 * @user_subdev_api: true if subdevs are not configured by the host driver
305 * @inh_sensor_ctrls: a flag indicating v4l2 controls are inherited from
306 * an image sensor subdev
307 */
308 struct fimc_vid_cap {
309 struct fimc_ctx *ctx;
310 struct vb2_alloc_ctx *alloc_ctx;
311 struct v4l2_subdev subdev;
312 struct exynos_video_entity ve;
313 struct media_pad vd_pad;
314 struct media_pad sd_pads[FIMC_SD_PADS_NUM];
315 struct v4l2_mbus_framefmt ci_fmt;
316 struct v4l2_mbus_framefmt wb_fmt;
317 struct fimc_source_info source_config;
318 struct list_head pending_buf_q;
319 struct list_head active_buf_q;
320 struct vb2_queue vbq;
321 int active_buf_cnt;
322 int buf_index;
323 unsigned int frame_count;
324 unsigned int reqbufs_count;
325 bool streaming;
326 int input_index;
327 u32 input;
328 bool user_subdev_api;
329 bool inh_sensor_ctrls;
330 };
331
332 /**
333 * struct fimc_pix_limit - image pixel size limits in various IP configurations
334 *
335 * @scaler_en_w: max input pixel width when the scaler is enabled
336 * @scaler_dis_w: max input pixel width when the scaler is disabled
337 * @in_rot_en_h: max input width with the input rotator is on
338 * @in_rot_dis_w: max input width with the input rotator is off
339 * @out_rot_en_w: max output width with the output rotator on
340 * @out_rot_dis_w: max output width with the output rotator off
341 */
342 struct fimc_pix_limit {
343 u16 scaler_en_w;
344 u16 scaler_dis_w;
345 u16 in_rot_en_h;
346 u16 in_rot_dis_w;
347 u16 out_rot_en_w;
348 u16 out_rot_dis_w;
349 };
350
351 /**
352 * struct fimc_variant - FIMC device variant information
353 * @has_inp_rot: set if has input rotator
354 * @has_out_rot: set if has output rotator
355 * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
356 * are present in this IP revision
357 * @has_cam_if: set if this instance has a camera input interface
358 * @has_isp_wb: set if this instance has ISP writeback input
359 * @pix_limit: pixel size constraints for the scaler
360 * @min_inp_pixsize: minimum input pixel size
361 * @min_out_pixsize: minimum output pixel size
362 * @hor_offs_align: horizontal pixel offset aligment
363 * @min_vsize_align: minimum vertical pixel size alignment
364 */
365 struct fimc_variant {
366 unsigned int has_inp_rot:1;
367 unsigned int has_out_rot:1;
368 unsigned int has_mainscaler_ext:1;
369 unsigned int has_cam_if:1;
370 unsigned int has_isp_wb:1;
371 const struct fimc_pix_limit *pix_limit;
372 u16 min_inp_pixsize;
373 u16 min_out_pixsize;
374 u16 hor_offs_align;
375 u16 min_vsize_align;
376 };
377
378 /**
379 * struct fimc_drvdata - per device type driver data
380 * @variant: variant information for this device
381 * @num_entities: number of fimc instances available in a SoC
382 * @lclk_frequency: local bus clock frequency
383 * @cistatus2: 1 if the FIMC IPs have CISTATUS2 register
384 * @dma_pix_hoff: the horizontal DMA offset unit: 1 - pixels, 0 - bytes
385 * @alpha_color: 1 if alpha color component is supported
386 * @out_buf_count: maximum number of output DMA buffers supported
387 */
388 struct fimc_drvdata {
389 const struct fimc_variant *variant[FIMC_MAX_DEVS];
390 int num_entities;
391 unsigned long lclk_frequency;
392 /* Fields common to all FIMC IP instances */
393 u8 cistatus2;
394 u8 dma_pix_hoff;
395 u8 alpha_color;
396 u8 out_buf_count;
397 };
398
399 #define fimc_get_drvdata(_pdev) \
400 ((struct fimc_drvdata *) platform_get_device_id(_pdev)->driver_data)
401
402 struct fimc_ctx;
403
404 /**
405 * struct fimc_dev - abstraction for FIMC entity
406 * @slock: the spinlock protecting this data structure
407 * @lock: the mutex protecting this data structure
408 * @pdev: pointer to the FIMC platform device
409 * @pdata: pointer to the device platform data
410 * @sysreg: pointer to the SYSREG regmap
411 * @variant: the IP variant information
412 * @id: FIMC device index (0..FIMC_MAX_DEVS)
413 * @clock: clocks required for FIMC operation
414 * @regs: the mapped hardware registers
415 * @irq_queue: interrupt handler waitqueue
416 * @v4l2_dev: root v4l2_device
417 * @m2m: memory-to-memory V4L2 device information
418 * @vid_cap: camera capture device information
419 * @state: flags used to synchronize m2m and capture mode operation
420 * @alloc_ctx: videobuf2 memory allocator context
421 * @pipeline: fimc video capture pipeline data structure
422 */
423 struct fimc_dev {
424 spinlock_t slock;
425 struct mutex lock;
426 struct platform_device *pdev;
427 struct s5p_platform_fimc *pdata;
428 struct regmap *sysreg;
429 const struct fimc_variant *variant;
430 const struct fimc_drvdata *drv_data;
431 int id;
432 struct clk *clock[MAX_FIMC_CLOCKS];
433 void __iomem *regs;
434 wait_queue_head_t irq_queue;
435 struct v4l2_device *v4l2_dev;
436 struct fimc_m2m_device m2m;
437 struct fimc_vid_cap vid_cap;
438 unsigned long state;
439 struct vb2_alloc_ctx *alloc_ctx;
440 };
441
442 /**
443 * struct fimc_ctrls - v4l2 controls structure
444 * @handler: the control handler
445 * @colorfx: image effect control
446 * @colorfx_cbcr: Cb/Cr coefficients control
447 * @rotate: image rotation control
448 * @hflip: horizontal flip control
449 * @vflip: vertical flip control
450 * @alpha: RGB alpha control
451 * @ready: true if @handler is initialized
452 */
453 struct fimc_ctrls {
454 struct v4l2_ctrl_handler handler;
455 struct {
456 struct v4l2_ctrl *colorfx;
457 struct v4l2_ctrl *colorfx_cbcr;
458 };
459 struct v4l2_ctrl *rotate;
460 struct v4l2_ctrl *hflip;
461 struct v4l2_ctrl *vflip;
462 struct v4l2_ctrl *alpha;
463 bool ready;
464 };
465
466 /**
467 * fimc_ctx - the device context data
468 * @s_frame: source frame properties
469 * @d_frame: destination frame properties
470 * @out_order_1p: output 1-plane YCBCR order
471 * @out_order_2p: output 2-plane YCBCR order
472 * @in_order_1p input 1-plane YCBCR order
473 * @in_order_2p: input 2-plane YCBCR order
474 * @in_path: input mode (DMA or camera)
475 * @out_path: output mode (DMA or FIFO)
476 * @scaler: image scaler properties
477 * @effect: image effect
478 * @rotation: image clockwise rotation in degrees
479 * @hflip: indicates image horizontal flip if set
480 * @vflip: indicates image vertical flip if set
481 * @flags: additional flags for image conversion
482 * @state: flags to keep track of user configuration
483 * @fimc_dev: the FIMC device this context applies to
484 * @fh: v4l2 file handle
485 * @ctrls: v4l2 controls structure
486 */
487 struct fimc_ctx {
488 struct fimc_frame s_frame;
489 struct fimc_frame d_frame;
490 u32 out_order_1p;
491 u32 out_order_2p;
492 u32 in_order_1p;
493 u32 in_order_2p;
494 enum fimc_datapath in_path;
495 enum fimc_datapath out_path;
496 struct fimc_scaler scaler;
497 struct fimc_effect effect;
498 int rotation;
499 unsigned int hflip:1;
500 unsigned int vflip:1;
501 u32 flags;
502 u32 state;
503 struct fimc_dev *fimc_dev;
504 struct v4l2_fh fh;
505 struct fimc_ctrls ctrls;
506 };
507
508 #define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh)
509
set_frame_bounds(struct fimc_frame * f,u32 width,u32 height)510 static inline void set_frame_bounds(struct fimc_frame *f, u32 width, u32 height)
511 {
512 f->o_width = width;
513 f->o_height = height;
514 f->f_width = width;
515 f->f_height = height;
516 }
517
set_frame_crop(struct fimc_frame * f,u32 left,u32 top,u32 width,u32 height)518 static inline void set_frame_crop(struct fimc_frame *f,
519 u32 left, u32 top, u32 width, u32 height)
520 {
521 f->offs_h = left;
522 f->offs_v = top;
523 f->width = width;
524 f->height = height;
525 }
526
fimc_get_format_depth(struct fimc_fmt * ff)527 static inline u32 fimc_get_format_depth(struct fimc_fmt *ff)
528 {
529 u32 i, depth = 0;
530
531 if (ff != NULL)
532 for (i = 0; i < ff->colplanes; i++)
533 depth += ff->depth[i];
534 return depth;
535 }
536
fimc_capture_active(struct fimc_dev * fimc)537 static inline bool fimc_capture_active(struct fimc_dev *fimc)
538 {
539 unsigned long flags;
540 bool ret;
541
542 spin_lock_irqsave(&fimc->slock, flags);
543 ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
544 fimc->state & (1 << ST_CAPT_PEND));
545 spin_unlock_irqrestore(&fimc->slock, flags);
546 return ret;
547 }
548
fimc_ctx_state_set(u32 state,struct fimc_ctx * ctx)549 static inline void fimc_ctx_state_set(u32 state, struct fimc_ctx *ctx)
550 {
551 unsigned long flags;
552
553 spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
554 ctx->state |= state;
555 spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
556 }
557
fimc_ctx_state_is_set(u32 mask,struct fimc_ctx * ctx)558 static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
559 {
560 unsigned long flags;
561 bool ret;
562
563 spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
564 ret = (ctx->state & mask) == mask;
565 spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
566 return ret;
567 }
568
tiled_fmt(struct fimc_fmt * fmt)569 static inline int tiled_fmt(struct fimc_fmt *fmt)
570 {
571 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
572 }
573
fimc_jpeg_fourcc(u32 pixelformat)574 static inline bool fimc_jpeg_fourcc(u32 pixelformat)
575 {
576 return (pixelformat == V4L2_PIX_FMT_JPEG ||
577 pixelformat == V4L2_PIX_FMT_S5C_UYVY_JPG);
578 }
579
fimc_user_defined_mbus_fmt(u32 code)580 static inline bool fimc_user_defined_mbus_fmt(u32 code)
581 {
582 return (code == MEDIA_BUS_FMT_JPEG_1X8 ||
583 code == MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8);
584 }
585
586 /* Return the alpha component bit mask */
fimc_get_alpha_mask(struct fimc_fmt * fmt)587 static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt)
588 {
589 switch (fmt->color) {
590 case FIMC_FMT_RGB444: return 0x0f;
591 case FIMC_FMT_RGB555: return 0x01;
592 case FIMC_FMT_RGB888: return 0xff;
593 default: return 0;
594 };
595 }
596
ctx_get_frame(struct fimc_ctx * ctx,enum v4l2_buf_type type)597 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
598 enum v4l2_buf_type type)
599 {
600 struct fimc_frame *frame;
601
602 if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
603 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
604 frame = &ctx->s_frame;
605 else
606 return ERR_PTR(-EINVAL);
607 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
608 frame = &ctx->d_frame;
609 } else {
610 v4l2_err(ctx->fimc_dev->v4l2_dev,
611 "Wrong buffer/video queue type (%d)\n", type);
612 return ERR_PTR(-EINVAL);
613 }
614
615 return frame;
616 }
617
618 /* -----------------------------------------------------*/
619 /* fimc-core.c */
620 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
621 struct v4l2_fmtdesc *f);
622 int fimc_ctrls_create(struct fimc_ctx *ctx);
623 void fimc_ctrls_delete(struct fimc_ctx *ctx);
624 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active);
625 void fimc_alpha_ctrl_update(struct fimc_ctx *ctx);
626 void __fimc_get_format(struct fimc_frame *frame, struct v4l2_format *f);
627 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
628 struct v4l2_pix_format_mplane *pix);
629 struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
630 unsigned int mask, int index);
631 struct fimc_fmt *fimc_get_format(unsigned int index);
632
633 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
634 int dw, int dh, int rotation);
635 int fimc_set_scaler_info(struct fimc_ctx *ctx);
636 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
637 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
638 struct fimc_frame *frame, struct fimc_addr *paddr);
639 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f);
640 void fimc_set_yuv_order(struct fimc_ctx *ctx);
641 void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf);
642
643 int fimc_register_m2m_device(struct fimc_dev *fimc,
644 struct v4l2_device *v4l2_dev);
645 void fimc_unregister_m2m_device(struct fimc_dev *fimc);
646 int fimc_register_driver(void);
647 void fimc_unregister_driver(void);
648
649 #ifdef CONFIG_MFD_SYSCON
fimc_get_sysreg_regmap(struct device_node * node)650 static inline struct regmap * fimc_get_sysreg_regmap(struct device_node *node)
651 {
652 return syscon_regmap_lookup_by_phandle(node, "samsung,sysreg");
653 }
654 #else
655 #define fimc_get_sysreg_regmap(node) (NULL)
656 #endif
657
658 /* -----------------------------------------------------*/
659 /* fimc-m2m.c */
660 void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state);
661
662 /* -----------------------------------------------------*/
663 /* fimc-capture.c */
664 int fimc_initialize_capture_subdev(struct fimc_dev *fimc);
665 void fimc_unregister_capture_subdev(struct fimc_dev *fimc);
666 int fimc_capture_ctrls_create(struct fimc_dev *fimc);
667 void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,
668 void *arg);
669 int fimc_capture_suspend(struct fimc_dev *fimc);
670 int fimc_capture_resume(struct fimc_dev *fimc);
671
672 /*
673 * Buffer list manipulation functions. Must be called with fimc.slock held.
674 */
675
676 /**
677 * fimc_active_queue_add - add buffer to the capture active buffers queue
678 * @buf: buffer to add to the active buffers list
679 */
fimc_active_queue_add(struct fimc_vid_cap * vid_cap,struct fimc_vid_buffer * buf)680 static inline void fimc_active_queue_add(struct fimc_vid_cap *vid_cap,
681 struct fimc_vid_buffer *buf)
682 {
683 list_add_tail(&buf->list, &vid_cap->active_buf_q);
684 vid_cap->active_buf_cnt++;
685 }
686
687 /**
688 * fimc_active_queue_pop - pop buffer from the capture active buffers queue
689 *
690 * The caller must assure the active_buf_q list is not empty.
691 */
fimc_active_queue_pop(struct fimc_vid_cap * vid_cap)692 static inline struct fimc_vid_buffer *fimc_active_queue_pop(
693 struct fimc_vid_cap *vid_cap)
694 {
695 struct fimc_vid_buffer *buf;
696 buf = list_entry(vid_cap->active_buf_q.next,
697 struct fimc_vid_buffer, list);
698 list_del(&buf->list);
699 vid_cap->active_buf_cnt--;
700 return buf;
701 }
702
703 /**
704 * fimc_pending_queue_add - add buffer to the capture pending buffers queue
705 * @buf: buffer to add to the pending buffers list
706 */
fimc_pending_queue_add(struct fimc_vid_cap * vid_cap,struct fimc_vid_buffer * buf)707 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
708 struct fimc_vid_buffer *buf)
709 {
710 list_add_tail(&buf->list, &vid_cap->pending_buf_q);
711 }
712
713 /**
714 * fimc_pending_queue_pop - pop buffer from the capture pending buffers queue
715 *
716 * The caller must assure the pending_buf_q list is not empty.
717 */
fimc_pending_queue_pop(struct fimc_vid_cap * vid_cap)718 static inline struct fimc_vid_buffer *fimc_pending_queue_pop(
719 struct fimc_vid_cap *vid_cap)
720 {
721 struct fimc_vid_buffer *buf;
722 buf = list_entry(vid_cap->pending_buf_q.next,
723 struct fimc_vid_buffer, list);
724 list_del(&buf->list);
725 return buf;
726 }
727
728 #endif /* FIMC_CORE_H_ */
729