1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2015 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
21
22 /* Linux PRO/1000 Ethernet Driver main header file */
23
24 #ifndef _E1000_H_
25 #define _E1000_H_
26
27 #include <linux/bitops.h>
28 #include <linux/types.h>
29 #include <linux/timer.h>
30 #include <linux/workqueue.h>
31 #include <linux/io.h>
32 #include <linux/netdevice.h>
33 #include <linux/pci.h>
34 #include <linux/pci-aspm.h>
35 #include <linux/crc32.h>
36 #include <linux/if_vlan.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/ptp_classify.h>
41 #include <linux/mii.h>
42 #include <linux/mdio.h>
43 #include <linux/pm_qos.h>
44 #include "hw.h"
45
46 struct e1000_info;
47
48 #define e_dbg(format, arg...) \
49 netdev_dbg(hw->adapter->netdev, format, ## arg)
50 #define e_err(format, arg...) \
51 netdev_err(adapter->netdev, format, ## arg)
52 #define e_info(format, arg...) \
53 netdev_info(adapter->netdev, format, ## arg)
54 #define e_warn(format, arg...) \
55 netdev_warn(adapter->netdev, format, ## arg)
56 #define e_notice(format, arg...) \
57 netdev_notice(adapter->netdev, format, ## arg)
58
59 /* Interrupt modes, as used by the IntMode parameter */
60 #define E1000E_INT_MODE_LEGACY 0
61 #define E1000E_INT_MODE_MSI 1
62 #define E1000E_INT_MODE_MSIX 2
63
64 /* Tx/Rx descriptor defines */
65 #define E1000_DEFAULT_TXD 256
66 #define E1000_MAX_TXD 4096
67 #define E1000_MIN_TXD 64
68
69 #define E1000_DEFAULT_RXD 256
70 #define E1000_MAX_RXD 4096
71 #define E1000_MIN_RXD 64
72
73 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
74 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
75
76 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
77
78 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
79 /* How many Rx Buffers do we bundle into one write to the hardware ? */
80 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
81
82 #define AUTO_ALL_MODES 0
83 #define E1000_EEPROM_APME 0x0400
84
85 #define E1000_MNG_VLAN_NONE (-1)
86
87 #define DEFAULT_JUMBO 9234
88
89 /* Time to wait before putting the device into D3 if there's no link (in ms). */
90 #define LINK_TIMEOUT 100
91
92 /* Count for polling __E1000_RESET condition every 10-20msec.
93 * Experimentation has shown the reset can take approximately 210msec.
94 */
95 #define E1000_CHECK_RESET_COUNT 25
96
97 #define DEFAULT_RDTR 0
98 #define DEFAULT_RADV 8
99 #define BURST_RDTR 0x20
100 #define BURST_RADV 0x20
101 #define PCICFG_DESC_RING_STATUS 0xe4
102 #define FLUSH_DESC_REQUIRED 0x100
103
104 /* in the case of WTHRESH, it appears at least the 82571/2 hardware
105 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
106 * WTHRESH=4, so a setting of 5 gives the most efficient bus
107 * utilization but to avoid possible Tx stalls, set it to 1
108 */
109 #define E1000_TXDCTL_DMA_BURST_ENABLE \
110 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
111 E1000_TXDCTL_COUNT_DESC | \
112 (1 << 16) | /* wthresh must be +1 more than desired */\
113 (1 << 8) | /* hthresh */ \
114 0x1f) /* pthresh */
115
116 #define E1000_RXDCTL_DMA_BURST_ENABLE \
117 (0x01000000 | /* set descriptor granularity */ \
118 (4 << 16) | /* set writeback threshold */ \
119 (4 << 8) | /* set prefetch threshold */ \
120 0x20) /* set hthresh */
121
122 #define E1000_TIDV_FPD (1 << 31)
123 #define E1000_RDTR_FPD (1 << 31)
124
125 enum e1000_boards {
126 board_82571,
127 board_82572,
128 board_82573,
129 board_82574,
130 board_82583,
131 board_80003es2lan,
132 board_ich8lan,
133 board_ich9lan,
134 board_ich10lan,
135 board_pchlan,
136 board_pch2lan,
137 board_pch_lpt,
138 board_pch_spt
139 };
140
141 struct e1000_ps_page {
142 struct page *page;
143 u64 dma; /* must be u64 - written to hw */
144 };
145
146 /* wrappers around a pointer to a socket buffer,
147 * so a DMA handle can be stored along with the buffer
148 */
149 struct e1000_buffer {
150 dma_addr_t dma;
151 struct sk_buff *skb;
152 union {
153 /* Tx */
154 struct {
155 unsigned long time_stamp;
156 u16 length;
157 u16 next_to_watch;
158 unsigned int segs;
159 unsigned int bytecount;
160 u16 mapped_as_page;
161 };
162 /* Rx */
163 struct {
164 /* arrays of page information for packet split */
165 struct e1000_ps_page *ps_pages;
166 struct page *page;
167 };
168 };
169 };
170
171 struct e1000_ring {
172 struct e1000_adapter *adapter; /* back pointer to adapter */
173 void *desc; /* pointer to ring memory */
174 dma_addr_t dma; /* phys address of ring */
175 unsigned int size; /* length of ring in bytes */
176 unsigned int count; /* number of desc. in ring */
177
178 u16 next_to_use;
179 u16 next_to_clean;
180
181 void __iomem *head;
182 void __iomem *tail;
183
184 /* array of buffer information structs */
185 struct e1000_buffer *buffer_info;
186
187 char name[IFNAMSIZ + 5];
188 u32 ims_val;
189 u32 itr_val;
190 void __iomem *itr_register;
191 int set_itr;
192
193 struct sk_buff *rx_skb_top;
194 };
195
196 /* PHY register snapshot values */
197 struct e1000_phy_regs {
198 u16 bmcr; /* basic mode control register */
199 u16 bmsr; /* basic mode status register */
200 u16 advertise; /* auto-negotiation advertisement */
201 u16 lpa; /* link partner ability register */
202 u16 expansion; /* auto-negotiation expansion reg */
203 u16 ctrl1000; /* 1000BASE-T control register */
204 u16 stat1000; /* 1000BASE-T status register */
205 u16 estatus; /* extended status register */
206 };
207
208 /* board specific private data structure */
209 struct e1000_adapter {
210 struct timer_list watchdog_timer;
211 struct timer_list phy_info_timer;
212 struct timer_list blink_timer;
213
214 struct work_struct reset_task;
215 struct work_struct watchdog_task;
216
217 const struct e1000_info *ei;
218
219 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
220 u32 bd_number;
221 u32 rx_buffer_len;
222 u16 mng_vlan_id;
223 u16 link_speed;
224 u16 link_duplex;
225 u16 eeprom_vers;
226
227 /* track device up/down/testing state */
228 unsigned long state;
229
230 /* Interrupt Throttle Rate */
231 u32 itr;
232 u32 itr_setting;
233 u16 tx_itr;
234 u16 rx_itr;
235
236 /* Tx - one ring per active queue */
237 struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;
238 u32 tx_fifo_limit;
239
240 struct napi_struct napi;
241
242 unsigned int uncorr_errors; /* uncorrectable ECC errors */
243 unsigned int corr_errors; /* correctable ECC errors */
244 unsigned int restart_queue;
245 u32 txd_cmd;
246
247 bool detect_tx_hung;
248 bool tx_hang_recheck;
249 u8 tx_timeout_factor;
250
251 u32 tx_int_delay;
252 u32 tx_abs_int_delay;
253
254 unsigned int total_tx_bytes;
255 unsigned int total_tx_packets;
256 unsigned int total_rx_bytes;
257 unsigned int total_rx_packets;
258
259 /* Tx stats */
260 u64 tpt_old;
261 u64 colc_old;
262 u32 gotc;
263 u64 gotc_old;
264 u32 tx_timeout_count;
265 u32 tx_fifo_head;
266 u32 tx_head_addr;
267 u32 tx_fifo_size;
268 u32 tx_dma_failed;
269 u32 tx_hwtstamp_timeouts;
270
271 /* Rx */
272 bool (*clean_rx)(struct e1000_ring *ring, int *work_done,
273 int work_to_do) ____cacheline_aligned_in_smp;
274 void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count,
275 gfp_t gfp);
276 struct e1000_ring *rx_ring;
277
278 u32 rx_int_delay;
279 u32 rx_abs_int_delay;
280
281 /* Rx stats */
282 u64 hw_csum_err;
283 u64 hw_csum_good;
284 u64 rx_hdr_split;
285 u32 gorc;
286 u64 gorc_old;
287 u32 alloc_rx_buff_failed;
288 u32 rx_dma_failed;
289 u32 rx_hwtstamp_cleared;
290
291 unsigned int rx_ps_pages;
292 u16 rx_ps_bsize0;
293 u32 max_frame_size;
294 u32 min_frame_size;
295
296 /* OS defined structs */
297 struct net_device *netdev;
298 struct pci_dev *pdev;
299
300 /* structs defined in e1000_hw.h */
301 struct e1000_hw hw;
302
303 spinlock_t stats64_lock; /* protects statistics counters */
304 struct e1000_hw_stats stats;
305 struct e1000_phy_info phy_info;
306 struct e1000_phy_stats phy_stats;
307
308 /* Snapshot of PHY registers */
309 struct e1000_phy_regs phy_regs;
310
311 struct e1000_ring test_tx_ring;
312 struct e1000_ring test_rx_ring;
313 u32 test_icr;
314
315 u32 msg_enable;
316 unsigned int num_vectors;
317 struct msix_entry *msix_entries;
318 int int_mode;
319 u32 eiac_mask;
320
321 u32 eeprom_wol;
322 u32 wol;
323 u32 pba;
324 u32 max_hw_frame_size;
325
326 bool fc_autoneg;
327
328 unsigned int flags;
329 unsigned int flags2;
330 struct work_struct downshift_task;
331 struct work_struct update_phy_task;
332 struct work_struct print_hang_task;
333
334 int phy_hang_count;
335
336 u16 tx_ring_count;
337 u16 rx_ring_count;
338
339 struct hwtstamp_config hwtstamp_config;
340 struct delayed_work systim_overflow_work;
341 struct sk_buff *tx_hwtstamp_skb;
342 unsigned long tx_hwtstamp_start;
343 struct work_struct tx_hwtstamp_work;
344 spinlock_t systim_lock; /* protects SYSTIML/H regsters */
345 struct cyclecounter cc;
346 struct timecounter tc;
347 struct ptp_clock *ptp_clock;
348 struct ptp_clock_info ptp_clock_info;
349 struct pm_qos_request pm_qos_req;
350
351 u16 eee_advert;
352 };
353
354 struct e1000_info {
355 enum e1000_mac_type mac;
356 unsigned int flags;
357 unsigned int flags2;
358 u32 pba;
359 u32 max_hw_frame_size;
360 s32 (*get_variants)(struct e1000_adapter *);
361 const struct e1000_mac_operations *mac_ops;
362 const struct e1000_phy_operations *phy_ops;
363 const struct e1000_nvm_operations *nvm_ops;
364 };
365
366 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
367
368 /* The system time is maintained by a 64-bit counter comprised of the 32-bit
369 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore
370 * its resolution) is based on the contents of the TIMINCA register - it
371 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
372 * For the best accuracy, the incperiod should be as small as possible. The
373 * incvalue is scaled by a factor as large as possible (while still fitting
374 * in bits 23:0) so that relatively small clock corrections can be made.
375 *
376 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
377 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
378 * bits to count nanoseconds leaving the rest for fractional nonseconds.
379 */
380 #define INCVALUE_96MHz 125
381 #define INCVALUE_SHIFT_96MHz 17
382 #define INCPERIOD_SHIFT_96MHz 2
383 #define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz)
384
385 #define INCVALUE_25MHz 40
386 #define INCVALUE_SHIFT_25MHz 18
387 #define INCPERIOD_25MHz 1
388
389 #define INCVALUE_24MHz 125
390 #define INCVALUE_SHIFT_24MHz 14
391 #define INCPERIOD_24MHz 3
392
393 /* Another drawback of scaling the incvalue by a large factor is the
394 * 64-bit SYSTIM register overflows more quickly. This is dealt with
395 * by simply reading the clock before it overflows.
396 *
397 * Clock ns bits Overflows after
398 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~
399 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
400 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours
401 */
402 #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4)
403 #define E1000_MAX_82574_SYSTIM_REREADS 50
404 #define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL)
405
406 /* hardware capability, feature, and workaround flags */
407 #define FLAG_HAS_AMT (1 << 0)
408 #define FLAG_HAS_FLASH (1 << 1)
409 #define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
410 #define FLAG_HAS_WOL (1 << 3)
411 /* reserved bit4 */
412 #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
413 #define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
414 #define FLAG_HAS_JUMBO_FRAMES (1 << 7)
415 #define FLAG_READ_ONLY_NVM (1 << 8)
416 #define FLAG_IS_ICH (1 << 9)
417 #define FLAG_HAS_MSIX (1 << 10)
418 #define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
419 #define FLAG_IS_QUAD_PORT_A (1 << 12)
420 #define FLAG_IS_QUAD_PORT (1 << 13)
421 #define FLAG_HAS_HW_TIMESTAMP (1 << 14)
422 #define FLAG_APME_IN_WUC (1 << 15)
423 #define FLAG_APME_IN_CTRL3 (1 << 16)
424 #define FLAG_APME_CHECK_PORT_B (1 << 17)
425 #define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
426 #define FLAG_NO_WAKE_UCAST (1 << 19)
427 #define FLAG_MNG_PT_ENABLED (1 << 20)
428 #define FLAG_RESET_OVERWRITES_LAA (1 << 21)
429 #define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
430 #define FLAG_TARC_SET_BIT_ZERO (1 << 23)
431 #define FLAG_RX_NEEDS_RESTART (1 << 24)
432 #define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
433 #define FLAG_SMART_POWER_DOWN (1 << 26)
434 #define FLAG_MSI_ENABLED (1 << 27)
435 /* reserved (1 << 28) */
436 #define FLAG_TSO_FORCE (1 << 29)
437 #define FLAG_RESTART_NOW (1 << 30)
438 #define FLAG_MSI_TEST_FAILED (1 << 31)
439
440 #define FLAG2_CRC_STRIPPING (1 << 0)
441 #define FLAG2_HAS_PHY_WAKEUP (1 << 1)
442 #define FLAG2_IS_DISCARDING (1 << 2)
443 #define FLAG2_DISABLE_ASPM_L1 (1 << 3)
444 #define FLAG2_HAS_PHY_STATS (1 << 4)
445 #define FLAG2_HAS_EEE (1 << 5)
446 #define FLAG2_DMA_BURST (1 << 6)
447 #define FLAG2_DISABLE_ASPM_L0S (1 << 7)
448 #define FLAG2_DISABLE_AIM (1 << 8)
449 #define FLAG2_CHECK_PHY_HANG (1 << 9)
450 #define FLAG2_NO_DISABLE_RX (1 << 10)
451 #define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11)
452 #define FLAG2_DFLT_CRC_STRIPPING (1 << 12)
453 #define FLAG2_CHECK_RX_HWTSTAMP (1 << 13)
454
455 #define E1000_RX_DESC_PS(R, i) \
456 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
457 #define E1000_RX_DESC_EXT(R, i) \
458 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
459 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
460 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
461 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
462
463 enum e1000_state_t {
464 __E1000_TESTING,
465 __E1000_RESETTING,
466 __E1000_ACCESS_SHARED_RESOURCE,
467 __E1000_DOWN
468 };
469
470 enum latency_range {
471 lowest_latency = 0,
472 low_latency = 1,
473 bulk_latency = 2,
474 latency_invalid = 255
475 };
476
477 extern char e1000e_driver_name[];
478 extern const char e1000e_driver_version[];
479
480 void e1000e_check_options(struct e1000_adapter *adapter);
481 void e1000e_set_ethtool_ops(struct net_device *netdev);
482
483 int e1000e_up(struct e1000_adapter *adapter);
484 void e1000e_down(struct e1000_adapter *adapter, bool reset);
485 void e1000e_reinit_locked(struct e1000_adapter *adapter);
486 void e1000e_reset(struct e1000_adapter *adapter);
487 void e1000e_power_up_phy(struct e1000_adapter *adapter);
488 int e1000e_setup_rx_resources(struct e1000_ring *ring);
489 int e1000e_setup_tx_resources(struct e1000_ring *ring);
490 void e1000e_free_rx_resources(struct e1000_ring *ring);
491 void e1000e_free_tx_resources(struct e1000_ring *ring);
492 struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
493 struct rtnl_link_stats64 *stats);
494 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
495 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
496 void e1000e_get_hw_control(struct e1000_adapter *adapter);
497 void e1000e_release_hw_control(struct e1000_adapter *adapter);
498 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
499
500 extern unsigned int copybreak;
501
502 extern const struct e1000_info e1000_82571_info;
503 extern const struct e1000_info e1000_82572_info;
504 extern const struct e1000_info e1000_82573_info;
505 extern const struct e1000_info e1000_82574_info;
506 extern const struct e1000_info e1000_82583_info;
507 extern const struct e1000_info e1000_ich8_info;
508 extern const struct e1000_info e1000_ich9_info;
509 extern const struct e1000_info e1000_ich10_info;
510 extern const struct e1000_info e1000_pch_info;
511 extern const struct e1000_info e1000_pch2_info;
512 extern const struct e1000_info e1000_pch_lpt_info;
513 extern const struct e1000_info e1000_pch_spt_info;
514 extern const struct e1000_info e1000_es2_info;
515
516 void e1000e_ptp_init(struct e1000_adapter *adapter);
517 void e1000e_ptp_remove(struct e1000_adapter *adapter);
518
e1000_phy_hw_reset(struct e1000_hw * hw)519 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
520 {
521 return hw->phy.ops.reset(hw);
522 }
523
e1e_rphy(struct e1000_hw * hw,u32 offset,u16 * data)524 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
525 {
526 return hw->phy.ops.read_reg(hw, offset, data);
527 }
528
e1e_rphy_locked(struct e1000_hw * hw,u32 offset,u16 * data)529 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
530 {
531 return hw->phy.ops.read_reg_locked(hw, offset, data);
532 }
533
e1e_wphy(struct e1000_hw * hw,u32 offset,u16 data)534 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
535 {
536 return hw->phy.ops.write_reg(hw, offset, data);
537 }
538
e1e_wphy_locked(struct e1000_hw * hw,u32 offset,u16 data)539 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
540 {
541 return hw->phy.ops.write_reg_locked(hw, offset, data);
542 }
543
544 void e1000e_reload_nvm_generic(struct e1000_hw *hw);
545
e1000e_read_mac_addr(struct e1000_hw * hw)546 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
547 {
548 if (hw->mac.ops.read_mac_addr)
549 return hw->mac.ops.read_mac_addr(hw);
550
551 return e1000_read_mac_addr_generic(hw);
552 }
553
e1000_validate_nvm_checksum(struct e1000_hw * hw)554 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
555 {
556 return hw->nvm.ops.validate(hw);
557 }
558
e1000e_update_nvm_checksum(struct e1000_hw * hw)559 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
560 {
561 return hw->nvm.ops.update(hw);
562 }
563
e1000_read_nvm(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)564 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,
565 u16 *data)
566 {
567 return hw->nvm.ops.read(hw, offset, words, data);
568 }
569
e1000_write_nvm(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)570 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
571 u16 *data)
572 {
573 return hw->nvm.ops.write(hw, offset, words, data);
574 }
575
e1000_get_phy_info(struct e1000_hw * hw)576 static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
577 {
578 return hw->phy.ops.get_info(hw);
579 }
580
__er32(struct e1000_hw * hw,unsigned long reg)581 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
582 {
583 return readl(hw->hw_addr + reg);
584 }
585
586 #define er32(reg) __er32(hw, E1000_##reg)
587
588 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val);
589
590 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
591
592 #define e1e_flush() er32(STATUS)
593
594 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
595 (__ew32((a), (reg + ((offset) << 2)), (value)))
596
597 #define E1000_READ_REG_ARRAY(a, reg, offset) \
598 (readl((a)->hw_addr + reg + ((offset) << 2)))
599
600 #endif /* _E1000_H_ */
601