1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2009-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef _T4FW_INTERFACE_H_ 36 #define _T4FW_INTERFACE_H_ 37 38 enum fw_retval { 39 FW_SUCCESS = 0, /* completed successfully */ 40 FW_EPERM = 1, /* operation not permitted */ 41 FW_ENOENT = 2, /* no such file or directory */ 42 FW_EIO = 5, /* input/output error; hw bad */ 43 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 44 FW_EAGAIN = 11, /* try again */ 45 FW_ENOMEM = 12, /* out of memory */ 46 FW_EFAULT = 14, /* bad address; fw bad */ 47 FW_EBUSY = 16, /* resource busy */ 48 FW_EEXIST = 17, /* file exists */ 49 FW_ENODEV = 19, /* no such device */ 50 FW_EINVAL = 22, /* invalid argument */ 51 FW_ENOSPC = 28, /* no space left on device */ 52 FW_ENOSYS = 38, /* functionality not implemented */ 53 FW_ENODATA = 61, /* no data available */ 54 FW_EPROTO = 71, /* protocol error */ 55 FW_EADDRINUSE = 98, /* address already in use */ 56 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 57 FW_ENETDOWN = 100, /* network is down */ 58 FW_ENETUNREACH = 101, /* network is unreachable */ 59 FW_ENOBUFS = 105, /* no buffer space available */ 60 FW_ETIMEDOUT = 110, /* timeout */ 61 FW_EINPROGRESS = 115, /* fw internal */ 62 FW_SCSI_ABORT_REQUESTED = 128, /* */ 63 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 64 FW_SCSI_ABORTED = 130, /* */ 65 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 66 FW_ERR_LINK_DOWN = 132, /* */ 67 FW_RDEV_NOT_READY = 133, /* */ 68 FW_ERR_RDEV_LOST = 134, /* */ 69 FW_ERR_RDEV_LOGO = 135, /* */ 70 FW_FCOE_NO_XCHG = 136, /* */ 71 FW_SCSI_RSP_ERR = 137, /* */ 72 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 73 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 74 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 75 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 76 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 77 }; 78 79 #define FW_T4VF_SGE_BASE_ADDR 0x0000 80 #define FW_T4VF_MPS_BASE_ADDR 0x0100 81 #define FW_T4VF_PL_BASE_ADDR 0x0200 82 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 83 #define FW_T4VF_CIM_BASE_ADDR 0x0300 84 85 enum fw_wr_opcodes { 86 FW_FILTER_WR = 0x02, 87 FW_ULPTX_WR = 0x04, 88 FW_TP_WR = 0x05, 89 FW_ETH_TX_PKT_WR = 0x08, 90 FW_OFLD_CONNECTION_WR = 0x2f, 91 FW_FLOWC_WR = 0x0a, 92 FW_OFLD_TX_DATA_WR = 0x0b, 93 FW_CMD_WR = 0x10, 94 FW_ETH_TX_PKT_VM_WR = 0x11, 95 FW_RI_RES_WR = 0x0c, 96 FW_RI_INIT_WR = 0x0d, 97 FW_RI_RDMA_WRITE_WR = 0x14, 98 FW_RI_SEND_WR = 0x15, 99 FW_RI_RDMA_READ_WR = 0x16, 100 FW_RI_RECV_WR = 0x17, 101 FW_RI_BIND_MW_WR = 0x18, 102 FW_RI_FR_NSMR_WR = 0x19, 103 FW_RI_INV_LSTAG_WR = 0x1a, 104 FW_LASTC2E_WR = 0x70 105 }; 106 107 struct fw_wr_hdr { 108 __be32 hi; 109 __be32 lo; 110 }; 111 112 /* work request opcode (hi) */ 113 #define FW_WR_OP_S 24 114 #define FW_WR_OP_M 0xff 115 #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S) 116 #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M) 117 118 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ 119 #define FW_WR_ATOMIC_S 23 120 #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S) 121 122 /* flush flag (hi) - firmware flushes flushable work request buffered 123 * in the flow context. 124 */ 125 #define FW_WR_FLUSH_S 22 126 #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S) 127 128 /* completion flag (hi) - firmware generates a cpl_fw6_ack */ 129 #define FW_WR_COMPL_S 21 130 #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S) 131 #define FW_WR_COMPL_F FW_WR_COMPL_V(1U) 132 133 /* work request immediate data length (hi) */ 134 #define FW_WR_IMMDLEN_S 0 135 #define FW_WR_IMMDLEN_M 0xff 136 #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S) 137 138 /* egress queue status update to associated ingress queue entry (lo) */ 139 #define FW_WR_EQUIQ_S 31 140 #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S) 141 #define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U) 142 143 /* egress queue status update to egress queue status entry (lo) */ 144 #define FW_WR_EQUEQ_S 30 145 #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S) 146 #define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U) 147 148 /* flow context identifier (lo) */ 149 #define FW_WR_FLOWID_S 8 150 #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S) 151 152 /* length in units of 16-bytes (lo) */ 153 #define FW_WR_LEN16_S 0 154 #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S) 155 156 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 157 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 158 159 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 160 enum fw_filter_wr_cookie { 161 FW_FILTER_WR_SUCCESS, 162 FW_FILTER_WR_FLT_ADDED, 163 FW_FILTER_WR_FLT_DELETED, 164 FW_FILTER_WR_SMT_TBL_FULL, 165 FW_FILTER_WR_EINVAL, 166 }; 167 168 struct fw_filter_wr { 169 __be32 op_pkd; 170 __be32 len16_pkd; 171 __be64 r3; 172 __be32 tid_to_iq; 173 __be32 del_filter_to_l2tix; 174 __be16 ethtype; 175 __be16 ethtypem; 176 __u8 frag_to_ovlan_vldm; 177 __u8 smac_sel; 178 __be16 rx_chan_rx_rpl_iq; 179 __be32 maci_to_matchtypem; 180 __u8 ptcl; 181 __u8 ptclm; 182 __u8 ttyp; 183 __u8 ttypm; 184 __be16 ivlan; 185 __be16 ivlanm; 186 __be16 ovlan; 187 __be16 ovlanm; 188 __u8 lip[16]; 189 __u8 lipm[16]; 190 __u8 fip[16]; 191 __u8 fipm[16]; 192 __be16 lp; 193 __be16 lpm; 194 __be16 fp; 195 __be16 fpm; 196 __be16 r7; 197 __u8 sma[6]; 198 }; 199 200 #define FW_FILTER_WR_TID_S 12 201 #define FW_FILTER_WR_TID_M 0xfffff 202 #define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S) 203 #define FW_FILTER_WR_TID_G(x) \ 204 (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M) 205 206 #define FW_FILTER_WR_RQTYPE_S 11 207 #define FW_FILTER_WR_RQTYPE_M 0x1 208 #define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S) 209 #define FW_FILTER_WR_RQTYPE_G(x) \ 210 (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M) 211 #define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U) 212 213 #define FW_FILTER_WR_NOREPLY_S 10 214 #define FW_FILTER_WR_NOREPLY_M 0x1 215 #define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S) 216 #define FW_FILTER_WR_NOREPLY_G(x) \ 217 (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M) 218 #define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U) 219 220 #define FW_FILTER_WR_IQ_S 0 221 #define FW_FILTER_WR_IQ_M 0x3ff 222 #define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S) 223 #define FW_FILTER_WR_IQ_G(x) \ 224 (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M) 225 226 #define FW_FILTER_WR_DEL_FILTER_S 31 227 #define FW_FILTER_WR_DEL_FILTER_M 0x1 228 #define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S) 229 #define FW_FILTER_WR_DEL_FILTER_G(x) \ 230 (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M) 231 #define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U) 232 233 #define FW_FILTER_WR_RPTTID_S 25 234 #define FW_FILTER_WR_RPTTID_M 0x1 235 #define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S) 236 #define FW_FILTER_WR_RPTTID_G(x) \ 237 (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M) 238 #define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U) 239 240 #define FW_FILTER_WR_DROP_S 24 241 #define FW_FILTER_WR_DROP_M 0x1 242 #define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S) 243 #define FW_FILTER_WR_DROP_G(x) \ 244 (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M) 245 #define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U) 246 247 #define FW_FILTER_WR_DIRSTEER_S 23 248 #define FW_FILTER_WR_DIRSTEER_M 0x1 249 #define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S) 250 #define FW_FILTER_WR_DIRSTEER_G(x) \ 251 (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M) 252 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U) 253 254 #define FW_FILTER_WR_MASKHASH_S 22 255 #define FW_FILTER_WR_MASKHASH_M 0x1 256 #define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S) 257 #define FW_FILTER_WR_MASKHASH_G(x) \ 258 (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M) 259 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U) 260 261 #define FW_FILTER_WR_DIRSTEERHASH_S 21 262 #define FW_FILTER_WR_DIRSTEERHASH_M 0x1 263 #define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S) 264 #define FW_FILTER_WR_DIRSTEERHASH_G(x) \ 265 (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M) 266 #define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U) 267 268 #define FW_FILTER_WR_LPBK_S 20 269 #define FW_FILTER_WR_LPBK_M 0x1 270 #define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S) 271 #define FW_FILTER_WR_LPBK_G(x) \ 272 (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M) 273 #define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U) 274 275 #define FW_FILTER_WR_DMAC_S 19 276 #define FW_FILTER_WR_DMAC_M 0x1 277 #define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S) 278 #define FW_FILTER_WR_DMAC_G(x) \ 279 (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M) 280 #define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U) 281 282 #define FW_FILTER_WR_SMAC_S 18 283 #define FW_FILTER_WR_SMAC_M 0x1 284 #define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S) 285 #define FW_FILTER_WR_SMAC_G(x) \ 286 (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M) 287 #define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U) 288 289 #define FW_FILTER_WR_INSVLAN_S 17 290 #define FW_FILTER_WR_INSVLAN_M 0x1 291 #define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S) 292 #define FW_FILTER_WR_INSVLAN_G(x) \ 293 (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M) 294 #define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U) 295 296 #define FW_FILTER_WR_RMVLAN_S 16 297 #define FW_FILTER_WR_RMVLAN_M 0x1 298 #define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S) 299 #define FW_FILTER_WR_RMVLAN_G(x) \ 300 (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M) 301 #define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U) 302 303 #define FW_FILTER_WR_HITCNTS_S 15 304 #define FW_FILTER_WR_HITCNTS_M 0x1 305 #define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S) 306 #define FW_FILTER_WR_HITCNTS_G(x) \ 307 (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M) 308 #define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U) 309 310 #define FW_FILTER_WR_TXCHAN_S 13 311 #define FW_FILTER_WR_TXCHAN_M 0x3 312 #define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S) 313 #define FW_FILTER_WR_TXCHAN_G(x) \ 314 (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M) 315 316 #define FW_FILTER_WR_PRIO_S 12 317 #define FW_FILTER_WR_PRIO_M 0x1 318 #define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S) 319 #define FW_FILTER_WR_PRIO_G(x) \ 320 (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M) 321 #define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U) 322 323 #define FW_FILTER_WR_L2TIX_S 0 324 #define FW_FILTER_WR_L2TIX_M 0xfff 325 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S) 326 #define FW_FILTER_WR_L2TIX_G(x) \ 327 (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M) 328 329 #define FW_FILTER_WR_FRAG_S 7 330 #define FW_FILTER_WR_FRAG_M 0x1 331 #define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S) 332 #define FW_FILTER_WR_FRAG_G(x) \ 333 (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M) 334 #define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U) 335 336 #define FW_FILTER_WR_FRAGM_S 6 337 #define FW_FILTER_WR_FRAGM_M 0x1 338 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S) 339 #define FW_FILTER_WR_FRAGM_G(x) \ 340 (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M) 341 #define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U) 342 343 #define FW_FILTER_WR_IVLAN_VLD_S 5 344 #define FW_FILTER_WR_IVLAN_VLD_M 0x1 345 #define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S) 346 #define FW_FILTER_WR_IVLAN_VLD_G(x) \ 347 (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M) 348 #define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U) 349 350 #define FW_FILTER_WR_OVLAN_VLD_S 4 351 #define FW_FILTER_WR_OVLAN_VLD_M 0x1 352 #define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S) 353 #define FW_FILTER_WR_OVLAN_VLD_G(x) \ 354 (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M) 355 #define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U) 356 357 #define FW_FILTER_WR_IVLAN_VLDM_S 3 358 #define FW_FILTER_WR_IVLAN_VLDM_M 0x1 359 #define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S) 360 #define FW_FILTER_WR_IVLAN_VLDM_G(x) \ 361 (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M) 362 #define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U) 363 364 #define FW_FILTER_WR_OVLAN_VLDM_S 2 365 #define FW_FILTER_WR_OVLAN_VLDM_M 0x1 366 #define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S) 367 #define FW_FILTER_WR_OVLAN_VLDM_G(x) \ 368 (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M) 369 #define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U) 370 371 #define FW_FILTER_WR_RX_CHAN_S 15 372 #define FW_FILTER_WR_RX_CHAN_M 0x1 373 #define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S) 374 #define FW_FILTER_WR_RX_CHAN_G(x) \ 375 (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M) 376 #define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U) 377 378 #define FW_FILTER_WR_RX_RPL_IQ_S 0 379 #define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff 380 #define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S) 381 #define FW_FILTER_WR_RX_RPL_IQ_G(x) \ 382 (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M) 383 384 #define FW_FILTER_WR_MACI_S 23 385 #define FW_FILTER_WR_MACI_M 0x1ff 386 #define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S) 387 #define FW_FILTER_WR_MACI_G(x) \ 388 (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M) 389 390 #define FW_FILTER_WR_MACIM_S 14 391 #define FW_FILTER_WR_MACIM_M 0x1ff 392 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S) 393 #define FW_FILTER_WR_MACIM_G(x) \ 394 (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M) 395 396 #define FW_FILTER_WR_FCOE_S 13 397 #define FW_FILTER_WR_FCOE_M 0x1 398 #define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S) 399 #define FW_FILTER_WR_FCOE_G(x) \ 400 (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M) 401 #define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U) 402 403 #define FW_FILTER_WR_FCOEM_S 12 404 #define FW_FILTER_WR_FCOEM_M 0x1 405 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S) 406 #define FW_FILTER_WR_FCOEM_G(x) \ 407 (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M) 408 #define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U) 409 410 #define FW_FILTER_WR_PORT_S 9 411 #define FW_FILTER_WR_PORT_M 0x7 412 #define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S) 413 #define FW_FILTER_WR_PORT_G(x) \ 414 (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M) 415 416 #define FW_FILTER_WR_PORTM_S 6 417 #define FW_FILTER_WR_PORTM_M 0x7 418 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S) 419 #define FW_FILTER_WR_PORTM_G(x) \ 420 (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M) 421 422 #define FW_FILTER_WR_MATCHTYPE_S 3 423 #define FW_FILTER_WR_MATCHTYPE_M 0x7 424 #define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S) 425 #define FW_FILTER_WR_MATCHTYPE_G(x) \ 426 (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M) 427 428 #define FW_FILTER_WR_MATCHTYPEM_S 0 429 #define FW_FILTER_WR_MATCHTYPEM_M 0x7 430 #define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S) 431 #define FW_FILTER_WR_MATCHTYPEM_G(x) \ 432 (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M) 433 434 struct fw_ulptx_wr { 435 __be32 op_to_compl; 436 __be32 flowid_len16; 437 u64 cookie; 438 }; 439 440 struct fw_tp_wr { 441 __be32 op_to_immdlen; 442 __be32 flowid_len16; 443 u64 cookie; 444 }; 445 446 struct fw_eth_tx_pkt_wr { 447 __be32 op_immdlen; 448 __be32 equiq_to_len16; 449 __be64 r3; 450 }; 451 452 struct fw_ofld_connection_wr { 453 __be32 op_compl; 454 __be32 len16_pkd; 455 __u64 cookie; 456 __be64 r2; 457 __be64 r3; 458 struct fw_ofld_connection_le { 459 __be32 version_cpl; 460 __be32 filter; 461 __be32 r1; 462 __be16 lport; 463 __be16 pport; 464 union fw_ofld_connection_leip { 465 struct fw_ofld_connection_le_ipv4 { 466 __be32 pip; 467 __be32 lip; 468 __be64 r0; 469 __be64 r1; 470 __be64 r2; 471 } ipv4; 472 struct fw_ofld_connection_le_ipv6 { 473 __be64 pip_hi; 474 __be64 pip_lo; 475 __be64 lip_hi; 476 __be64 lip_lo; 477 } ipv6; 478 } u; 479 } le; 480 struct fw_ofld_connection_tcb { 481 __be32 t_state_to_astid; 482 __be16 cplrxdataack_cplpassacceptrpl; 483 __be16 rcv_adv; 484 __be32 rcv_nxt; 485 __be32 tx_max; 486 __be64 opt0; 487 __be32 opt2; 488 __be32 r1; 489 __be64 r2; 490 __be64 r3; 491 } tcb; 492 }; 493 494 #define FW_OFLD_CONNECTION_WR_VERSION_S 31 495 #define FW_OFLD_CONNECTION_WR_VERSION_M 0x1 496 #define FW_OFLD_CONNECTION_WR_VERSION_V(x) \ 497 ((x) << FW_OFLD_CONNECTION_WR_VERSION_S) 498 #define FW_OFLD_CONNECTION_WR_VERSION_G(x) \ 499 (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \ 500 FW_OFLD_CONNECTION_WR_VERSION_M) 501 #define FW_OFLD_CONNECTION_WR_VERSION_F \ 502 FW_OFLD_CONNECTION_WR_VERSION_V(1U) 503 504 #define FW_OFLD_CONNECTION_WR_CPL_S 30 505 #define FW_OFLD_CONNECTION_WR_CPL_M 0x1 506 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S) 507 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \ 508 (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M) 509 #define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U) 510 511 #define FW_OFLD_CONNECTION_WR_T_STATE_S 28 512 #define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf 513 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \ 514 ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S) 515 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \ 516 (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \ 517 FW_OFLD_CONNECTION_WR_T_STATE_M) 518 519 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24 520 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf 521 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \ 522 ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S) 523 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \ 524 (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \ 525 FW_OFLD_CONNECTION_WR_RCV_SCALE_M) 526 527 #define FW_OFLD_CONNECTION_WR_ASTID_S 0 528 #define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff 529 #define FW_OFLD_CONNECTION_WR_ASTID_V(x) \ 530 ((x) << FW_OFLD_CONNECTION_WR_ASTID_S) 531 #define FW_OFLD_CONNECTION_WR_ASTID_G(x) \ 532 (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M) 533 534 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15 535 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1 536 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \ 537 ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) 538 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \ 539 (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \ 540 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M) 541 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \ 542 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U) 543 544 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14 545 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1 546 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \ 547 ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) 548 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \ 549 (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \ 550 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M) 551 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \ 552 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U) 553 554 enum fw_flowc_mnem { 555 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 556 FW_FLOWC_MNEM_CH, 557 FW_FLOWC_MNEM_PORT, 558 FW_FLOWC_MNEM_IQID, 559 FW_FLOWC_MNEM_SNDNXT, 560 FW_FLOWC_MNEM_RCVNXT, 561 FW_FLOWC_MNEM_SNDBUF, 562 FW_FLOWC_MNEM_MSS, 563 FW_FLOWC_MNEM_TXDATAPLEN_MAX, 564 }; 565 566 struct fw_flowc_mnemval { 567 u8 mnemonic; 568 u8 r4[3]; 569 __be32 val; 570 }; 571 572 struct fw_flowc_wr { 573 __be32 op_to_nparams; 574 __be32 flowid_len16; 575 struct fw_flowc_mnemval mnemval[0]; 576 }; 577 578 #define FW_FLOWC_WR_NPARAMS_S 0 579 #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S) 580 581 struct fw_ofld_tx_data_wr { 582 __be32 op_to_immdlen; 583 __be32 flowid_len16; 584 __be32 plen; 585 __be32 tunnel_to_proxy; 586 }; 587 588 #define FW_OFLD_TX_DATA_WR_TUNNEL_S 19 589 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S) 590 591 #define FW_OFLD_TX_DATA_WR_SAVE_S 18 592 #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S) 593 594 #define FW_OFLD_TX_DATA_WR_FLUSH_S 17 595 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S) 596 #define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U) 597 598 #define FW_OFLD_TX_DATA_WR_URGENT_S 16 599 #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S) 600 601 #define FW_OFLD_TX_DATA_WR_MORE_S 15 602 #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S) 603 604 #define FW_OFLD_TX_DATA_WR_SHOVE_S 14 605 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S) 606 #define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U) 607 608 #define FW_OFLD_TX_DATA_WR_ULPMODE_S 10 609 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S) 610 611 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6 612 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \ 613 ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S) 614 615 struct fw_cmd_wr { 616 __be32 op_dma; 617 __be32 len16_pkd; 618 __be64 cookie_daddr; 619 }; 620 621 #define FW_CMD_WR_DMA_S 17 622 #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S) 623 624 struct fw_eth_tx_pkt_vm_wr { 625 __be32 op_immdlen; 626 __be32 equiq_to_len16; 627 __be32 r3[2]; 628 u8 ethmacdst[6]; 629 u8 ethmacsrc[6]; 630 __be16 ethtype; 631 __be16 vlantci; 632 }; 633 634 #define FW_CMD_MAX_TIMEOUT 10000 635 636 /* 637 * If a host driver does a HELLO and discovers that there's already a MASTER 638 * selected, we may have to wait for that MASTER to finish issuing RESET, 639 * configuration and INITIALIZE commands. Also, there's a possibility that 640 * our own HELLO may get lost if it happens right as the MASTER is issuign a 641 * RESET command, so we need to be willing to make a few retries of our HELLO. 642 */ 643 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 644 #define FW_CMD_HELLO_RETRIES 3 645 646 647 enum fw_cmd_opcodes { 648 FW_LDST_CMD = 0x01, 649 FW_RESET_CMD = 0x03, 650 FW_HELLO_CMD = 0x04, 651 FW_BYE_CMD = 0x05, 652 FW_INITIALIZE_CMD = 0x06, 653 FW_CAPS_CONFIG_CMD = 0x07, 654 FW_PARAMS_CMD = 0x08, 655 FW_PFVF_CMD = 0x09, 656 FW_IQ_CMD = 0x10, 657 FW_EQ_MNGT_CMD = 0x11, 658 FW_EQ_ETH_CMD = 0x12, 659 FW_EQ_CTRL_CMD = 0x13, 660 FW_EQ_OFLD_CMD = 0x21, 661 FW_VI_CMD = 0x14, 662 FW_VI_MAC_CMD = 0x15, 663 FW_VI_RXMODE_CMD = 0x16, 664 FW_VI_ENABLE_CMD = 0x17, 665 FW_ACL_MAC_CMD = 0x18, 666 FW_ACL_VLAN_CMD = 0x19, 667 FW_VI_STATS_CMD = 0x1a, 668 FW_PORT_CMD = 0x1b, 669 FW_PORT_STATS_CMD = 0x1c, 670 FW_PORT_LB_STATS_CMD = 0x1d, 671 FW_PORT_TRACE_CMD = 0x1e, 672 FW_PORT_TRACE_MMAP_CMD = 0x1f, 673 FW_RSS_IND_TBL_CMD = 0x20, 674 FW_RSS_GLB_CONFIG_CMD = 0x22, 675 FW_RSS_VI_CONFIG_CMD = 0x23, 676 FW_DEVLOG_CMD = 0x25, 677 FW_CLIP_CMD = 0x28, 678 FW_LASTC2E_CMD = 0x40, 679 FW_ERROR_CMD = 0x80, 680 FW_DEBUG_CMD = 0x81, 681 }; 682 683 enum fw_cmd_cap { 684 FW_CMD_CAP_PF = 0x01, 685 FW_CMD_CAP_DMAQ = 0x02, 686 FW_CMD_CAP_PORT = 0x04, 687 FW_CMD_CAP_PORTPROMISC = 0x08, 688 FW_CMD_CAP_PORTSTATS = 0x10, 689 FW_CMD_CAP_VF = 0x80, 690 }; 691 692 /* 693 * Generic command header flit0 694 */ 695 struct fw_cmd_hdr { 696 __be32 hi; 697 __be32 lo; 698 }; 699 700 #define FW_CMD_OP_S 24 701 #define FW_CMD_OP_M 0xff 702 #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S) 703 #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M) 704 705 #define FW_CMD_REQUEST_S 23 706 #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S) 707 #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U) 708 709 #define FW_CMD_READ_S 22 710 #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S) 711 #define FW_CMD_READ_F FW_CMD_READ_V(1U) 712 713 #define FW_CMD_WRITE_S 21 714 #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S) 715 #define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U) 716 717 #define FW_CMD_EXEC_S 20 718 #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S) 719 #define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U) 720 721 #define FW_CMD_RAMASK_S 20 722 #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S) 723 724 #define FW_CMD_RETVAL_S 8 725 #define FW_CMD_RETVAL_M 0xff 726 #define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S) 727 #define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M) 728 729 #define FW_CMD_LEN16_S 0 730 #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S) 731 732 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 733 734 enum fw_ldst_addrspc { 735 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 736 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 737 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 738 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 739 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 740 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 741 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 742 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 743 FW_LDST_ADDRSPC_MDIO = 0x0018, 744 FW_LDST_ADDRSPC_MPS = 0x0020, 745 FW_LDST_ADDRSPC_FUNC = 0x0028, 746 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 747 }; 748 749 enum fw_ldst_mps_fid { 750 FW_LDST_MPS_ATRB, 751 FW_LDST_MPS_RPLC 752 }; 753 754 enum fw_ldst_func_access_ctl { 755 FW_LDST_FUNC_ACC_CTL_VIID, 756 FW_LDST_FUNC_ACC_CTL_FID 757 }; 758 759 enum fw_ldst_func_mod_index { 760 FW_LDST_FUNC_MPS 761 }; 762 763 struct fw_ldst_cmd { 764 __be32 op_to_addrspace; 765 __be32 cycles_to_len16; 766 union fw_ldst { 767 struct fw_ldst_addrval { 768 __be32 addr; 769 __be32 val; 770 } addrval; 771 struct fw_ldst_idctxt { 772 __be32 physid; 773 __be32 msg_ctxtflush; 774 __be32 ctxt_data7; 775 __be32 ctxt_data6; 776 __be32 ctxt_data5; 777 __be32 ctxt_data4; 778 __be32 ctxt_data3; 779 __be32 ctxt_data2; 780 __be32 ctxt_data1; 781 __be32 ctxt_data0; 782 } idctxt; 783 struct fw_ldst_mdio { 784 __be16 paddr_mmd; 785 __be16 raddr; 786 __be16 vctl; 787 __be16 rval; 788 } mdio; 789 struct fw_ldst_cim_rq { 790 u8 req_first64[8]; 791 u8 req_second64[8]; 792 u8 resp_first64[8]; 793 u8 resp_second64[8]; 794 __be32 r3[2]; 795 } cim_rq; 796 union fw_ldst_mps { 797 struct fw_ldst_mps_rplc { 798 __be16 fid_idx; 799 __be16 rplcpf_pkd; 800 __be32 rplc255_224; 801 __be32 rplc223_192; 802 __be32 rplc191_160; 803 __be32 rplc159_128; 804 __be32 rplc127_96; 805 __be32 rplc95_64; 806 __be32 rplc63_32; 807 __be32 rplc31_0; 808 } rplc; 809 struct fw_ldst_mps_atrb { 810 __be16 fid_mpsid; 811 __be16 r2[3]; 812 __be32 r3[2]; 813 __be32 r4; 814 __be32 atrb; 815 __be16 vlan[16]; 816 } atrb; 817 } mps; 818 struct fw_ldst_func { 819 u8 access_ctl; 820 u8 mod_index; 821 __be16 ctl_id; 822 __be32 offset; 823 __be64 data0; 824 __be64 data1; 825 } func; 826 struct fw_ldst_pcie { 827 u8 ctrl_to_fn; 828 u8 bnum; 829 u8 r; 830 u8 ext_r; 831 u8 select_naccess; 832 u8 pcie_fn; 833 __be16 nset_pkd; 834 __be32 data[12]; 835 } pcie; 836 struct fw_ldst_i2c_deprecated { 837 u8 pid_pkd; 838 u8 base; 839 u8 boffset; 840 u8 data; 841 __be32 r9; 842 } i2c_deprecated; 843 struct fw_ldst_i2c { 844 u8 pid; 845 u8 did; 846 u8 boffset; 847 u8 blen; 848 __be32 r9; 849 __u8 data[48]; 850 } i2c; 851 struct fw_ldst_le { 852 __be32 index; 853 __be32 r9; 854 u8 val[33]; 855 u8 r11[7]; 856 } le; 857 } u; 858 }; 859 860 #define FW_LDST_CMD_ADDRSPACE_S 0 861 #define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S) 862 863 #define FW_LDST_CMD_MSG_S 31 864 #define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S) 865 866 #define FW_LDST_CMD_CTXTFLUSH_S 30 867 #define FW_LDST_CMD_CTXTFLUSH_V(x) ((x) << FW_LDST_CMD_CTXTFLUSH_S) 868 #define FW_LDST_CMD_CTXTFLUSH_F FW_LDST_CMD_CTXTFLUSH_V(1U) 869 870 #define FW_LDST_CMD_PADDR_S 8 871 #define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S) 872 873 #define FW_LDST_CMD_MMD_S 0 874 #define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S) 875 876 #define FW_LDST_CMD_FID_S 15 877 #define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S) 878 879 #define FW_LDST_CMD_IDX_S 0 880 #define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S) 881 882 #define FW_LDST_CMD_RPLCPF_S 0 883 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S) 884 885 #define FW_LDST_CMD_LC_S 4 886 #define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S) 887 #define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U) 888 889 #define FW_LDST_CMD_FN_S 0 890 #define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S) 891 892 #define FW_LDST_CMD_NACCESS_S 0 893 #define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S) 894 895 struct fw_reset_cmd { 896 __be32 op_to_write; 897 __be32 retval_len16; 898 __be32 val; 899 __be32 halt_pkd; 900 }; 901 902 #define FW_RESET_CMD_HALT_S 31 903 #define FW_RESET_CMD_HALT_M 0x1 904 #define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S) 905 #define FW_RESET_CMD_HALT_G(x) \ 906 (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M) 907 #define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1U) 908 909 enum fw_hellow_cmd { 910 fw_hello_cmd_stage_os = 0x0 911 }; 912 913 struct fw_hello_cmd { 914 __be32 op_to_write; 915 __be32 retval_len16; 916 __be32 err_to_clearinit; 917 __be32 fwrev; 918 }; 919 920 #define FW_HELLO_CMD_ERR_S 31 921 #define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S) 922 #define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1U) 923 924 #define FW_HELLO_CMD_INIT_S 30 925 #define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S) 926 #define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1U) 927 928 #define FW_HELLO_CMD_MASTERDIS_S 29 929 #define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S) 930 931 #define FW_HELLO_CMD_MASTERFORCE_S 28 932 #define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S) 933 934 #define FW_HELLO_CMD_MBMASTER_S 24 935 #define FW_HELLO_CMD_MBMASTER_M 0xfU 936 #define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S) 937 #define FW_HELLO_CMD_MBMASTER_G(x) \ 938 (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M) 939 940 #define FW_HELLO_CMD_MBASYNCNOTINT_S 23 941 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S) 942 943 #define FW_HELLO_CMD_MBASYNCNOT_S 20 944 #define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S) 945 946 #define FW_HELLO_CMD_STAGE_S 17 947 #define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S) 948 949 #define FW_HELLO_CMD_CLEARINIT_S 16 950 #define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S) 951 #define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1U) 952 953 struct fw_bye_cmd { 954 __be32 op_to_write; 955 __be32 retval_len16; 956 __be64 r3; 957 }; 958 959 struct fw_initialize_cmd { 960 __be32 op_to_write; 961 __be32 retval_len16; 962 __be64 r3; 963 }; 964 965 enum fw_caps_config_hm { 966 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 967 FW_CAPS_CONFIG_HM_PL = 0x00000002, 968 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 969 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 970 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 971 FW_CAPS_CONFIG_HM_TP = 0x00000020, 972 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 973 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 974 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 975 FW_CAPS_CONFIG_HM_MC = 0x00000200, 976 FW_CAPS_CONFIG_HM_LE = 0x00000400, 977 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 978 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 979 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 980 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 981 FW_CAPS_CONFIG_HM_MI = 0x00008000, 982 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 983 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 984 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 985 FW_CAPS_CONFIG_HM_MA = 0x00080000, 986 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 987 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 988 FW_CAPS_CONFIG_HM_UART = 0x00400000, 989 FW_CAPS_CONFIG_HM_SF = 0x00800000, 990 }; 991 992 enum fw_caps_config_nbm { 993 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 994 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 995 }; 996 997 enum fw_caps_config_link { 998 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 999 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 1000 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 1001 }; 1002 1003 enum fw_caps_config_switch { 1004 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 1005 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 1006 }; 1007 1008 enum fw_caps_config_nic { 1009 FW_CAPS_CONFIG_NIC = 0x00000001, 1010 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 1011 }; 1012 1013 enum fw_caps_config_ofld { 1014 FW_CAPS_CONFIG_OFLD = 0x00000001, 1015 }; 1016 1017 enum fw_caps_config_rdma { 1018 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 1019 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 1020 }; 1021 1022 enum fw_caps_config_iscsi { 1023 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 1024 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 1025 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 1026 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 1027 }; 1028 1029 enum fw_caps_config_fcoe { 1030 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 1031 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 1032 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 1033 }; 1034 1035 enum fw_memtype_cf { 1036 FW_MEMTYPE_CF_EDC0 = 0x0, 1037 FW_MEMTYPE_CF_EDC1 = 0x1, 1038 FW_MEMTYPE_CF_EXTMEM = 0x2, 1039 FW_MEMTYPE_CF_FLASH = 0x4, 1040 FW_MEMTYPE_CF_INTERNAL = 0x5, 1041 FW_MEMTYPE_CF_EXTMEM1 = 0x6, 1042 }; 1043 1044 struct fw_caps_config_cmd { 1045 __be32 op_to_write; 1046 __be32 cfvalid_to_len16; 1047 __be32 r2; 1048 __be32 hwmbitmap; 1049 __be16 nbmcaps; 1050 __be16 linkcaps; 1051 __be16 switchcaps; 1052 __be16 r3; 1053 __be16 niccaps; 1054 __be16 ofldcaps; 1055 __be16 rdmacaps; 1056 __be16 r4; 1057 __be16 iscsicaps; 1058 __be16 fcoecaps; 1059 __be32 cfcsum; 1060 __be32 finiver; 1061 __be32 finicsum; 1062 }; 1063 1064 #define FW_CAPS_CONFIG_CMD_CFVALID_S 27 1065 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S) 1066 #define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1U) 1067 1068 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24 1069 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \ 1070 ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S) 1071 1072 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16 1073 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \ 1074 ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S) 1075 1076 /* 1077 * params command mnemonics 1078 */ 1079 enum fw_params_mnem { 1080 FW_PARAMS_MNEM_DEV = 1, /* device params */ 1081 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 1082 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 1083 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 1084 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 1085 FW_PARAMS_MNEM_LAST 1086 }; 1087 1088 /* 1089 * device parameters 1090 */ 1091 enum fw_params_param_dev { 1092 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 1093 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 1094 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 1095 * allocated by the device's 1096 * Lookup Engine 1097 */ 1098 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 1099 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04, 1100 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05, 1101 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06, 1102 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07, 1103 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08, 1104 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09, 1105 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A, 1106 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 1107 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 1108 FW_PARAMS_PARAM_DEV_CF = 0x0D, 1109 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 1110 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 1111 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */ 1112 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */ 1113 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 1114 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 1115 }; 1116 1117 /* 1118 * physical and virtual function parameters 1119 */ 1120 enum fw_params_param_pfvf { 1121 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 1122 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 1123 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 1124 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 1125 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 1126 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 1127 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 1128 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 1129 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 1130 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 1131 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 1132 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 1133 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 1134 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 1135 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 1136 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 1137 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 1138 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 1139 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 1140 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 1141 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 1142 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 1143 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 1144 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 1145 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 1146 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 1147 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 1148 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 1149 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 1150 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 1151 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 1152 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 1153 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 1154 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 1155 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 1156 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 1157 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 1158 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 1159 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31 1160 }; 1161 1162 /* 1163 * dma queue parameters 1164 */ 1165 enum fw_params_param_dmaq { 1166 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 1167 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 1168 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 1169 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 1170 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 1171 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 1172 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 1173 }; 1174 1175 enum fw_params_param_dev_phyfw { 1176 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 1177 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 1178 }; 1179 1180 enum fw_params_param_dev_diag { 1181 FW_PARAM_DEV_DIAG_TMP = 0x00, 1182 FW_PARAM_DEV_DIAG_VDD = 0x01, 1183 }; 1184 1185 enum fw_params_param_dev_fwcache { 1186 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 1187 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 1188 }; 1189 1190 #define FW_PARAMS_MNEM_S 24 1191 #define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S) 1192 1193 #define FW_PARAMS_PARAM_X_S 16 1194 #define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S) 1195 1196 #define FW_PARAMS_PARAM_Y_S 8 1197 #define FW_PARAMS_PARAM_Y_M 0xffU 1198 #define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S) 1199 #define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\ 1200 FW_PARAMS_PARAM_Y_M) 1201 1202 #define FW_PARAMS_PARAM_Z_S 0 1203 #define FW_PARAMS_PARAM_Z_M 0xffu 1204 #define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S) 1205 #define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\ 1206 FW_PARAMS_PARAM_Z_M) 1207 1208 #define FW_PARAMS_PARAM_XYZ_S 0 1209 #define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S) 1210 1211 #define FW_PARAMS_PARAM_YZ_S 0 1212 #define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S) 1213 1214 struct fw_params_cmd { 1215 __be32 op_to_vfn; 1216 __be32 retval_len16; 1217 struct fw_params_param { 1218 __be32 mnem; 1219 __be32 val; 1220 } param[7]; 1221 }; 1222 1223 #define FW_PARAMS_CMD_PFN_S 8 1224 #define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S) 1225 1226 #define FW_PARAMS_CMD_VFN_S 0 1227 #define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S) 1228 1229 struct fw_pfvf_cmd { 1230 __be32 op_to_vfn; 1231 __be32 retval_len16; 1232 __be32 niqflint_niq; 1233 __be32 type_to_neq; 1234 __be32 tc_to_nexactf; 1235 __be32 r_caps_to_nethctrl; 1236 __be16 nricq; 1237 __be16 nriqp; 1238 __be32 r4; 1239 }; 1240 1241 #define FW_PFVF_CMD_PFN_S 8 1242 #define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S) 1243 1244 #define FW_PFVF_CMD_VFN_S 0 1245 #define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S) 1246 1247 #define FW_PFVF_CMD_NIQFLINT_S 20 1248 #define FW_PFVF_CMD_NIQFLINT_M 0xfff 1249 #define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S) 1250 #define FW_PFVF_CMD_NIQFLINT_G(x) \ 1251 (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M) 1252 1253 #define FW_PFVF_CMD_NIQ_S 0 1254 #define FW_PFVF_CMD_NIQ_M 0xfffff 1255 #define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S) 1256 #define FW_PFVF_CMD_NIQ_G(x) \ 1257 (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M) 1258 1259 #define FW_PFVF_CMD_TYPE_S 31 1260 #define FW_PFVF_CMD_TYPE_M 0x1 1261 #define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S) 1262 #define FW_PFVF_CMD_TYPE_G(x) \ 1263 (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M) 1264 #define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1U) 1265 1266 #define FW_PFVF_CMD_CMASK_S 24 1267 #define FW_PFVF_CMD_CMASK_M 0xf 1268 #define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S) 1269 #define FW_PFVF_CMD_CMASK_G(x) \ 1270 (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M) 1271 1272 #define FW_PFVF_CMD_PMASK_S 20 1273 #define FW_PFVF_CMD_PMASK_M 0xf 1274 #define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S) 1275 #define FW_PFVF_CMD_PMASK_G(x) \ 1276 (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M) 1277 1278 #define FW_PFVF_CMD_NEQ_S 0 1279 #define FW_PFVF_CMD_NEQ_M 0xfffff 1280 #define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S) 1281 #define FW_PFVF_CMD_NEQ_G(x) \ 1282 (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M) 1283 1284 #define FW_PFVF_CMD_TC_S 24 1285 #define FW_PFVF_CMD_TC_M 0xff 1286 #define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S) 1287 #define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M) 1288 1289 #define FW_PFVF_CMD_NVI_S 16 1290 #define FW_PFVF_CMD_NVI_M 0xff 1291 #define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S) 1292 #define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M) 1293 1294 #define FW_PFVF_CMD_NEXACTF_S 0 1295 #define FW_PFVF_CMD_NEXACTF_M 0xffff 1296 #define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S) 1297 #define FW_PFVF_CMD_NEXACTF_G(x) \ 1298 (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M) 1299 1300 #define FW_PFVF_CMD_R_CAPS_S 24 1301 #define FW_PFVF_CMD_R_CAPS_M 0xff 1302 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S) 1303 #define FW_PFVF_CMD_R_CAPS_G(x) \ 1304 (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M) 1305 1306 #define FW_PFVF_CMD_WX_CAPS_S 16 1307 #define FW_PFVF_CMD_WX_CAPS_M 0xff 1308 #define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S) 1309 #define FW_PFVF_CMD_WX_CAPS_G(x) \ 1310 (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M) 1311 1312 #define FW_PFVF_CMD_NETHCTRL_S 0 1313 #define FW_PFVF_CMD_NETHCTRL_M 0xffff 1314 #define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S) 1315 #define FW_PFVF_CMD_NETHCTRL_G(x) \ 1316 (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M) 1317 1318 enum fw_iq_type { 1319 FW_IQ_TYPE_FL_INT_CAP, 1320 FW_IQ_TYPE_NO_FL_INT_CAP 1321 }; 1322 1323 struct fw_iq_cmd { 1324 __be32 op_to_vfn; 1325 __be32 alloc_to_len16; 1326 __be16 physiqid; 1327 __be16 iqid; 1328 __be16 fl0id; 1329 __be16 fl1id; 1330 __be32 type_to_iqandstindex; 1331 __be16 iqdroprss_to_iqesize; 1332 __be16 iqsize; 1333 __be64 iqaddr; 1334 __be32 iqns_to_fl0congen; 1335 __be16 fl0dcaen_to_fl0cidxfthresh; 1336 __be16 fl0size; 1337 __be64 fl0addr; 1338 __be32 fl1cngchmap_to_fl1congen; 1339 __be16 fl1dcaen_to_fl1cidxfthresh; 1340 __be16 fl1size; 1341 __be64 fl1addr; 1342 }; 1343 1344 #define FW_IQ_CMD_PFN_S 8 1345 #define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S) 1346 1347 #define FW_IQ_CMD_VFN_S 0 1348 #define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S) 1349 1350 #define FW_IQ_CMD_ALLOC_S 31 1351 #define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S) 1352 #define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1U) 1353 1354 #define FW_IQ_CMD_FREE_S 30 1355 #define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S) 1356 #define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1U) 1357 1358 #define FW_IQ_CMD_MODIFY_S 29 1359 #define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S) 1360 #define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1U) 1361 1362 #define FW_IQ_CMD_IQSTART_S 28 1363 #define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S) 1364 #define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1U) 1365 1366 #define FW_IQ_CMD_IQSTOP_S 27 1367 #define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S) 1368 #define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1U) 1369 1370 #define FW_IQ_CMD_TYPE_S 29 1371 #define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S) 1372 1373 #define FW_IQ_CMD_IQASYNCH_S 28 1374 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S) 1375 1376 #define FW_IQ_CMD_VIID_S 16 1377 #define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S) 1378 1379 #define FW_IQ_CMD_IQANDST_S 15 1380 #define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S) 1381 1382 #define FW_IQ_CMD_IQANUS_S 14 1383 #define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S) 1384 1385 #define FW_IQ_CMD_IQANUD_S 12 1386 #define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S) 1387 1388 #define FW_IQ_CMD_IQANDSTINDEX_S 0 1389 #define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S) 1390 1391 #define FW_IQ_CMD_IQDROPRSS_S 15 1392 #define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S) 1393 #define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1U) 1394 1395 #define FW_IQ_CMD_IQGTSMODE_S 14 1396 #define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S) 1397 #define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1U) 1398 1399 #define FW_IQ_CMD_IQPCIECH_S 12 1400 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S) 1401 1402 #define FW_IQ_CMD_IQDCAEN_S 11 1403 #define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S) 1404 1405 #define FW_IQ_CMD_IQDCACPU_S 6 1406 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S) 1407 1408 #define FW_IQ_CMD_IQINTCNTTHRESH_S 4 1409 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S) 1410 1411 #define FW_IQ_CMD_IQO_S 3 1412 #define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S) 1413 #define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1U) 1414 1415 #define FW_IQ_CMD_IQCPRIO_S 2 1416 #define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S) 1417 1418 #define FW_IQ_CMD_IQESIZE_S 0 1419 #define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S) 1420 1421 #define FW_IQ_CMD_IQNS_S 31 1422 #define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S) 1423 1424 #define FW_IQ_CMD_IQRO_S 30 1425 #define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S) 1426 1427 #define FW_IQ_CMD_IQFLINTIQHSEN_S 28 1428 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S) 1429 1430 #define FW_IQ_CMD_IQFLINTCONGEN_S 27 1431 #define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S) 1432 #define FW_IQ_CMD_IQFLINTCONGEN_F FW_IQ_CMD_IQFLINTCONGEN_V(1U) 1433 1434 #define FW_IQ_CMD_IQFLINTISCSIC_S 26 1435 #define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S) 1436 1437 #define FW_IQ_CMD_FL0CNGCHMAP_S 20 1438 #define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S) 1439 1440 #define FW_IQ_CMD_FL0CACHELOCK_S 15 1441 #define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S) 1442 1443 #define FW_IQ_CMD_FL0DBP_S 14 1444 #define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S) 1445 1446 #define FW_IQ_CMD_FL0DATANS_S 13 1447 #define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S) 1448 1449 #define FW_IQ_CMD_FL0DATARO_S 12 1450 #define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S) 1451 #define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1U) 1452 1453 #define FW_IQ_CMD_FL0CONGCIF_S 11 1454 #define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S) 1455 #define FW_IQ_CMD_FL0CONGCIF_F FW_IQ_CMD_FL0CONGCIF_V(1U) 1456 1457 #define FW_IQ_CMD_FL0ONCHIP_S 10 1458 #define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S) 1459 1460 #define FW_IQ_CMD_FL0STATUSPGNS_S 9 1461 #define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S) 1462 1463 #define FW_IQ_CMD_FL0STATUSPGRO_S 8 1464 #define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S) 1465 1466 #define FW_IQ_CMD_FL0FETCHNS_S 7 1467 #define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S) 1468 1469 #define FW_IQ_CMD_FL0FETCHRO_S 6 1470 #define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S) 1471 #define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1U) 1472 1473 #define FW_IQ_CMD_FL0HOSTFCMODE_S 4 1474 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S) 1475 1476 #define FW_IQ_CMD_FL0CPRIO_S 3 1477 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S) 1478 1479 #define FW_IQ_CMD_FL0PADEN_S 2 1480 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S) 1481 #define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1U) 1482 1483 #define FW_IQ_CMD_FL0PACKEN_S 1 1484 #define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S) 1485 #define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1U) 1486 1487 #define FW_IQ_CMD_FL0CONGEN_S 0 1488 #define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S) 1489 #define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1U) 1490 1491 #define FW_IQ_CMD_FL0DCAEN_S 15 1492 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S) 1493 1494 #define FW_IQ_CMD_FL0DCACPU_S 10 1495 #define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S) 1496 1497 #define FW_IQ_CMD_FL0FBMIN_S 7 1498 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S) 1499 1500 #define FW_IQ_CMD_FL0FBMAX_S 4 1501 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S) 1502 1503 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3 1504 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S) 1505 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U) 1506 1507 #define FW_IQ_CMD_FL0CIDXFTHRESH_S 0 1508 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S) 1509 1510 #define FW_IQ_CMD_FL1CNGCHMAP_S 20 1511 #define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S) 1512 1513 #define FW_IQ_CMD_FL1CACHELOCK_S 15 1514 #define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S) 1515 1516 #define FW_IQ_CMD_FL1DBP_S 14 1517 #define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S) 1518 1519 #define FW_IQ_CMD_FL1DATANS_S 13 1520 #define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S) 1521 1522 #define FW_IQ_CMD_FL1DATARO_S 12 1523 #define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S) 1524 1525 #define FW_IQ_CMD_FL1CONGCIF_S 11 1526 #define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S) 1527 1528 #define FW_IQ_CMD_FL1ONCHIP_S 10 1529 #define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S) 1530 1531 #define FW_IQ_CMD_FL1STATUSPGNS_S 9 1532 #define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S) 1533 1534 #define FW_IQ_CMD_FL1STATUSPGRO_S 8 1535 #define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S) 1536 1537 #define FW_IQ_CMD_FL1FETCHNS_S 7 1538 #define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S) 1539 1540 #define FW_IQ_CMD_FL1FETCHRO_S 6 1541 #define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S) 1542 1543 #define FW_IQ_CMD_FL1HOSTFCMODE_S 4 1544 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S) 1545 1546 #define FW_IQ_CMD_FL1CPRIO_S 3 1547 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S) 1548 1549 #define FW_IQ_CMD_FL1PADEN_S 2 1550 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S) 1551 #define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1U) 1552 1553 #define FW_IQ_CMD_FL1PACKEN_S 1 1554 #define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S) 1555 #define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1U) 1556 1557 #define FW_IQ_CMD_FL1CONGEN_S 0 1558 #define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S) 1559 #define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1U) 1560 1561 #define FW_IQ_CMD_FL1DCAEN_S 15 1562 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S) 1563 1564 #define FW_IQ_CMD_FL1DCACPU_S 10 1565 #define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S) 1566 1567 #define FW_IQ_CMD_FL1FBMIN_S 7 1568 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S) 1569 1570 #define FW_IQ_CMD_FL1FBMAX_S 4 1571 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S) 1572 1573 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3 1574 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S) 1575 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U) 1576 1577 #define FW_IQ_CMD_FL1CIDXFTHRESH_S 0 1578 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S) 1579 1580 struct fw_eq_eth_cmd { 1581 __be32 op_to_vfn; 1582 __be32 alloc_to_len16; 1583 __be32 eqid_pkd; 1584 __be32 physeqid_pkd; 1585 __be32 fetchszm_to_iqid; 1586 __be32 dcaen_to_eqsize; 1587 __be64 eqaddr; 1588 __be32 viid_pkd; 1589 __be32 r8_lo; 1590 __be64 r9; 1591 }; 1592 1593 #define FW_EQ_ETH_CMD_PFN_S 8 1594 #define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S) 1595 1596 #define FW_EQ_ETH_CMD_VFN_S 0 1597 #define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S) 1598 1599 #define FW_EQ_ETH_CMD_ALLOC_S 31 1600 #define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S) 1601 #define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1U) 1602 1603 #define FW_EQ_ETH_CMD_FREE_S 30 1604 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S) 1605 #define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1U) 1606 1607 #define FW_EQ_ETH_CMD_MODIFY_S 29 1608 #define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S) 1609 #define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1U) 1610 1611 #define FW_EQ_ETH_CMD_EQSTART_S 28 1612 #define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S) 1613 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U) 1614 1615 #define FW_EQ_ETH_CMD_EQSTOP_S 27 1616 #define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S) 1617 #define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U) 1618 1619 #define FW_EQ_ETH_CMD_EQID_S 0 1620 #define FW_EQ_ETH_CMD_EQID_M 0xfffff 1621 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S) 1622 #define FW_EQ_ETH_CMD_EQID_G(x) \ 1623 (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M) 1624 1625 #define FW_EQ_ETH_CMD_PHYSEQID_S 0 1626 #define FW_EQ_ETH_CMD_PHYSEQID_M 0xfffff 1627 #define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S) 1628 #define FW_EQ_ETH_CMD_PHYSEQID_G(x) \ 1629 (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M) 1630 1631 #define FW_EQ_ETH_CMD_FETCHSZM_S 26 1632 #define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S) 1633 #define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1U) 1634 1635 #define FW_EQ_ETH_CMD_STATUSPGNS_S 25 1636 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S) 1637 1638 #define FW_EQ_ETH_CMD_STATUSPGRO_S 24 1639 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S) 1640 1641 #define FW_EQ_ETH_CMD_FETCHNS_S 23 1642 #define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S) 1643 1644 #define FW_EQ_ETH_CMD_FETCHRO_S 22 1645 #define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S) 1646 #define FW_EQ_ETH_CMD_FETCHRO_F FW_EQ_ETH_CMD_FETCHRO_V(1U) 1647 1648 #define FW_EQ_ETH_CMD_HOSTFCMODE_S 20 1649 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S) 1650 1651 #define FW_EQ_ETH_CMD_CPRIO_S 19 1652 #define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S) 1653 1654 #define FW_EQ_ETH_CMD_ONCHIP_S 18 1655 #define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S) 1656 1657 #define FW_EQ_ETH_CMD_PCIECHN_S 16 1658 #define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S) 1659 1660 #define FW_EQ_ETH_CMD_IQID_S 0 1661 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S) 1662 1663 #define FW_EQ_ETH_CMD_DCAEN_S 31 1664 #define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S) 1665 1666 #define FW_EQ_ETH_CMD_DCACPU_S 26 1667 #define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S) 1668 1669 #define FW_EQ_ETH_CMD_FBMIN_S 23 1670 #define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S) 1671 1672 #define FW_EQ_ETH_CMD_FBMAX_S 20 1673 #define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S) 1674 1675 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19 1676 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S) 1677 1678 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16 1679 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S) 1680 1681 #define FW_EQ_ETH_CMD_EQSIZE_S 0 1682 #define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S) 1683 1684 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30 1685 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S) 1686 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U) 1687 1688 #define FW_EQ_ETH_CMD_VIID_S 16 1689 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S) 1690 1691 struct fw_eq_ctrl_cmd { 1692 __be32 op_to_vfn; 1693 __be32 alloc_to_len16; 1694 __be32 cmpliqid_eqid; 1695 __be32 physeqid_pkd; 1696 __be32 fetchszm_to_iqid; 1697 __be32 dcaen_to_eqsize; 1698 __be64 eqaddr; 1699 }; 1700 1701 #define FW_EQ_CTRL_CMD_PFN_S 8 1702 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S) 1703 1704 #define FW_EQ_CTRL_CMD_VFN_S 0 1705 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S) 1706 1707 #define FW_EQ_CTRL_CMD_ALLOC_S 31 1708 #define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S) 1709 #define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1U) 1710 1711 #define FW_EQ_CTRL_CMD_FREE_S 30 1712 #define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S) 1713 #define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1U) 1714 1715 #define FW_EQ_CTRL_CMD_MODIFY_S 29 1716 #define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S) 1717 #define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1U) 1718 1719 #define FW_EQ_CTRL_CMD_EQSTART_S 28 1720 #define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S) 1721 #define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1U) 1722 1723 #define FW_EQ_CTRL_CMD_EQSTOP_S 27 1724 #define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S) 1725 #define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1U) 1726 1727 #define FW_EQ_CTRL_CMD_CMPLIQID_S 20 1728 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S) 1729 1730 #define FW_EQ_CTRL_CMD_EQID_S 0 1731 #define FW_EQ_CTRL_CMD_EQID_M 0xfffff 1732 #define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S) 1733 #define FW_EQ_CTRL_CMD_EQID_G(x) \ 1734 (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M) 1735 1736 #define FW_EQ_CTRL_CMD_PHYSEQID_S 0 1737 #define FW_EQ_CTRL_CMD_PHYSEQID_M 0xfffff 1738 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x) \ 1739 (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M) 1740 1741 #define FW_EQ_CTRL_CMD_FETCHSZM_S 26 1742 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S) 1743 #define FW_EQ_CTRL_CMD_FETCHSZM_F FW_EQ_CTRL_CMD_FETCHSZM_V(1U) 1744 1745 #define FW_EQ_CTRL_CMD_STATUSPGNS_S 25 1746 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S) 1747 #define FW_EQ_CTRL_CMD_STATUSPGNS_F FW_EQ_CTRL_CMD_STATUSPGNS_V(1U) 1748 1749 #define FW_EQ_CTRL_CMD_STATUSPGRO_S 24 1750 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S) 1751 #define FW_EQ_CTRL_CMD_STATUSPGRO_F FW_EQ_CTRL_CMD_STATUSPGRO_V(1U) 1752 1753 #define FW_EQ_CTRL_CMD_FETCHNS_S 23 1754 #define FW_EQ_CTRL_CMD_FETCHNS_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHNS_S) 1755 #define FW_EQ_CTRL_CMD_FETCHNS_F FW_EQ_CTRL_CMD_FETCHNS_V(1U) 1756 1757 #define FW_EQ_CTRL_CMD_FETCHRO_S 22 1758 #define FW_EQ_CTRL_CMD_FETCHRO_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHRO_S) 1759 #define FW_EQ_CTRL_CMD_FETCHRO_F FW_EQ_CTRL_CMD_FETCHRO_V(1U) 1760 1761 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S 20 1762 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S) 1763 1764 #define FW_EQ_CTRL_CMD_CPRIO_S 19 1765 #define FW_EQ_CTRL_CMD_CPRIO_V(x) ((x) << FW_EQ_CTRL_CMD_CPRIO_S) 1766 1767 #define FW_EQ_CTRL_CMD_ONCHIP_S 18 1768 #define FW_EQ_CTRL_CMD_ONCHIP_V(x) ((x) << FW_EQ_CTRL_CMD_ONCHIP_S) 1769 1770 #define FW_EQ_CTRL_CMD_PCIECHN_S 16 1771 #define FW_EQ_CTRL_CMD_PCIECHN_V(x) ((x) << FW_EQ_CTRL_CMD_PCIECHN_S) 1772 1773 #define FW_EQ_CTRL_CMD_IQID_S 0 1774 #define FW_EQ_CTRL_CMD_IQID_V(x) ((x) << FW_EQ_CTRL_CMD_IQID_S) 1775 1776 #define FW_EQ_CTRL_CMD_DCAEN_S 31 1777 #define FW_EQ_CTRL_CMD_DCAEN_V(x) ((x) << FW_EQ_CTRL_CMD_DCAEN_S) 1778 1779 #define FW_EQ_CTRL_CMD_DCACPU_S 26 1780 #define FW_EQ_CTRL_CMD_DCACPU_V(x) ((x) << FW_EQ_CTRL_CMD_DCACPU_S) 1781 1782 #define FW_EQ_CTRL_CMD_FBMIN_S 23 1783 #define FW_EQ_CTRL_CMD_FBMIN_V(x) ((x) << FW_EQ_CTRL_CMD_FBMIN_S) 1784 1785 #define FW_EQ_CTRL_CMD_FBMAX_S 20 1786 #define FW_EQ_CTRL_CMD_FBMAX_V(x) ((x) << FW_EQ_CTRL_CMD_FBMAX_S) 1787 1788 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S 19 1789 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x) \ 1790 ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S) 1791 1792 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S 16 1793 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S) 1794 1795 #define FW_EQ_CTRL_CMD_EQSIZE_S 0 1796 #define FW_EQ_CTRL_CMD_EQSIZE_V(x) ((x) << FW_EQ_CTRL_CMD_EQSIZE_S) 1797 1798 struct fw_eq_ofld_cmd { 1799 __be32 op_to_vfn; 1800 __be32 alloc_to_len16; 1801 __be32 eqid_pkd; 1802 __be32 physeqid_pkd; 1803 __be32 fetchszm_to_iqid; 1804 __be32 dcaen_to_eqsize; 1805 __be64 eqaddr; 1806 }; 1807 1808 #define FW_EQ_OFLD_CMD_PFN_S 8 1809 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S) 1810 1811 #define FW_EQ_OFLD_CMD_VFN_S 0 1812 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S) 1813 1814 #define FW_EQ_OFLD_CMD_ALLOC_S 31 1815 #define FW_EQ_OFLD_CMD_ALLOC_V(x) ((x) << FW_EQ_OFLD_CMD_ALLOC_S) 1816 #define FW_EQ_OFLD_CMD_ALLOC_F FW_EQ_OFLD_CMD_ALLOC_V(1U) 1817 1818 #define FW_EQ_OFLD_CMD_FREE_S 30 1819 #define FW_EQ_OFLD_CMD_FREE_V(x) ((x) << FW_EQ_OFLD_CMD_FREE_S) 1820 #define FW_EQ_OFLD_CMD_FREE_F FW_EQ_OFLD_CMD_FREE_V(1U) 1821 1822 #define FW_EQ_OFLD_CMD_MODIFY_S 29 1823 #define FW_EQ_OFLD_CMD_MODIFY_V(x) ((x) << FW_EQ_OFLD_CMD_MODIFY_S) 1824 #define FW_EQ_OFLD_CMD_MODIFY_F FW_EQ_OFLD_CMD_MODIFY_V(1U) 1825 1826 #define FW_EQ_OFLD_CMD_EQSTART_S 28 1827 #define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S) 1828 #define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1U) 1829 1830 #define FW_EQ_OFLD_CMD_EQSTOP_S 27 1831 #define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S) 1832 #define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1U) 1833 1834 #define FW_EQ_OFLD_CMD_EQID_S 0 1835 #define FW_EQ_OFLD_CMD_EQID_M 0xfffff 1836 #define FW_EQ_OFLD_CMD_EQID_V(x) ((x) << FW_EQ_OFLD_CMD_EQID_S) 1837 #define FW_EQ_OFLD_CMD_EQID_G(x) \ 1838 (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M) 1839 1840 #define FW_EQ_OFLD_CMD_PHYSEQID_S 0 1841 #define FW_EQ_OFLD_CMD_PHYSEQID_M 0xfffff 1842 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x) \ 1843 (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M) 1844 1845 #define FW_EQ_OFLD_CMD_FETCHSZM_S 26 1846 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S) 1847 1848 #define FW_EQ_OFLD_CMD_STATUSPGNS_S 25 1849 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S) 1850 1851 #define FW_EQ_OFLD_CMD_STATUSPGRO_S 24 1852 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S) 1853 1854 #define FW_EQ_OFLD_CMD_FETCHNS_S 23 1855 #define FW_EQ_OFLD_CMD_FETCHNS_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHNS_S) 1856 1857 #define FW_EQ_OFLD_CMD_FETCHRO_S 22 1858 #define FW_EQ_OFLD_CMD_FETCHRO_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHRO_S) 1859 #define FW_EQ_OFLD_CMD_FETCHRO_F FW_EQ_OFLD_CMD_FETCHRO_V(1U) 1860 1861 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S 20 1862 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S) 1863 1864 #define FW_EQ_OFLD_CMD_CPRIO_S 19 1865 #define FW_EQ_OFLD_CMD_CPRIO_V(x) ((x) << FW_EQ_OFLD_CMD_CPRIO_S) 1866 1867 #define FW_EQ_OFLD_CMD_ONCHIP_S 18 1868 #define FW_EQ_OFLD_CMD_ONCHIP_V(x) ((x) << FW_EQ_OFLD_CMD_ONCHIP_S) 1869 1870 #define FW_EQ_OFLD_CMD_PCIECHN_S 16 1871 #define FW_EQ_OFLD_CMD_PCIECHN_V(x) ((x) << FW_EQ_OFLD_CMD_PCIECHN_S) 1872 1873 #define FW_EQ_OFLD_CMD_IQID_S 0 1874 #define FW_EQ_OFLD_CMD_IQID_V(x) ((x) << FW_EQ_OFLD_CMD_IQID_S) 1875 1876 #define FW_EQ_OFLD_CMD_DCAEN_S 31 1877 #define FW_EQ_OFLD_CMD_DCAEN_V(x) ((x) << FW_EQ_OFLD_CMD_DCAEN_S) 1878 1879 #define FW_EQ_OFLD_CMD_DCACPU_S 26 1880 #define FW_EQ_OFLD_CMD_DCACPU_V(x) ((x) << FW_EQ_OFLD_CMD_DCACPU_S) 1881 1882 #define FW_EQ_OFLD_CMD_FBMIN_S 23 1883 #define FW_EQ_OFLD_CMD_FBMIN_V(x) ((x) << FW_EQ_OFLD_CMD_FBMIN_S) 1884 1885 #define FW_EQ_OFLD_CMD_FBMAX_S 20 1886 #define FW_EQ_OFLD_CMD_FBMAX_V(x) ((x) << FW_EQ_OFLD_CMD_FBMAX_S) 1887 1888 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S 19 1889 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x) \ 1890 ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S) 1891 1892 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S 16 1893 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S) 1894 1895 #define FW_EQ_OFLD_CMD_EQSIZE_S 0 1896 #define FW_EQ_OFLD_CMD_EQSIZE_V(x) ((x) << FW_EQ_OFLD_CMD_EQSIZE_S) 1897 1898 /* 1899 * Macros for VIID parsing: 1900 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number 1901 */ 1902 1903 #define FW_VIID_PFN_S 8 1904 #define FW_VIID_PFN_M 0x7 1905 #define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M) 1906 1907 #define FW_VIID_VIVLD_S 7 1908 #define FW_VIID_VIVLD_M 0x1 1909 #define FW_VIID_VIVLD_G(x) (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M) 1910 1911 #define FW_VIID_VIN_S 0 1912 #define FW_VIID_VIN_M 0x7F 1913 #define FW_VIID_VIN_G(x) (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M) 1914 1915 struct fw_vi_cmd { 1916 __be32 op_to_vfn; 1917 __be32 alloc_to_len16; 1918 __be16 type_viid; 1919 u8 mac[6]; 1920 u8 portid_pkd; 1921 u8 nmac; 1922 u8 nmac0[6]; 1923 __be16 rsssize_pkd; 1924 u8 nmac1[6]; 1925 __be16 idsiiq_pkd; 1926 u8 nmac2[6]; 1927 __be16 idseiq_pkd; 1928 u8 nmac3[6]; 1929 __be64 r9; 1930 __be64 r10; 1931 }; 1932 1933 #define FW_VI_CMD_PFN_S 8 1934 #define FW_VI_CMD_PFN_V(x) ((x) << FW_VI_CMD_PFN_S) 1935 1936 #define FW_VI_CMD_VFN_S 0 1937 #define FW_VI_CMD_VFN_V(x) ((x) << FW_VI_CMD_VFN_S) 1938 1939 #define FW_VI_CMD_ALLOC_S 31 1940 #define FW_VI_CMD_ALLOC_V(x) ((x) << FW_VI_CMD_ALLOC_S) 1941 #define FW_VI_CMD_ALLOC_F FW_VI_CMD_ALLOC_V(1U) 1942 1943 #define FW_VI_CMD_FREE_S 30 1944 #define FW_VI_CMD_FREE_V(x) ((x) << FW_VI_CMD_FREE_S) 1945 #define FW_VI_CMD_FREE_F FW_VI_CMD_FREE_V(1U) 1946 1947 #define FW_VI_CMD_VIID_S 0 1948 #define FW_VI_CMD_VIID_M 0xfff 1949 #define FW_VI_CMD_VIID_V(x) ((x) << FW_VI_CMD_VIID_S) 1950 #define FW_VI_CMD_VIID_G(x) (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M) 1951 1952 #define FW_VI_CMD_PORTID_S 4 1953 #define FW_VI_CMD_PORTID_M 0xf 1954 #define FW_VI_CMD_PORTID_V(x) ((x) << FW_VI_CMD_PORTID_S) 1955 #define FW_VI_CMD_PORTID_G(x) \ 1956 (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M) 1957 1958 #define FW_VI_CMD_RSSSIZE_S 0 1959 #define FW_VI_CMD_RSSSIZE_M 0x7ff 1960 #define FW_VI_CMD_RSSSIZE_G(x) \ 1961 (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M) 1962 1963 /* Special VI_MAC command index ids */ 1964 #define FW_VI_MAC_ADD_MAC 0x3FF 1965 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 1966 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 1967 #define FW_CLS_TCAM_NUM_ENTRIES 336 1968 1969 enum fw_vi_mac_smac { 1970 FW_VI_MAC_MPS_TCAM_ENTRY, 1971 FW_VI_MAC_MPS_TCAM_ONLY, 1972 FW_VI_MAC_SMT_ONLY, 1973 FW_VI_MAC_SMT_AND_MPSTCAM 1974 }; 1975 1976 enum fw_vi_mac_result { 1977 FW_VI_MAC_R_SUCCESS, 1978 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 1979 FW_VI_MAC_R_SMAC_FAIL, 1980 FW_VI_MAC_R_F_ACL_CHECK 1981 }; 1982 1983 struct fw_vi_mac_cmd { 1984 __be32 op_to_viid; 1985 __be32 freemacs_to_len16; 1986 union fw_vi_mac { 1987 struct fw_vi_mac_exact { 1988 __be16 valid_to_idx; 1989 u8 macaddr[6]; 1990 } exact[7]; 1991 struct fw_vi_mac_hash { 1992 __be64 hashvec; 1993 } hash; 1994 } u; 1995 }; 1996 1997 #define FW_VI_MAC_CMD_VIID_S 0 1998 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S) 1999 2000 #define FW_VI_MAC_CMD_FREEMACS_S 31 2001 #define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S) 2002 2003 #define FW_VI_MAC_CMD_HASHVECEN_S 23 2004 #define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S) 2005 #define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1U) 2006 2007 #define FW_VI_MAC_CMD_HASHUNIEN_S 22 2008 #define FW_VI_MAC_CMD_HASHUNIEN_V(x) ((x) << FW_VI_MAC_CMD_HASHUNIEN_S) 2009 2010 #define FW_VI_MAC_CMD_VALID_S 15 2011 #define FW_VI_MAC_CMD_VALID_V(x) ((x) << FW_VI_MAC_CMD_VALID_S) 2012 #define FW_VI_MAC_CMD_VALID_F FW_VI_MAC_CMD_VALID_V(1U) 2013 2014 #define FW_VI_MAC_CMD_PRIO_S 12 2015 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S) 2016 2017 #define FW_VI_MAC_CMD_SMAC_RESULT_S 10 2018 #define FW_VI_MAC_CMD_SMAC_RESULT_M 0x3 2019 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x) ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S) 2020 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x) \ 2021 (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M) 2022 2023 #define FW_VI_MAC_CMD_IDX_S 0 2024 #define FW_VI_MAC_CMD_IDX_M 0x3ff 2025 #define FW_VI_MAC_CMD_IDX_V(x) ((x) << FW_VI_MAC_CMD_IDX_S) 2026 #define FW_VI_MAC_CMD_IDX_G(x) \ 2027 (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M) 2028 2029 #define FW_RXMODE_MTU_NO_CHG 65535 2030 2031 struct fw_vi_rxmode_cmd { 2032 __be32 op_to_viid; 2033 __be32 retval_len16; 2034 __be32 mtu_to_vlanexen; 2035 __be32 r4_lo; 2036 }; 2037 2038 #define FW_VI_RXMODE_CMD_VIID_S 0 2039 #define FW_VI_RXMODE_CMD_VIID_V(x) ((x) << FW_VI_RXMODE_CMD_VIID_S) 2040 2041 #define FW_VI_RXMODE_CMD_MTU_S 16 2042 #define FW_VI_RXMODE_CMD_MTU_M 0xffff 2043 #define FW_VI_RXMODE_CMD_MTU_V(x) ((x) << FW_VI_RXMODE_CMD_MTU_S) 2044 2045 #define FW_VI_RXMODE_CMD_PROMISCEN_S 14 2046 #define FW_VI_RXMODE_CMD_PROMISCEN_M 0x3 2047 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S) 2048 2049 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S 12 2050 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M 0x3 2051 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x) \ 2052 ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S) 2053 2054 #define FW_VI_RXMODE_CMD_BROADCASTEN_S 10 2055 #define FW_VI_RXMODE_CMD_BROADCASTEN_M 0x3 2056 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x) \ 2057 ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S) 2058 2059 #define FW_VI_RXMODE_CMD_VLANEXEN_S 8 2060 #define FW_VI_RXMODE_CMD_VLANEXEN_M 0x3 2061 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x) ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S) 2062 2063 struct fw_vi_enable_cmd { 2064 __be32 op_to_viid; 2065 __be32 ien_to_len16; 2066 __be16 blinkdur; 2067 __be16 r3; 2068 __be32 r4; 2069 }; 2070 2071 #define FW_VI_ENABLE_CMD_VIID_S 0 2072 #define FW_VI_ENABLE_CMD_VIID_V(x) ((x) << FW_VI_ENABLE_CMD_VIID_S) 2073 2074 #define FW_VI_ENABLE_CMD_IEN_S 31 2075 #define FW_VI_ENABLE_CMD_IEN_V(x) ((x) << FW_VI_ENABLE_CMD_IEN_S) 2076 2077 #define FW_VI_ENABLE_CMD_EEN_S 30 2078 #define FW_VI_ENABLE_CMD_EEN_V(x) ((x) << FW_VI_ENABLE_CMD_EEN_S) 2079 2080 #define FW_VI_ENABLE_CMD_LED_S 29 2081 #define FW_VI_ENABLE_CMD_LED_V(x) ((x) << FW_VI_ENABLE_CMD_LED_S) 2082 #define FW_VI_ENABLE_CMD_LED_F FW_VI_ENABLE_CMD_LED_V(1U) 2083 2084 #define FW_VI_ENABLE_CMD_DCB_INFO_S 28 2085 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x) ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S) 2086 2087 /* VI VF stats offset definitions */ 2088 #define VI_VF_NUM_STATS 16 2089 enum fw_vi_stats_vf_index { 2090 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 2091 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 2092 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 2093 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 2094 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 2095 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 2096 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 2097 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 2098 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 2099 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 2100 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 2101 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 2102 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 2103 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 2104 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 2105 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 2106 }; 2107 2108 /* VI PF stats offset definitions */ 2109 #define VI_PF_NUM_STATS 17 2110 enum fw_vi_stats_pf_index { 2111 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 2112 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 2113 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 2114 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 2115 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 2116 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 2117 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 2118 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 2119 FW_VI_PF_STAT_RX_BYTES_IX, 2120 FW_VI_PF_STAT_RX_FRAMES_IX, 2121 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 2122 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 2123 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 2124 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 2125 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 2126 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 2127 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 2128 }; 2129 2130 struct fw_vi_stats_cmd { 2131 __be32 op_to_viid; 2132 __be32 retval_len16; 2133 union fw_vi_stats { 2134 struct fw_vi_stats_ctl { 2135 __be16 nstats_ix; 2136 __be16 r6; 2137 __be32 r7; 2138 __be64 stat0; 2139 __be64 stat1; 2140 __be64 stat2; 2141 __be64 stat3; 2142 __be64 stat4; 2143 __be64 stat5; 2144 } ctl; 2145 struct fw_vi_stats_pf { 2146 __be64 tx_bcast_bytes; 2147 __be64 tx_bcast_frames; 2148 __be64 tx_mcast_bytes; 2149 __be64 tx_mcast_frames; 2150 __be64 tx_ucast_bytes; 2151 __be64 tx_ucast_frames; 2152 __be64 tx_offload_bytes; 2153 __be64 tx_offload_frames; 2154 __be64 rx_pf_bytes; 2155 __be64 rx_pf_frames; 2156 __be64 rx_bcast_bytes; 2157 __be64 rx_bcast_frames; 2158 __be64 rx_mcast_bytes; 2159 __be64 rx_mcast_frames; 2160 __be64 rx_ucast_bytes; 2161 __be64 rx_ucast_frames; 2162 __be64 rx_err_frames; 2163 } pf; 2164 struct fw_vi_stats_vf { 2165 __be64 tx_bcast_bytes; 2166 __be64 tx_bcast_frames; 2167 __be64 tx_mcast_bytes; 2168 __be64 tx_mcast_frames; 2169 __be64 tx_ucast_bytes; 2170 __be64 tx_ucast_frames; 2171 __be64 tx_drop_frames; 2172 __be64 tx_offload_bytes; 2173 __be64 tx_offload_frames; 2174 __be64 rx_bcast_bytes; 2175 __be64 rx_bcast_frames; 2176 __be64 rx_mcast_bytes; 2177 __be64 rx_mcast_frames; 2178 __be64 rx_ucast_bytes; 2179 __be64 rx_ucast_frames; 2180 __be64 rx_err_frames; 2181 } vf; 2182 } u; 2183 }; 2184 2185 #define FW_VI_STATS_CMD_VIID_S 0 2186 #define FW_VI_STATS_CMD_VIID_V(x) ((x) << FW_VI_STATS_CMD_VIID_S) 2187 2188 #define FW_VI_STATS_CMD_NSTATS_S 12 2189 #define FW_VI_STATS_CMD_NSTATS_V(x) ((x) << FW_VI_STATS_CMD_NSTATS_S) 2190 2191 #define FW_VI_STATS_CMD_IX_S 0 2192 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S) 2193 2194 struct fw_acl_mac_cmd { 2195 __be32 op_to_vfn; 2196 __be32 en_to_len16; 2197 u8 nmac; 2198 u8 r3[7]; 2199 __be16 r4; 2200 u8 macaddr0[6]; 2201 __be16 r5; 2202 u8 macaddr1[6]; 2203 __be16 r6; 2204 u8 macaddr2[6]; 2205 __be16 r7; 2206 u8 macaddr3[6]; 2207 }; 2208 2209 #define FW_ACL_MAC_CMD_PFN_S 8 2210 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S) 2211 2212 #define FW_ACL_MAC_CMD_VFN_S 0 2213 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S) 2214 2215 #define FW_ACL_MAC_CMD_EN_S 31 2216 #define FW_ACL_MAC_CMD_EN_V(x) ((x) << FW_ACL_MAC_CMD_EN_S) 2217 2218 struct fw_acl_vlan_cmd { 2219 __be32 op_to_vfn; 2220 __be32 en_to_len16; 2221 u8 nvlan; 2222 u8 dropnovlan_fm; 2223 u8 r3_lo[6]; 2224 __be16 vlanid[16]; 2225 }; 2226 2227 #define FW_ACL_VLAN_CMD_PFN_S 8 2228 #define FW_ACL_VLAN_CMD_PFN_V(x) ((x) << FW_ACL_VLAN_CMD_PFN_S) 2229 2230 #define FW_ACL_VLAN_CMD_VFN_S 0 2231 #define FW_ACL_VLAN_CMD_VFN_V(x) ((x) << FW_ACL_VLAN_CMD_VFN_S) 2232 2233 #define FW_ACL_VLAN_CMD_EN_S 31 2234 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S) 2235 2236 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7 2237 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S) 2238 2239 #define FW_ACL_VLAN_CMD_FM_S 6 2240 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S) 2241 2242 enum fw_port_cap { 2243 FW_PORT_CAP_SPEED_100M = 0x0001, 2244 FW_PORT_CAP_SPEED_1G = 0x0002, 2245 FW_PORT_CAP_SPEED_2_5G = 0x0004, 2246 FW_PORT_CAP_SPEED_10G = 0x0008, 2247 FW_PORT_CAP_SPEED_40G = 0x0010, 2248 FW_PORT_CAP_SPEED_100G = 0x0020, 2249 FW_PORT_CAP_FC_RX = 0x0040, 2250 FW_PORT_CAP_FC_TX = 0x0080, 2251 FW_PORT_CAP_ANEG = 0x0100, 2252 FW_PORT_CAP_MDI_0 = 0x0200, 2253 FW_PORT_CAP_MDI_1 = 0x0400, 2254 FW_PORT_CAP_BEAN = 0x0800, 2255 FW_PORT_CAP_PMA_LPBK = 0x1000, 2256 FW_PORT_CAP_PCS_LPBK = 0x2000, 2257 FW_PORT_CAP_PHYXS_LPBK = 0x4000, 2258 FW_PORT_CAP_FAR_END_LPBK = 0x8000, 2259 }; 2260 2261 enum fw_port_mdi { 2262 FW_PORT_CAP_MDI_UNCHANGED, 2263 FW_PORT_CAP_MDI_AUTO, 2264 FW_PORT_CAP_MDI_F_STRAIGHT, 2265 FW_PORT_CAP_MDI_F_CROSSOVER 2266 }; 2267 2268 #define FW_PORT_CAP_MDI_S 9 2269 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S) 2270 2271 enum fw_port_action { 2272 FW_PORT_ACTION_L1_CFG = 0x0001, 2273 FW_PORT_ACTION_L2_CFG = 0x0002, 2274 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 2275 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 2276 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 2277 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 2278 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 2279 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 2280 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 2281 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 2282 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 2283 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 2284 FW_PORT_ACTION_L1_LPBK = 0x0021, 2285 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022, 2286 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023, 2287 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024, 2288 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025, 2289 FW_PORT_ACTION_PHY_RESET = 0x0040, 2290 FW_PORT_ACTION_PMA_RESET = 0x0041, 2291 FW_PORT_ACTION_PCS_RESET = 0x0042, 2292 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 2293 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 2294 FW_PORT_ACTION_AN_RESET = 0x0045 2295 }; 2296 2297 enum fw_port_l2cfg_ctlbf { 2298 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 2299 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 2300 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 2301 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 2302 FW_PORT_L2_CTLBF_IVLAN = 0x10, 2303 FW_PORT_L2_CTLBF_TXIPG = 0x20 2304 }; 2305 2306 enum fw_port_dcb_versions { 2307 FW_PORT_DCB_VER_UNKNOWN, 2308 FW_PORT_DCB_VER_CEE1D0, 2309 FW_PORT_DCB_VER_CEE1D01, 2310 FW_PORT_DCB_VER_IEEE, 2311 FW_PORT_DCB_VER_AUTO = 7 2312 }; 2313 2314 enum fw_port_dcb_cfg { 2315 FW_PORT_DCB_CFG_PG = 0x01, 2316 FW_PORT_DCB_CFG_PFC = 0x02, 2317 FW_PORT_DCB_CFG_APPL = 0x04 2318 }; 2319 2320 enum fw_port_dcb_cfg_rc { 2321 FW_PORT_DCB_CFG_SUCCESS = 0x0, 2322 FW_PORT_DCB_CFG_ERROR = 0x1 2323 }; 2324 2325 enum fw_port_dcb_type { 2326 FW_PORT_DCB_TYPE_PGID = 0x00, 2327 FW_PORT_DCB_TYPE_PGRATE = 0x01, 2328 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 2329 FW_PORT_DCB_TYPE_PFC = 0x03, 2330 FW_PORT_DCB_TYPE_APP_ID = 0x04, 2331 FW_PORT_DCB_TYPE_CONTROL = 0x05, 2332 }; 2333 2334 enum fw_port_dcb_feature_state { 2335 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 2336 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 2337 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 2338 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 2339 }; 2340 2341 struct fw_port_cmd { 2342 __be32 op_to_portid; 2343 __be32 action_to_len16; 2344 union fw_port { 2345 struct fw_port_l1cfg { 2346 __be32 rcap; 2347 __be32 r; 2348 } l1cfg; 2349 struct fw_port_l2cfg { 2350 __u8 ctlbf; 2351 __u8 ovlan3_to_ivlan0; 2352 __be16 ivlantype; 2353 __be16 txipg_force_pinfo; 2354 __be16 mtu; 2355 __be16 ovlan0mask; 2356 __be16 ovlan0type; 2357 __be16 ovlan1mask; 2358 __be16 ovlan1type; 2359 __be16 ovlan2mask; 2360 __be16 ovlan2type; 2361 __be16 ovlan3mask; 2362 __be16 ovlan3type; 2363 } l2cfg; 2364 struct fw_port_info { 2365 __be32 lstatus_to_modtype; 2366 __be16 pcap; 2367 __be16 acap; 2368 __be16 mtu; 2369 __u8 cbllen; 2370 __u8 auxlinfo; 2371 __u8 dcbxdis_pkd; 2372 __u8 r8_lo[3]; 2373 __be64 r9; 2374 } info; 2375 struct fw_port_diags { 2376 __u8 diagop; 2377 __u8 r[3]; 2378 __be32 diagval; 2379 } diags; 2380 union fw_port_dcb { 2381 struct fw_port_dcb_pgid { 2382 __u8 type; 2383 __u8 apply_pkd; 2384 __u8 r10_lo[2]; 2385 __be32 pgid; 2386 __be64 r11; 2387 } pgid; 2388 struct fw_port_dcb_pgrate { 2389 __u8 type; 2390 __u8 apply_pkd; 2391 __u8 r10_lo[5]; 2392 __u8 num_tcs_supported; 2393 __u8 pgrate[8]; 2394 __u8 tsa[8]; 2395 } pgrate; 2396 struct fw_port_dcb_priorate { 2397 __u8 type; 2398 __u8 apply_pkd; 2399 __u8 r10_lo[6]; 2400 __u8 strict_priorate[8]; 2401 } priorate; 2402 struct fw_port_dcb_pfc { 2403 __u8 type; 2404 __u8 pfcen; 2405 __u8 r10[5]; 2406 __u8 max_pfc_tcs; 2407 __be64 r11; 2408 } pfc; 2409 struct fw_port_app_priority { 2410 __u8 type; 2411 __u8 r10[2]; 2412 __u8 idx; 2413 __u8 user_prio_map; 2414 __u8 sel_field; 2415 __be16 protocolid; 2416 __be64 r12; 2417 } app_priority; 2418 struct fw_port_dcb_control { 2419 __u8 type; 2420 __u8 all_syncd_pkd; 2421 __be16 dcb_version_to_app_state; 2422 __be32 r11; 2423 __be64 r12; 2424 } control; 2425 } dcb; 2426 } u; 2427 }; 2428 2429 #define FW_PORT_CMD_READ_S 22 2430 #define FW_PORT_CMD_READ_V(x) ((x) << FW_PORT_CMD_READ_S) 2431 #define FW_PORT_CMD_READ_F FW_PORT_CMD_READ_V(1U) 2432 2433 #define FW_PORT_CMD_PORTID_S 0 2434 #define FW_PORT_CMD_PORTID_M 0xf 2435 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S) 2436 #define FW_PORT_CMD_PORTID_G(x) \ 2437 (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M) 2438 2439 #define FW_PORT_CMD_ACTION_S 16 2440 #define FW_PORT_CMD_ACTION_M 0xffff 2441 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S) 2442 #define FW_PORT_CMD_ACTION_G(x) \ 2443 (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M) 2444 2445 #define FW_PORT_CMD_OVLAN3_S 7 2446 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S) 2447 2448 #define FW_PORT_CMD_OVLAN2_S 6 2449 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S) 2450 2451 #define FW_PORT_CMD_OVLAN1_S 5 2452 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S) 2453 2454 #define FW_PORT_CMD_OVLAN0_S 4 2455 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S) 2456 2457 #define FW_PORT_CMD_IVLAN0_S 3 2458 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S) 2459 2460 #define FW_PORT_CMD_TXIPG_S 3 2461 #define FW_PORT_CMD_TXIPG_V(x) ((x) << FW_PORT_CMD_TXIPG_S) 2462 2463 #define FW_PORT_CMD_LSTATUS_S 31 2464 #define FW_PORT_CMD_LSTATUS_M 0x1 2465 #define FW_PORT_CMD_LSTATUS_V(x) ((x) << FW_PORT_CMD_LSTATUS_S) 2466 #define FW_PORT_CMD_LSTATUS_G(x) \ 2467 (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M) 2468 #define FW_PORT_CMD_LSTATUS_F FW_PORT_CMD_LSTATUS_V(1U) 2469 2470 #define FW_PORT_CMD_LSPEED_S 24 2471 #define FW_PORT_CMD_LSPEED_M 0x3f 2472 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S) 2473 #define FW_PORT_CMD_LSPEED_G(x) \ 2474 (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M) 2475 2476 #define FW_PORT_CMD_TXPAUSE_S 23 2477 #define FW_PORT_CMD_TXPAUSE_V(x) ((x) << FW_PORT_CMD_TXPAUSE_S) 2478 #define FW_PORT_CMD_TXPAUSE_F FW_PORT_CMD_TXPAUSE_V(1U) 2479 2480 #define FW_PORT_CMD_RXPAUSE_S 22 2481 #define FW_PORT_CMD_RXPAUSE_V(x) ((x) << FW_PORT_CMD_RXPAUSE_S) 2482 #define FW_PORT_CMD_RXPAUSE_F FW_PORT_CMD_RXPAUSE_V(1U) 2483 2484 #define FW_PORT_CMD_MDIOCAP_S 21 2485 #define FW_PORT_CMD_MDIOCAP_V(x) ((x) << FW_PORT_CMD_MDIOCAP_S) 2486 #define FW_PORT_CMD_MDIOCAP_F FW_PORT_CMD_MDIOCAP_V(1U) 2487 2488 #define FW_PORT_CMD_MDIOADDR_S 16 2489 #define FW_PORT_CMD_MDIOADDR_M 0x1f 2490 #define FW_PORT_CMD_MDIOADDR_G(x) \ 2491 (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M) 2492 2493 #define FW_PORT_CMD_LPTXPAUSE_S 15 2494 #define FW_PORT_CMD_LPTXPAUSE_V(x) ((x) << FW_PORT_CMD_LPTXPAUSE_S) 2495 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U) 2496 2497 #define FW_PORT_CMD_LPRXPAUSE_S 14 2498 #define FW_PORT_CMD_LPRXPAUSE_V(x) ((x) << FW_PORT_CMD_LPRXPAUSE_S) 2499 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U) 2500 2501 #define FW_PORT_CMD_PTYPE_S 8 2502 #define FW_PORT_CMD_PTYPE_M 0x1f 2503 #define FW_PORT_CMD_PTYPE_G(x) \ 2504 (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M) 2505 2506 #define FW_PORT_CMD_MODTYPE_S 0 2507 #define FW_PORT_CMD_MODTYPE_M 0x1f 2508 #define FW_PORT_CMD_MODTYPE_V(x) ((x) << FW_PORT_CMD_MODTYPE_S) 2509 #define FW_PORT_CMD_MODTYPE_G(x) \ 2510 (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M) 2511 2512 #define FW_PORT_CMD_DCBXDIS_S 7 2513 #define FW_PORT_CMD_DCBXDIS_V(x) ((x) << FW_PORT_CMD_DCBXDIS_S) 2514 #define FW_PORT_CMD_DCBXDIS_F FW_PORT_CMD_DCBXDIS_V(1U) 2515 2516 #define FW_PORT_CMD_APPLY_S 7 2517 #define FW_PORT_CMD_APPLY_V(x) ((x) << FW_PORT_CMD_APPLY_S) 2518 #define FW_PORT_CMD_APPLY_F FW_PORT_CMD_APPLY_V(1U) 2519 2520 #define FW_PORT_CMD_ALL_SYNCD_S 7 2521 #define FW_PORT_CMD_ALL_SYNCD_V(x) ((x) << FW_PORT_CMD_ALL_SYNCD_S) 2522 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U) 2523 2524 #define FW_PORT_CMD_DCB_VERSION_S 12 2525 #define FW_PORT_CMD_DCB_VERSION_M 0x7 2526 #define FW_PORT_CMD_DCB_VERSION_G(x) \ 2527 (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M) 2528 2529 enum fw_port_type { 2530 FW_PORT_TYPE_FIBER_XFI, 2531 FW_PORT_TYPE_FIBER_XAUI, 2532 FW_PORT_TYPE_BT_SGMII, 2533 FW_PORT_TYPE_BT_XFI, 2534 FW_PORT_TYPE_BT_XAUI, 2535 FW_PORT_TYPE_KX4, 2536 FW_PORT_TYPE_CX4, 2537 FW_PORT_TYPE_KX, 2538 FW_PORT_TYPE_KR, 2539 FW_PORT_TYPE_SFP, 2540 FW_PORT_TYPE_BP_AP, 2541 FW_PORT_TYPE_BP4_AP, 2542 FW_PORT_TYPE_QSFP_10G, 2543 FW_PORT_TYPE_QSA, 2544 FW_PORT_TYPE_QSFP, 2545 FW_PORT_TYPE_BP40_BA, 2546 2547 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M 2548 }; 2549 2550 enum fw_port_module_type { 2551 FW_PORT_MOD_TYPE_NA, 2552 FW_PORT_MOD_TYPE_LR, 2553 FW_PORT_MOD_TYPE_SR, 2554 FW_PORT_MOD_TYPE_ER, 2555 FW_PORT_MOD_TYPE_TWINAX_PASSIVE, 2556 FW_PORT_MOD_TYPE_TWINAX_ACTIVE, 2557 FW_PORT_MOD_TYPE_LRM, 2558 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_M - 3, 2559 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_M - 2, 2560 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_M - 1, 2561 2562 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M 2563 }; 2564 2565 enum fw_port_mod_sub_type { 2566 FW_PORT_MOD_SUB_TYPE_NA, 2567 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 2568 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 2569 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 2570 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 2571 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 2572 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 2573 2574 /* The following will never been in the VPD. They are TWINAX cable 2575 * lengths decoded from SFP+ module i2c PROMs. These should 2576 * almost certainly go somewhere else ... 2577 */ 2578 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 2579 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 2580 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 2581 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 2582 }; 2583 2584 enum fw_port_stats_tx_index { 2585 FW_STAT_TX_PORT_BYTES_IX = 0, 2586 FW_STAT_TX_PORT_FRAMES_IX, 2587 FW_STAT_TX_PORT_BCAST_IX, 2588 FW_STAT_TX_PORT_MCAST_IX, 2589 FW_STAT_TX_PORT_UCAST_IX, 2590 FW_STAT_TX_PORT_ERROR_IX, 2591 FW_STAT_TX_PORT_64B_IX, 2592 FW_STAT_TX_PORT_65B_127B_IX, 2593 FW_STAT_TX_PORT_128B_255B_IX, 2594 FW_STAT_TX_PORT_256B_511B_IX, 2595 FW_STAT_TX_PORT_512B_1023B_IX, 2596 FW_STAT_TX_PORT_1024B_1518B_IX, 2597 FW_STAT_TX_PORT_1519B_MAX_IX, 2598 FW_STAT_TX_PORT_DROP_IX, 2599 FW_STAT_TX_PORT_PAUSE_IX, 2600 FW_STAT_TX_PORT_PPP0_IX, 2601 FW_STAT_TX_PORT_PPP1_IX, 2602 FW_STAT_TX_PORT_PPP2_IX, 2603 FW_STAT_TX_PORT_PPP3_IX, 2604 FW_STAT_TX_PORT_PPP4_IX, 2605 FW_STAT_TX_PORT_PPP5_IX, 2606 FW_STAT_TX_PORT_PPP6_IX, 2607 FW_STAT_TX_PORT_PPP7_IX, 2608 FW_NUM_PORT_TX_STATS 2609 }; 2610 2611 enum fw_port_stat_rx_index { 2612 FW_STAT_RX_PORT_BYTES_IX = 0, 2613 FW_STAT_RX_PORT_FRAMES_IX, 2614 FW_STAT_RX_PORT_BCAST_IX, 2615 FW_STAT_RX_PORT_MCAST_IX, 2616 FW_STAT_RX_PORT_UCAST_IX, 2617 FW_STAT_RX_PORT_MTU_ERROR_IX, 2618 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 2619 FW_STAT_RX_PORT_CRC_ERROR_IX, 2620 FW_STAT_RX_PORT_LEN_ERROR_IX, 2621 FW_STAT_RX_PORT_SYM_ERROR_IX, 2622 FW_STAT_RX_PORT_64B_IX, 2623 FW_STAT_RX_PORT_65B_127B_IX, 2624 FW_STAT_RX_PORT_128B_255B_IX, 2625 FW_STAT_RX_PORT_256B_511B_IX, 2626 FW_STAT_RX_PORT_512B_1023B_IX, 2627 FW_STAT_RX_PORT_1024B_1518B_IX, 2628 FW_STAT_RX_PORT_1519B_MAX_IX, 2629 FW_STAT_RX_PORT_PAUSE_IX, 2630 FW_STAT_RX_PORT_PPP0_IX, 2631 FW_STAT_RX_PORT_PPP1_IX, 2632 FW_STAT_RX_PORT_PPP2_IX, 2633 FW_STAT_RX_PORT_PPP3_IX, 2634 FW_STAT_RX_PORT_PPP4_IX, 2635 FW_STAT_RX_PORT_PPP5_IX, 2636 FW_STAT_RX_PORT_PPP6_IX, 2637 FW_STAT_RX_PORT_PPP7_IX, 2638 FW_STAT_RX_PORT_LESS_64B_IX, 2639 FW_STAT_RX_PORT_MAC_ERROR_IX, 2640 FW_NUM_PORT_RX_STATS 2641 }; 2642 2643 /* port stats */ 2644 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS) 2645 2646 struct fw_port_stats_cmd { 2647 __be32 op_to_portid; 2648 __be32 retval_len16; 2649 union fw_port_stats { 2650 struct fw_port_stats_ctl { 2651 u8 nstats_bg_bm; 2652 u8 tx_ix; 2653 __be16 r6; 2654 __be32 r7; 2655 __be64 stat0; 2656 __be64 stat1; 2657 __be64 stat2; 2658 __be64 stat3; 2659 __be64 stat4; 2660 __be64 stat5; 2661 } ctl; 2662 struct fw_port_stats_all { 2663 __be64 tx_bytes; 2664 __be64 tx_frames; 2665 __be64 tx_bcast; 2666 __be64 tx_mcast; 2667 __be64 tx_ucast; 2668 __be64 tx_error; 2669 __be64 tx_64b; 2670 __be64 tx_65b_127b; 2671 __be64 tx_128b_255b; 2672 __be64 tx_256b_511b; 2673 __be64 tx_512b_1023b; 2674 __be64 tx_1024b_1518b; 2675 __be64 tx_1519b_max; 2676 __be64 tx_drop; 2677 __be64 tx_pause; 2678 __be64 tx_ppp0; 2679 __be64 tx_ppp1; 2680 __be64 tx_ppp2; 2681 __be64 tx_ppp3; 2682 __be64 tx_ppp4; 2683 __be64 tx_ppp5; 2684 __be64 tx_ppp6; 2685 __be64 tx_ppp7; 2686 __be64 rx_bytes; 2687 __be64 rx_frames; 2688 __be64 rx_bcast; 2689 __be64 rx_mcast; 2690 __be64 rx_ucast; 2691 __be64 rx_mtu_error; 2692 __be64 rx_mtu_crc_error; 2693 __be64 rx_crc_error; 2694 __be64 rx_len_error; 2695 __be64 rx_sym_error; 2696 __be64 rx_64b; 2697 __be64 rx_65b_127b; 2698 __be64 rx_128b_255b; 2699 __be64 rx_256b_511b; 2700 __be64 rx_512b_1023b; 2701 __be64 rx_1024b_1518b; 2702 __be64 rx_1519b_max; 2703 __be64 rx_pause; 2704 __be64 rx_ppp0; 2705 __be64 rx_ppp1; 2706 __be64 rx_ppp2; 2707 __be64 rx_ppp3; 2708 __be64 rx_ppp4; 2709 __be64 rx_ppp5; 2710 __be64 rx_ppp6; 2711 __be64 rx_ppp7; 2712 __be64 rx_less_64b; 2713 __be64 rx_bg_drop; 2714 __be64 rx_bg_trunc; 2715 } all; 2716 } u; 2717 }; 2718 2719 /* port loopback stats */ 2720 #define FW_NUM_LB_STATS 16 2721 enum fw_port_lb_stats_index { 2722 FW_STAT_LB_PORT_BYTES_IX, 2723 FW_STAT_LB_PORT_FRAMES_IX, 2724 FW_STAT_LB_PORT_BCAST_IX, 2725 FW_STAT_LB_PORT_MCAST_IX, 2726 FW_STAT_LB_PORT_UCAST_IX, 2727 FW_STAT_LB_PORT_ERROR_IX, 2728 FW_STAT_LB_PORT_64B_IX, 2729 FW_STAT_LB_PORT_65B_127B_IX, 2730 FW_STAT_LB_PORT_128B_255B_IX, 2731 FW_STAT_LB_PORT_256B_511B_IX, 2732 FW_STAT_LB_PORT_512B_1023B_IX, 2733 FW_STAT_LB_PORT_1024B_1518B_IX, 2734 FW_STAT_LB_PORT_1519B_MAX_IX, 2735 FW_STAT_LB_PORT_DROP_FRAMES_IX 2736 }; 2737 2738 struct fw_port_lb_stats_cmd { 2739 __be32 op_to_lbport; 2740 __be32 retval_len16; 2741 union fw_port_lb_stats { 2742 struct fw_port_lb_stats_ctl { 2743 u8 nstats_bg_bm; 2744 u8 ix_pkd; 2745 __be16 r6; 2746 __be32 r7; 2747 __be64 stat0; 2748 __be64 stat1; 2749 __be64 stat2; 2750 __be64 stat3; 2751 __be64 stat4; 2752 __be64 stat5; 2753 } ctl; 2754 struct fw_port_lb_stats_all { 2755 __be64 tx_bytes; 2756 __be64 tx_frames; 2757 __be64 tx_bcast; 2758 __be64 tx_mcast; 2759 __be64 tx_ucast; 2760 __be64 tx_error; 2761 __be64 tx_64b; 2762 __be64 tx_65b_127b; 2763 __be64 tx_128b_255b; 2764 __be64 tx_256b_511b; 2765 __be64 tx_512b_1023b; 2766 __be64 tx_1024b_1518b; 2767 __be64 tx_1519b_max; 2768 __be64 rx_lb_drop; 2769 __be64 rx_lb_trunc; 2770 } all; 2771 } u; 2772 }; 2773 2774 struct fw_rss_ind_tbl_cmd { 2775 __be32 op_to_viid; 2776 __be32 retval_len16; 2777 __be16 niqid; 2778 __be16 startidx; 2779 __be32 r3; 2780 __be32 iq0_to_iq2; 2781 __be32 iq3_to_iq5; 2782 __be32 iq6_to_iq8; 2783 __be32 iq9_to_iq11; 2784 __be32 iq12_to_iq14; 2785 __be32 iq15_to_iq17; 2786 __be32 iq18_to_iq20; 2787 __be32 iq21_to_iq23; 2788 __be32 iq24_to_iq26; 2789 __be32 iq27_to_iq29; 2790 __be32 iq30_iq31; 2791 __be32 r15_lo; 2792 }; 2793 2794 #define FW_RSS_IND_TBL_CMD_VIID_S 0 2795 #define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S) 2796 2797 #define FW_RSS_IND_TBL_CMD_IQ0_S 20 2798 #define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S) 2799 2800 #define FW_RSS_IND_TBL_CMD_IQ1_S 10 2801 #define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S) 2802 2803 #define FW_RSS_IND_TBL_CMD_IQ2_S 0 2804 #define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S) 2805 2806 struct fw_rss_glb_config_cmd { 2807 __be32 op_to_write; 2808 __be32 retval_len16; 2809 union fw_rss_glb_config { 2810 struct fw_rss_glb_config_manual { 2811 __be32 mode_pkd; 2812 __be32 r3; 2813 __be64 r4; 2814 __be64 r5; 2815 } manual; 2816 struct fw_rss_glb_config_basicvirtual { 2817 __be32 mode_pkd; 2818 __be32 synmapen_to_hashtoeplitz; 2819 __be64 r8; 2820 __be64 r9; 2821 } basicvirtual; 2822 } u; 2823 }; 2824 2825 #define FW_RSS_GLB_CONFIG_CMD_MODE_S 28 2826 #define FW_RSS_GLB_CONFIG_CMD_MODE_M 0xf 2827 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S) 2828 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \ 2829 (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M) 2830 2831 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 2832 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 2833 2834 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8 2835 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \ 2836 ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S) 2837 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \ 2838 FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U) 2839 2840 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7 2841 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \ 2842 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S) 2843 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \ 2844 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U) 2845 2846 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6 2847 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \ 2848 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S) 2849 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \ 2850 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U) 2851 2852 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5 2853 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \ 2854 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S) 2855 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \ 2856 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U) 2857 2858 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4 2859 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \ 2860 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S) 2861 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \ 2862 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U) 2863 2864 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3 2865 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \ 2866 ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S) 2867 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \ 2868 FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U) 2869 2870 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2 2871 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \ 2872 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S) 2873 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \ 2874 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U) 2875 2876 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1 2877 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \ 2878 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S) 2879 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \ 2880 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U) 2881 2882 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0 2883 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \ 2884 ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S) 2885 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \ 2886 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U) 2887 2888 struct fw_rss_vi_config_cmd { 2889 __be32 op_to_viid; 2890 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0) 2891 __be32 retval_len16; 2892 union fw_rss_vi_config { 2893 struct fw_rss_vi_config_manual { 2894 __be64 r3; 2895 __be64 r4; 2896 __be64 r5; 2897 } manual; 2898 struct fw_rss_vi_config_basicvirtual { 2899 __be32 r6; 2900 __be32 defaultq_to_udpen; 2901 __be64 r9; 2902 __be64 r10; 2903 } basicvirtual; 2904 } u; 2905 }; 2906 2907 #define FW_RSS_VI_CONFIG_CMD_VIID_S 0 2908 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S) 2909 2910 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16 2911 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0x3ff 2912 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \ 2913 ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) 2914 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \ 2915 (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \ 2916 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M) 2917 2918 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4 2919 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \ 2920 ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S) 2921 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \ 2922 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U) 2923 2924 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3 2925 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \ 2926 ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S) 2927 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \ 2928 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U) 2929 2930 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2 2931 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \ 2932 ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S) 2933 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \ 2934 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U) 2935 2936 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1 2937 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \ 2938 ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S) 2939 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \ 2940 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U) 2941 2942 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0 2943 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S) 2944 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U) 2945 2946 struct fw_clip_cmd { 2947 __be32 op_to_write; 2948 __be32 alloc_to_len16; 2949 __be64 ip_hi; 2950 __be64 ip_lo; 2951 __be32 r4[2]; 2952 }; 2953 2954 #define FW_CLIP_CMD_ALLOC_S 31 2955 #define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S) 2956 #define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1U) 2957 2958 #define FW_CLIP_CMD_FREE_S 30 2959 #define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S) 2960 #define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1U) 2961 2962 enum fw_error_type { 2963 FW_ERROR_TYPE_EXCEPTION = 0x0, 2964 FW_ERROR_TYPE_HWMODULE = 0x1, 2965 FW_ERROR_TYPE_WR = 0x2, 2966 FW_ERROR_TYPE_ACL = 0x3, 2967 }; 2968 2969 struct fw_error_cmd { 2970 __be32 op_to_type; 2971 __be32 len16_pkd; 2972 union fw_error { 2973 struct fw_error_exception { 2974 __be32 info[6]; 2975 } exception; 2976 struct fw_error_hwmodule { 2977 __be32 regaddr; 2978 __be32 regval; 2979 } hwmodule; 2980 struct fw_error_wr { 2981 __be16 cidx; 2982 __be16 pfn_vfn; 2983 __be32 eqid; 2984 u8 wrhdr[16]; 2985 } wr; 2986 struct fw_error_acl { 2987 __be16 cidx; 2988 __be16 pfn_vfn; 2989 __be32 eqid; 2990 __be16 mv_pkd; 2991 u8 val[6]; 2992 __be64 r4; 2993 } acl; 2994 } u; 2995 }; 2996 2997 struct fw_debug_cmd { 2998 __be32 op_type; 2999 __be32 len16_pkd; 3000 union fw_debug { 3001 struct fw_debug_assert { 3002 __be32 fcid; 3003 __be32 line; 3004 __be32 x; 3005 __be32 y; 3006 u8 filename_0_7[8]; 3007 u8 filename_8_15[8]; 3008 __be64 r3; 3009 } assert; 3010 struct fw_debug_prt { 3011 __be16 dprtstridx; 3012 __be16 r3[3]; 3013 __be32 dprtstrparam0; 3014 __be32 dprtstrparam1; 3015 __be32 dprtstrparam2; 3016 __be32 dprtstrparam3; 3017 } prt; 3018 } u; 3019 }; 3020 3021 #define FW_DEBUG_CMD_TYPE_S 0 3022 #define FW_DEBUG_CMD_TYPE_M 0xff 3023 #define FW_DEBUG_CMD_TYPE_G(x) \ 3024 (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M) 3025 3026 #define PCIE_FW_ERR_S 31 3027 #define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S) 3028 #define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U) 3029 3030 #define PCIE_FW_INIT_S 30 3031 #define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S) 3032 #define PCIE_FW_INIT_F PCIE_FW_INIT_V(1U) 3033 3034 #define PCIE_FW_HALT_S 29 3035 #define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S) 3036 #define PCIE_FW_HALT_F PCIE_FW_HALT_V(1U) 3037 3038 #define PCIE_FW_EVAL_S 24 3039 #define PCIE_FW_EVAL_M 0x7 3040 #define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M) 3041 3042 #define PCIE_FW_MASTER_VLD_S 15 3043 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S) 3044 #define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1U) 3045 3046 #define PCIE_FW_MASTER_S 12 3047 #define PCIE_FW_MASTER_M 0x7 3048 #define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S) 3049 #define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M) 3050 3051 struct fw_hdr { 3052 u8 ver; 3053 u8 chip; /* terminator chip type */ 3054 __be16 len512; /* bin length in units of 512-bytes */ 3055 __be32 fw_ver; /* firmware version */ 3056 __be32 tp_microcode_ver; 3057 u8 intfver_nic; 3058 u8 intfver_vnic; 3059 u8 intfver_ofld; 3060 u8 intfver_ri; 3061 u8 intfver_iscsipdu; 3062 u8 intfver_iscsi; 3063 u8 intfver_fcoepdu; 3064 u8 intfver_fcoe; 3065 __u32 reserved2; 3066 __u32 reserved3; 3067 __u32 reserved4; 3068 __be32 flags; 3069 __be32 reserved6[23]; 3070 }; 3071 3072 enum fw_hdr_chip { 3073 FW_HDR_CHIP_T4, 3074 FW_HDR_CHIP_T5, 3075 FW_HDR_CHIP_T6 3076 }; 3077 3078 #define FW_HDR_FW_VER_MAJOR_S 24 3079 #define FW_HDR_FW_VER_MAJOR_M 0xff 3080 #define FW_HDR_FW_VER_MAJOR_V(x) \ 3081 ((x) << FW_HDR_FW_VER_MAJOR_S) 3082 #define FW_HDR_FW_VER_MAJOR_G(x) \ 3083 (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M) 3084 3085 #define FW_HDR_FW_VER_MINOR_S 16 3086 #define FW_HDR_FW_VER_MINOR_M 0xff 3087 #define FW_HDR_FW_VER_MINOR_V(x) \ 3088 ((x) << FW_HDR_FW_VER_MINOR_S) 3089 #define FW_HDR_FW_VER_MINOR_G(x) \ 3090 (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M) 3091 3092 #define FW_HDR_FW_VER_MICRO_S 8 3093 #define FW_HDR_FW_VER_MICRO_M 0xff 3094 #define FW_HDR_FW_VER_MICRO_V(x) \ 3095 ((x) << FW_HDR_FW_VER_MICRO_S) 3096 #define FW_HDR_FW_VER_MICRO_G(x) \ 3097 (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M) 3098 3099 #define FW_HDR_FW_VER_BUILD_S 0 3100 #define FW_HDR_FW_VER_BUILD_M 0xff 3101 #define FW_HDR_FW_VER_BUILD_V(x) \ 3102 ((x) << FW_HDR_FW_VER_BUILD_S) 3103 #define FW_HDR_FW_VER_BUILD_G(x) \ 3104 (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M) 3105 3106 enum fw_hdr_intfver { 3107 FW_HDR_INTFVER_NIC = 0x00, 3108 FW_HDR_INTFVER_VNIC = 0x00, 3109 FW_HDR_INTFVER_OFLD = 0x00, 3110 FW_HDR_INTFVER_RI = 0x00, 3111 FW_HDR_INTFVER_ISCSIPDU = 0x00, 3112 FW_HDR_INTFVER_ISCSI = 0x00, 3113 FW_HDR_INTFVER_FCOEPDU = 0x00, 3114 FW_HDR_INTFVER_FCOE = 0x00, 3115 }; 3116 3117 enum fw_hdr_flags { 3118 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 3119 }; 3120 3121 /* length of the formatting string */ 3122 #define FW_DEVLOG_FMT_LEN 192 3123 3124 /* maximum number of the formatting string parameters */ 3125 #define FW_DEVLOG_FMT_PARAMS_NUM 8 3126 3127 /* priority levels */ 3128 enum fw_devlog_level { 3129 FW_DEVLOG_LEVEL_EMERG = 0x0, 3130 FW_DEVLOG_LEVEL_CRIT = 0x1, 3131 FW_DEVLOG_LEVEL_ERR = 0x2, 3132 FW_DEVLOG_LEVEL_NOTICE = 0x3, 3133 FW_DEVLOG_LEVEL_INFO = 0x4, 3134 FW_DEVLOG_LEVEL_DEBUG = 0x5, 3135 FW_DEVLOG_LEVEL_MAX = 0x5, 3136 }; 3137 3138 /* facilities that may send a log message */ 3139 enum fw_devlog_facility { 3140 FW_DEVLOG_FACILITY_CORE = 0x00, 3141 FW_DEVLOG_FACILITY_CF = 0x01, 3142 FW_DEVLOG_FACILITY_SCHED = 0x02, 3143 FW_DEVLOG_FACILITY_TIMER = 0x04, 3144 FW_DEVLOG_FACILITY_RES = 0x06, 3145 FW_DEVLOG_FACILITY_HW = 0x08, 3146 FW_DEVLOG_FACILITY_FLR = 0x10, 3147 FW_DEVLOG_FACILITY_DMAQ = 0x12, 3148 FW_DEVLOG_FACILITY_PHY = 0x14, 3149 FW_DEVLOG_FACILITY_MAC = 0x16, 3150 FW_DEVLOG_FACILITY_PORT = 0x18, 3151 FW_DEVLOG_FACILITY_VI = 0x1A, 3152 FW_DEVLOG_FACILITY_FILTER = 0x1C, 3153 FW_DEVLOG_FACILITY_ACL = 0x1E, 3154 FW_DEVLOG_FACILITY_TM = 0x20, 3155 FW_DEVLOG_FACILITY_QFC = 0x22, 3156 FW_DEVLOG_FACILITY_DCB = 0x24, 3157 FW_DEVLOG_FACILITY_ETH = 0x26, 3158 FW_DEVLOG_FACILITY_OFLD = 0x28, 3159 FW_DEVLOG_FACILITY_RI = 0x2A, 3160 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 3161 FW_DEVLOG_FACILITY_FCOE = 0x2E, 3162 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 3163 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 3164 FW_DEVLOG_FACILITY_CHNET = 0x34, 3165 FW_DEVLOG_FACILITY_MAX = 0x34, 3166 }; 3167 3168 /* log message format */ 3169 struct fw_devlog_e { 3170 __be64 timestamp; 3171 __be32 seqno; 3172 __be16 reserved1; 3173 __u8 level; 3174 __u8 facility; 3175 __u8 fmt[FW_DEVLOG_FMT_LEN]; 3176 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 3177 __be32 reserved3[4]; 3178 }; 3179 3180 struct fw_devlog_cmd { 3181 __be32 op_to_write; 3182 __be32 retval_len16; 3183 __u8 level; 3184 __u8 r2[7]; 3185 __be32 memtype_devlog_memaddr16_devlog; 3186 __be32 memsize_devlog; 3187 __be32 r3[2]; 3188 }; 3189 3190 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28 3191 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf 3192 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \ 3193 (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \ 3194 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M) 3195 3196 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0 3197 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff 3198 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \ 3199 (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \ 3200 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M) 3201 3202 /* P C I E F W P F 7 R E G I S T E R */ 3203 3204 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to 3205 * access the "devlog" which needing to contact firmware. The encoding is 3206 * mostly the same as that returned by the DEVLOG command except for the size 3207 * which is encoded as the number of entries in multiples-1 of 128 here rather 3208 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 3209 * and 15 means 2048. This of course in turn constrains the allowed values 3210 * for the devlog size ... 3211 */ 3212 #define PCIE_FW_PF_DEVLOG 7 3213 3214 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28 3215 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf 3216 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \ 3217 ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S) 3218 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \ 3219 (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \ 3220 PCIE_FW_PF_DEVLOG_NENTRIES128_M) 3221 3222 #define PCIE_FW_PF_DEVLOG_ADDR16_S 4 3223 #define PCIE_FW_PF_DEVLOG_ADDR16_M 0xffffff 3224 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x) ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S) 3225 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \ 3226 (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M) 3227 3228 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0 3229 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf 3230 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S) 3231 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \ 3232 (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M) 3233 3234 #endif /* _T4FW_INTERFACE_H_ */ 3235