1 /* 2 * dim2_reg.h - Definitions for registers of DIM2 3 * (MediaLB, Device Interface Macro IP, OS62420) 4 * 5 * Copyright (C) 2015, Microchip Technology Germany II GmbH & Co. KG 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * This file is licensed under GPLv2. 13 */ 14 15 #ifndef DIM2_OS62420_H 16 #define DIM2_OS62420_H 17 18 #include <linux/types.h> 19 20 #ifdef __cplusplus 21 extern "C" { 22 #endif 23 24 25 struct dim2_regs { 26 /* 0x00 */ u32 MLBC0; 27 /* 0x01 */ u32 rsvd0[1]; 28 /* 0x02 */ u32 MLBPC0; 29 /* 0x03 */ u32 MS0; 30 /* 0x04 */ u32 rsvd1[1]; 31 /* 0x05 */ u32 MS1; 32 /* 0x06 */ u32 rsvd2[2]; 33 /* 0x08 */ u32 MSS; 34 /* 0x09 */ u32 MSD; 35 /* 0x0A */ u32 rsvd3[1]; 36 /* 0x0B */ u32 MIEN; 37 /* 0x0C */ u32 rsvd4[1]; 38 /* 0x0D */ u32 MLBPC2; 39 /* 0x0E */ u32 MLBPC1; 40 /* 0x0F */ u32 MLBC1; 41 /* 0x10 */ u32 rsvd5[0x10]; 42 /* 0x20 */ u32 HCTL; 43 /* 0x21 */ u32 rsvd6[1]; 44 /* 0x22 */ u32 HCMR0; 45 /* 0x23 */ u32 HCMR1; 46 /* 0x24 */ u32 HCER0; 47 /* 0x25 */ u32 HCER1; 48 /* 0x26 */ u32 HCBR0; 49 /* 0x27 */ u32 HCBR1; 50 /* 0x28 */ u32 rsvd7[8]; 51 /* 0x30 */ u32 MDAT0; 52 /* 0x31 */ u32 MDAT1; 53 /* 0x32 */ u32 MDAT2; 54 /* 0x33 */ u32 MDAT3; 55 /* 0x34 */ u32 MDWE0; 56 /* 0x35 */ u32 MDWE1; 57 /* 0x36 */ u32 MDWE2; 58 /* 0x37 */ u32 MDWE3; 59 /* 0x38 */ u32 MCTL; 60 /* 0x39 */ u32 MADR; 61 /* 0x3A */ u32 rsvd8[0xB6]; 62 /* 0xF0 */ u32 ACTL; 63 /* 0xF1 */ u32 rsvd9[3]; 64 /* 0xF4 */ u32 ACSR0; 65 /* 0xF5 */ u32 ACSR1; 66 /* 0xF6 */ u32 ACMR0; 67 /* 0xF7 */ u32 ACMR1; 68 }; 69 70 71 #define DIM2_MASK(n) (~((~(u32)0)<<(n))) 72 73 enum { 74 MLBC0_MLBLK_BIT = 7, 75 76 MLBC0_MLBPEN_BIT = 5, 77 78 MLBC0_MLBCLK_SHIFT = 2, 79 MLBC0_MLBCLK_VAL_256FS = 0, 80 MLBC0_MLBCLK_VAL_512FS = 1, 81 MLBC0_MLBCLK_VAL_1024FS = 2, 82 MLBC0_MLBCLK_VAL_2048FS = 3, 83 84 MLBC0_FCNT_SHIFT = 15, 85 MLBC0_FCNT_MASK = 7, 86 MLBC0_FCNT_VAL_1FPSB = 0, 87 MLBC0_FCNT_VAL_2FPSB = 1, 88 MLBC0_FCNT_VAL_4FPSB = 2, 89 MLBC0_FCNT_VAL_8FPSB = 3, 90 MLBC0_FCNT_VAL_16FPSB = 4, 91 MLBC0_FCNT_VAL_32FPSB = 5, 92 MLBC0_FCNT_VAL_64FPSB = 6, 93 94 MLBC0_MLBEN_BIT = 0, 95 96 MIEN_CTX_BREAK_BIT = 29, 97 MIEN_CTX_PE_BIT = 28, 98 MIEN_CTX_DONE_BIT = 27, 99 100 MIEN_CRX_BREAK_BIT = 26, 101 MIEN_CRX_PE_BIT = 25, 102 MIEN_CRX_DONE_BIT = 24, 103 104 MIEN_ATX_BREAK_BIT = 22, 105 MIEN_ATX_PE_BIT = 21, 106 MIEN_ATX_DONE_BIT = 20, 107 108 MIEN_ARX_BREAK_BIT = 19, 109 MIEN_ARX_PE_BIT = 18, 110 MIEN_ARX_DONE_BIT = 17, 111 112 MIEN_SYNC_PE_BIT = 16, 113 114 MIEN_ISOC_BUFO_BIT = 1, 115 MIEN_ISOC_PE_BIT = 0, 116 117 MLBC1_NDA_SHIFT = 8, 118 MLBC1_NDA_MASK = 0xFF, 119 120 MLBC1_CLKMERR_BIT = 7, 121 MLBC1_LOCKERR_BIT = 6, 122 123 ACTL_DMA_MODE_BIT = 2, 124 ACTL_DMA_MODE_VAL_DMA_MODE_0 = 0, 125 ACTL_DMA_MODE_VAL_DMA_MODE_1 = 1, 126 ACTL_SCE_BIT = 0, 127 128 HCTL_EN_BIT = 15 129 }; 130 131 enum { 132 CDT1_BS_ISOC_SHIFT = 0, 133 CDT1_BS_ISOC_MASK = DIM2_MASK(9), 134 135 CDT3_BD_SHIFT = 0, 136 CDT3_BD_MASK = DIM2_MASK(12), 137 CDT3_BD_ISOC_MASK = DIM2_MASK(13), 138 CDT3_BA_SHIFT = 16, 139 140 ADT0_CE_BIT = 15, 141 ADT0_LE_BIT = 14, 142 ADT0_PG_BIT = 13, 143 144 ADT1_RDY_BIT = 15, 145 ADT1_DNE_BIT = 14, 146 ADT1_ERR_BIT = 13, 147 ADT1_PS_BIT = 12, 148 ADT1_MEP_BIT = 11, 149 ADT1_BD_SHIFT = 0, 150 ADT1_CTRL_ASYNC_BD_MASK = DIM2_MASK(11), 151 ADT1_ISOC_SYNC_BD_MASK = DIM2_MASK(13), 152 153 CAT_MFE_BIT = 14, 154 155 CAT_MT_BIT = 13, 156 157 CAT_RNW_BIT = 12, 158 159 CAT_CE_BIT = 11, 160 161 CAT_CT_SHIFT = 8, 162 CAT_CT_VAL_SYNC = 0, 163 CAT_CT_VAL_CONTROL = 1, 164 CAT_CT_VAL_ASYNC = 2, 165 CAT_CT_VAL_ISOC = 3, 166 167 CAT_CL_SHIFT = 0, 168 CAT_CL_MASK = DIM2_MASK(6) 169 }; 170 171 172 #ifdef __cplusplus 173 } 174 #endif 175 176 #endif /* DIM2_OS62420_H */ 177