1 /*
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2015 Intel Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * BSD LICENSE
20 *
21 * Copyright(c) 2015 Intel Corporation.
22 *
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
25 * are met:
26 *
27 * - Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * - Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in
31 * the documentation and/or other materials provided with the
32 * distribution.
33 * - Neither the name of Intel Corporation nor the names of its
34 * contributors may be used to endorse or promote products derived
35 * from this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 */
50
51 #ifndef _COMMON_H
52 #define _COMMON_H
53
54 #include <rdma/hfi/hfi1_user.h>
55
56 /*
57 * This file contains defines, structures, etc. that are used
58 * to communicate between kernel and user code.
59 */
60
61 /* version of protocol header (known to chip also). In the long run,
62 * we should be able to generate and accept a range of version numbers;
63 * for now we only accept one, and it's compiled in.
64 */
65 #define IPS_PROTO_VERSION 2
66
67 /*
68 * These are compile time constants that you may want to enable or disable
69 * if you are trying to debug problems with code or performance.
70 * HFI1_VERBOSE_TRACING define as 1 if you want additional tracing in
71 * fast path code
72 * HFI1_TRACE_REGWRITES define as 1 if you want register writes to be
73 * traced in fast path code
74 * _HFI1_TRACING define as 0 if you want to remove all tracing in a
75 * compilation unit
76 */
77
78 /*
79 * If a packet's QP[23:16] bits match this value, then it is
80 * a PSM packet and the hardware will expect a KDETH header
81 * following the BTH.
82 */
83 #define DEFAULT_KDETH_QP 0x80
84
85 /* driver/hw feature set bitmask */
86 #define HFI1_CAP_USER_SHIFT 24
87 #define HFI1_CAP_MASK ((1UL << HFI1_CAP_USER_SHIFT) - 1)
88 /* locked flag - if set, only HFI1_CAP_WRITABLE_MASK bits can be set */
89 #define HFI1_CAP_LOCKED_SHIFT 63
90 #define HFI1_CAP_LOCKED_MASK 0x1ULL
91 #define HFI1_CAP_LOCKED_SMASK (HFI1_CAP_LOCKED_MASK << HFI1_CAP_LOCKED_SHIFT)
92 /* extra bits used between kernel and user processes */
93 #define HFI1_CAP_MISC_SHIFT (HFI1_CAP_USER_SHIFT * 2)
94 #define HFI1_CAP_MISC_MASK ((1ULL << (HFI1_CAP_LOCKED_SHIFT - \
95 HFI1_CAP_MISC_SHIFT)) - 1)
96
97 #define HFI1_CAP_KSET(cap) ({ hfi1_cap_mask |= HFI1_CAP_##cap; hfi1_cap_mask; })
98 #define HFI1_CAP_KCLEAR(cap) \
99 ({ \
100 hfi1_cap_mask &= ~HFI1_CAP_##cap; \
101 hfi1_cap_mask; \
102 })
103 #define HFI1_CAP_USET(cap) \
104 ({ \
105 hfi1_cap_mask |= (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
106 hfi1_cap_mask; \
107 })
108 #define HFI1_CAP_UCLEAR(cap) \
109 ({ \
110 hfi1_cap_mask &= ~(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
111 hfi1_cap_mask; \
112 })
113 #define HFI1_CAP_SET(cap) \
114 ({ \
115 hfi1_cap_mask |= (HFI1_CAP_##cap | (HFI1_CAP_##cap << \
116 HFI1_CAP_USER_SHIFT)); \
117 hfi1_cap_mask; \
118 })
119 #define HFI1_CAP_CLEAR(cap) \
120 ({ \
121 hfi1_cap_mask &= ~(HFI1_CAP_##cap | \
122 (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT)); \
123 hfi1_cap_mask; \
124 })
125 #define HFI1_CAP_LOCK() \
126 ({ hfi1_cap_mask |= HFI1_CAP_LOCKED_SMASK; hfi1_cap_mask; })
127 #define HFI1_CAP_LOCKED() (!!(hfi1_cap_mask & HFI1_CAP_LOCKED_SMASK))
128 /*
129 * The set of capability bits that can be changed after initial load
130 * This set is the same for kernel and user contexts. However, for
131 * user contexts, the set can be further filtered by using the
132 * HFI1_CAP_RESERVED_MASK bits.
133 */
134 #define HFI1_CAP_WRITABLE_MASK (HFI1_CAP_SDMA_AHG | \
135 HFI1_CAP_HDRSUPP | \
136 HFI1_CAP_MULTI_PKT_EGR | \
137 HFI1_CAP_NODROP_RHQ_FULL | \
138 HFI1_CAP_NODROP_EGR_FULL | \
139 HFI1_CAP_ALLOW_PERM_JKEY | \
140 HFI1_CAP_STATIC_RATE_CTRL | \
141 HFI1_CAP_PRINT_UNIMPL)
142 /*
143 * A set of capability bits that are "global" and are not allowed to be
144 * set in the user bitmask.
145 */
146 #define HFI1_CAP_RESERVED_MASK ((HFI1_CAP_SDMA | \
147 HFI1_CAP_USE_SDMA_HEAD | \
148 HFI1_CAP_EXTENDED_PSN | \
149 HFI1_CAP_PRINT_UNIMPL | \
150 HFI1_CAP_NO_INTEGRITY | \
151 HFI1_CAP_PKEY_CHECK) << \
152 HFI1_CAP_USER_SHIFT)
153 /*
154 * Set of capabilities that need to be enabled for kernel context in
155 * order to be allowed for user contexts, as well.
156 */
157 #define HFI1_CAP_MUST_HAVE_KERN (HFI1_CAP_STATIC_RATE_CTRL)
158 /* Default enabled capabilities (both kernel and user) */
159 #define HFI1_CAP_MASK_DEFAULT (HFI1_CAP_HDRSUPP | \
160 HFI1_CAP_NODROP_RHQ_FULL | \
161 HFI1_CAP_NODROP_EGR_FULL | \
162 HFI1_CAP_SDMA | \
163 HFI1_CAP_PRINT_UNIMPL | \
164 HFI1_CAP_STATIC_RATE_CTRL | \
165 HFI1_CAP_PKEY_CHECK | \
166 HFI1_CAP_MULTI_PKT_EGR | \
167 HFI1_CAP_EXTENDED_PSN | \
168 ((HFI1_CAP_HDRSUPP | \
169 HFI1_CAP_MULTI_PKT_EGR | \
170 HFI1_CAP_STATIC_RATE_CTRL | \
171 HFI1_CAP_PKEY_CHECK | \
172 HFI1_CAP_EARLY_CREDIT_RETURN) << \
173 HFI1_CAP_USER_SHIFT))
174 /*
175 * A bitmask of kernel/global capabilities that should be communicated
176 * to user level processes.
177 */
178 #define HFI1_CAP_K2U (HFI1_CAP_SDMA | \
179 HFI1_CAP_EXTENDED_PSN | \
180 HFI1_CAP_PKEY_CHECK | \
181 HFI1_CAP_NO_INTEGRITY)
182
183 #define HFI1_USER_SWVERSION ((HFI1_USER_SWMAJOR << 16) | HFI1_USER_SWMINOR)
184
185 #ifndef HFI1_KERN_TYPE
186 #define HFI1_KERN_TYPE 0
187 #endif
188
189 /*
190 * Similarly, this is the kernel version going back to the user. It's
191 * slightly different, in that we want to tell if the driver was built as
192 * part of a Intel release, or from the driver from openfabrics.org,
193 * kernel.org, or a standard distribution, for support reasons.
194 * The high bit is 0 for non-Intel and 1 for Intel-built/supplied.
195 *
196 * It's returned by the driver to the user code during initialization in the
197 * spi_sw_version field of hfi1_base_info, so the user code can in turn
198 * check for compatibility with the kernel.
199 */
200 #define HFI1_KERN_SWVERSION ((HFI1_KERN_TYPE << 31) | HFI1_USER_SWVERSION)
201
202 /*
203 * Define the driver version number. This is something that refers only
204 * to the driver itself, not the software interfaces it supports.
205 */
206 #ifndef HFI1_DRIVER_VERSION_BASE
207 #define HFI1_DRIVER_VERSION_BASE "0.9-294"
208 #endif
209
210 /* create the final driver version string */
211 #ifdef HFI1_IDSTR
212 #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE " " HFI1_IDSTR
213 #else
214 #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE
215 #endif
216
217 /*
218 * Diagnostics can send a packet by writing the following
219 * struct to the diag packet special file.
220 *
221 * This allows a custom PBC qword, so that special modes and deliberate
222 * changes to CRCs can be used.
223 */
224 #define _DIAG_PKT_VERS 1
225 struct diag_pkt {
226 __u16 version; /* structure version */
227 __u16 unit; /* which device */
228 __u16 sw_index; /* send sw index to use */
229 __u16 len; /* data length, in bytes */
230 __u16 port; /* port number */
231 __u16 unused;
232 __u32 flags; /* call flags */
233 __u64 data; /* user data pointer */
234 __u64 pbc; /* PBC for the packet */
235 };
236
237 /* diag_pkt flags */
238 #define F_DIAGPKT_WAIT 0x1 /* wait until packet is sent */
239
240 /*
241 * The next set of defines are for packet headers, and chip register
242 * and memory bits that are visible to and/or used by user-mode software.
243 */
244
245 /*
246 * Receive Header Flags
247 */
248 #define RHF_PKT_LEN_SHIFT 0
249 #define RHF_PKT_LEN_MASK 0xfffull
250 #define RHF_PKT_LEN_SMASK (RHF_PKT_LEN_MASK << RHF_PKT_LEN_SHIFT)
251
252 #define RHF_RCV_TYPE_SHIFT 12
253 #define RHF_RCV_TYPE_MASK 0x7ull
254 #define RHF_RCV_TYPE_SMASK (RHF_RCV_TYPE_MASK << RHF_RCV_TYPE_SHIFT)
255
256 #define RHF_USE_EGR_BFR_SHIFT 15
257 #define RHF_USE_EGR_BFR_MASK 0x1ull
258 #define RHF_USE_EGR_BFR_SMASK (RHF_USE_EGR_BFR_MASK << RHF_USE_EGR_BFR_SHIFT)
259
260 #define RHF_EGR_INDEX_SHIFT 16
261 #define RHF_EGR_INDEX_MASK 0x7ffull
262 #define RHF_EGR_INDEX_SMASK (RHF_EGR_INDEX_MASK << RHF_EGR_INDEX_SHIFT)
263
264 #define RHF_DC_INFO_SHIFT 27
265 #define RHF_DC_INFO_MASK 0x1ull
266 #define RHF_DC_INFO_SMASK (RHF_DC_INFO_MASK << RHF_DC_INFO_SHIFT)
267
268 #define RHF_RCV_SEQ_SHIFT 28
269 #define RHF_RCV_SEQ_MASK 0xfull
270 #define RHF_RCV_SEQ_SMASK (RHF_RCV_SEQ_MASK << RHF_RCV_SEQ_SHIFT)
271
272 #define RHF_EGR_OFFSET_SHIFT 32
273 #define RHF_EGR_OFFSET_MASK 0xfffull
274 #define RHF_EGR_OFFSET_SMASK (RHF_EGR_OFFSET_MASK << RHF_EGR_OFFSET_SHIFT)
275 #define RHF_HDRQ_OFFSET_SHIFT 44
276 #define RHF_HDRQ_OFFSET_MASK 0x1ffull
277 #define RHF_HDRQ_OFFSET_SMASK (RHF_HDRQ_OFFSET_MASK << RHF_HDRQ_OFFSET_SHIFT)
278 #define RHF_K_HDR_LEN_ERR (0x1ull << 53)
279 #define RHF_DC_UNC_ERR (0x1ull << 54)
280 #define RHF_DC_ERR (0x1ull << 55)
281 #define RHF_RCV_TYPE_ERR_SHIFT 56
282 #define RHF_RCV_TYPE_ERR_MASK 0x7ul
283 #define RHF_RCV_TYPE_ERR_SMASK (RHF_RCV_TYPE_ERR_MASK << RHF_RCV_TYPE_ERR_SHIFT)
284 #define RHF_TID_ERR (0x1ull << 59)
285 #define RHF_LEN_ERR (0x1ull << 60)
286 #define RHF_ECC_ERR (0x1ull << 61)
287 #define RHF_VCRC_ERR (0x1ull << 62)
288 #define RHF_ICRC_ERR (0x1ull << 63)
289
290 #define RHF_ERROR_SMASK 0xffe0000000000000ull /* bits 63:53 */
291
292 /* RHF receive types */
293 #define RHF_RCV_TYPE_EXPECTED 0
294 #define RHF_RCV_TYPE_EAGER 1
295 #define RHF_RCV_TYPE_IB 2 /* normal IB, IB Raw, or IPv6 */
296 #define RHF_RCV_TYPE_ERROR 3
297 #define RHF_RCV_TYPE_BYPASS 4
298 #define RHF_RCV_TYPE_INVALID5 5
299 #define RHF_RCV_TYPE_INVALID6 6
300 #define RHF_RCV_TYPE_INVALID7 7
301
302 /* RHF receive type error - expected packet errors */
303 #define RHF_RTE_EXPECTED_FLOW_SEQ_ERR 0x2
304 #define RHF_RTE_EXPECTED_FLOW_GEN_ERR 0x4
305
306 /* RHF receive type error - eager packet errors */
307 #define RHF_RTE_EAGER_NO_ERR 0x0
308
309 /* RHF receive type error - IB packet errors */
310 #define RHF_RTE_IB_NO_ERR 0x0
311
312 /* RHF receive type error - error packet errors */
313 #define RHF_RTE_ERROR_NO_ERR 0x0
314 #define RHF_RTE_ERROR_OP_CODE_ERR 0x1
315 #define RHF_RTE_ERROR_KHDR_MIN_LEN_ERR 0x2
316 #define RHF_RTE_ERROR_KHDR_HCRC_ERR 0x3
317 #define RHF_RTE_ERROR_KHDR_KVER_ERR 0x4
318 #define RHF_RTE_ERROR_CONTEXT_ERR 0x5
319 #define RHF_RTE_ERROR_KHDR_TID_ERR 0x6
320
321 /* RHF receive type error - bypass packet errors */
322 #define RHF_RTE_BYPASS_NO_ERR 0x0
323
324 /*
325 * This structure contains the first field common to all protocols
326 * that employ this chip.
327 */
328 struct hfi1_message_header {
329 __be16 lrh[4];
330 };
331
332 /* IB - LRH header constants */
333 #define HFI1_LRH_GRH 0x0003 /* 1. word of IB LRH - next header: GRH */
334 #define HFI1_LRH_BTH 0x0002 /* 1. word of IB LRH - next header: BTH */
335
336 /* misc. */
337 #define SIZE_OF_CRC 1
338
339 #define LIM_MGMT_P_KEY 0x7FFF
340 #define FULL_MGMT_P_KEY 0xFFFF
341
342 #define DEFAULT_P_KEY LIM_MGMT_P_KEY
343 #define HFI1_PERMISSIVE_LID 0xFFFF
344 #define HFI1_AETH_CREDIT_SHIFT 24
345 #define HFI1_AETH_CREDIT_MASK 0x1F
346 #define HFI1_AETH_CREDIT_INVAL 0x1F
347 #define HFI1_MSN_MASK 0xFFFFFF
348 #define HFI1_QPN_MASK 0xFFFFFF
349 #define HFI1_FECN_SHIFT 31
350 #define HFI1_FECN_MASK 1
351 #define HFI1_FECN_SMASK (1 << HFI1_FECN_SHIFT)
352 #define HFI1_BECN_SHIFT 30
353 #define HFI1_BECN_MASK 1
354 #define HFI1_BECN_SMASK (1 << HFI1_BECN_SHIFT)
355 #define HFI1_MULTICAST_LID_BASE 0xC000
356
rhf_to_cpu(const __le32 * rbuf)357 static inline __u64 rhf_to_cpu(const __le32 *rbuf)
358 {
359 return __le64_to_cpu(*((__le64 *)rbuf));
360 }
361
rhf_err_flags(u64 rhf)362 static inline u64 rhf_err_flags(u64 rhf)
363 {
364 return rhf & RHF_ERROR_SMASK;
365 }
366
rhf_rcv_type(u64 rhf)367 static inline u32 rhf_rcv_type(u64 rhf)
368 {
369 return (rhf >> RHF_RCV_TYPE_SHIFT) & RHF_RCV_TYPE_MASK;
370 }
371
rhf_rcv_type_err(u64 rhf)372 static inline u32 rhf_rcv_type_err(u64 rhf)
373 {
374 return (rhf >> RHF_RCV_TYPE_ERR_SHIFT) & RHF_RCV_TYPE_ERR_MASK;
375 }
376
377 /* return size is in bytes, not DWORDs */
rhf_pkt_len(u64 rhf)378 static inline u32 rhf_pkt_len(u64 rhf)
379 {
380 return ((rhf & RHF_PKT_LEN_SMASK) >> RHF_PKT_LEN_SHIFT) << 2;
381 }
382
rhf_egr_index(u64 rhf)383 static inline u32 rhf_egr_index(u64 rhf)
384 {
385 return (rhf >> RHF_EGR_INDEX_SHIFT) & RHF_EGR_INDEX_MASK;
386 }
387
rhf_rcv_seq(u64 rhf)388 static inline u32 rhf_rcv_seq(u64 rhf)
389 {
390 return (rhf >> RHF_RCV_SEQ_SHIFT) & RHF_RCV_SEQ_MASK;
391 }
392
393 /* returned offset is in DWORDS */
rhf_hdrq_offset(u64 rhf)394 static inline u32 rhf_hdrq_offset(u64 rhf)
395 {
396 return (rhf >> RHF_HDRQ_OFFSET_SHIFT) & RHF_HDRQ_OFFSET_MASK;
397 }
398
rhf_use_egr_bfr(u64 rhf)399 static inline u64 rhf_use_egr_bfr(u64 rhf)
400 {
401 return rhf & RHF_USE_EGR_BFR_SMASK;
402 }
403
rhf_dc_info(u64 rhf)404 static inline u64 rhf_dc_info(u64 rhf)
405 {
406 return rhf & RHF_DC_INFO_SMASK;
407 }
408
rhf_egr_buf_offset(u64 rhf)409 static inline u32 rhf_egr_buf_offset(u64 rhf)
410 {
411 return (rhf >> RHF_EGR_OFFSET_SHIFT) & RHF_EGR_OFFSET_MASK;
412 }
413 #endif /* _COMMON_H */
414