1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_TYPE_H_
28 #define _I40E_TYPE_H_
29
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
34 #include "i40e_hmc.h"
35 #include "i40e_lan_hmc.h"
36 #include "i40e_devids.h"
37
38 /* I40E_MASK is a macro used on 32 bit registers */
39 #define I40E_MASK(mask, shift) (mask << shift)
40
41 #define I40E_MAX_VSI_QP 16
42 #define I40E_MAX_VF_VSI 3
43 #define I40E_MAX_CHAINED_RX_BUFFERS 5
44 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
45
46 /* Max default timeout in ms, */
47 #define I40E_MAX_NVM_TIMEOUT 18000
48
49 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
50 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
51
52 /* forward declaration */
53 struct i40e_hw;
54 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
55
56 /* Data type manipulation macros. */
57
58 #define I40E_DESC_UNUSED(R) \
59 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
60 (R)->next_to_clean - (R)->next_to_use - 1)
61
62 /* bitfields for Tx queue mapping in QTX_CTL */
63 #define I40E_QTX_CTL_VF_QUEUE 0x0
64 #define I40E_QTX_CTL_VM_QUEUE 0x1
65 #define I40E_QTX_CTL_PF_QUEUE 0x2
66
67 /* debug masks - set these bits in hw->debug_mask to control output */
68 enum i40e_debug_mask {
69 I40E_DEBUG_INIT = 0x00000001,
70 I40E_DEBUG_RELEASE = 0x00000002,
71
72 I40E_DEBUG_LINK = 0x00000010,
73 I40E_DEBUG_PHY = 0x00000020,
74 I40E_DEBUG_HMC = 0x00000040,
75 I40E_DEBUG_NVM = 0x00000080,
76 I40E_DEBUG_LAN = 0x00000100,
77 I40E_DEBUG_FLOW = 0x00000200,
78 I40E_DEBUG_DCB = 0x00000400,
79 I40E_DEBUG_DIAG = 0x00000800,
80 I40E_DEBUG_FD = 0x00001000,
81
82 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
83 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
84 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
85 I40E_DEBUG_AQ_COMMAND = 0x06000000,
86 I40E_DEBUG_AQ = 0x0F000000,
87
88 I40E_DEBUG_USER = 0xF0000000,
89
90 I40E_DEBUG_ALL = 0xFFFFFFFF
91 };
92
93 /* These are structs for managing the hardware information and the operations.
94 * The structures of function pointers are filled out at init time when we
95 * know for sure exactly which hardware we're working with. This gives us the
96 * flexibility of using the same main driver code but adapting to slightly
97 * different hardware needs as new parts are developed. For this architecture,
98 * the Firmware and AdminQ are intended to insulate the driver from most of the
99 * future changes, but these structures will also do part of the job.
100 */
101 enum i40e_mac_type {
102 I40E_MAC_UNKNOWN = 0,
103 I40E_MAC_X710,
104 I40E_MAC_XL710,
105 I40E_MAC_VF,
106 I40E_MAC_X722,
107 I40E_MAC_X722_VF,
108 I40E_MAC_GENERIC,
109 };
110
111 enum i40e_media_type {
112 I40E_MEDIA_TYPE_UNKNOWN = 0,
113 I40E_MEDIA_TYPE_FIBER,
114 I40E_MEDIA_TYPE_BASET,
115 I40E_MEDIA_TYPE_BACKPLANE,
116 I40E_MEDIA_TYPE_CX4,
117 I40E_MEDIA_TYPE_DA,
118 I40E_MEDIA_TYPE_VIRTUAL
119 };
120
121 enum i40e_fc_mode {
122 I40E_FC_NONE = 0,
123 I40E_FC_RX_PAUSE,
124 I40E_FC_TX_PAUSE,
125 I40E_FC_FULL,
126 I40E_FC_PFC,
127 I40E_FC_DEFAULT
128 };
129
130 enum i40e_set_fc_aq_failures {
131 I40E_SET_FC_AQ_FAIL_NONE = 0,
132 I40E_SET_FC_AQ_FAIL_GET = 1,
133 I40E_SET_FC_AQ_FAIL_SET = 2,
134 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
135 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
136 };
137
138 enum i40e_vsi_type {
139 I40E_VSI_MAIN = 0,
140 I40E_VSI_VMDQ1 = 1,
141 I40E_VSI_VMDQ2 = 2,
142 I40E_VSI_CTRL = 3,
143 I40E_VSI_FCOE = 4,
144 I40E_VSI_MIRROR = 5,
145 I40E_VSI_SRIOV = 6,
146 I40E_VSI_FDIR = 7,
147 I40E_VSI_TYPE_UNKNOWN
148 };
149
150 enum i40e_queue_type {
151 I40E_QUEUE_TYPE_RX = 0,
152 I40E_QUEUE_TYPE_TX,
153 I40E_QUEUE_TYPE_PE_CEQ,
154 I40E_QUEUE_TYPE_UNKNOWN
155 };
156
157 struct i40e_link_status {
158 enum i40e_aq_phy_type phy_type;
159 enum i40e_aq_link_speed link_speed;
160 u8 link_info;
161 u8 an_info;
162 u8 ext_info;
163 u8 loopback;
164 /* is Link Status Event notification to SW enabled */
165 bool lse_enable;
166 u16 max_frame_size;
167 bool crc_enable;
168 u8 pacing;
169 u8 requested_speeds;
170 u8 module_type[3];
171 /* 1st byte: module identifier */
172 #define I40E_MODULE_TYPE_SFP 0x03
173 #define I40E_MODULE_TYPE_QSFP 0x0D
174 /* 2nd byte: ethernet compliance codes for 10/40G */
175 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
176 #define I40E_MODULE_TYPE_40G_LR4 0x02
177 #define I40E_MODULE_TYPE_40G_SR4 0x04
178 #define I40E_MODULE_TYPE_40G_CR4 0x08
179 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
180 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
181 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
182 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
183 /* 3rd byte: ethernet compliance codes for 1G */
184 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
185 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
186 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
187 #define I40E_MODULE_TYPE_1000BASE_T 0x08
188 };
189
190 enum i40e_aq_capabilities_phy_type {
191 I40E_CAP_PHY_TYPE_SGMII = BIT(I40E_PHY_TYPE_SGMII),
192 I40E_CAP_PHY_TYPE_1000BASE_KX = BIT(I40E_PHY_TYPE_1000BASE_KX),
193 I40E_CAP_PHY_TYPE_10GBASE_KX4 = BIT(I40E_PHY_TYPE_10GBASE_KX4),
194 I40E_CAP_PHY_TYPE_10GBASE_KR = BIT(I40E_PHY_TYPE_10GBASE_KR),
195 I40E_CAP_PHY_TYPE_40GBASE_KR4 = BIT(I40E_PHY_TYPE_40GBASE_KR4),
196 I40E_CAP_PHY_TYPE_XAUI = BIT(I40E_PHY_TYPE_XAUI),
197 I40E_CAP_PHY_TYPE_XFI = BIT(I40E_PHY_TYPE_XFI),
198 I40E_CAP_PHY_TYPE_SFI = BIT(I40E_PHY_TYPE_SFI),
199 I40E_CAP_PHY_TYPE_XLAUI = BIT(I40E_PHY_TYPE_XLAUI),
200 I40E_CAP_PHY_TYPE_XLPPI = BIT(I40E_PHY_TYPE_XLPPI),
201 I40E_CAP_PHY_TYPE_40GBASE_CR4_CU = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
202 I40E_CAP_PHY_TYPE_10GBASE_CR1_CU = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
203 I40E_CAP_PHY_TYPE_10GBASE_AOC = BIT(I40E_PHY_TYPE_10GBASE_AOC),
204 I40E_CAP_PHY_TYPE_40GBASE_AOC = BIT(I40E_PHY_TYPE_40GBASE_AOC),
205 I40E_CAP_PHY_TYPE_100BASE_TX = BIT(I40E_PHY_TYPE_100BASE_TX),
206 I40E_CAP_PHY_TYPE_1000BASE_T = BIT(I40E_PHY_TYPE_1000BASE_T),
207 I40E_CAP_PHY_TYPE_10GBASE_T = BIT(I40E_PHY_TYPE_10GBASE_T),
208 I40E_CAP_PHY_TYPE_10GBASE_SR = BIT(I40E_PHY_TYPE_10GBASE_SR),
209 I40E_CAP_PHY_TYPE_10GBASE_LR = BIT(I40E_PHY_TYPE_10GBASE_LR),
210 I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
211 I40E_CAP_PHY_TYPE_10GBASE_CR1 = BIT(I40E_PHY_TYPE_10GBASE_CR1),
212 I40E_CAP_PHY_TYPE_40GBASE_CR4 = BIT(I40E_PHY_TYPE_40GBASE_CR4),
213 I40E_CAP_PHY_TYPE_40GBASE_SR4 = BIT(I40E_PHY_TYPE_40GBASE_SR4),
214 I40E_CAP_PHY_TYPE_40GBASE_LR4 = BIT(I40E_PHY_TYPE_40GBASE_LR4),
215 I40E_CAP_PHY_TYPE_1000BASE_SX = BIT(I40E_PHY_TYPE_1000BASE_SX),
216 I40E_CAP_PHY_TYPE_1000BASE_LX = BIT(I40E_PHY_TYPE_1000BASE_LX),
217 I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL =
218 BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
219 I40E_CAP_PHY_TYPE_20GBASE_KR2 = BIT(I40E_PHY_TYPE_20GBASE_KR2)
220 };
221
222 struct i40e_phy_info {
223 struct i40e_link_status link_info;
224 struct i40e_link_status link_info_old;
225 bool get_link_info;
226 enum i40e_media_type media_type;
227 /* all the phy types the NVM is capable of */
228 enum i40e_aq_capabilities_phy_type phy_types;
229 };
230
231 #define I40E_HW_CAP_MAX_GPIO 30
232 /* Capabilities of a PF or a VF or the whole device */
233 struct i40e_hw_capabilities {
234 u32 switch_mode;
235 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
236 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
237 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
238
239 u32 management_mode;
240 u32 npar_enable;
241 u32 os2bmc;
242 u32 valid_functions;
243 bool sr_iov_1_1;
244 bool vmdq;
245 bool evb_802_1_qbg; /* Edge Virtual Bridging */
246 bool evb_802_1_qbh; /* Bridge Port Extension */
247 bool dcb;
248 bool fcoe;
249 bool iscsi; /* Indicates iSCSI enabled */
250 bool flex10_enable;
251 bool flex10_capable;
252 u32 flex10_mode;
253 #define I40E_FLEX10_MODE_UNKNOWN 0x0
254 #define I40E_FLEX10_MODE_DCC 0x1
255 #define I40E_FLEX10_MODE_DCI 0x2
256
257 u32 flex10_status;
258 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
259 #define I40E_FLEX10_STATUS_VC_MODE 0x2
260
261 bool mgmt_cem;
262 bool ieee_1588;
263 bool iwarp;
264 bool fd;
265 u32 fd_filters_guaranteed;
266 u32 fd_filters_best_effort;
267 bool rss;
268 u32 rss_table_size;
269 u32 rss_table_entry_width;
270 bool led[I40E_HW_CAP_MAX_GPIO];
271 bool sdp[I40E_HW_CAP_MAX_GPIO];
272 u32 nvm_image_type;
273 u32 num_flow_director_filters;
274 u32 num_vfs;
275 u32 vf_base_id;
276 u32 num_vsis;
277 u32 num_rx_qp;
278 u32 num_tx_qp;
279 u32 base_queue;
280 u32 num_msix_vectors;
281 u32 num_msix_vectors_vf;
282 u32 led_pin_num;
283 u32 sdp_pin_num;
284 u32 mdio_port_num;
285 u32 mdio_port_mode;
286 u8 rx_buf_chain_len;
287 u32 enabled_tcmap;
288 u32 maxtc;
289 u64 wr_csr_prot;
290 };
291
292 struct i40e_mac_info {
293 enum i40e_mac_type type;
294 u8 addr[ETH_ALEN];
295 u8 perm_addr[ETH_ALEN];
296 u8 san_addr[ETH_ALEN];
297 u8 port_addr[ETH_ALEN];
298 u16 max_fcoeq;
299 };
300
301 enum i40e_aq_resources_ids {
302 I40E_NVM_RESOURCE_ID = 1
303 };
304
305 enum i40e_aq_resource_access_type {
306 I40E_RESOURCE_READ = 1,
307 I40E_RESOURCE_WRITE
308 };
309
310 struct i40e_nvm_info {
311 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
312 u32 timeout; /* [ms] */
313 u16 sr_size; /* Shadow RAM size in words */
314 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
315 u16 version; /* NVM package version */
316 u32 eetrack; /* NVM data version */
317 u32 oem_ver; /* OEM version info */
318 };
319
320 /* definitions used in NVM update support */
321
322 enum i40e_nvmupd_cmd {
323 I40E_NVMUPD_INVALID,
324 I40E_NVMUPD_READ_CON,
325 I40E_NVMUPD_READ_SNT,
326 I40E_NVMUPD_READ_LCB,
327 I40E_NVMUPD_READ_SA,
328 I40E_NVMUPD_WRITE_ERA,
329 I40E_NVMUPD_WRITE_CON,
330 I40E_NVMUPD_WRITE_SNT,
331 I40E_NVMUPD_WRITE_LCB,
332 I40E_NVMUPD_WRITE_SA,
333 I40E_NVMUPD_CSUM_CON,
334 I40E_NVMUPD_CSUM_SA,
335 I40E_NVMUPD_CSUM_LCB,
336 I40E_NVMUPD_STATUS,
337 I40E_NVMUPD_EXEC_AQ,
338 I40E_NVMUPD_GET_AQ_RESULT,
339 };
340
341 enum i40e_nvmupd_state {
342 I40E_NVMUPD_STATE_INIT,
343 I40E_NVMUPD_STATE_READING,
344 I40E_NVMUPD_STATE_WRITING,
345 I40E_NVMUPD_STATE_INIT_WAIT,
346 I40E_NVMUPD_STATE_WRITE_WAIT,
347 };
348
349 /* nvm_access definition and its masks/shifts need to be accessible to
350 * application, core driver, and shared code. Where is the right file?
351 */
352 #define I40E_NVM_READ 0xB
353 #define I40E_NVM_WRITE 0xC
354
355 #define I40E_NVM_MOD_PNT_MASK 0xFF
356
357 #define I40E_NVM_TRANS_SHIFT 8
358 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
359 #define I40E_NVM_CON 0x0
360 #define I40E_NVM_SNT 0x1
361 #define I40E_NVM_LCB 0x2
362 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
363 #define I40E_NVM_ERA 0x4
364 #define I40E_NVM_CSUM 0x8
365 #define I40E_NVM_EXEC 0xf
366
367 #define I40E_NVM_ADAPT_SHIFT 16
368 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
369
370 #define I40E_NVMUPD_MAX_DATA 4096
371 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
372
373 struct i40e_nvm_access {
374 u32 command;
375 u32 config;
376 u32 offset; /* in bytes */
377 u32 data_size; /* in bytes */
378 u8 data[1];
379 };
380
381 /* PCI bus types */
382 enum i40e_bus_type {
383 i40e_bus_type_unknown = 0,
384 i40e_bus_type_pci,
385 i40e_bus_type_pcix,
386 i40e_bus_type_pci_express,
387 i40e_bus_type_reserved
388 };
389
390 /* PCI bus speeds */
391 enum i40e_bus_speed {
392 i40e_bus_speed_unknown = 0,
393 i40e_bus_speed_33 = 33,
394 i40e_bus_speed_66 = 66,
395 i40e_bus_speed_100 = 100,
396 i40e_bus_speed_120 = 120,
397 i40e_bus_speed_133 = 133,
398 i40e_bus_speed_2500 = 2500,
399 i40e_bus_speed_5000 = 5000,
400 i40e_bus_speed_8000 = 8000,
401 i40e_bus_speed_reserved
402 };
403
404 /* PCI bus widths */
405 enum i40e_bus_width {
406 i40e_bus_width_unknown = 0,
407 i40e_bus_width_pcie_x1 = 1,
408 i40e_bus_width_pcie_x2 = 2,
409 i40e_bus_width_pcie_x4 = 4,
410 i40e_bus_width_pcie_x8 = 8,
411 i40e_bus_width_32 = 32,
412 i40e_bus_width_64 = 64,
413 i40e_bus_width_reserved
414 };
415
416 /* Bus parameters */
417 struct i40e_bus_info {
418 enum i40e_bus_speed speed;
419 enum i40e_bus_width width;
420 enum i40e_bus_type type;
421
422 u16 func;
423 u16 device;
424 u16 lan_id;
425 };
426
427 /* Flow control (FC) parameters */
428 struct i40e_fc_info {
429 enum i40e_fc_mode current_mode; /* FC mode in effect */
430 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
431 };
432
433 #define I40E_MAX_TRAFFIC_CLASS 8
434 #define I40E_MAX_USER_PRIORITY 8
435 #define I40E_DCBX_MAX_APPS 32
436 #define I40E_LLDPDU_SIZE 1500
437 #define I40E_TLV_STATUS_OPER 0x1
438 #define I40E_TLV_STATUS_SYNC 0x2
439 #define I40E_TLV_STATUS_ERR 0x4
440 #define I40E_CEE_OPER_MAX_APPS 3
441 #define I40E_APP_PROTOID_FCOE 0x8906
442 #define I40E_APP_PROTOID_ISCSI 0x0cbc
443 #define I40E_APP_PROTOID_FIP 0x8914
444 #define I40E_APP_SEL_ETHTYPE 0x1
445 #define I40E_APP_SEL_TCPIP 0x2
446 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
447 #define I40E_CEE_APP_SEL_TCPIP 0x1
448
449 /* CEE or IEEE 802.1Qaz ETS Configuration data */
450 struct i40e_dcb_ets_config {
451 u8 willing;
452 u8 cbs;
453 u8 maxtcs;
454 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
455 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
456 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
457 };
458
459 /* CEE or IEEE 802.1Qaz PFC Configuration data */
460 struct i40e_dcb_pfc_config {
461 u8 willing;
462 u8 mbc;
463 u8 pfccap;
464 u8 pfcenable;
465 };
466
467 /* CEE or IEEE 802.1Qaz Application Priority data */
468 struct i40e_dcb_app_priority_table {
469 u8 priority;
470 u8 selector;
471 u16 protocolid;
472 };
473
474 struct i40e_dcbx_config {
475 u8 dcbx_mode;
476 #define I40E_DCBX_MODE_CEE 0x1
477 #define I40E_DCBX_MODE_IEEE 0x2
478 u8 app_mode;
479 #define I40E_DCBX_APPS_NON_WILLING 0x1
480 u32 numapps;
481 u32 tlv_status; /* CEE mode TLV status */
482 struct i40e_dcb_ets_config etscfg;
483 struct i40e_dcb_ets_config etsrec;
484 struct i40e_dcb_pfc_config pfc;
485 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
486 };
487
488 /* Port hardware description */
489 struct i40e_hw {
490 u8 __iomem *hw_addr;
491 void *back;
492
493 /* subsystem structs */
494 struct i40e_phy_info phy;
495 struct i40e_mac_info mac;
496 struct i40e_bus_info bus;
497 struct i40e_nvm_info nvm;
498 struct i40e_fc_info fc;
499
500 /* pci info */
501 u16 device_id;
502 u16 vendor_id;
503 u16 subsystem_device_id;
504 u16 subsystem_vendor_id;
505 u8 revision_id;
506 u8 port;
507 bool adapter_stopped;
508
509 /* capabilities for entire device and PCI func */
510 struct i40e_hw_capabilities dev_caps;
511 struct i40e_hw_capabilities func_caps;
512
513 /* Flow Director shared filter space */
514 u16 fdir_shared_filter_count;
515
516 /* device profile info */
517 u8 pf_id;
518 u16 main_vsi_seid;
519
520 /* for multi-function MACs */
521 u16 partition_id;
522 u16 num_partitions;
523 u16 num_ports;
524
525 /* Closest numa node to the device */
526 u16 numa_node;
527
528 /* Admin Queue info */
529 struct i40e_adminq_info aq;
530
531 /* state of nvm update process */
532 enum i40e_nvmupd_state nvmupd_state;
533 struct i40e_aq_desc nvm_wb_desc;
534 struct i40e_virt_mem nvm_buff;
535
536 /* HMC info */
537 struct i40e_hmc_info hmc; /* HMC info struct */
538
539 /* LLDP/DCBX Status */
540 u16 dcbx_status;
541
542 /* DCBX info */
543 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
544 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
545 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
546
547 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
548 u64 flags;
549
550 /* debug mask */
551 u32 debug_mask;
552 char err_str[16];
553 };
554
i40e_is_vf(struct i40e_hw * hw)555 static inline bool i40e_is_vf(struct i40e_hw *hw)
556 {
557 return (hw->mac.type == I40E_MAC_VF ||
558 hw->mac.type == I40E_MAC_X722_VF);
559 }
560
561 struct i40e_driver_version {
562 u8 major_version;
563 u8 minor_version;
564 u8 build_version;
565 u8 subbuild_version;
566 u8 driver_string[32];
567 };
568
569 /* RX Descriptors */
570 union i40e_16byte_rx_desc {
571 struct {
572 __le64 pkt_addr; /* Packet buffer address */
573 __le64 hdr_addr; /* Header buffer address */
574 } read;
575 struct {
576 struct {
577 struct {
578 union {
579 __le16 mirroring_status;
580 __le16 fcoe_ctx_id;
581 } mirr_fcoe;
582 __le16 l2tag1;
583 } lo_dword;
584 union {
585 __le32 rss; /* RSS Hash */
586 __le32 fd_id; /* Flow director filter id */
587 __le32 fcoe_param; /* FCoE DDP Context id */
588 } hi_dword;
589 } qword0;
590 struct {
591 /* ext status/error/pktype/length */
592 __le64 status_error_len;
593 } qword1;
594 } wb; /* writeback */
595 };
596
597 union i40e_32byte_rx_desc {
598 struct {
599 __le64 pkt_addr; /* Packet buffer address */
600 __le64 hdr_addr; /* Header buffer address */
601 /* bit 0 of hdr_buffer_addr is DD bit */
602 __le64 rsvd1;
603 __le64 rsvd2;
604 } read;
605 struct {
606 struct {
607 struct {
608 union {
609 __le16 mirroring_status;
610 __le16 fcoe_ctx_id;
611 } mirr_fcoe;
612 __le16 l2tag1;
613 } lo_dword;
614 union {
615 __le32 rss; /* RSS Hash */
616 __le32 fcoe_param; /* FCoE DDP Context id */
617 /* Flow director filter id in case of
618 * Programming status desc WB
619 */
620 __le32 fd_id;
621 } hi_dword;
622 } qword0;
623 struct {
624 /* status/error/pktype/length */
625 __le64 status_error_len;
626 } qword1;
627 struct {
628 __le16 ext_status; /* extended status */
629 __le16 rsvd;
630 __le16 l2tag2_1;
631 __le16 l2tag2_2;
632 } qword2;
633 struct {
634 union {
635 __le32 flex_bytes_lo;
636 __le32 pe_status;
637 } lo_dword;
638 union {
639 __le32 flex_bytes_hi;
640 __le32 fd_id;
641 } hi_dword;
642 } qword3;
643 } wb; /* writeback */
644 };
645
646 enum i40e_rx_desc_status_bits {
647 /* Note: These are predefined bit offsets */
648 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
649 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
650 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
651 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
652 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
653 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
654 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
655 /* Note: Bit 8 is reserved in X710 and XL710 */
656 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
657 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
658 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
659 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
660 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
661 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
662 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
663 /* Note: For non-tunnel packets INT_UDP_0 is the right status for
664 * UDP header
665 */
666 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
667 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
668 };
669
670 #define I40E_RXD_QW1_STATUS_SHIFT 0
671 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
672 << I40E_RXD_QW1_STATUS_SHIFT)
673
674 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
675 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
676 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
677
678 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
679 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
680 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
681
682 enum i40e_rx_desc_fltstat_values {
683 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
684 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
685 I40E_RX_DESC_FLTSTAT_RSV = 2,
686 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
687 };
688
689 #define I40E_RXD_QW1_ERROR_SHIFT 19
690 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
691
692 enum i40e_rx_desc_error_bits {
693 /* Note: These are predefined bit offsets */
694 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
695 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
696 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
697 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
698 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
699 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
700 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
701 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
702 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
703 };
704
705 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
706 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
707 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
708 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
709 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
710 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
711 };
712
713 #define I40E_RXD_QW1_PTYPE_SHIFT 30
714 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
715
716 /* Packet type non-ip values */
717 enum i40e_rx_l2_ptype {
718 I40E_RX_PTYPE_L2_RESERVED = 0,
719 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
720 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
721 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
722 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
723 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
724 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
725 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
726 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
727 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
728 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
729 I40E_RX_PTYPE_L2_ARP = 11,
730 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
731 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
732 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
733 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
734 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
735 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
736 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
737 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
738 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
739 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
740 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
741 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
742 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
743 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
744 };
745
746 struct i40e_rx_ptype_decoded {
747 u32 ptype:8;
748 u32 known:1;
749 u32 outer_ip:1;
750 u32 outer_ip_ver:1;
751 u32 outer_frag:1;
752 u32 tunnel_type:3;
753 u32 tunnel_end_prot:2;
754 u32 tunnel_end_frag:1;
755 u32 inner_prot:4;
756 u32 payload_layer:3;
757 };
758
759 enum i40e_rx_ptype_outer_ip {
760 I40E_RX_PTYPE_OUTER_L2 = 0,
761 I40E_RX_PTYPE_OUTER_IP = 1
762 };
763
764 enum i40e_rx_ptype_outer_ip_ver {
765 I40E_RX_PTYPE_OUTER_NONE = 0,
766 I40E_RX_PTYPE_OUTER_IPV4 = 0,
767 I40E_RX_PTYPE_OUTER_IPV6 = 1
768 };
769
770 enum i40e_rx_ptype_outer_fragmented {
771 I40E_RX_PTYPE_NOT_FRAG = 0,
772 I40E_RX_PTYPE_FRAG = 1
773 };
774
775 enum i40e_rx_ptype_tunnel_type {
776 I40E_RX_PTYPE_TUNNEL_NONE = 0,
777 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
778 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
779 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
780 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
781 };
782
783 enum i40e_rx_ptype_tunnel_end_prot {
784 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
785 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
786 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
787 };
788
789 enum i40e_rx_ptype_inner_prot {
790 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
791 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
792 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
793 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
794 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
795 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
796 };
797
798 enum i40e_rx_ptype_payload_layer {
799 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
800 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
801 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
802 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
803 };
804
805 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
806 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
807 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
808
809 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
810 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
811 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
812
813 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
814 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
815
816 enum i40e_rx_desc_ext_status_bits {
817 /* Note: These are predefined bit offsets */
818 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
819 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
820 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
821 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
822 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
823 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
824 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
825 };
826
827 enum i40e_rx_desc_pe_status_bits {
828 /* Note: These are predefined bit offsets */
829 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
830 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
831 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
832 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
833 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
834 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
835 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
836 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
837 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
838 };
839
840 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
841 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
842
843 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
844 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
845 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
846
847 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
848 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
849 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
850
851 enum i40e_rx_prog_status_desc_status_bits {
852 /* Note: These are predefined bit offsets */
853 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
854 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
855 };
856
857 enum i40e_rx_prog_status_desc_prog_id_masks {
858 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
859 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
860 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
861 };
862
863 enum i40e_rx_prog_status_desc_error_bits {
864 /* Note: These are predefined bit offsets */
865 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
866 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
867 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
868 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
869 };
870
871 /* TX Descriptor */
872 struct i40e_tx_desc {
873 __le64 buffer_addr; /* Address of descriptor's data buf */
874 __le64 cmd_type_offset_bsz;
875 };
876
877 #define I40E_TXD_QW1_DTYPE_SHIFT 0
878 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
879
880 enum i40e_tx_desc_dtype_value {
881 I40E_TX_DESC_DTYPE_DATA = 0x0,
882 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
883 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
884 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
885 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
886 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
887 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
888 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
889 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
890 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
891 };
892
893 #define I40E_TXD_QW1_CMD_SHIFT 4
894 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
895
896 enum i40e_tx_desc_cmd_bits {
897 I40E_TX_DESC_CMD_EOP = 0x0001,
898 I40E_TX_DESC_CMD_RS = 0x0002,
899 I40E_TX_DESC_CMD_ICRC = 0x0004,
900 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
901 I40E_TX_DESC_CMD_DUMMY = 0x0010,
902 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
903 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
904 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
905 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
906 I40E_TX_DESC_CMD_FCOET = 0x0080,
907 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
908 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
909 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
910 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
911 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
912 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
913 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
914 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
915 };
916
917 #define I40E_TXD_QW1_OFFSET_SHIFT 16
918 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
919 I40E_TXD_QW1_OFFSET_SHIFT)
920
921 enum i40e_tx_desc_length_fields {
922 /* Note: These are predefined bit offsets */
923 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
924 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
925 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
926 };
927
928 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
929 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
930 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
931
932 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
933 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
934
935 /* Context descriptors */
936 struct i40e_tx_context_desc {
937 __le32 tunneling_params;
938 __le16 l2tag2;
939 __le16 rsvd;
940 __le64 type_cmd_tso_mss;
941 };
942
943 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
944 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
945
946 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
947 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
948
949 enum i40e_tx_ctx_desc_cmd_bits {
950 I40E_TX_CTX_DESC_TSO = 0x01,
951 I40E_TX_CTX_DESC_TSYN = 0x02,
952 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
953 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
954 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
955 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
956 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
957 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
958 I40E_TX_CTX_DESC_SWPE = 0x40
959 };
960
961 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
962 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
963 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
964
965 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
966 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
967 I40E_TXD_CTX_QW1_MSS_SHIFT)
968
969 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
970 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
971
972 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
973 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
974 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
975
976 enum i40e_tx_ctx_desc_eipt_offload {
977 I40E_TX_CTX_EXT_IP_NONE = 0x0,
978 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
979 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
980 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
981 };
982
983 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
984 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
985 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
986
987 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
988 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
989
990 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
991 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
992
993 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
994 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
995 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
996
997 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
998
999 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1000 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1001 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1002
1003 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1004 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1005 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1006
1007 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1008 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1009 struct i40e_filter_program_desc {
1010 __le32 qindex_flex_ptype_vsi;
1011 __le32 rsvd;
1012 __le32 dtype_cmd_cntindex;
1013 __le32 fd_id;
1014 };
1015 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1016 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1017 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1018 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1019 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1020 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1021 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1022 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1023 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1024
1025 /* Packet Classifier Types for filters */
1026 enum i40e_filter_pctype {
1027 /* Note: Values 0-28 are reserved for future use.
1028 * Value 29, 30, 32 are not supported on XL710 and X710.
1029 */
1030 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1031 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1032 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1033 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1034 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1035 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1036 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1037 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1038 /* Note: Values 37-38 are reserved for future use.
1039 * Value 39, 40, 42 are not supported on XL710 and X710.
1040 */
1041 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1042 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1043 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1044 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1045 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1046 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1047 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1048 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1049 /* Note: Value 47 is reserved for future use */
1050 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1051 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1052 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1053 /* Note: Values 51-62 are reserved for future use */
1054 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1055 };
1056
1057 enum i40e_filter_program_desc_dest {
1058 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1059 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1060 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1061 };
1062
1063 enum i40e_filter_program_desc_fd_status {
1064 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1065 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1066 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1067 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1068 };
1069
1070 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1071 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1072 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1073
1074 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1075 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1076 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1077
1078 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1079 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1080
1081 enum i40e_filter_program_desc_pcmd {
1082 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1083 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1084 };
1085
1086 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1087 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1088
1089 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1090 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1091
1092 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1093 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1094 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1095 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1096
1097 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1098 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1099 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1100
1101 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1102 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1103 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1104
1105 enum i40e_filter_type {
1106 I40E_FLOW_DIRECTOR_FLTR = 0,
1107 I40E_PE_QUAD_HASH_FLTR = 1,
1108 I40E_ETHERTYPE_FLTR,
1109 I40E_FCOE_CTX_FLTR,
1110 I40E_MAC_VLAN_FLTR,
1111 I40E_HASH_FLTR
1112 };
1113
1114 struct i40e_vsi_context {
1115 u16 seid;
1116 u16 uplink_seid;
1117 u16 vsi_number;
1118 u16 vsis_allocated;
1119 u16 vsis_unallocated;
1120 u16 flags;
1121 u8 pf_num;
1122 u8 vf_num;
1123 u8 connection_type;
1124 struct i40e_aqc_vsi_properties_data info;
1125 };
1126
1127 struct i40e_veb_context {
1128 u16 seid;
1129 u16 uplink_seid;
1130 u16 veb_number;
1131 u16 vebs_allocated;
1132 u16 vebs_unallocated;
1133 u16 flags;
1134 struct i40e_aqc_get_veb_parameters_completion info;
1135 };
1136
1137 /* Statistics collected by each port, VSI, VEB, and S-channel */
1138 struct i40e_eth_stats {
1139 u64 rx_bytes; /* gorc */
1140 u64 rx_unicast; /* uprc */
1141 u64 rx_multicast; /* mprc */
1142 u64 rx_broadcast; /* bprc */
1143 u64 rx_discards; /* rdpc */
1144 u64 rx_unknown_protocol; /* rupp */
1145 u64 tx_bytes; /* gotc */
1146 u64 tx_unicast; /* uptc */
1147 u64 tx_multicast; /* mptc */
1148 u64 tx_broadcast; /* bptc */
1149 u64 tx_discards; /* tdpc */
1150 u64 tx_errors; /* tepc */
1151 };
1152
1153 /* Statistics collected per VEB per TC */
1154 struct i40e_veb_tc_stats {
1155 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1156 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1157 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1158 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1159 };
1160
1161 #ifdef I40E_FCOE
1162 /* Statistics collected per function for FCoE */
1163 struct i40e_fcoe_stats {
1164 u64 rx_fcoe_packets; /* fcoeprc */
1165 u64 rx_fcoe_dwords; /* focedwrc */
1166 u64 rx_fcoe_dropped; /* fcoerpdc */
1167 u64 tx_fcoe_packets; /* fcoeptc */
1168 u64 tx_fcoe_dwords; /* focedwtc */
1169 u64 fcoe_bad_fccrc; /* fcoecrc */
1170 u64 fcoe_last_error; /* fcoelast */
1171 u64 fcoe_ddp_count; /* fcoeddpc */
1172 };
1173
1174 /* offset to per function FCoE statistics block */
1175 #define I40E_FCOE_VF_STAT_OFFSET 0
1176 #define I40E_FCOE_PF_STAT_OFFSET 128
1177 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1178
1179 #endif
1180 /* Statistics collected by the MAC */
1181 struct i40e_hw_port_stats {
1182 /* eth stats collected by the port */
1183 struct i40e_eth_stats eth;
1184
1185 /* additional port specific stats */
1186 u64 tx_dropped_link_down; /* tdold */
1187 u64 crc_errors; /* crcerrs */
1188 u64 illegal_bytes; /* illerrc */
1189 u64 error_bytes; /* errbc */
1190 u64 mac_local_faults; /* mlfc */
1191 u64 mac_remote_faults; /* mrfc */
1192 u64 rx_length_errors; /* rlec */
1193 u64 link_xon_rx; /* lxonrxc */
1194 u64 link_xoff_rx; /* lxoffrxc */
1195 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1196 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1197 u64 link_xon_tx; /* lxontxc */
1198 u64 link_xoff_tx; /* lxofftxc */
1199 u64 priority_xon_tx[8]; /* pxontxc[8] */
1200 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1201 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1202 u64 rx_size_64; /* prc64 */
1203 u64 rx_size_127; /* prc127 */
1204 u64 rx_size_255; /* prc255 */
1205 u64 rx_size_511; /* prc511 */
1206 u64 rx_size_1023; /* prc1023 */
1207 u64 rx_size_1522; /* prc1522 */
1208 u64 rx_size_big; /* prc9522 */
1209 u64 rx_undersize; /* ruc */
1210 u64 rx_fragments; /* rfc */
1211 u64 rx_oversize; /* roc */
1212 u64 rx_jabber; /* rjc */
1213 u64 tx_size_64; /* ptc64 */
1214 u64 tx_size_127; /* ptc127 */
1215 u64 tx_size_255; /* ptc255 */
1216 u64 tx_size_511; /* ptc511 */
1217 u64 tx_size_1023; /* ptc1023 */
1218 u64 tx_size_1522; /* ptc1522 */
1219 u64 tx_size_big; /* ptc9522 */
1220 u64 mac_short_packet_dropped; /* mspdc */
1221 u64 checksum_error; /* xec */
1222 /* flow director stats */
1223 u64 fd_atr_match;
1224 u64 fd_sb_match;
1225 u64 fd_atr_tunnel_match;
1226 u32 fd_atr_status;
1227 u32 fd_sb_status;
1228 /* EEE LPI */
1229 u32 tx_lpi_status;
1230 u32 rx_lpi_status;
1231 u64 tx_lpi_count; /* etlpic */
1232 u64 rx_lpi_count; /* erlpic */
1233 };
1234
1235 /* Checksum and Shadow RAM pointers */
1236 #define I40E_SR_NVM_CONTROL_WORD 0x00
1237 #define I40E_SR_EMP_MODULE_PTR 0x0F
1238 #define I40E_SR_PBA_FLAGS 0x15
1239 #define I40E_SR_PBA_BLOCK_PTR 0x16
1240 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1241 #define I40E_NVM_OEM_VER_OFF 0x83
1242 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1243 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1244 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1245 #define I40E_SR_NVM_EETRACK_LO 0x2D
1246 #define I40E_SR_NVM_EETRACK_HI 0x2E
1247 #define I40E_SR_VPD_PTR 0x2F
1248 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1249 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1250
1251 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1252 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1253 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1254 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1255 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1256
1257 /* Shadow RAM related */
1258 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1259 #define I40E_SR_WORDS_IN_1KB 512
1260 /* Checksum should be calculated such that after adding all the words,
1261 * including the checksum word itself, the sum should be 0xBABA.
1262 */
1263 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1264
1265 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1266
1267 #ifdef I40E_FCOE
1268 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1269
1270 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1271 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1272 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1273 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1274 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1275 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1276 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1277 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1278 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1279 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1280 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1281 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1282 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1283 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1284 };
1285
1286 /* FCoE DDP Context descriptor */
1287 struct i40e_fcoe_ddp_context_desc {
1288 __le64 rsvd;
1289 __le64 type_cmd_foff_lsize;
1290 };
1291
1292 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1293 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1294 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1295
1296 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1297 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1298 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1299
1300 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1301 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1302 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1303 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1304 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1305 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1306 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1307 };
1308
1309 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1310 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1311 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1312
1313 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1314 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1315 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1316
1317 /* FCoE DDP/DWO Queue Context descriptor */
1318 struct i40e_fcoe_queue_context_desc {
1319 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1320 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1321 };
1322
1323 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1324 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1325 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1326
1327 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1328 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1329 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1330
1331 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1332 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1333 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1334
1335 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1336 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1337 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1338
1339 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1340 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1341 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1342 };
1343
1344 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1345 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1346 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1347
1348 /* FCoE DDP/DWO Filter Context descriptor */
1349 struct i40e_fcoe_filter_context_desc {
1350 __le32 param;
1351 __le16 seqn;
1352
1353 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1354 __le16 rsvd_dmaindx;
1355
1356 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1357 __le64 flags_rsvd_lanq;
1358 };
1359
1360 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1361 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1362 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1363
1364 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1365 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1366 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1367 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1368 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1369 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1370 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1371 };
1372
1373 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1374 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1375 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1376
1377 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1378 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1379 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1380
1381 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1382 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1383 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1384
1385 #endif /* I40E_FCOE */
1386 enum i40e_switch_element_types {
1387 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1388 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1389 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1390 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1391 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1392 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1393 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1394 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1395 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1396 };
1397
1398 /* Supported EtherType filters */
1399 enum i40e_ether_type_index {
1400 I40E_ETHER_TYPE_1588 = 0,
1401 I40E_ETHER_TYPE_FIP = 1,
1402 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1403 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1404 I40E_ETHER_TYPE_LLDP = 4,
1405 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1406 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1407 I40E_ETHER_TYPE_QCN_CNM = 7,
1408 I40E_ETHER_TYPE_8021X = 8,
1409 I40E_ETHER_TYPE_ARP = 9,
1410 I40E_ETHER_TYPE_RSV1 = 10,
1411 I40E_ETHER_TYPE_RSV2 = 11,
1412 };
1413
1414 /* Filter context base size is 1K */
1415 #define I40E_HASH_FILTER_BASE_SIZE 1024
1416 /* Supported Hash filter values */
1417 enum i40e_hash_filter_size {
1418 I40E_HASH_FILTER_SIZE_1K = 0,
1419 I40E_HASH_FILTER_SIZE_2K = 1,
1420 I40E_HASH_FILTER_SIZE_4K = 2,
1421 I40E_HASH_FILTER_SIZE_8K = 3,
1422 I40E_HASH_FILTER_SIZE_16K = 4,
1423 I40E_HASH_FILTER_SIZE_32K = 5,
1424 I40E_HASH_FILTER_SIZE_64K = 6,
1425 I40E_HASH_FILTER_SIZE_128K = 7,
1426 I40E_HASH_FILTER_SIZE_256K = 8,
1427 I40E_HASH_FILTER_SIZE_512K = 9,
1428 I40E_HASH_FILTER_SIZE_1M = 10,
1429 };
1430
1431 /* DMA context base size is 0.5K */
1432 #define I40E_DMA_CNTX_BASE_SIZE 512
1433 /* Supported DMA context values */
1434 enum i40e_dma_cntx_size {
1435 I40E_DMA_CNTX_SIZE_512 = 0,
1436 I40E_DMA_CNTX_SIZE_1K = 1,
1437 I40E_DMA_CNTX_SIZE_2K = 2,
1438 I40E_DMA_CNTX_SIZE_4K = 3,
1439 I40E_DMA_CNTX_SIZE_8K = 4,
1440 I40E_DMA_CNTX_SIZE_16K = 5,
1441 I40E_DMA_CNTX_SIZE_32K = 6,
1442 I40E_DMA_CNTX_SIZE_64K = 7,
1443 I40E_DMA_CNTX_SIZE_128K = 8,
1444 I40E_DMA_CNTX_SIZE_256K = 9,
1445 };
1446
1447 /* Supported Hash look up table (LUT) sizes */
1448 enum i40e_hash_lut_size {
1449 I40E_HASH_LUT_SIZE_128 = 0,
1450 I40E_HASH_LUT_SIZE_512 = 1,
1451 };
1452
1453 /* Structure to hold a per PF filter control settings */
1454 struct i40e_filter_control_settings {
1455 /* number of PE Quad Hash filter buckets */
1456 enum i40e_hash_filter_size pe_filt_num;
1457 /* number of PE Quad Hash contexts */
1458 enum i40e_dma_cntx_size pe_cntx_num;
1459 /* number of FCoE filter buckets */
1460 enum i40e_hash_filter_size fcoe_filt_num;
1461 /* number of FCoE DDP contexts */
1462 enum i40e_dma_cntx_size fcoe_cntx_num;
1463 /* size of the Hash LUT */
1464 enum i40e_hash_lut_size hash_lut_size;
1465 /* enable FDIR filters for PF and its VFs */
1466 bool enable_fdir;
1467 /* enable Ethertype filters for PF and its VFs */
1468 bool enable_ethtype;
1469 /* enable MAC/VLAN filters for PF and its VFs */
1470 bool enable_macvlan;
1471 };
1472
1473 /* Structure to hold device level control filter counts */
1474 struct i40e_control_filter_stats {
1475 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1476 u16 etype_used; /* Used perfect EtherType filters */
1477 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1478 u16 etype_free; /* Un-used perfect EtherType filters */
1479 };
1480
1481 enum i40e_reset_type {
1482 I40E_RESET_POR = 0,
1483 I40E_RESET_CORER = 1,
1484 I40E_RESET_GLOBR = 2,
1485 I40E_RESET_EMPR = 3,
1486 };
1487
1488 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1489 #define I40E_NVM_LLDP_CFG_PTR 0xD
1490 struct i40e_lldp_variables {
1491 u16 length;
1492 u16 adminstatus;
1493 u16 msgfasttx;
1494 u16 msgtxinterval;
1495 u16 txparams;
1496 u16 timers;
1497 u16 crc8;
1498 };
1499
1500 /* Offsets into Alternate Ram */
1501 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1502 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1503 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1504 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1505 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1506 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1507
1508 /* Alternate Ram Bandwidth Masks */
1509 #define I40E_ALT_BW_VALUE_MASK 0xFF
1510 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1511 #define I40E_ALT_BW_VALID_MASK 0x80000000
1512
1513 /* RSS Hash Table Size */
1514 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1515 #endif /* _I40E_TYPE_H_ */
1516