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1 /*
2  * Copyright 2010 Tilera Corporation. All Rights Reserved.
3  *
4  *   This program is free software; you can redistribute it and/or
5  *   modify it under the terms of the GNU General Public License
6  *   as published by the Free Software Foundation, version 2.
7  *
8  *   This program is distributed in the hope that it will be useful, but
9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11  *   NON INFRINGEMENT.  See the GNU General Public License for
12  *   more details.
13  */
14 
15 #ifndef __ARCH_INTERRUPTS_H__
16 #define __ARCH_INTERRUPTS_H__
17 
18 #ifndef __KERNEL__
19 /** Mask for an interrupt. */
20 /* Note: must handle breaking interrupts into high and low words manually. */
21 #define INT_MASK_LO(intno) (1 << (intno))
22 #define INT_MASK_HI(intno) (1 << ((intno) - 32))
23 
24 #ifndef __ASSEMBLER__
25 #define INT_MASK(intno) (1ULL << (intno))
26 #endif
27 #endif
28 
29 
30 /** Where a given interrupt executes */
31 #define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
32 
33 /** Where to store a vector for a given interrupt. */
34 #define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
35 
36 /** The base address of user-level interrupts. */
37 #define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
38 
39 
40 /** Additional synthetic interrupt. */
41 #define INT_BREAKPOINT (63)
42 
43 #define INT_ITLB_MISS    0
44 #define INT_MEM_ERROR    1
45 #define INT_ILL    2
46 #define INT_GPV    3
47 #define INT_SN_ACCESS    4
48 #define INT_IDN_ACCESS    5
49 #define INT_UDN_ACCESS    6
50 #define INT_IDN_REFILL    7
51 #define INT_UDN_REFILL    8
52 #define INT_IDN_COMPLETE    9
53 #define INT_UDN_COMPLETE   10
54 #define INT_SWINT_3   11
55 #define INT_SWINT_2   12
56 #define INT_SWINT_1   13
57 #define INT_SWINT_0   14
58 #define INT_UNALIGN_DATA   15
59 #define INT_DTLB_MISS   16
60 #define INT_DTLB_ACCESS   17
61 #define INT_DMATLB_MISS   18
62 #define INT_DMATLB_ACCESS   19
63 #define INT_SNITLB_MISS   20
64 #define INT_SN_NOTIFY   21
65 #define INT_SN_FIREWALL   22
66 #define INT_IDN_FIREWALL   23
67 #define INT_UDN_FIREWALL   24
68 #define INT_TILE_TIMER   25
69 #define INT_IDN_TIMER   26
70 #define INT_UDN_TIMER   27
71 #define INT_DMA_NOTIFY   28
72 #define INT_IDN_CA   29
73 #define INT_UDN_CA   30
74 #define INT_IDN_AVAIL   31
75 #define INT_UDN_AVAIL   32
76 #define INT_PERF_COUNT   33
77 #define INT_INTCTRL_3   34
78 #define INT_INTCTRL_2   35
79 #define INT_INTCTRL_1   36
80 #define INT_INTCTRL_0   37
81 #define INT_BOOT_ACCESS   38
82 #define INT_WORLD_ACCESS   39
83 #define INT_I_ASID   40
84 #define INT_D_ASID   41
85 #define INT_DMA_ASID   42
86 #define INT_SNI_ASID   43
87 #define INT_DMA_CPL   44
88 #define INT_SN_CPL   45
89 #define INT_DOUBLE_FAULT   46
90 #define INT_SN_STATIC_ACCESS   47
91 #define INT_AUX_PERF_COUNT   48
92 
93 #define NUM_INTERRUPTS 49
94 
95 #ifndef __ASSEMBLER__
96 #define QUEUED_INTERRUPTS ( \
97     (1ULL << INT_MEM_ERROR) | \
98     (1ULL << INT_DMATLB_MISS) | \
99     (1ULL << INT_DMATLB_ACCESS) | \
100     (1ULL << INT_SNITLB_MISS) | \
101     (1ULL << INT_SN_NOTIFY) | \
102     (1ULL << INT_SN_FIREWALL) | \
103     (1ULL << INT_IDN_FIREWALL) | \
104     (1ULL << INT_UDN_FIREWALL) | \
105     (1ULL << INT_TILE_TIMER) | \
106     (1ULL << INT_IDN_TIMER) | \
107     (1ULL << INT_UDN_TIMER) | \
108     (1ULL << INT_DMA_NOTIFY) | \
109     (1ULL << INT_IDN_CA) | \
110     (1ULL << INT_UDN_CA) | \
111     (1ULL << INT_IDN_AVAIL) | \
112     (1ULL << INT_UDN_AVAIL) | \
113     (1ULL << INT_PERF_COUNT) | \
114     (1ULL << INT_INTCTRL_3) | \
115     (1ULL << INT_INTCTRL_2) | \
116     (1ULL << INT_INTCTRL_1) | \
117     (1ULL << INT_INTCTRL_0) | \
118     (1ULL << INT_BOOT_ACCESS) | \
119     (1ULL << INT_WORLD_ACCESS) | \
120     (1ULL << INT_I_ASID) | \
121     (1ULL << INT_D_ASID) | \
122     (1ULL << INT_DMA_ASID) | \
123     (1ULL << INT_SNI_ASID) | \
124     (1ULL << INT_DMA_CPL) | \
125     (1ULL << INT_SN_CPL) | \
126     (1ULL << INT_DOUBLE_FAULT) | \
127     (1ULL << INT_AUX_PERF_COUNT) | \
128     0)
129 #define NONQUEUED_INTERRUPTS ( \
130     (1ULL << INT_ITLB_MISS) | \
131     (1ULL << INT_ILL) | \
132     (1ULL << INT_GPV) | \
133     (1ULL << INT_SN_ACCESS) | \
134     (1ULL << INT_IDN_ACCESS) | \
135     (1ULL << INT_UDN_ACCESS) | \
136     (1ULL << INT_IDN_REFILL) | \
137     (1ULL << INT_UDN_REFILL) | \
138     (1ULL << INT_IDN_COMPLETE) | \
139     (1ULL << INT_UDN_COMPLETE) | \
140     (1ULL << INT_SWINT_3) | \
141     (1ULL << INT_SWINT_2) | \
142     (1ULL << INT_SWINT_1) | \
143     (1ULL << INT_SWINT_0) | \
144     (1ULL << INT_UNALIGN_DATA) | \
145     (1ULL << INT_DTLB_MISS) | \
146     (1ULL << INT_DTLB_ACCESS) | \
147     (1ULL << INT_SN_STATIC_ACCESS) | \
148     0)
149 #define CRITICAL_MASKED_INTERRUPTS ( \
150     (1ULL << INT_MEM_ERROR) | \
151     (1ULL << INT_DMATLB_MISS) | \
152     (1ULL << INT_DMATLB_ACCESS) | \
153     (1ULL << INT_SNITLB_MISS) | \
154     (1ULL << INT_SN_NOTIFY) | \
155     (1ULL << INT_SN_FIREWALL) | \
156     (1ULL << INT_IDN_FIREWALL) | \
157     (1ULL << INT_UDN_FIREWALL) | \
158     (1ULL << INT_TILE_TIMER) | \
159     (1ULL << INT_IDN_TIMER) | \
160     (1ULL << INT_UDN_TIMER) | \
161     (1ULL << INT_DMA_NOTIFY) | \
162     (1ULL << INT_IDN_CA) | \
163     (1ULL << INT_UDN_CA) | \
164     (1ULL << INT_IDN_AVAIL) | \
165     (1ULL << INT_UDN_AVAIL) | \
166     (1ULL << INT_PERF_COUNT) | \
167     (1ULL << INT_INTCTRL_3) | \
168     (1ULL << INT_INTCTRL_2) | \
169     (1ULL << INT_INTCTRL_1) | \
170     (1ULL << INT_INTCTRL_0) | \
171     (1ULL << INT_AUX_PERF_COUNT) | \
172     0)
173 #define CRITICAL_UNMASKED_INTERRUPTS ( \
174     (1ULL << INT_ITLB_MISS) | \
175     (1ULL << INT_ILL) | \
176     (1ULL << INT_GPV) | \
177     (1ULL << INT_SN_ACCESS) | \
178     (1ULL << INT_IDN_ACCESS) | \
179     (1ULL << INT_UDN_ACCESS) | \
180     (1ULL << INT_IDN_REFILL) | \
181     (1ULL << INT_UDN_REFILL) | \
182     (1ULL << INT_IDN_COMPLETE) | \
183     (1ULL << INT_UDN_COMPLETE) | \
184     (1ULL << INT_SWINT_3) | \
185     (1ULL << INT_SWINT_2) | \
186     (1ULL << INT_SWINT_1) | \
187     (1ULL << INT_SWINT_0) | \
188     (1ULL << INT_UNALIGN_DATA) | \
189     (1ULL << INT_DTLB_MISS) | \
190     (1ULL << INT_DTLB_ACCESS) | \
191     (1ULL << INT_BOOT_ACCESS) | \
192     (1ULL << INT_WORLD_ACCESS) | \
193     (1ULL << INT_I_ASID) | \
194     (1ULL << INT_D_ASID) | \
195     (1ULL << INT_DMA_ASID) | \
196     (1ULL << INT_SNI_ASID) | \
197     (1ULL << INT_DMA_CPL) | \
198     (1ULL << INT_SN_CPL) | \
199     (1ULL << INT_DOUBLE_FAULT) | \
200     (1ULL << INT_SN_STATIC_ACCESS) | \
201     0)
202 #define MASKABLE_INTERRUPTS ( \
203     (1ULL << INT_MEM_ERROR) | \
204     (1ULL << INT_IDN_REFILL) | \
205     (1ULL << INT_UDN_REFILL) | \
206     (1ULL << INT_IDN_COMPLETE) | \
207     (1ULL << INT_UDN_COMPLETE) | \
208     (1ULL << INT_DMATLB_MISS) | \
209     (1ULL << INT_DMATLB_ACCESS) | \
210     (1ULL << INT_SNITLB_MISS) | \
211     (1ULL << INT_SN_NOTIFY) | \
212     (1ULL << INT_SN_FIREWALL) | \
213     (1ULL << INT_IDN_FIREWALL) | \
214     (1ULL << INT_UDN_FIREWALL) | \
215     (1ULL << INT_TILE_TIMER) | \
216     (1ULL << INT_IDN_TIMER) | \
217     (1ULL << INT_UDN_TIMER) | \
218     (1ULL << INT_DMA_NOTIFY) | \
219     (1ULL << INT_IDN_CA) | \
220     (1ULL << INT_UDN_CA) | \
221     (1ULL << INT_IDN_AVAIL) | \
222     (1ULL << INT_UDN_AVAIL) | \
223     (1ULL << INT_PERF_COUNT) | \
224     (1ULL << INT_INTCTRL_3) | \
225     (1ULL << INT_INTCTRL_2) | \
226     (1ULL << INT_INTCTRL_1) | \
227     (1ULL << INT_INTCTRL_0) | \
228     (1ULL << INT_AUX_PERF_COUNT) | \
229     0)
230 #define UNMASKABLE_INTERRUPTS ( \
231     (1ULL << INT_ITLB_MISS) | \
232     (1ULL << INT_ILL) | \
233     (1ULL << INT_GPV) | \
234     (1ULL << INT_SN_ACCESS) | \
235     (1ULL << INT_IDN_ACCESS) | \
236     (1ULL << INT_UDN_ACCESS) | \
237     (1ULL << INT_SWINT_3) | \
238     (1ULL << INT_SWINT_2) | \
239     (1ULL << INT_SWINT_1) | \
240     (1ULL << INT_SWINT_0) | \
241     (1ULL << INT_UNALIGN_DATA) | \
242     (1ULL << INT_DTLB_MISS) | \
243     (1ULL << INT_DTLB_ACCESS) | \
244     (1ULL << INT_BOOT_ACCESS) | \
245     (1ULL << INT_WORLD_ACCESS) | \
246     (1ULL << INT_I_ASID) | \
247     (1ULL << INT_D_ASID) | \
248     (1ULL << INT_DMA_ASID) | \
249     (1ULL << INT_SNI_ASID) | \
250     (1ULL << INT_DMA_CPL) | \
251     (1ULL << INT_SN_CPL) | \
252     (1ULL << INT_DOUBLE_FAULT) | \
253     (1ULL << INT_SN_STATIC_ACCESS) | \
254     0)
255 #define SYNC_INTERRUPTS ( \
256     (1ULL << INT_ITLB_MISS) | \
257     (1ULL << INT_ILL) | \
258     (1ULL << INT_GPV) | \
259     (1ULL << INT_SN_ACCESS) | \
260     (1ULL << INT_IDN_ACCESS) | \
261     (1ULL << INT_UDN_ACCESS) | \
262     (1ULL << INT_IDN_REFILL) | \
263     (1ULL << INT_UDN_REFILL) | \
264     (1ULL << INT_IDN_COMPLETE) | \
265     (1ULL << INT_UDN_COMPLETE) | \
266     (1ULL << INT_SWINT_3) | \
267     (1ULL << INT_SWINT_2) | \
268     (1ULL << INT_SWINT_1) | \
269     (1ULL << INT_SWINT_0) | \
270     (1ULL << INT_UNALIGN_DATA) | \
271     (1ULL << INT_DTLB_MISS) | \
272     (1ULL << INT_DTLB_ACCESS) | \
273     (1ULL << INT_SN_STATIC_ACCESS) | \
274     0)
275 #define NON_SYNC_INTERRUPTS ( \
276     (1ULL << INT_MEM_ERROR) | \
277     (1ULL << INT_DMATLB_MISS) | \
278     (1ULL << INT_DMATLB_ACCESS) | \
279     (1ULL << INT_SNITLB_MISS) | \
280     (1ULL << INT_SN_NOTIFY) | \
281     (1ULL << INT_SN_FIREWALL) | \
282     (1ULL << INT_IDN_FIREWALL) | \
283     (1ULL << INT_UDN_FIREWALL) | \
284     (1ULL << INT_TILE_TIMER) | \
285     (1ULL << INT_IDN_TIMER) | \
286     (1ULL << INT_UDN_TIMER) | \
287     (1ULL << INT_DMA_NOTIFY) | \
288     (1ULL << INT_IDN_CA) | \
289     (1ULL << INT_UDN_CA) | \
290     (1ULL << INT_IDN_AVAIL) | \
291     (1ULL << INT_UDN_AVAIL) | \
292     (1ULL << INT_PERF_COUNT) | \
293     (1ULL << INT_INTCTRL_3) | \
294     (1ULL << INT_INTCTRL_2) | \
295     (1ULL << INT_INTCTRL_1) | \
296     (1ULL << INT_INTCTRL_0) | \
297     (1ULL << INT_BOOT_ACCESS) | \
298     (1ULL << INT_WORLD_ACCESS) | \
299     (1ULL << INT_I_ASID) | \
300     (1ULL << INT_D_ASID) | \
301     (1ULL << INT_DMA_ASID) | \
302     (1ULL << INT_SNI_ASID) | \
303     (1ULL << INT_DMA_CPL) | \
304     (1ULL << INT_SN_CPL) | \
305     (1ULL << INT_DOUBLE_FAULT) | \
306     (1ULL << INT_AUX_PERF_COUNT) | \
307     0)
308 #endif /* !__ASSEMBLER__ */
309 #endif /* !__ARCH_INTERRUPTS_H__ */
310