1 /*!************************************************************************** 2 *! 3 *! MACROS: 4 *! IO_MASK(reg,field) 5 *! IO_STATE(reg,field,state) 6 *! IO_EXTRACT(reg,field,val) 7 *! IO_STATE_VALUE(reg,field,state) 8 *! IO_BITNR(reg,field) 9 *! IO_WIDTH(reg,field) 10 *! IO_FIELD(reg,field,val) 11 *! IO_RD(reg) 12 *! All moderegister addresses and fields of these. 13 *! 14 *!**************************************************************************/ 15 16 #ifndef __sv_addr_ag_h__ 17 #define __sv_addr_ag_h__ 18 19 20 #define __test_sv_addr__ 0 21 22 /*------------------------------------------------------------ 23 !* General macros to manipulate moderegisters. 24 !*-----------------------------------------------------------*/ 25 26 /* IO_MASK returns a mask for a specified bitfield in a register. 27 Note that this macro doesn't work when field width is 32 bits. */ 28 #define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_) 29 #define IO_MASK_(reg_, field_) \ 30 ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR ) 31 32 /* IO_STATE returns a constant corresponding to a one of the symbolic 33 states that the bitfield can have. (Shifted to correct position) */ 34 #define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state) 35 #define IO_STATE_(reg_, field_, _state) \ 36 ( reg_##_##field_##_state << reg_##_##field_##_BITNR ) 37 38 /* IO_EXTRACT returns the masked and shifted value corresponding to the 39 bitfield can have. */ 40 #define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val) 41 #define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \ 42 - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR ) 43 44 /* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic 45 states that the bitfield can have. (Not shifted) */ 46 #define IO_STATE_VALUE(reg, field, state) \ 47 IO_STATE_VALUE_ (reg##_, field##_, _##state) 48 #define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state ) 49 50 /* IO_FIELD shifts the val parameter to be aligned with the bitfield 51 specified. */ 52 #define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val) 53 #define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR) 54 55 /* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is 56 LSB and the returned bitnumber is LSB of the field. */ 57 #define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_) 58 #define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR) 59 60 /* IO_WIDTH returns the width, in bits, of a bitfield. */ 61 #define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_) 62 #define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH) 63 64 /*--- Obsolete. Kept for backw compatibility. ---*/ 65 /* Reads (or writes) a byte/uword/udword from the specified mode 66 register. */ 67 #define IO_RD(reg) (*(volatile u32*)(reg)) 68 #define IO_RD_B(reg) (*(volatile u8*)(reg)) 69 #define IO_RD_W(reg) (*(volatile u16*)(reg)) 70 #define IO_RD_D(reg) (*(volatile u32*)(reg)) 71 72 /*------------------------------------------------------------ 73 !* Start addresses of the different memory areas. 74 !*-----------------------------------------------------------*/ 75 76 #define MEM_CSE0_START (0x00000000) 77 #define MEM_CSE0_SIZE (0x04000000) 78 #define MEM_CSE1_START (0x04000000) 79 #define MEM_CSE1_SIZE (0x04000000) 80 #define MEM_CSR0_START (0x08000000) 81 #define MEM_CSR1_START (0x0c000000) 82 #define MEM_CSP0_START (0x10000000) 83 #define MEM_CSP1_START (0x14000000) 84 #define MEM_CSP2_START (0x18000000) 85 #define MEM_CSP3_START (0x1c000000) 86 #define MEM_CSP4_START (0x20000000) 87 #define MEM_CSP5_START (0x24000000) 88 #define MEM_CSP6_START (0x28000000) 89 #define MEM_CSP7_START (0x2c000000) 90 #define MEM_DRAM_START (0x40000000) 91 92 #define MEM_NON_CACHEABLE (0x80000000) 93 94 /*------------------------------------------------------------ 95 !* Type casts used in mode register macros, making pointer 96 !* dereferencing possible. Empty in assembler. 97 !*-----------------------------------------------------------*/ 98 99 #ifndef __ASSEMBLER__ 100 # define IO_TYPECAST_UDWORD (volatile u32*) 101 # define IO_TYPECAST_RO_UDWORD (const volatile u32*) 102 # define IO_TYPECAST_UWORD (volatile u16*) 103 # define IO_TYPECAST_RO_UWORD (const volatile u16*) 104 # define IO_TYPECAST_BYTE (volatile u8*) 105 # define IO_TYPECAST_RO_BYTE (const volatile u8*) 106 #else 107 # define IO_TYPECAST_UDWORD 108 # define IO_TYPECAST_RO_UDWORD 109 # define IO_TYPECAST_UWORD 110 # define IO_TYPECAST_RO_UWORD 111 # define IO_TYPECAST_BYTE 112 # define IO_TYPECAST_RO_BYTE 113 #endif 114 115 /*------------------------------------------------------------*/ 116 117 #include <arch/sv_addr.agh> 118 119 #if __test_sv_addr__ 120 /* IO_MASK( R_BUS_CONFIG , CE ) */ 121 IO_MASK( R_WAITSTATES , SRAM_WS ) 122 IO_MASK( R_TEST , W32 ) 123 124 IO_STATE( R_BUS_CONFIG, CE, DISABLE ) 125 IO_STATE( R_BUS_CONFIG, CE, ENABLE ) 126 127 IO_STATE( R_DRAM_TIMING, REF, IVAL2 ) 128 129 IO_MASK( R_DRAM_TIMING, REF ) 130 131 IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT ) 132 133 IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S ) 134 == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED ) 135 #endif 136 137 138 #endif /* ifndef __sv_addr_ag_h__ */ 139 140