1 /*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16 #ifndef __ASM_CPUTYPE_H
17 #define __ASM_CPUTYPE_H
18
19 #define INVALID_HWID ULONG_MAX
20
21 #define MPIDR_UP_BITMASK (0x1 << 30)
22 #define MPIDR_MT_BITMASK (0x1 << 24)
23 #define MPIDR_HWID_BITMASK 0xff00ffffff
24
25 #define MPIDR_LEVEL_BITS_SHIFT 3
26 #define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
27 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
28
29 #define MPIDR_LEVEL_SHIFT(level) \
30 (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
31
32 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
33 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
34
35 #define MIDR_REVISION_MASK 0xf
36 #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
37 #define MIDR_PARTNUM_SHIFT 4
38 #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
39 #define MIDR_PARTNUM(midr) \
40 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
41 #define MIDR_ARCHITECTURE_SHIFT 16
42 #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
43 #define MIDR_ARCHITECTURE(midr) \
44 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
45 #define MIDR_VARIANT_SHIFT 20
46 #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
47 #define MIDR_VARIANT(midr) \
48 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
49 #define MIDR_IMPLEMENTOR_SHIFT 24
50 #define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
51 #define MIDR_IMPLEMENTOR(midr) \
52 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
53
54 #define MIDR_CPU_VAR_REV(var, rev) \
55 (((var) << MIDR_VARIANT_SHIFT) | (rev))
56
57 #define MIDR_CPU_PART_MASK \
58 (MIDR_IMPLEMENTOR_MASK | \
59 MIDR_ARCHITECTURE_MASK | \
60 MIDR_PARTNUM_MASK)
61
62 #define MIDR_CPU_MODEL(imp, partnum) \
63 (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \
64 (0xf << MIDR_ARCHITECTURE_SHIFT) | \
65 ((partnum) << MIDR_PARTNUM_SHIFT))
66
67 #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
68 MIDR_ARCHITECTURE_MASK)
69
70 #define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \
71 ({ \
72 u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \
73 u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \
74 \
75 _model == (model) && rv >= (rv_min) && rv <= (rv_max); \
76 })
77
78 #define ARM_CPU_IMP_ARM 0x41
79 #define ARM_CPU_IMP_APM 0x50
80 #define ARM_CPU_IMP_CAVIUM 0x43
81
82 #define ARM_CPU_PART_AEM_V8 0xD0F
83 #define ARM_CPU_PART_FOUNDATION 0xD00
84 #define ARM_CPU_PART_CORTEX_A57 0xD07
85 #define ARM_CPU_PART_CORTEX_A53 0xD03
86 #define ARM_CPU_PART_CORTEX_A55 0xD05
87
88 #define APM_CPU_PART_POTENZA 0x000
89
90 #define CAVIUM_CPU_PART_THUNDERX 0x0A1
91
92 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
93 #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
94 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
95 #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
96
97 #ifndef __ASSEMBLY__
98
99 #include <asm/sysreg.h>
100
101 #define read_cpuid(reg) ({ \
102 u64 __val; \
103 asm("mrs_s %0, " __stringify(reg) : "=r" (__val)); \
104 __val; \
105 })
106
107 /*
108 * The CPU ID never changes at run time, so we might as well tell the
109 * compiler that it's constant. Use this function to read the CPU ID
110 * rather than directly reading processor_id or read_cpuid() directly.
111 */
read_cpuid_id(void)112 static inline u32 __attribute_const__ read_cpuid_id(void)
113 {
114 return read_cpuid(SYS_MIDR_EL1);
115 }
116
read_cpuid_mpidr(void)117 static inline u64 __attribute_const__ read_cpuid_mpidr(void)
118 {
119 return read_cpuid(SYS_MPIDR_EL1);
120 }
121
read_cpuid_implementor(void)122 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
123 {
124 return MIDR_IMPLEMENTOR(read_cpuid_id());
125 }
126
read_cpuid_part_number(void)127 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
128 {
129 return MIDR_PARTNUM(read_cpuid_id());
130 }
131
read_cpuid_cachetype(void)132 static inline u32 __attribute_const__ read_cpuid_cachetype(void)
133 {
134 return read_cpuid(SYS_CTR_EL0);
135 }
136 #endif /* __ASSEMBLY__ */
137
138 #endif
139