1 /* 2 * Copyright © 2006 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28 #ifndef _I830_BIOS_H_ 29 #define _I830_BIOS_H_ 30 31 #include <drm/drmP.h> 32 33 struct vbt_header { 34 u8 signature[20]; /**< Always starts with 'VBT$' */ 35 u16 version; /**< decimal */ 36 u16 header_size; /**< in bytes */ 37 u16 vbt_size; /**< in bytes */ 38 u8 vbt_checksum; 39 u8 reserved0; 40 u32 bdb_offset; /**< from beginning of VBT */ 41 u32 aim_offset[4]; /**< from beginning of VBT */ 42 } __packed; 43 44 struct bdb_header { 45 u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */ 46 u16 version; /**< decimal */ 47 u16 header_size; /**< in bytes */ 48 u16 bdb_size; /**< in bytes */ 49 } __packed; 50 51 /* strictly speaking, this is a "skip" block, but it has interesting info */ 52 struct vbios_data { 53 u8 type; /* 0 == desktop, 1 == mobile */ 54 u8 relstage; 55 u8 chipset; 56 u8 lvds_present:1; 57 u8 tv_present:1; 58 u8 rsvd2:6; /* finish byte */ 59 u8 rsvd3[4]; 60 u8 signon[155]; 61 u8 copyright[61]; 62 u16 code_segment; 63 u8 dos_boot_mode; 64 u8 bandwidth_percent; 65 u8 rsvd4; /* popup memory size */ 66 u8 resize_pci_bios; 67 u8 rsvd5; /* is crt already on ddc2 */ 68 } __packed; 69 70 /* 71 * There are several types of BIOS data blocks (BDBs), each block has 72 * an ID and size in the first 3 bytes (ID in first, size in next 2). 73 * Known types are listed below. 74 */ 75 #define BDB_GENERAL_FEATURES 1 76 #define BDB_GENERAL_DEFINITIONS 2 77 #define BDB_OLD_TOGGLE_LIST 3 78 #define BDB_MODE_SUPPORT_LIST 4 79 #define BDB_GENERIC_MODE_TABLE 5 80 #define BDB_EXT_MMIO_REGS 6 81 #define BDB_SWF_IO 7 82 #define BDB_SWF_MMIO 8 83 #define BDB_PSR 9 84 #define BDB_MODE_REMOVAL_TABLE 10 85 #define BDB_CHILD_DEVICE_TABLE 11 86 #define BDB_DRIVER_FEATURES 12 87 #define BDB_DRIVER_PERSISTENCE 13 88 #define BDB_EXT_TABLE_PTRS 14 89 #define BDB_DOT_CLOCK_OVERRIDE 15 90 #define BDB_DISPLAY_SELECT 16 91 /* 17 rsvd */ 92 #define BDB_DRIVER_ROTATION 18 93 #define BDB_DISPLAY_REMOVE 19 94 #define BDB_OEM_CUSTOM 20 95 #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ 96 #define BDB_SDVO_LVDS_OPTIONS 22 97 #define BDB_SDVO_PANEL_DTDS 23 98 #define BDB_SDVO_LVDS_PNP_IDS 24 99 #define BDB_SDVO_LVDS_POWER_SEQ 25 100 #define BDB_TV_OPTIONS 26 101 #define BDB_EDP 27 102 #define BDB_LVDS_OPTIONS 40 103 #define BDB_LVDS_LFP_DATA_PTRS 41 104 #define BDB_LVDS_LFP_DATA 42 105 #define BDB_LVDS_BACKLIGHT 43 106 #define BDB_LVDS_POWER 44 107 #define BDB_MIPI_CONFIG 52 108 #define BDB_MIPI_SEQUENCE 53 109 #define BDB_SKIP 254 /* VBIOS private block, ignore */ 110 111 struct bdb_general_features { 112 /* bits 1 */ 113 u8 panel_fitting:2; 114 u8 flexaim:1; 115 u8 msg_enable:1; 116 u8 clear_screen:3; 117 u8 color_flip:1; 118 119 /* bits 2 */ 120 u8 download_ext_vbt:1; 121 u8 enable_ssc:1; 122 u8 ssc_freq:1; 123 u8 enable_lfp_on_override:1; 124 u8 disable_ssc_ddt:1; 125 u8 rsvd7:1; 126 u8 display_clock_mode:1; 127 u8 rsvd8:1; /* finish byte */ 128 129 /* bits 3 */ 130 u8 disable_smooth_vision:1; 131 u8 single_dvi:1; 132 u8 rsvd9:1; 133 u8 fdi_rx_polarity_inverted:1; 134 u8 rsvd10:4; /* finish byte */ 135 136 /* bits 4 */ 137 u8 legacy_monitor_detect; 138 139 /* bits 5 */ 140 u8 int_crt_support:1; 141 u8 int_tv_support:1; 142 u8 int_efp_support:1; 143 u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ 144 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ 145 u8 rsvd11:3; /* finish byte */ 146 } __packed; 147 148 /* pre-915 */ 149 #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ 150 #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ 151 #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ 152 #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ 153 154 /* Pre 915 */ 155 #define DEVICE_TYPE_NONE 0x00 156 #define DEVICE_TYPE_CRT 0x01 157 #define DEVICE_TYPE_TV 0x09 158 #define DEVICE_TYPE_EFP 0x12 159 #define DEVICE_TYPE_LFP 0x22 160 /* On 915+ */ 161 #define DEVICE_TYPE_CRT_DPMS 0x6001 162 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 163 #define DEVICE_TYPE_TV_COMPOSITE 0x0209 164 #define DEVICE_TYPE_TV_MACROVISION 0x0289 165 #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c 166 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 167 #define DEVICE_TYPE_TV_SCART 0x0209 168 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 169 #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 170 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 171 #define DEVICE_TYPE_EFP_DVI_I 0x6053 172 #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 173 #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 174 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 175 #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 176 #define DEVICE_TYPE_LFP_PANELLINK 0x5012 177 #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 178 #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 179 #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 180 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 181 182 #define DEVICE_CFG_NONE 0x00 183 #define DEVICE_CFG_12BIT_DVOB 0x01 184 #define DEVICE_CFG_12BIT_DVOC 0x02 185 #define DEVICE_CFG_24BIT_DVOBC 0x09 186 #define DEVICE_CFG_24BIT_DVOCB 0x0a 187 #define DEVICE_CFG_DUAL_DVOB 0x11 188 #define DEVICE_CFG_DUAL_DVOC 0x12 189 #define DEVICE_CFG_DUAL_DVOBC 0x13 190 #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 191 #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a 192 193 #define DEVICE_WIRE_NONE 0x00 194 #define DEVICE_WIRE_DVOB 0x01 195 #define DEVICE_WIRE_DVOC 0x02 196 #define DEVICE_WIRE_DVOBC 0x03 197 #define DEVICE_WIRE_DVOBB 0x05 198 #define DEVICE_WIRE_DVOCC 0x06 199 #define DEVICE_WIRE_DVOB_MASTER 0x0d 200 #define DEVICE_WIRE_DVOC_MASTER 0x0e 201 202 #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ 203 #define DEVICE_PORT_DVOB 0x01 204 #define DEVICE_PORT_DVOC 0x02 205 206 /* 207 * We used to keep this struct but without any version control. We should avoid 208 * using it in the future, but it should be safe to keep using it in the old 209 * code. Do not change; we rely on its size. 210 */ 211 struct old_child_dev_config { 212 u16 handle; 213 u16 device_type; 214 u8 device_id[10]; /* ascii string */ 215 u16 addin_offset; 216 u8 dvo_port; /* See Device_PORT_* above */ 217 u8 i2c_pin; 218 u8 slave_addr; 219 u8 ddc_pin; 220 u16 edid_ptr; 221 u8 dvo_cfg; /* See DEVICE_CFG_* above */ 222 u8 dvo2_port; 223 u8 i2c2_pin; 224 u8 slave2_addr; 225 u8 ddc2_pin; 226 u8 capabilities; 227 u8 dvo_wiring;/* See DEVICE_WIRE_* above */ 228 u8 dvo2_wiring; 229 u16 extended_type; 230 u8 dvo_function; 231 } __packed; 232 233 /* This one contains field offsets that are known to be common for all BDB 234 * versions. Notice that the meaning of the contents contents may still change, 235 * but at least the offsets are consistent. */ 236 237 /* Definitions for flags_1 */ 238 #define IBOOST_ENABLE (1<<3) 239 240 struct common_child_dev_config { 241 u16 handle; 242 u16 device_type; 243 u8 not_common1[12]; 244 u8 dvo_port; 245 u8 not_common2[2]; 246 u8 ddc_pin; 247 u16 edid_ptr; 248 u8 obsolete; 249 u8 flags_1; 250 u8 not_common3[13]; 251 u8 iboost_level; 252 } __packed; 253 254 255 /* This field changes depending on the BDB version, so the most reliable way to 256 * read it is by checking the BDB version and reading the raw pointer. */ 257 union child_device_config { 258 /* This one is safe to be used anywhere, but the code should still check 259 * the BDB version. */ 260 u8 raw[33]; 261 /* This one should only be kept for legacy code. */ 262 struct old_child_dev_config old; 263 /* This one should also be safe to use anywhere, even without version 264 * checks. */ 265 struct common_child_dev_config common; 266 } __packed; 267 268 struct bdb_general_definitions { 269 /* DDC GPIO */ 270 u8 crt_ddc_gmbus_pin; 271 272 /* DPMS bits */ 273 u8 dpms_acpi:1; 274 u8 skip_boot_crt_detect:1; 275 u8 dpms_aim:1; 276 u8 rsvd1:5; /* finish byte */ 277 278 /* boot device bits */ 279 u8 boot_display[2]; 280 u8 child_dev_size; 281 282 /* 283 * Device info: 284 * If TV is present, it'll be at devices[0]. 285 * LVDS will be next, either devices[0] or [1], if present. 286 * On some platforms the number of device is 6. But could be as few as 287 * 4 if both TV and LVDS are missing. 288 * And the device num is related with the size of general definition 289 * block. It is obtained by using the following formula: 290 * number = (block_size - sizeof(bdb_general_definitions))/ 291 * defs->child_dev_size; 292 */ 293 uint8_t devices[0]; 294 } __packed; 295 296 /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */ 297 #define MODE_MASK 0x3 298 299 struct bdb_lvds_options { 300 u8 panel_type; 301 u8 rsvd1; 302 /* LVDS capabilities, stored in a dword */ 303 u8 pfit_mode:2; 304 u8 pfit_text_mode_enhanced:1; 305 u8 pfit_gfx_mode_enhanced:1; 306 u8 pfit_ratio_auto:1; 307 u8 pixel_dither:1; 308 u8 lvds_edid:1; 309 u8 rsvd2:1; 310 u8 rsvd4; 311 /* LVDS Panel channel bits stored here */ 312 u32 lvds_panel_channel_bits; 313 /* LVDS SSC (Spread Spectrum Clock) bits stored here. */ 314 u16 ssc_bits; 315 u16 ssc_freq; 316 u16 ssc_ddt; 317 /* Panel color depth defined here */ 318 u16 panel_color_depth; 319 /* LVDS panel type bits stored here */ 320 u32 dps_panel_type_bits; 321 /* LVDS backlight control type bits stored here */ 322 u32 blt_control_type_bits; 323 } __packed; 324 325 /* LFP pointer table contains entries to the struct below */ 326 struct bdb_lvds_lfp_data_ptr { 327 u16 fp_timing_offset; /* offsets are from start of bdb */ 328 u8 fp_table_size; 329 u16 dvo_timing_offset; 330 u8 dvo_table_size; 331 u16 panel_pnp_id_offset; 332 u8 pnp_table_size; 333 } __packed; 334 335 struct bdb_lvds_lfp_data_ptrs { 336 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ 337 struct bdb_lvds_lfp_data_ptr ptr[16]; 338 } __packed; 339 340 /* LFP data has 3 blocks per entry */ 341 struct lvds_fp_timing { 342 u16 x_res; 343 u16 y_res; 344 u32 lvds_reg; 345 u32 lvds_reg_val; 346 u32 pp_on_reg; 347 u32 pp_on_reg_val; 348 u32 pp_off_reg; 349 u32 pp_off_reg_val; 350 u32 pp_cycle_reg; 351 u32 pp_cycle_reg_val; 352 u32 pfit_reg; 353 u32 pfit_reg_val; 354 u16 terminator; 355 } __packed; 356 357 struct lvds_dvo_timing { 358 u16 clock; /**< In 10khz */ 359 u8 hactive_lo; 360 u8 hblank_lo; 361 u8 hblank_hi:4; 362 u8 hactive_hi:4; 363 u8 vactive_lo; 364 u8 vblank_lo; 365 u8 vblank_hi:4; 366 u8 vactive_hi:4; 367 u8 hsync_off_lo; 368 u8 hsync_pulse_width; 369 u8 vsync_pulse_width:4; 370 u8 vsync_off:4; 371 u8 rsvd0:6; 372 u8 hsync_off_hi:2; 373 u8 h_image; 374 u8 v_image; 375 u8 max_hv; 376 u8 h_border; 377 u8 v_border; 378 u8 rsvd1:3; 379 u8 digital:2; 380 u8 vsync_positive:1; 381 u8 hsync_positive:1; 382 u8 rsvd2:1; 383 } __packed; 384 385 struct lvds_pnp_id { 386 u16 mfg_name; 387 u16 product_code; 388 u32 serial; 389 u8 mfg_week; 390 u8 mfg_year; 391 } __packed; 392 393 struct bdb_lvds_lfp_data_entry { 394 struct lvds_fp_timing fp_timing; 395 struct lvds_dvo_timing dvo_timing; 396 struct lvds_pnp_id pnp_id; 397 } __packed; 398 399 struct bdb_lvds_lfp_data { 400 struct bdb_lvds_lfp_data_entry data[16]; 401 } __packed; 402 403 #define BDB_BACKLIGHT_TYPE_NONE 0 404 #define BDB_BACKLIGHT_TYPE_PWM 2 405 406 struct bdb_lfp_backlight_data_entry { 407 u8 type:2; 408 u8 active_low_pwm:1; 409 u8 obsolete1:5; 410 u16 pwm_freq_hz; 411 u8 min_brightness; 412 u8 obsolete2; 413 u8 obsolete3; 414 } __packed; 415 416 struct bdb_lfp_backlight_data { 417 u8 entry_size; 418 struct bdb_lfp_backlight_data_entry data[16]; 419 u8 level[16]; 420 } __packed; 421 422 struct aimdb_header { 423 char signature[16]; 424 char oem_device[20]; 425 u16 aimdb_version; 426 u16 aimdb_header_size; 427 u16 aimdb_size; 428 } __packed; 429 430 struct aimdb_block { 431 u8 aimdb_id; 432 u16 aimdb_size; 433 } __packed; 434 435 struct vch_panel_data { 436 u16 fp_timing_offset; 437 u8 fp_timing_size; 438 u16 dvo_timing_offset; 439 u8 dvo_timing_size; 440 u16 text_fitting_offset; 441 u8 text_fitting_size; 442 u16 graphics_fitting_offset; 443 u8 graphics_fitting_size; 444 } __packed; 445 446 struct vch_bdb_22 { 447 struct aimdb_block aimdb_block; 448 struct vch_panel_data panels[16]; 449 } __packed; 450 451 struct bdb_sdvo_lvds_options { 452 u8 panel_backlight; 453 u8 h40_set_panel_type; 454 u8 panel_type; 455 u8 ssc_clk_freq; 456 u16 als_low_trip; 457 u16 als_high_trip; 458 u8 sclalarcoeff_tab_row_num; 459 u8 sclalarcoeff_tab_row_size; 460 u8 coefficient[8]; 461 u8 panel_misc_bits_1; 462 u8 panel_misc_bits_2; 463 u8 panel_misc_bits_3; 464 u8 panel_misc_bits_4; 465 } __packed; 466 467 468 #define BDB_DRIVER_FEATURE_NO_LVDS 0 469 #define BDB_DRIVER_FEATURE_INT_LVDS 1 470 #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 471 #define BDB_DRIVER_FEATURE_EDP 3 472 473 struct bdb_driver_features { 474 u8 boot_dev_algorithm:1; 475 u8 block_display_switch:1; 476 u8 allow_display_switch:1; 477 u8 hotplug_dvo:1; 478 u8 dual_view_zoom:1; 479 u8 int15h_hook:1; 480 u8 sprite_in_clone:1; 481 u8 primary_lfp_id:1; 482 483 u16 boot_mode_x; 484 u16 boot_mode_y; 485 u8 boot_mode_bpp; 486 u8 boot_mode_refresh; 487 488 u16 enable_lfp_primary:1; 489 u16 selective_mode_pruning:1; 490 u16 dual_frequency:1; 491 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ 492 u16 nt_clone_support:1; 493 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ 494 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ 495 u16 cui_aspect_scaling:1; 496 u16 preserve_aspect_ratio:1; 497 u16 sdvo_device_power_down:1; 498 u16 crt_hotplug:1; 499 u16 lvds_config:2; 500 u16 tv_hotplug:1; 501 u16 hdmi_config:2; 502 503 u8 static_display:1; 504 u8 reserved2:7; 505 u16 legacy_crt_max_x; 506 u16 legacy_crt_max_y; 507 u8 legacy_crt_max_refresh; 508 509 u8 hdmi_termination; 510 u8 custom_vbt_version; 511 /* Driver features data block */ 512 u16 rmpm_enabled:1; 513 u16 s2ddt_enabled:1; 514 u16 dpst_enabled:1; 515 u16 bltclt_enabled:1; 516 u16 adb_enabled:1; 517 u16 drrs_enabled:1; 518 u16 grs_enabled:1; 519 u16 gpmt_enabled:1; 520 u16 tbt_enabled:1; 521 u16 psr_enabled:1; 522 u16 ips_enabled:1; 523 u16 reserved3:4; 524 u16 pc_feature_valid:1; 525 } __packed; 526 527 #define EDP_18BPP 0 528 #define EDP_24BPP 1 529 #define EDP_30BPP 2 530 #define EDP_RATE_1_62 0 531 #define EDP_RATE_2_7 1 532 #define EDP_LANE_1 0 533 #define EDP_LANE_2 1 534 #define EDP_LANE_4 3 535 #define EDP_PREEMPHASIS_NONE 0 536 #define EDP_PREEMPHASIS_3_5dB 1 537 #define EDP_PREEMPHASIS_6dB 2 538 #define EDP_PREEMPHASIS_9_5dB 3 539 #define EDP_VSWING_0_4V 0 540 #define EDP_VSWING_0_6V 1 541 #define EDP_VSWING_0_8V 2 542 #define EDP_VSWING_1_2V 3 543 544 struct edp_power_seq { 545 u16 t1_t3; 546 u16 t8; 547 u16 t9; 548 u16 t10; 549 u16 t11_t12; 550 } __packed; 551 552 struct edp_link_params { 553 u8 rate:4; 554 u8 lanes:4; 555 u8 preemphasis:4; 556 u8 vswing:4; 557 } __packed; 558 559 struct bdb_edp { 560 struct edp_power_seq power_seqs[16]; 561 u32 color_depth; 562 struct edp_link_params link_params[16]; 563 u32 sdrrs_msa_timing_delay; 564 565 /* ith bit indicates enabled/disabled for (i+1)th panel */ 566 u16 edp_s3d_feature; 567 u16 edp_t3_optimization; 568 u64 edp_vswing_preemph; /* v173 */ 569 } __packed; 570 571 struct psr_table { 572 /* Feature bits */ 573 u8 full_link:1; 574 u8 require_aux_to_wakeup:1; 575 u8 feature_bits_rsvd:6; 576 577 /* Wait times */ 578 u8 idle_frames:4; 579 u8 lines_to_wait:3; 580 u8 wait_times_rsvd:1; 581 582 /* TP wake up time in multiple of 100 */ 583 u16 tp1_wakeup_time; 584 u16 tp2_tp3_wakeup_time; 585 } __packed; 586 587 struct bdb_psr { 588 struct psr_table psr_table[16]; 589 } __packed; 590 591 int intel_parse_bios(struct drm_device *dev); 592 593 /* 594 * Driver<->VBIOS interaction occurs through scratch bits in 595 * GR18 & SWF*. 596 */ 597 598 /* GR18 bits are set on display switch and hotkey events */ 599 #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ 600 #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ 601 #define GR18_HK_NONE (0x0<<3) 602 #define GR18_HK_LFP_STRETCH (0x1<<3) 603 #define GR18_HK_TOGGLE_DISP (0x2<<3) 604 #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ 605 #define GR18_HK_POPUP_DISABLED (0x6<<3) 606 #define GR18_HK_POPUP_ENABLED (0x7<<3) 607 #define GR18_HK_PFIT (0x8<<3) 608 #define GR18_HK_APM_CHANGE (0xa<<3) 609 #define GR18_HK_MULTIPLE (0xc<<3) 610 #define GR18_USER_INT_EN (1<<2) 611 #define GR18_A0000_FLUSH_EN (1<<1) 612 #define GR18_SMM_EN (1<<0) 613 614 /* Set by driver, cleared by VBIOS */ 615 #define SWF00_YRES_SHIFT 16 616 #define SWF00_XRES_SHIFT 0 617 #define SWF00_RES_MASK 0xffff 618 619 /* Set by VBIOS at boot time and driver at runtime */ 620 #define SWF01_TV2_FORMAT_SHIFT 8 621 #define SWF01_TV1_FORMAT_SHIFT 0 622 #define SWF01_TV_FORMAT_MASK 0xffff 623 624 #define SWF10_VBIOS_BLC_I2C_EN (1<<29) 625 #define SWF10_GTT_OVERRIDE_EN (1<<28) 626 #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ 627 #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) 628 #define SWF10_OLD_TOGGLE 0x0 629 #define SWF10_TOGGLE_LIST_1 0x1 630 #define SWF10_TOGGLE_LIST_2 0x2 631 #define SWF10_TOGGLE_LIST_3 0x3 632 #define SWF10_TOGGLE_LIST_4 0x4 633 #define SWF10_PANNING_EN (1<<23) 634 #define SWF10_DRIVER_LOADED (1<<22) 635 #define SWF10_EXTENDED_DESKTOP (1<<21) 636 #define SWF10_EXCLUSIVE_MODE (1<<20) 637 #define SWF10_OVERLAY_EN (1<<19) 638 #define SWF10_PLANEB_HOLDOFF (1<<18) 639 #define SWF10_PLANEA_HOLDOFF (1<<17) 640 #define SWF10_VGA_HOLDOFF (1<<16) 641 #define SWF10_ACTIVE_DISP_MASK 0xffff 642 #define SWF10_PIPEB_LFP2 (1<<15) 643 #define SWF10_PIPEB_EFP2 (1<<14) 644 #define SWF10_PIPEB_TV2 (1<<13) 645 #define SWF10_PIPEB_CRT2 (1<<12) 646 #define SWF10_PIPEB_LFP (1<<11) 647 #define SWF10_PIPEB_EFP (1<<10) 648 #define SWF10_PIPEB_TV (1<<9) 649 #define SWF10_PIPEB_CRT (1<<8) 650 #define SWF10_PIPEA_LFP2 (1<<7) 651 #define SWF10_PIPEA_EFP2 (1<<6) 652 #define SWF10_PIPEA_TV2 (1<<5) 653 #define SWF10_PIPEA_CRT2 (1<<4) 654 #define SWF10_PIPEA_LFP (1<<3) 655 #define SWF10_PIPEA_EFP (1<<2) 656 #define SWF10_PIPEA_TV (1<<1) 657 #define SWF10_PIPEA_CRT (1<<0) 658 659 #define SWF11_MEMORY_SIZE_SHIFT 16 660 #define SWF11_SV_TEST_EN (1<<15) 661 #define SWF11_IS_AGP (1<<14) 662 #define SWF11_DISPLAY_HOLDOFF (1<<13) 663 #define SWF11_DPMS_REDUCED (1<<12) 664 #define SWF11_IS_VBE_MODE (1<<11) 665 #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ 666 #define SWF11_DPMS_MASK 0x07 667 #define SWF11_DPMS_OFF (1<<2) 668 #define SWF11_DPMS_SUSPEND (1<<1) 669 #define SWF11_DPMS_STANDBY (1<<0) 670 #define SWF11_DPMS_ON 0 671 672 #define SWF14_GFX_PFIT_EN (1<<31) 673 #define SWF14_TEXT_PFIT_EN (1<<30) 674 #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ 675 #define SWF14_POPUP_EN (1<<28) 676 #define SWF14_DISPLAY_HOLDOFF (1<<27) 677 #define SWF14_DISP_DETECT_EN (1<<26) 678 #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ 679 #define SWF14_DRIVER_STATUS (1<<24) 680 #define SWF14_OS_TYPE_WIN9X (1<<23) 681 #define SWF14_OS_TYPE_WINNT (1<<22) 682 /* 21:19 rsvd */ 683 #define SWF14_PM_TYPE_MASK 0x00070000 684 #define SWF14_PM_ACPI_VIDEO (0x4 << 16) 685 #define SWF14_PM_ACPI (0x3 << 16) 686 #define SWF14_PM_APM_12 (0x2 << 16) 687 #define SWF14_PM_APM_11 (0x1 << 16) 688 #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ 689 /* if GR18 indicates a display switch */ 690 #define SWF14_DS_PIPEB_LFP2_EN (1<<15) 691 #define SWF14_DS_PIPEB_EFP2_EN (1<<14) 692 #define SWF14_DS_PIPEB_TV2_EN (1<<13) 693 #define SWF14_DS_PIPEB_CRT2_EN (1<<12) 694 #define SWF14_DS_PIPEB_LFP_EN (1<<11) 695 #define SWF14_DS_PIPEB_EFP_EN (1<<10) 696 #define SWF14_DS_PIPEB_TV_EN (1<<9) 697 #define SWF14_DS_PIPEB_CRT_EN (1<<8) 698 #define SWF14_DS_PIPEA_LFP2_EN (1<<7) 699 #define SWF14_DS_PIPEA_EFP2_EN (1<<6) 700 #define SWF14_DS_PIPEA_TV2_EN (1<<5) 701 #define SWF14_DS_PIPEA_CRT2_EN (1<<4) 702 #define SWF14_DS_PIPEA_LFP_EN (1<<3) 703 #define SWF14_DS_PIPEA_EFP_EN (1<<2) 704 #define SWF14_DS_PIPEA_TV_EN (1<<1) 705 #define SWF14_DS_PIPEA_CRT_EN (1<<0) 706 /* if GR18 indicates a panel fitting request */ 707 #define SWF14_PFIT_EN (1<<0) /* 0 means disable */ 708 /* if GR18 indicates an APM change request */ 709 #define SWF14_APM_HIBERNATE 0x4 710 #define SWF14_APM_SUSPEND 0x3 711 #define SWF14_APM_STANDBY 0x1 712 #define SWF14_APM_RESTORE 0x0 713 714 /* Add the device class for LFP, TV, HDMI */ 715 #define DEVICE_TYPE_INT_LFP 0x1022 716 #define DEVICE_TYPE_INT_TV 0x1009 717 #define DEVICE_TYPE_HDMI 0x60D2 718 #define DEVICE_TYPE_DP 0x68C6 719 #define DEVICE_TYPE_eDP 0x78C6 720 721 #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) 722 #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) 723 #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) 724 #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) 725 #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) 726 #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) 727 #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) 728 #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) 729 #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) 730 #define DEVICE_TYPE_LVDS_SINGALING (1 << 5) 731 #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) 732 #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) 733 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) 734 #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) 735 #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) 736 737 /* 738 * Bits we care about when checking for DEVICE_TYPE_eDP 739 * Depending on the system, the other bits may or may not 740 * be set for eDP outputs. 741 */ 742 #define DEVICE_TYPE_eDP_BITS \ 743 (DEVICE_TYPE_INTERNAL_CONNECTOR | \ 744 DEVICE_TYPE_MIPI_OUTPUT | \ 745 DEVICE_TYPE_COMPOSITE_OUTPUT | \ 746 DEVICE_TYPE_DUAL_CHANNEL | \ 747 DEVICE_TYPE_LVDS_SINGALING | \ 748 DEVICE_TYPE_TMDS_DVI_SIGNALING | \ 749 DEVICE_TYPE_VIDEO_SIGNALING | \ 750 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ 751 DEVICE_TYPE_ANALOG_OUTPUT) 752 753 /* define the DVO port for HDMI output type */ 754 #define DVO_B 1 755 #define DVO_C 2 756 #define DVO_D 3 757 758 /* Possible values for the "DVO Port" field for versions >= 155: */ 759 #define DVO_PORT_HDMIA 0 760 #define DVO_PORT_HDMIB 1 761 #define DVO_PORT_HDMIC 2 762 #define DVO_PORT_HDMID 3 763 #define DVO_PORT_LVDS 4 764 #define DVO_PORT_TV 5 765 #define DVO_PORT_CRT 6 766 #define DVO_PORT_DPB 7 767 #define DVO_PORT_DPC 8 768 #define DVO_PORT_DPD 9 769 #define DVO_PORT_DPA 10 770 #define DVO_PORT_DPE 11 771 #define DVO_PORT_HDMIE 12 772 #define DVO_PORT_MIPIA 21 773 #define DVO_PORT_MIPIB 22 774 #define DVO_PORT_MIPIC 23 775 #define DVO_PORT_MIPID 24 776 777 /* Block 52 contains MIPI Panel info 778 * 6 such enteries will there. Index into correct 779 * entery is based on the panel_index in #40 LFP 780 */ 781 #define MAX_MIPI_CONFIGURATIONS 6 782 783 #define MIPI_DSI_UNDEFINED_PANEL_ID 0 784 #define MIPI_DSI_GENERIC_PANEL_ID 1 785 786 /* 787 * PMIC vs SoC Backlight support specified in pwm_blc 788 * field in mipi_config block below. 789 */ 790 #define PPS_BLC_PMIC 0 791 #define PPS_BLC_SOC 1 792 793 struct mipi_config { 794 u16 panel_id; 795 796 /* General Params */ 797 u32 enable_dithering:1; 798 u32 rsvd1:1; 799 u32 is_bridge:1; 800 801 u32 panel_arch_type:2; 802 u32 is_cmd_mode:1; 803 804 #define NON_BURST_SYNC_PULSE 0x1 805 #define NON_BURST_SYNC_EVENTS 0x2 806 #define BURST_MODE 0x3 807 u32 video_transfer_mode:2; 808 809 u32 cabc_supported:1; 810 u32 pwm_blc:1; 811 812 /* Bit 13:10 */ 813 #define PIXEL_FORMAT_RGB565 0x1 814 #define PIXEL_FORMAT_RGB666 0x2 815 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3 816 #define PIXEL_FORMAT_RGB888 0x4 817 u32 videomode_color_format:4; 818 819 /* Bit 15:14 */ 820 #define ENABLE_ROTATION_0 0x0 821 #define ENABLE_ROTATION_90 0x1 822 #define ENABLE_ROTATION_180 0x2 823 #define ENABLE_ROTATION_270 0x3 824 u32 rotation:2; 825 u32 bta_enabled:1; 826 u32 rsvd2:15; 827 828 /* 2 byte Port Description */ 829 #define DUAL_LINK_NOT_SUPPORTED 0 830 #define DUAL_LINK_FRONT_BACK 1 831 #define DUAL_LINK_PIXEL_ALT 2 832 u16 dual_link:2; 833 u16 lane_cnt:2; 834 u16 pixel_overlap:3; 835 u16 rsvd3:9; 836 837 u16 rsvd4; 838 839 u8 rsvd5; 840 u32 target_burst_mode_freq; 841 u32 dsi_ddr_clk; 842 u32 bridge_ref_clk; 843 844 #define BYTE_CLK_SEL_20MHZ 0 845 #define BYTE_CLK_SEL_10MHZ 1 846 #define BYTE_CLK_SEL_5MHZ 2 847 u8 byte_clk_sel:2; 848 849 u8 rsvd6:6; 850 851 /* DPHY Flags */ 852 u16 dphy_param_valid:1; 853 u16 eot_pkt_disabled:1; 854 u16 enable_clk_stop:1; 855 u16 rsvd7:13; 856 857 u32 hs_tx_timeout; 858 u32 lp_rx_timeout; 859 u32 turn_around_timeout; 860 u32 device_reset_timer; 861 u32 master_init_timer; 862 u32 dbi_bw_timer; 863 u32 lp_byte_clk_val; 864 865 /* 4 byte Dphy Params */ 866 u32 prepare_cnt:6; 867 u32 rsvd8:2; 868 u32 clk_zero_cnt:8; 869 u32 trail_cnt:5; 870 u32 rsvd9:3; 871 u32 exit_zero_cnt:6; 872 u32 rsvd10:2; 873 874 u32 clk_lane_switch_cnt; 875 u32 hl_switch_cnt; 876 877 u32 rsvd11[6]; 878 879 /* timings based on dphy spec */ 880 u8 tclk_miss; 881 u8 tclk_post; 882 u8 rsvd12; 883 u8 tclk_pre; 884 u8 tclk_prepare; 885 u8 tclk_settle; 886 u8 tclk_term_enable; 887 u8 tclk_trail; 888 u16 tclk_prepare_clkzero; 889 u8 rsvd13; 890 u8 td_term_enable; 891 u8 teot; 892 u8 ths_exit; 893 u8 ths_prepare; 894 u16 ths_prepare_hszero; 895 u8 rsvd14; 896 u8 ths_settle; 897 u8 ths_skip; 898 u8 ths_trail; 899 u8 tinit; 900 u8 tlpx; 901 u8 rsvd15[3]; 902 903 /* GPIOs */ 904 u8 panel_enable; 905 u8 bl_enable; 906 u8 pwm_enable; 907 u8 reset_r_n; 908 u8 pwr_down_r; 909 u8 stdby_r_n; 910 911 } __packed; 912 913 /* Block 52 contains MIPI configuration block 914 * 6 * bdb_mipi_config, followed by 6 pps data 915 * block below 916 * 917 * all delays has a unit of 100us 918 */ 919 struct mipi_pps_data { 920 u16 panel_on_delay; 921 u16 bl_enable_delay; 922 u16 bl_disable_delay; 923 u16 panel_off_delay; 924 u16 panel_power_cycle_delay; 925 } __packed; 926 927 struct bdb_mipi_config { 928 struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; 929 struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; 930 } __packed; 931 932 /* Block 53 contains MIPI sequences as needed by the panel 933 * for enabling it. This block can be variable in size and 934 * can be maximum of 6 blocks 935 */ 936 struct bdb_mipi_sequence { 937 u8 version; 938 u8 data[0]; 939 } __packed; 940 941 /* MIPI Sequnece Block definitions */ 942 enum mipi_seq { 943 MIPI_SEQ_UNDEFINED = 0, 944 MIPI_SEQ_ASSERT_RESET, 945 MIPI_SEQ_INIT_OTP, 946 MIPI_SEQ_DISPLAY_ON, 947 MIPI_SEQ_DISPLAY_OFF, 948 MIPI_SEQ_DEASSERT_RESET, 949 MIPI_SEQ_MAX 950 }; 951 952 enum mipi_seq_element { 953 MIPI_SEQ_ELEM_UNDEFINED = 0, 954 MIPI_SEQ_ELEM_SEND_PKT, 955 MIPI_SEQ_ELEM_DELAY, 956 MIPI_SEQ_ELEM_GPIO, 957 MIPI_SEQ_ELEM_STATUS, 958 MIPI_SEQ_ELEM_MAX 959 }; 960 961 enum mipi_gpio_pin_index { 962 MIPI_GPIO_UNDEFINED = 0, 963 MIPI_GPIO_PANEL_ENABLE, 964 MIPI_GPIO_BL_ENABLE, 965 MIPI_GPIO_PWM_ENABLE, 966 MIPI_GPIO_RESET_N, 967 MIPI_GPIO_PWR_DOWN_R, 968 MIPI_GPIO_STDBY_RST_N, 969 MIPI_GPIO_MAX 970 }; 971 972 #endif /* _I830_BIOS_H_ */ 973