1 /**********************************************************************
2 * Author: Cavium, Inc.
3 *
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
6 *
7 * Copyright (c) 2003-2015 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * This file may also be available under a different license from Cavium.
20 * Contact Cavium, Inc. for more information
21 **********************************************************************/
22
23 /*! \file octeon_device.h
24 * \brief Host Driver: This file defines the octeon device structure.
25 */
26
27 #ifndef _OCTEON_DEVICE_H_
28 #define _OCTEON_DEVICE_H_
29
30 /** PCI VendorId Device Id */
31 #define OCTEON_CN68XX_PCIID 0x91177d
32 #define OCTEON_CN66XX_PCIID 0x92177d
33
34 /** Driver identifies chips by these Ids, created by clubbing together
35 * DeviceId+RevisionId; Where Revision Id is not used to distinguish
36 * between chips, a value of 0 is used for revision id.
37 */
38 #define OCTEON_CN68XX 0x0091
39 #define OCTEON_CN66XX 0x0092
40
41 /** Endian-swap modes supported by Octeon. */
42 enum octeon_pci_swap_mode {
43 OCTEON_PCI_PASSTHROUGH = 0,
44 OCTEON_PCI_64BIT_SWAP = 1,
45 OCTEON_PCI_32BIT_BYTE_SWAP = 2,
46 OCTEON_PCI_32BIT_LW_SWAP = 3
47 };
48
49 /*--------------- PCI BAR1 index registers -------------*/
50
51 /* BAR1 Mask */
52 #define PCI_BAR1_ENABLE_CA 1
53 #define PCI_BAR1_ENDIAN_MODE OCTEON_PCI_64BIT_SWAP
54 #define PCI_BAR1_ENTRY_VALID 1
55 #define PCI_BAR1_MASK ((PCI_BAR1_ENABLE_CA << 3) \
56 | (PCI_BAR1_ENDIAN_MODE << 1) \
57 | PCI_BAR1_ENTRY_VALID)
58
59 /** Octeon Device state.
60 * Each octeon device goes through each of these states
61 * as it is initialized.
62 */
63 #define OCT_DEV_BEGIN_STATE 0x0
64 #define OCT_DEV_PCI_MAP_DONE 0x1
65 #define OCT_DEV_DISPATCH_INIT_DONE 0x2
66 #define OCT_DEV_INSTR_QUEUE_INIT_DONE 0x3
67 #define OCT_DEV_SC_BUFF_POOL_INIT_DONE 0x4
68 #define OCT_DEV_RESP_LIST_INIT_DONE 0x5
69 #define OCT_DEV_DROQ_INIT_DONE 0x6
70 #define OCT_DEV_IO_QUEUES_DONE 0x7
71 #define OCT_DEV_CONSOLE_INIT_DONE 0x8
72 #define OCT_DEV_HOST_OK 0x9
73 #define OCT_DEV_CORE_OK 0xa
74 #define OCT_DEV_RUNNING 0xb
75 #define OCT_DEV_IN_RESET 0xc
76 #define OCT_DEV_STATE_INVALID 0xd
77
78 #define OCT_DEV_STATES OCT_DEV_STATE_INVALID
79
80 /** Octeon Device interrupts
81 * These interrupt bits are set in int_status filed of
82 * octeon_device structure
83 */
84 #define OCT_DEV_INTR_DMA0_FORCE 0x01
85 #define OCT_DEV_INTR_DMA1_FORCE 0x02
86 #define OCT_DEV_INTR_PKT_DATA 0x04
87
88 #define LIO_RESET_SECS (3)
89
90 /*---------------------------DISPATCH LIST-------------------------------*/
91
92 /** The dispatch list entry.
93 * The driver keeps a record of functions registered for each
94 * response header opcode in this structure. Since the opcode is
95 * hashed to index into the driver's list, more than one opcode
96 * can hash to the same entry, in which case the list field points
97 * to a linked list with the other entries.
98 */
99 struct octeon_dispatch {
100 /** List head for this entry */
101 struct list_head list;
102
103 /** The opcode for which the dispatch function & arg should be used */
104 u16 opcode;
105
106 /** The function to be called for a packet received by the driver */
107 octeon_dispatch_fn_t dispatch_fn;
108
109 /* The application specified argument to be passed to the above
110 * function along with the received packet
111 */
112 void *arg;
113 };
114
115 /** The dispatch list structure. */
116 struct octeon_dispatch_list {
117 /** access to dispatch list must be atomic */
118 spinlock_t lock;
119
120 /** Count of dispatch functions currently registered */
121 u32 count;
122
123 /** The list of dispatch functions */
124 struct octeon_dispatch *dlist;
125 };
126
127 /*----------------------- THE OCTEON DEVICE ---------------------------*/
128
129 #define OCT_MEM_REGIONS 3
130 /** PCI address space mapping information.
131 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of
132 * Octeon gets mapped to different physical address spaces in
133 * the kernel.
134 */
135 struct octeon_mmio {
136 /** PCI address to which the BAR is mapped. */
137 u64 start;
138
139 /** Length of this PCI address space. */
140 u32 len;
141
142 /** Length that has been mapped to phys. address space. */
143 u32 mapped_len;
144
145 /** The physical address to which the PCI address space is mapped. */
146 u8 __iomem *hw_addr;
147
148 /** Flag indicating the mapping was successful. */
149 u32 done;
150 };
151
152 #define MAX_OCTEON_MAPS 32
153
154 struct octeon_io_enable {
155 u32 iq;
156 u32 oq;
157 u32 iq64B;
158 };
159
160 struct octeon_reg_list {
161 u32 __iomem *pci_win_wr_addr_hi;
162 u32 __iomem *pci_win_wr_addr_lo;
163 u64 __iomem *pci_win_wr_addr;
164
165 u32 __iomem *pci_win_rd_addr_hi;
166 u32 __iomem *pci_win_rd_addr_lo;
167 u64 __iomem *pci_win_rd_addr;
168
169 u32 __iomem *pci_win_wr_data_hi;
170 u32 __iomem *pci_win_wr_data_lo;
171 u64 __iomem *pci_win_wr_data;
172
173 u32 __iomem *pci_win_rd_data_hi;
174 u32 __iomem *pci_win_rd_data_lo;
175 u64 __iomem *pci_win_rd_data;
176 };
177
178 #define OCTEON_CONSOLE_MAX_READ_BYTES 512
179 struct octeon_console {
180 u32 active;
181 u32 waiting;
182 u64 addr;
183 u32 buffer_size;
184 u64 input_base_addr;
185 u64 output_base_addr;
186 char leftover[OCTEON_CONSOLE_MAX_READ_BYTES];
187 };
188
189 struct octeon_board_info {
190 char name[OCT_BOARD_NAME];
191 char serial_number[OCT_SERIAL_LEN];
192 u64 major;
193 u64 minor;
194 };
195
196 struct octeon_fn_list {
197 void (*setup_iq_regs)(struct octeon_device *, u32);
198 void (*setup_oq_regs)(struct octeon_device *, u32);
199
200 irqreturn_t (*process_interrupt_regs)(void *);
201 int (*soft_reset)(struct octeon_device *);
202 int (*setup_device_regs)(struct octeon_device *);
203 void (*reinit_regs)(struct octeon_device *);
204 void (*bar1_idx_setup)(struct octeon_device *, u64, u32, int);
205 void (*bar1_idx_write)(struct octeon_device *, u32, u32);
206 u32 (*bar1_idx_read)(struct octeon_device *, u32);
207 u32 (*update_iq_read_idx)(struct octeon_device *,
208 struct octeon_instr_queue *);
209
210 void (*enable_oq_pkt_time_intr)(struct octeon_device *, u32);
211 void (*disable_oq_pkt_time_intr)(struct octeon_device *, u32);
212
213 void (*enable_interrupt)(void *);
214 void (*disable_interrupt)(void *);
215
216 void (*enable_io_queues)(struct octeon_device *);
217 void (*disable_io_queues)(struct octeon_device *);
218 };
219
220 /* Must be multiple of 8, changing breaks ABI */
221 #define CVMX_BOOTMEM_NAME_LEN 128
222
223 /* Structure for named memory blocks
224 * Number of descriptors
225 * available can be changed without affecting compatiblity,
226 * but name length changes require a bump in the bootmem
227 * descriptor version
228 * Note: This structure must be naturally 64 bit aligned, as a single
229 * memory image will be used by both 32 and 64 bit programs.
230 */
231 struct cvmx_bootmem_named_block_desc {
232 /** Base address of named block */
233 u64 base_addr;
234
235 /** Size actually allocated for named block */
236 u64 size;
237
238 /** name of named block */
239 char name[CVMX_BOOTMEM_NAME_LEN];
240 };
241
242 struct oct_fw_info {
243 u32 max_nic_ports; /** max nic ports for the device */
244 u32 num_gmx_ports; /** num gmx ports */
245 u64 app_cap_flags; /** firmware cap flags */
246
247 /** The core application is running in this mode.
248 * See octeon-drv-opcodes.h for values.
249 */
250 u32 app_mode;
251 char liquidio_firmware_version[32];
252 };
253
254 /* wrappers around work structs */
255 struct cavium_wk {
256 struct delayed_work work;
257 void *ctxptr;
258 size_t ctxul;
259 };
260
261 struct cavium_wq {
262 struct workqueue_struct *wq;
263 struct cavium_wk wk;
264 };
265
266 struct octdev_props {
267 /* Each interface in the Octeon device has a network
268 * device pointer (used for OS specific calls).
269 */
270 struct net_device *netdev;
271 };
272
273 /** The Octeon device.
274 * Each Octeon device has this structure to represent all its
275 * components.
276 */
277 struct octeon_device {
278 /** Lock for PCI window configuration accesses */
279 spinlock_t pci_win_lock;
280
281 /** Lock for memory accesses */
282 spinlock_t mem_access_lock;
283
284 /** PCI device pointer */
285 struct pci_dev *pci_dev;
286
287 /** Chip specific information. */
288 void *chip;
289
290 /** Number of interfaces detected in this octeon device. */
291 u32 ifcount;
292
293 struct octdev_props props[MAX_OCTEON_LINKS];
294
295 /** Octeon Chip type. */
296 u16 chip_id;
297 u16 rev_id;
298
299 /** This device's id - set by the driver. */
300 u32 octeon_id;
301
302 /** This device's PCIe port used for traffic. */
303 u16 pcie_port;
304
305 u16 flags;
306 #define LIO_FLAG_MSI_ENABLED (u32)(1 << 1)
307 #define LIO_FLAG_MSIX_ENABLED (u32)(1 << 2)
308
309 /** The state of this device */
310 atomic_t status;
311
312 /** memory mapped io range */
313 struct octeon_mmio mmio[OCT_MEM_REGIONS];
314
315 struct octeon_reg_list reg_list;
316
317 struct octeon_fn_list fn_list;
318
319 struct octeon_board_info boardinfo;
320
321 u32 num_iqs;
322
323 /* The pool containing pre allocated buffers used for soft commands */
324 struct octeon_sc_buffer_pool sc_buf_pool;
325
326 /** The input instruction queues */
327 struct octeon_instr_queue *instr_queue[MAX_OCTEON_INSTR_QUEUES];
328
329 /** The doubly-linked list of instruction response */
330 struct octeon_response_list response_list[MAX_RESPONSE_LISTS];
331
332 u32 num_oqs;
333
334 /** The DROQ output queues */
335 struct octeon_droq *droq[MAX_OCTEON_OUTPUT_QUEUES];
336
337 struct octeon_io_enable io_qmask;
338
339 /** List of dispatch functions */
340 struct octeon_dispatch_list dispatch;
341
342 /* Interrupt Moderation */
343 struct oct_intrmod_cfg intrmod;
344
345 u32 int_status;
346
347 u64 droq_intr;
348
349 /** Physical location of the cvmx_bootmem_desc_t in octeon memory */
350 u64 bootmem_desc_addr;
351
352 /** Placeholder memory for named blocks.
353 * Assumes single-threaded access
354 */
355 struct cvmx_bootmem_named_block_desc bootmem_named_block_desc;
356
357 /** Address of consoles descriptor */
358 u64 console_desc_addr;
359
360 /** Number of consoles available. 0 means they are inaccessible */
361 u32 num_consoles;
362
363 /* Console caches */
364 struct octeon_console console[MAX_OCTEON_MAPS];
365
366 /* Coprocessor clock rate. */
367 u64 coproc_clock_rate;
368
369 /** The core application is running in this mode. See liquidio_common.h
370 * for values.
371 */
372 u32 app_mode;
373
374 struct oct_fw_info fw_info;
375
376 /** The name given to this device. */
377 char device_name[32];
378
379 /** Application Context */
380 void *app_ctx;
381
382 struct cavium_wq dma_comp_wq;
383
384 struct cavium_wq check_db_wq[MAX_OCTEON_INSTR_QUEUES];
385
386 struct cavium_wk nic_poll_work;
387
388 struct cavium_wk console_poll_work[MAX_OCTEON_MAPS];
389
390 void *priv;
391 };
392
393 #define OCTEON_CN6XXX(oct) ((oct->chip_id == OCTEON_CN66XX) || \
394 (oct->chip_id == OCTEON_CN68XX))
395 #define CHIP_FIELD(oct, TYPE, field) \
396 (((struct octeon_ ## TYPE *)(oct->chip))->field)
397
398 struct oct_intrmod_cmd {
399 struct octeon_device *oct_dev;
400 struct octeon_soft_command *sc;
401 struct oct_intrmod_cfg *cfg;
402 };
403
404 /*------------------ Function Prototypes ----------------------*/
405
406 /** Initialize device list memory */
407 void octeon_init_device_list(int conf_type);
408
409 /** Free memory for Input and Output queue structures for a octeon device */
410 void octeon_free_device_mem(struct octeon_device *);
411
412 /* Look up a free entry in the octeon_device table and allocate resources
413 * for the octeon_device structure for an octeon device. Called at init
414 * time.
415 */
416 struct octeon_device *octeon_allocate_device(u32 pci_id,
417 u32 priv_size);
418
419 /** Initialize the driver's dispatch list which is a mix of a hash table
420 * and a linked list. This is done at driver load time.
421 * @param octeon_dev - pointer to the octeon device structure.
422 * @return 0 on success, else -ve error value
423 */
424 int octeon_init_dispatch_list(struct octeon_device *octeon_dev);
425
426 /** Delete the driver's dispatch list and all registered entries.
427 * This is done at driver unload time.
428 * @param octeon_dev - pointer to the octeon device structure.
429 */
430 void octeon_delete_dispatch_list(struct octeon_device *octeon_dev);
431
432 /** Initialize the core device fields with the info returned by the FW.
433 * @param recv_info - Receive info structure
434 * @param buf - Receive buffer
435 */
436 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf);
437
438 /** Gets the dispatch function registered to receive packets with a
439 * given opcode/subcode.
440 * @param octeon_dev - the octeon device pointer.
441 * @param opcode - the opcode for which the dispatch function
442 * is to checked.
443 * @param subcode - the subcode for which the dispatch function
444 * is to checked.
445 *
446 * @return Success: octeon_dispatch_fn_t (dispatch function pointer)
447 * @return Failure: NULL
448 *
449 * Looks up the dispatch list to get the dispatch function for a
450 * given opcode.
451 */
452 octeon_dispatch_fn_t
453 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode,
454 u16 subcode);
455
456 /** Get the octeon device pointer.
457 * @param octeon_id - The id for which the octeon device pointer is required.
458 * @return Success: Octeon device pointer.
459 * @return Failure: NULL.
460 */
461 struct octeon_device *lio_get_device(u32 octeon_id);
462
463 /** Get the octeon id assigned to the octeon device passed as argument.
464 * This function is exported to other modules.
465 * @param dev - octeon device pointer passed as a void *.
466 * @return octeon device id
467 */
468 int lio_get_device_id(void *dev);
469
OCTEON_MAJOR_REV(struct octeon_device * oct)470 static inline u16 OCTEON_MAJOR_REV(struct octeon_device *oct)
471 {
472 u16 rev = (oct->rev_id & 0xC) >> 2;
473
474 return (rev == 0) ? 1 : rev;
475 }
476
OCTEON_MINOR_REV(struct octeon_device * oct)477 static inline u16 OCTEON_MINOR_REV(struct octeon_device *oct)
478 {
479 return oct->rev_id & 0x3;
480 }
481
482 /** Read windowed register.
483 * @param oct - pointer to the Octeon device.
484 * @param addr - Address of the register to read.
485 *
486 * This routine is called to read from the indirectly accessed
487 * Octeon registers that are visible through a PCI BAR0 mapped window
488 * register.
489 * @return - 64 bit value read from the register.
490 */
491
492 u64 lio_pci_readq(struct octeon_device *oct, u64 addr);
493
494 /** Write windowed register.
495 * @param oct - pointer to the Octeon device.
496 * @param val - Value to write
497 * @param addr - Address of the register to write
498 *
499 * This routine is called to write to the indirectly accessed
500 * Octeon registers that are visible through a PCI BAR0 mapped window
501 * register.
502 * @return Nothing.
503 */
504 void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr);
505
506 /* Routines for reading and writing CSRs */
507 #define octeon_write_csr(oct_dev, reg_off, value) \
508 writel(value, oct_dev->mmio[0].hw_addr + reg_off)
509
510 #define octeon_write_csr64(oct_dev, reg_off, val64) \
511 writeq(val64, oct_dev->mmio[0].hw_addr + reg_off)
512
513 #define octeon_read_csr(oct_dev, reg_off) \
514 readl(oct_dev->mmio[0].hw_addr + reg_off)
515
516 #define octeon_read_csr64(oct_dev, reg_off) \
517 readq(oct_dev->mmio[0].hw_addr + reg_off)
518
519 /**
520 * Checks if memory access is okay
521 *
522 * @param oct which octeon to send to
523 * @return Zero on success, negative on failure.
524 */
525 int octeon_mem_access_ok(struct octeon_device *oct);
526
527 /**
528 * Waits for DDR initialization.
529 *
530 * @param oct which octeon to send to
531 * @param timeout_in_ms pointer to how long to wait until DDR is initialized
532 * in ms.
533 * If contents are 0, it waits until contents are non-zero
534 * before starting to check.
535 * @return Zero on success, negative on failure.
536 */
537 int octeon_wait_for_ddr_init(struct octeon_device *oct,
538 u32 *timeout_in_ms);
539
540 /**
541 * Wait for u-boot to boot and be waiting for a command.
542 *
543 * @param wait_time_hundredths
544 * Maximum time to wait
545 *
546 * @return Zero on success, negative on failure.
547 */
548 int octeon_wait_for_bootloader(struct octeon_device *oct,
549 u32 wait_time_hundredths);
550
551 /**
552 * Initialize console access
553 *
554 * @param oct which octeon initialize
555 * @return Zero on success, negative on failure.
556 */
557 int octeon_init_consoles(struct octeon_device *oct);
558
559 /**
560 * Adds access to a console to the device.
561 *
562 * @param oct which octeon to add to
563 * @param console_num which console
564 * @return Zero on success, negative on failure.
565 */
566 int octeon_add_console(struct octeon_device *oct, u32 console_num);
567
568 /** write or read from a console */
569 int octeon_console_write(struct octeon_device *oct, u32 console_num,
570 char *buffer, u32 write_request_size, u32 flags);
571 int octeon_console_write_avail(struct octeon_device *oct, u32 console_num);
572 int octeon_console_read(struct octeon_device *oct, u32 console_num,
573 char *buffer, u32 buf_size, u32 flags);
574 int octeon_console_read_avail(struct octeon_device *oct, u32 console_num);
575
576 /** Removes all attached consoles. */
577 void octeon_remove_consoles(struct octeon_device *oct);
578
579 /**
580 * Send a string to u-boot on console 0 as a command.
581 *
582 * @param oct which octeon to send to
583 * @param cmd_str String to send
584 * @param wait_hundredths Time to wait for u-boot to accept the command.
585 *
586 * @return Zero on success, negative on failure.
587 */
588 int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str,
589 u32 wait_hundredths);
590
591 /** Parses, validates, and downloads firmware, then boots associated cores.
592 * @param oct which octeon to download firmware to
593 * @param data - The complete firmware file image
594 * @param size - The size of the data
595 *
596 * @return 0 if success.
597 * -EINVAL if file is incompatible or badly formatted.
598 * -ENODEV if no handler was found for the application type or an
599 * invalid octeon id was passed.
600 */
601 int octeon_download_firmware(struct octeon_device *oct, const u8 *data,
602 size_t size);
603
604 char *lio_get_state_string(atomic_t *state_ptr);
605
606 /** Sets up instruction queues for the device
607 * @param oct which octeon to setup
608 *
609 * @return 0 if success. 1 if fails
610 */
611 int octeon_setup_instr_queues(struct octeon_device *oct);
612
613 /** Sets up output queues for the device
614 * @param oct which octeon to setup
615 *
616 * @return 0 if success. 1 if fails
617 */
618 int octeon_setup_output_queues(struct octeon_device *oct);
619
620 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no);
621
622 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no);
623
624 /** Turns off the input and output queues for the device
625 * @param oct which octeon to disable
626 */
627 void octeon_set_io_queues_off(struct octeon_device *oct);
628
629 /** Turns on or off the given output queue for the device
630 * @param oct which octeon to change
631 * @param q_no which queue
632 * @param enable 1 to enable, 0 to disable
633 */
634 void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, u32 enable);
635
636 /** Retrieve the config for the device
637 * @param oct which octeon
638 * @param card_type type of card
639 *
640 * @returns pointer to configuration
641 */
642 void *oct_get_config_info(struct octeon_device *oct, u16 card_type);
643
644 /** Gets the octeon device configuration
645 * @return - pointer to the octeon configuration struture
646 */
647 struct octeon_config *octeon_get_conf(struct octeon_device *oct);
648
649 #endif
650