1 #ifndef __MCB_INTERNAL 2 #define __MCB_INTERNAL 3 4 #include <linux/types.h> 5 6 #define PCI_VENDOR_ID_MEN 0x1a88 7 #define PCI_DEVICE_ID_MEN_CHAMELEON 0x4d45 8 #define CHAMELEON_FILENAME_LEN 12 9 #define CHAMELEONV2_MAGIC 0xabce 10 #define CHAM_HEADER_SIZE 0x200 11 12 enum chameleon_descriptor_type { 13 CHAMELEON_DTYPE_GENERAL = 0x0, 14 CHAMELEON_DTYPE_BRIDGE = 0x1, 15 CHAMELEON_DTYPE_CPU = 0x2, 16 CHAMELEON_DTYPE_BAR = 0x3, 17 CHAMELEON_DTYPE_END = 0xf, 18 }; 19 20 enum chameleon_bus_type { 21 CHAMELEON_BUS_WISHBONE, 22 CHAMELEON_BUS_AVALON, 23 CHAMELEON_BUS_LPC, 24 CHAMELEON_BUS_ISA, 25 }; 26 27 /** 28 * struct chameleon_fpga_header 29 * 30 * @revision: Revison of Chameleon table in FPGA 31 * @model: Chameleon table model ASCII char 32 * @minor: Revision minor 33 * @bus_type: Bus type (usually %CHAMELEON_BUS_WISHBONE) 34 * @magic: Chameleon header magic number (0xabce for version 2) 35 * @reserved: Reserved 36 * @filename: Filename of FPGA bitstream 37 */ 38 struct chameleon_fpga_header { 39 u8 revision; 40 char model; 41 u8 minor; 42 u8 bus_type; 43 u16 magic; 44 u16 reserved; 45 /* This one has no '\0' at the end!!! */ 46 char filename[CHAMELEON_FILENAME_LEN]; 47 } __packed; 48 #define HEADER_MAGIC_OFFSET 0x4 49 50 /** 51 * struct chameleon_gdd - Chameleon General Device Descriptor 52 * 53 * @irq: the position in the FPGA's IRQ controller vector 54 * @rev: the revision of the variant's implementation 55 * @var: the variant of the IP core 56 * @dev: the device the IP core is 57 * @dtype: device descriptor type 58 * @bar: BAR offset that must be added to module offset 59 * @inst: the instance number of the device, 0 is first instance 60 * @group: the group the device belongs to (0 = no group) 61 * @reserved: reserved 62 * @offset: beginning of the address window of desired module 63 * @size: size of the module's address window 64 */ 65 struct chameleon_gdd { 66 __le32 reg1; 67 __le32 reg2; 68 __le32 offset; 69 __le32 size; 70 71 } __packed; 72 73 /* GDD Register 1 fields */ 74 #define GDD_IRQ(x) ((x) & 0x1f) 75 #define GDD_REV(x) (((x) >> 5) & 0x3f) 76 #define GDD_VAR(x) (((x) >> 11) & 0x3f) 77 #define GDD_DEV(x) (((x) >> 18) & 0x3ff) 78 #define GDD_DTY(x) (((x) >> 28) & 0xf) 79 80 /* GDD Register 2 fields */ 81 #define GDD_BAR(x) ((x) & 0x7) 82 #define GDD_INS(x) (((x) >> 3) & 0x3f) 83 #define GDD_GRP(x) (((x) >> 9) & 0x3f) 84 85 /** 86 * struct chameleon_bdd - Chameleon Bridge Device Descriptor 87 * 88 * @irq: the position in the FPGA's IRQ controller vector 89 * @rev: the revision of the variant's implementation 90 * @var: the variant of the IP core 91 * @dev: the device the IP core is 92 * @dtype: device descriptor type 93 * @bar: BAR offset that must be added to module offset 94 * @inst: the instance number of the device, 0 is first instance 95 * @dbar: destination bar from the bus _behind_ the bridge 96 * @chamoff: offset within the BAR of the source bus 97 * @offset: 98 * @size: 99 */ 100 struct chameleon_bdd { 101 unsigned int irq:6; 102 unsigned int rev:6; 103 unsigned int var:6; 104 unsigned int dev:10; 105 unsigned int dtype:4; 106 unsigned int bar:3; 107 unsigned int inst:6; 108 unsigned int dbar:3; 109 unsigned int group:6; 110 unsigned int reserved:14; 111 u32 chamoff; 112 u32 offset; 113 u32 size; 114 } __packed; 115 116 int chameleon_parse_cells(struct mcb_bus *bus, phys_addr_t mapbase, 117 void __iomem *base); 118 119 #endif 120