1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
21 #define _ASM_X86_AMD_IOMMU_TYPES_H
22
23 #include <linux/types.h>
24 #include <linux/mutex.h>
25 #include <linux/list.h>
26 #include <linux/spinlock.h>
27 #include <linux/pci.h>
28 #include <linux/irqreturn.h>
29
30 /*
31 * Maximum number of IOMMUs supported
32 */
33 #define MAX_IOMMUS 32
34
35 /*
36 * some size calculation constants
37 */
38 #define DEV_TABLE_ENTRY_SIZE 32
39 #define ALIAS_TABLE_ENTRY_SIZE 2
40 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
41
42 /* Capability offsets used by the driver */
43 #define MMIO_CAP_HDR_OFFSET 0x00
44 #define MMIO_RANGE_OFFSET 0x0c
45 #define MMIO_MISC_OFFSET 0x10
46
47 /* Masks, shifts and macros to parse the device range capability */
48 #define MMIO_RANGE_LD_MASK 0xff000000
49 #define MMIO_RANGE_FD_MASK 0x00ff0000
50 #define MMIO_RANGE_BUS_MASK 0x0000ff00
51 #define MMIO_RANGE_LD_SHIFT 24
52 #define MMIO_RANGE_FD_SHIFT 16
53 #define MMIO_RANGE_BUS_SHIFT 8
54 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
55 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
56 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
57 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
58
59 /* Flag masks for the AMD IOMMU exclusion range */
60 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
61 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
62
63 /* Used offsets into the MMIO space */
64 #define MMIO_DEV_TABLE_OFFSET 0x0000
65 #define MMIO_CMD_BUF_OFFSET 0x0008
66 #define MMIO_EVT_BUF_OFFSET 0x0010
67 #define MMIO_CONTROL_OFFSET 0x0018
68 #define MMIO_EXCL_BASE_OFFSET 0x0020
69 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
70 #define MMIO_EXT_FEATURES 0x0030
71 #define MMIO_PPR_LOG_OFFSET 0x0038
72 #define MMIO_CMD_HEAD_OFFSET 0x2000
73 #define MMIO_CMD_TAIL_OFFSET 0x2008
74 #define MMIO_EVT_HEAD_OFFSET 0x2010
75 #define MMIO_EVT_TAIL_OFFSET 0x2018
76 #define MMIO_STATUS_OFFSET 0x2020
77 #define MMIO_PPR_HEAD_OFFSET 0x2030
78 #define MMIO_PPR_TAIL_OFFSET 0x2038
79 #define MMIO_CNTR_CONF_OFFSET 0x4000
80 #define MMIO_CNTR_REG_OFFSET 0x40000
81 #define MMIO_REG_END_OFFSET 0x80000
82
83
84
85 /* Extended Feature Bits */
86 #define FEATURE_PREFETCH (1ULL<<0)
87 #define FEATURE_PPR (1ULL<<1)
88 #define FEATURE_X2APIC (1ULL<<2)
89 #define FEATURE_NX (1ULL<<3)
90 #define FEATURE_GT (1ULL<<4)
91 #define FEATURE_IA (1ULL<<6)
92 #define FEATURE_GA (1ULL<<7)
93 #define FEATURE_HE (1ULL<<8)
94 #define FEATURE_PC (1ULL<<9)
95
96 #define FEATURE_PASID_SHIFT 32
97 #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT)
98
99 #define FEATURE_GLXVAL_SHIFT 14
100 #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT)
101
102 /* Note:
103 * The current driver only support 16-bit PASID.
104 * Currently, hardware only implement upto 16-bit PASID
105 * even though the spec says it could have upto 20 bits.
106 */
107 #define PASID_MASK 0x0000ffff
108
109 /* MMIO status bits */
110 #define MMIO_STATUS_EVT_INT_MASK (1 << 1)
111 #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2)
112 #define MMIO_STATUS_PPR_INT_MASK (1 << 6)
113
114 /* event logging constants */
115 #define EVENT_ENTRY_SIZE 0x10
116 #define EVENT_TYPE_SHIFT 28
117 #define EVENT_TYPE_MASK 0xf
118 #define EVENT_TYPE_ILL_DEV 0x1
119 #define EVENT_TYPE_IO_FAULT 0x2
120 #define EVENT_TYPE_DEV_TAB_ERR 0x3
121 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
122 #define EVENT_TYPE_ILL_CMD 0x5
123 #define EVENT_TYPE_CMD_HARD_ERR 0x6
124 #define EVENT_TYPE_IOTLB_INV_TO 0x7
125 #define EVENT_TYPE_INV_DEV_REQ 0x8
126 #define EVENT_DEVID_MASK 0xffff
127 #define EVENT_DEVID_SHIFT 0
128 #define EVENT_DOMID_MASK 0xffff
129 #define EVENT_DOMID_SHIFT 0
130 #define EVENT_FLAGS_MASK 0xfff
131 #define EVENT_FLAGS_SHIFT 0x10
132
133 /* feature control bits */
134 #define CONTROL_IOMMU_EN 0x00ULL
135 #define CONTROL_HT_TUN_EN 0x01ULL
136 #define CONTROL_EVT_LOG_EN 0x02ULL
137 #define CONTROL_EVT_INT_EN 0x03ULL
138 #define CONTROL_COMWAIT_EN 0x04ULL
139 #define CONTROL_INV_TIMEOUT 0x05ULL
140 #define CONTROL_PASSPW_EN 0x08ULL
141 #define CONTROL_RESPASSPW_EN 0x09ULL
142 #define CONTROL_COHERENT_EN 0x0aULL
143 #define CONTROL_ISOC_EN 0x0bULL
144 #define CONTROL_CMDBUF_EN 0x0cULL
145 #define CONTROL_PPFLOG_EN 0x0dULL
146 #define CONTROL_PPFINT_EN 0x0eULL
147 #define CONTROL_PPR_EN 0x0fULL
148 #define CONTROL_GT_EN 0x10ULL
149
150 #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT)
151 #define CTRL_INV_TO_NONE 0
152 #define CTRL_INV_TO_1MS 1
153 #define CTRL_INV_TO_10MS 2
154 #define CTRL_INV_TO_100MS 3
155 #define CTRL_INV_TO_1S 4
156 #define CTRL_INV_TO_10S 5
157 #define CTRL_INV_TO_100S 6
158
159 /* command specific defines */
160 #define CMD_COMPL_WAIT 0x01
161 #define CMD_INV_DEV_ENTRY 0x02
162 #define CMD_INV_IOMMU_PAGES 0x03
163 #define CMD_INV_IOTLB_PAGES 0x04
164 #define CMD_INV_IRT 0x05
165 #define CMD_COMPLETE_PPR 0x07
166 #define CMD_INV_ALL 0x08
167
168 #define CMD_COMPL_WAIT_STORE_MASK 0x01
169 #define CMD_COMPL_WAIT_INT_MASK 0x02
170 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
171 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
172 #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04
173
174 #define PPR_STATUS_MASK 0xf
175 #define PPR_STATUS_SHIFT 12
176
177 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
178
179 /* macros and definitions for device table entries */
180 #define DEV_ENTRY_VALID 0x00
181 #define DEV_ENTRY_TRANSLATION 0x01
182 #define DEV_ENTRY_IR 0x3d
183 #define DEV_ENTRY_IW 0x3e
184 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
185 #define DEV_ENTRY_EX 0x67
186 #define DEV_ENTRY_SYSMGT1 0x68
187 #define DEV_ENTRY_SYSMGT2 0x69
188 #define DEV_ENTRY_IRQ_TBL_EN 0x80
189 #define DEV_ENTRY_INIT_PASS 0xb8
190 #define DEV_ENTRY_EINT_PASS 0xb9
191 #define DEV_ENTRY_NMI_PASS 0xba
192 #define DEV_ENTRY_LINT0_PASS 0xbe
193 #define DEV_ENTRY_LINT1_PASS 0xbf
194 #define DEV_ENTRY_MODE_MASK 0x07
195 #define DEV_ENTRY_MODE_SHIFT 0x09
196
197 #define MAX_DEV_TABLE_ENTRIES 0xffff
198
199 /* constants to configure the command buffer */
200 #define CMD_BUFFER_SIZE 8192
201 #define CMD_BUFFER_UNINITIALIZED 1
202 #define CMD_BUFFER_ENTRIES 512
203 #define MMIO_CMD_SIZE_SHIFT 56
204 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
205
206 /* constants for event buffer handling */
207 #define EVT_BUFFER_SIZE 8192 /* 512 entries */
208 #define EVT_LEN_MASK (0x9ULL << 56)
209
210 /* Constants for PPR Log handling */
211 #define PPR_LOG_ENTRIES 512
212 #define PPR_LOG_SIZE_SHIFT 56
213 #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT)
214 #define PPR_ENTRY_SIZE 16
215 #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
216
217 #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
218 #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL)
219 #define PPR_DEVID(x) ((x) & 0xffffULL)
220 #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL)
221 #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL)
222 #define PPR_PASID2(x) (((x) >> 42) & 0xfULL)
223 #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
224
225 #define PPR_REQ_FAULT 0x01
226
227 #define PAGE_MODE_NONE 0x00
228 #define PAGE_MODE_1_LEVEL 0x01
229 #define PAGE_MODE_2_LEVEL 0x02
230 #define PAGE_MODE_3_LEVEL 0x03
231 #define PAGE_MODE_4_LEVEL 0x04
232 #define PAGE_MODE_5_LEVEL 0x05
233 #define PAGE_MODE_6_LEVEL 0x06
234
235 #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
236 #define PM_LEVEL_SIZE(x) (((x) < 6) ? \
237 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
238 (0xffffffffffffffffULL))
239 #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
240 #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
241 #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
242 IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
243 #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
244
245 #define PM_MAP_4k 0
246 #define PM_ADDR_MASK 0x000ffffffffff000ULL
247 #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
248 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
249 #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
250
251 /*
252 * Returns the page table level to use for a given page size
253 * Pagesize is expected to be a power-of-two
254 */
255 #define PAGE_SIZE_LEVEL(pagesize) \
256 ((__ffs(pagesize) - 12) / 9)
257 /*
258 * Returns the number of ptes to use for a given page size
259 * Pagesize is expected to be a power-of-two
260 */
261 #define PAGE_SIZE_PTE_COUNT(pagesize) \
262 (1ULL << ((__ffs(pagesize) - 12) % 9))
263
264 /*
265 * Aligns a given io-virtual address to a given page size
266 * Pagesize is expected to be a power-of-two
267 */
268 #define PAGE_SIZE_ALIGN(address, pagesize) \
269 ((address) & ~((pagesize) - 1))
270 /*
271 * Creates an IOMMU PTE for an address and a given pagesize
272 * The PTE has no permission bits set
273 * Pagesize is expected to be a power-of-two larger than 4096
274 */
275 #define PAGE_SIZE_PTE(address, pagesize) \
276 (((address) | ((pagesize) - 1)) & \
277 (~(pagesize >> 1)) & PM_ADDR_MASK)
278
279 /*
280 * Takes a PTE value with mode=0x07 and returns the page size it maps
281 */
282 #define PTE_PAGE_SIZE(pte) \
283 (1ULL << (1 + ffz(((pte) | 0xfffULL))))
284
285 /*
286 * Takes a page-table level and returns the default page-size for this level
287 */
288 #define PTE_LEVEL_PAGE_SIZE(level) \
289 (1ULL << (12 + (9 * (level))))
290
291 #define IOMMU_PTE_P (1ULL << 0)
292 #define IOMMU_PTE_TV (1ULL << 1)
293 #define IOMMU_PTE_U (1ULL << 59)
294 #define IOMMU_PTE_FC (1ULL << 60)
295 #define IOMMU_PTE_IR (1ULL << 61)
296 #define IOMMU_PTE_IW (1ULL << 62)
297
298 #define DTE_FLAG_IOTLB (1ULL << 32)
299 #define DTE_FLAG_GV (1ULL << 55)
300 #define DTE_FLAG_MASK (0x3ffULL << 32)
301 #define DTE_GLX_SHIFT (56)
302 #define DTE_GLX_MASK (3)
303
304 #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL)
305 #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL)
306 #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0x1fffffULL)
307
308 #define DTE_GCR3_INDEX_A 0
309 #define DTE_GCR3_INDEX_B 1
310 #define DTE_GCR3_INDEX_C 1
311
312 #define DTE_GCR3_SHIFT_A 58
313 #define DTE_GCR3_SHIFT_B 16
314 #define DTE_GCR3_SHIFT_C 43
315
316 #define GCR3_VALID 0x01ULL
317
318 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
319 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
320 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
321 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
322
323 #define IOMMU_PROT_MASK 0x03
324 #define IOMMU_PROT_IR 0x01
325 #define IOMMU_PROT_IW 0x02
326
327 /* IOMMU capabilities */
328 #define IOMMU_CAP_IOTLB 24
329 #define IOMMU_CAP_NPCACHE 26
330 #define IOMMU_CAP_EFR 27
331
332 #define MAX_DOMAIN_ID 65536
333
334 /* Protection domain flags */
335 #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */
336 #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops
337 domain for an IOMMU */
338 #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page
339 translation */
340 #define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */
341
342 extern bool amd_iommu_dump;
343 #define DUMP_printk(format, arg...) \
344 do { \
345 if (amd_iommu_dump) \
346 printk(KERN_INFO "AMD-Vi: " format, ## arg); \
347 } while(0);
348
349 /* global flag if IOMMUs cache non-present entries */
350 extern bool amd_iommu_np_cache;
351 /* Only true if all IOMMUs support device IOTLBs */
352 extern bool amd_iommu_iotlb_sup;
353
354 /*
355 * AMD IOMMU hardware only support 512 IRTEs despite
356 * the architectural limitation of 2048 entries.
357 */
358 #define MAX_IRQS_PER_TABLE 512
359 #define IRQ_TABLE_ALIGNMENT 128
360
361 struct irq_remap_table {
362 spinlock_t lock;
363 unsigned min_index;
364 u32 *table;
365 };
366
367 extern struct irq_remap_table **irq_lookup_table;
368
369 /* Interrupt remapping feature used? */
370 extern bool amd_iommu_irq_remap;
371
372 /* kmem_cache to get tables with 128 byte alignement */
373 extern struct kmem_cache *amd_iommu_irq_cache;
374
375 /*
376 * Make iterating over all IOMMUs easier
377 */
378 #define for_each_iommu(iommu) \
379 list_for_each_entry((iommu), &amd_iommu_list, list)
380 #define for_each_iommu_safe(iommu, next) \
381 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
382
383 #define APERTURE_RANGE_SHIFT 27 /* 128 MB */
384 #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT)
385 #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
386 #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */
387 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
388 #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
389
390
391 /*
392 * This struct is used to pass information about
393 * incoming PPR faults around.
394 */
395 struct amd_iommu_fault {
396 u64 address; /* IO virtual address of the fault*/
397 u32 pasid; /* Address space identifier */
398 u16 device_id; /* Originating PCI device id */
399 u16 tag; /* PPR tag */
400 u16 flags; /* Fault flags */
401
402 };
403
404
405 struct iommu_domain;
406 struct irq_domain;
407
408 /*
409 * This structure contains generic data for IOMMU protection domains
410 * independent of their use.
411 */
412 struct protection_domain {
413 struct list_head list; /* for list of all protection domains */
414 struct list_head dev_list; /* List of all devices in this domain */
415 struct iommu_domain domain; /* generic domain handle used by
416 iommu core code */
417 spinlock_t lock; /* mostly used to lock the page table*/
418 struct mutex api_lock; /* protect page tables in the iommu-api path */
419 u16 id; /* the domain id written to the device table */
420 int mode; /* paging mode (0-6 levels) */
421 u64 *pt_root; /* page table root pointer */
422 int glx; /* Number of levels for GCR3 table */
423 u64 *gcr3_tbl; /* Guest CR3 table */
424 unsigned long flags; /* flags to find out type of domain */
425 bool updated; /* complete domain flush required */
426 unsigned dev_cnt; /* devices assigned to this domain */
427 unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
428 void *priv; /* private data */
429 };
430
431 /*
432 * For dynamic growth the aperture size is split into ranges of 128MB of
433 * DMA address space each. This struct represents one such range.
434 */
435 struct aperture_range {
436
437 /* address allocation bitmap */
438 unsigned long *bitmap;
439
440 /*
441 * Array of PTE pages for the aperture. In this array we save all the
442 * leaf pages of the domain page table used for the aperture. This way
443 * we don't need to walk the page table to find a specific PTE. We can
444 * just calculate its address in constant time.
445 */
446 u64 *pte_pages[64];
447
448 unsigned long offset;
449 };
450
451 /*
452 * Data container for a dma_ops specific protection domain
453 */
454 struct dma_ops_domain {
455 /* generic protection domain information */
456 struct protection_domain domain;
457
458 /* size of the aperture for the mappings */
459 unsigned long aperture_size;
460
461 /* address we start to search for free addresses */
462 unsigned long next_address;
463
464 /* address space relevant data */
465 struct aperture_range *aperture[APERTURE_MAX_RANGES];
466
467 /* This will be set to true when TLB needs to be flushed */
468 bool need_flush;
469 };
470
471 /*
472 * Structure where we save information about one hardware AMD IOMMU in the
473 * system.
474 */
475 struct amd_iommu {
476 struct list_head list;
477
478 /* Index within the IOMMU array */
479 int index;
480
481 /* locks the accesses to the hardware */
482 spinlock_t lock;
483
484 /* Pointer to PCI device of this IOMMU */
485 struct pci_dev *dev;
486
487 /* Cache pdev to root device for resume quirks */
488 struct pci_dev *root_pdev;
489
490 /* physical address of MMIO space */
491 u64 mmio_phys;
492
493 /* physical end address of MMIO space */
494 u64 mmio_phys_end;
495
496 /* virtual address of MMIO space */
497 u8 __iomem *mmio_base;
498
499 /* capabilities of that IOMMU read from ACPI */
500 u32 cap;
501
502 /* flags read from acpi table */
503 u8 acpi_flags;
504
505 /* Extended features */
506 u64 features;
507
508 /* IOMMUv2 */
509 bool is_iommu_v2;
510
511 /* PCI device id of the IOMMU device */
512 u16 devid;
513
514 /*
515 * Capability pointer. There could be more than one IOMMU per PCI
516 * device function if there are more than one AMD IOMMU capability
517 * pointers.
518 */
519 u16 cap_ptr;
520
521 /* pci domain of this IOMMU */
522 u16 pci_seg;
523
524 /* start of exclusion range of that IOMMU */
525 u64 exclusion_start;
526 /* length of exclusion range of that IOMMU */
527 u64 exclusion_length;
528
529 /* command buffer virtual address */
530 u8 *cmd_buf;
531
532 /* event buffer virtual address */
533 u8 *evt_buf;
534
535 /* Base of the PPR log, if present */
536 u8 *ppr_log;
537
538 /* true if interrupts for this IOMMU are already enabled */
539 bool int_enabled;
540
541 /* if one, we need to send a completion wait command */
542 bool need_sync;
543
544 /* IOMMU sysfs device */
545 struct device *iommu_dev;
546
547 /*
548 * We can't rely on the BIOS to restore all values on reinit, so we
549 * need to stash them
550 */
551
552 /* The iommu BAR */
553 u32 stored_addr_lo;
554 u32 stored_addr_hi;
555
556 /*
557 * Each iommu has 6 l1s, each of which is documented as having 0x12
558 * registers
559 */
560 u32 stored_l1[6][0x12];
561
562 /* The l2 indirect registers */
563 u32 stored_l2[0x83];
564
565 /* The maximum PC banks and counters/bank (PCSup=1) */
566 u8 max_banks;
567 u8 max_counters;
568 #ifdef CONFIG_IRQ_REMAP
569 struct irq_domain *ir_domain;
570 struct irq_domain *msi_domain;
571 #endif
572 };
573
574 struct devid_map {
575 struct list_head list;
576 u8 id;
577 u16 devid;
578 bool cmd_line;
579 };
580
581 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */
582 extern struct list_head ioapic_map;
583 extern struct list_head hpet_map;
584
585 /*
586 * List with all IOMMUs in the system. This list is not locked because it is
587 * only written and read at driver initialization or suspend time
588 */
589 extern struct list_head amd_iommu_list;
590
591 /*
592 * Array with pointers to each IOMMU struct
593 * The indices are referenced in the protection domains
594 */
595 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
596
597 /* Number of IOMMUs present in the system */
598 extern int amd_iommus_present;
599
600 /*
601 * Declarations for the global list of all protection domains
602 */
603 extern spinlock_t amd_iommu_pd_lock;
604 extern struct list_head amd_iommu_pd_list;
605
606 /*
607 * Structure defining one entry in the device table
608 */
609 struct dev_table_entry {
610 u64 data[4];
611 };
612
613 /*
614 * One entry for unity mappings parsed out of the ACPI table.
615 */
616 struct unity_map_entry {
617 struct list_head list;
618
619 /* starting device id this entry is used for (including) */
620 u16 devid_start;
621 /* end device id this entry is used for (including) */
622 u16 devid_end;
623
624 /* start address to unity map (including) */
625 u64 address_start;
626 /* end address to unity map (including) */
627 u64 address_end;
628
629 /* required protection */
630 int prot;
631 };
632
633 /*
634 * List of all unity mappings. It is not locked because as runtime it is only
635 * read. It is created at ACPI table parsing time.
636 */
637 extern struct list_head amd_iommu_unity_map;
638
639 /*
640 * Data structures for device handling
641 */
642
643 /*
644 * Device table used by hardware. Read and write accesses by software are
645 * locked with the amd_iommu_pd_table lock.
646 */
647 extern struct dev_table_entry *amd_iommu_dev_table;
648
649 /*
650 * Alias table to find requestor ids to device ids. Not locked because only
651 * read on runtime.
652 */
653 extern u16 *amd_iommu_alias_table;
654
655 /*
656 * Reverse lookup table to find the IOMMU which translates a specific device.
657 */
658 extern struct amd_iommu **amd_iommu_rlookup_table;
659
660 /* size of the dma_ops aperture as power of 2 */
661 extern unsigned amd_iommu_aperture_order;
662
663 /* largest PCI device id we expect translation requests for */
664 extern u16 amd_iommu_last_bdf;
665
666 /* allocation bitmap for domain ids */
667 extern unsigned long *amd_iommu_pd_alloc_bitmap;
668
669 /*
670 * If true, the addresses will be flushed on unmap time, not when
671 * they are reused
672 */
673 extern bool amd_iommu_unmap_flush;
674
675 /* Smallest max PASID supported by any IOMMU in the system */
676 extern u32 amd_iommu_max_pasid;
677
678 extern bool amd_iommu_v2_present;
679
680 extern bool amd_iommu_force_isolation;
681
682 /* Max levels of glxval supported */
683 extern int amd_iommu_max_glx_val;
684
685 /*
686 * This function flushes all internal caches of
687 * the IOMMU used by this driver.
688 */
689 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
690
get_ioapic_devid(int id)691 static inline int get_ioapic_devid(int id)
692 {
693 struct devid_map *entry;
694
695 list_for_each_entry(entry, &ioapic_map, list) {
696 if (entry->id == id)
697 return entry->devid;
698 }
699
700 return -EINVAL;
701 }
702
get_hpet_devid(int id)703 static inline int get_hpet_devid(int id)
704 {
705 struct devid_map *entry;
706
707 list_for_each_entry(entry, &hpet_map, list) {
708 if (entry->id == id)
709 return entry->devid;
710 }
711
712 return -EINVAL;
713 }
714
715 #ifdef CONFIG_AMD_IOMMU_STATS
716
717 struct __iommu_counter {
718 char *name;
719 struct dentry *dent;
720 u64 value;
721 };
722
723 #define DECLARE_STATS_COUNTER(nm) \
724 static struct __iommu_counter nm = { \
725 .name = #nm, \
726 }
727
728 #define INC_STATS_COUNTER(name) name.value += 1
729 #define ADD_STATS_COUNTER(name, x) name.value += (x)
730 #define SUB_STATS_COUNTER(name, x) name.value -= (x)
731
732 #else /* CONFIG_AMD_IOMMU_STATS */
733
734 #define DECLARE_STATS_COUNTER(name)
735 #define INC_STATS_COUNTER(name)
736 #define ADD_STATS_COUNTER(name, x)
737 #define SUB_STATS_COUNTER(name, x)
738
739 #endif /* CONFIG_AMD_IOMMU_STATS */
740
741 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */
742