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Searched defs:R4600_V2_HIT_CACHEOP_WAR (Results 1 – 13 of 13) sorted by relevance

/arch/mips/include/asm/mach-malta/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-ip22/
Dwar.h17 #define R4600_V2_HIT_CACHEOP_WAR 1 macro
/arch/mips/include/asm/mach-ip32/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-ip27/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-ip28/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-generic/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-rc32434/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-sead3/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-rm/
Dwar.h17 #define R4600_V2_HIT_CACHEOP_WAR 1 macro
/arch/mips/include/asm/mach-tx49xx/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-pmcs-msp71xx/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-cavium-octeon/
Dwar.h14 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-sibyte/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro