1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Parts of this file are based on Ralink's 2.6.21 BSP 7 * 8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org> 11 */ 12 13 #ifndef _RT305X_REGS_H_ 14 #define _RT305X_REGS_H_ 15 16 extern enum ralink_soc_type ralink_soc; 17 soc_is_rt3050(void)18static inline int soc_is_rt3050(void) 19 { 20 return ralink_soc == RT305X_SOC_RT3050; 21 } 22 soc_is_rt3052(void)23static inline int soc_is_rt3052(void) 24 { 25 return ralink_soc == RT305X_SOC_RT3052; 26 } 27 soc_is_rt305x(void)28static inline int soc_is_rt305x(void) 29 { 30 return soc_is_rt3050() || soc_is_rt3052(); 31 } 32 soc_is_rt3350(void)33static inline int soc_is_rt3350(void) 34 { 35 return ralink_soc == RT305X_SOC_RT3350; 36 } 37 soc_is_rt3352(void)38static inline int soc_is_rt3352(void) 39 { 40 return ralink_soc == RT305X_SOC_RT3352; 41 } 42 soc_is_rt5350(void)43static inline int soc_is_rt5350(void) 44 { 45 return ralink_soc == RT305X_SOC_RT5350; 46 } 47 48 #define RT305X_SYSC_BASE 0x10000000 49 50 #define SYSC_REG_CHIP_NAME0 0x00 51 #define SYSC_REG_CHIP_NAME1 0x04 52 #define SYSC_REG_CHIP_ID 0x0c 53 #define SYSC_REG_SYSTEM_CONFIG 0x10 54 55 #define RT3052_CHIP_NAME0 0x30335452 56 #define RT3052_CHIP_NAME1 0x20203235 57 58 #define RT3350_CHIP_NAME0 0x33335452 59 #define RT3350_CHIP_NAME1 0x20203035 60 61 #define RT3352_CHIP_NAME0 0x33335452 62 #define RT3352_CHIP_NAME1 0x20203235 63 64 #define RT5350_CHIP_NAME0 0x33355452 65 #define RT5350_CHIP_NAME1 0x20203035 66 67 #define CHIP_ID_ID_MASK 0xff 68 #define CHIP_ID_ID_SHIFT 8 69 #define CHIP_ID_REV_MASK 0xff 70 71 #define RT305X_SYSCFG_CPUCLK_SHIFT 18 72 #define RT305X_SYSCFG_CPUCLK_MASK 0x1 73 #define RT305X_SYSCFG_CPUCLK_LOW 0x0 74 #define RT305X_SYSCFG_CPUCLK_HIGH 0x1 75 76 #define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2 77 #define RT305X_SYSCFG_CPUCLK_MASK 0x1 78 #define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1 79 80 #define RT3352_SYSCFG0_CPUCLK_SHIFT 8 81 #define RT3352_SYSCFG0_CPUCLK_MASK 0x1 82 #define RT3352_SYSCFG0_CPUCLK_LOW 0x0 83 #define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 84 85 #define RT5350_SYSCFG0_CPUCLK_SHIFT 8 86 #define RT5350_SYSCFG0_CPUCLK_MASK 0x3 87 #define RT5350_SYSCFG0_CPUCLK_360 0x0 88 #define RT5350_SYSCFG0_CPUCLK_320 0x2 89 #define RT5350_SYSCFG0_CPUCLK_300 0x3 90 91 #define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12 92 #define RT5350_SYSCFG0_DRAM_SIZE_MASK 7 93 #define RT5350_SYSCFG0_DRAM_SIZE_2M 0 94 #define RT5350_SYSCFG0_DRAM_SIZE_8M 1 95 #define RT5350_SYSCFG0_DRAM_SIZE_16M 2 96 #define RT5350_SYSCFG0_DRAM_SIZE_32M 3 97 #define RT5350_SYSCFG0_DRAM_SIZE_64M 4 98 99 /* multi function gpio pins */ 100 #define RT305X_GPIO_I2C_SD 1 101 #define RT305X_GPIO_I2C_SCLK 2 102 #define RT305X_GPIO_SPI_EN 3 103 #define RT305X_GPIO_SPI_CLK 4 104 /* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */ 105 #define RT305X_GPIO_7 7 106 #define RT305X_GPIO_10 10 107 #define RT305X_GPIO_14 14 108 #define RT305X_GPIO_UART1_TXD 15 109 #define RT305X_GPIO_UART1_RXD 16 110 #define RT305X_GPIO_JTAG_TDO 17 111 #define RT305X_GPIO_JTAG_TDI 18 112 #define RT305X_GPIO_MDIO_MDC 22 113 #define RT305X_GPIO_MDIO_MDIO 23 114 #define RT305X_GPIO_SDRAM_MD16 24 115 #define RT305X_GPIO_SDRAM_MD31 39 116 #define RT305X_GPIO_GE0_TXD0 40 117 #define RT305X_GPIO_GE0_RXCLK 51 118 119 #define RT305X_GPIO_MODE_UART0_SHIFT 2 120 #define RT305X_GPIO_MODE_UART0_MASK 0x7 121 #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT) 122 #define RT305X_GPIO_MODE_UARTF 0 123 #define RT305X_GPIO_MODE_PCM_UARTF 1 124 #define RT305X_GPIO_MODE_PCM_I2S 2 125 #define RT305X_GPIO_MODE_I2S_UARTF 3 126 #define RT305X_GPIO_MODE_PCM_GPIO 4 127 #define RT305X_GPIO_MODE_GPIO_UARTF 5 128 #define RT305X_GPIO_MODE_GPIO_I2S 6 129 #define RT305X_GPIO_MODE_GPIO 7 130 131 #define RT305X_GPIO_MODE_I2C 0 132 #define RT305X_GPIO_MODE_SPI 1 133 #define RT305X_GPIO_MODE_UART1 5 134 #define RT305X_GPIO_MODE_JTAG 6 135 #define RT305X_GPIO_MODE_MDIO 7 136 #define RT305X_GPIO_MODE_SDRAM 8 137 #define RT305X_GPIO_MODE_RGMII 9 138 #define RT5350_GPIO_MODE_PHY_LED 14 139 #define RT5350_GPIO_MODE_SPI_CS1 21 140 #define RT3352_GPIO_MODE_LNA 18 141 #define RT3352_GPIO_MODE_PA 20 142 143 #define RT3352_SYSC_REG_SYSCFG0 0x010 144 #define RT3352_SYSC_REG_SYSCFG1 0x014 145 #define RT3352_SYSC_REG_CLKCFG1 0x030 146 #define RT3352_SYSC_REG_RSTCTRL 0x034 147 #define RT3352_SYSC_REG_USB_PS 0x05c 148 149 #define RT3352_CLKCFG0_XTAL_SEL BIT(20) 150 #define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) 151 #define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20) 152 #define RT3352_RSTCTRL_UHST BIT(22) 153 #define RT3352_RSTCTRL_UDEV BIT(25) 154 #define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) 155 156 #define RT305X_SDRAM_BASE 0x00000000 157 #define RT305X_MEM_SIZE_MIN 2 158 #define RT305X_MEM_SIZE_MAX 64 159 #define RT3352_MEM_SIZE_MIN 2 160 #define RT3352_MEM_SIZE_MAX 256 161 162 #endif 163