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1 #ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
2 #define __ARCH_ARM_MACH_OMAP2_SDRC_H
3 
4 /*
5  * OMAP2/3 SDRC/SMS macros and prototypes
6  *
7  * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
8  * Copyright (C) 2007-2008 Nokia Corporation
9  *
10  * Paul Walmsley
11  * Tony Lindgren
12  * Richard Woodruff
13  *
14  * This program is free software; you can redistribute it and/or modify
15  * it under the terms of the GNU General Public License version 2 as
16  * published by the Free Software Foundation.
17  */
18 #undef DEBUG
19 
20 #ifndef __ASSEMBLER__
21 
22 #include <linux/io.h>
23 
24 extern void __iomem *omap2_sdrc_base;
25 extern void __iomem *omap2_sms_base;
26 
27 #define OMAP_SDRC_REGADDR(reg)			(omap2_sdrc_base + (reg))
28 #define OMAP_SMS_REGADDR(reg)			(omap2_sms_base + (reg))
29 
30 /* SDRC global register get/set */
31 
sdrc_write_reg(u32 val,u16 reg)32 static inline void sdrc_write_reg(u32 val, u16 reg)
33 {
34 	writel_relaxed(val, OMAP_SDRC_REGADDR(reg));
35 }
36 
sdrc_read_reg(u16 reg)37 static inline u32 sdrc_read_reg(u16 reg)
38 {
39 	return readl_relaxed(OMAP_SDRC_REGADDR(reg));
40 }
41 
42 /* SMS global register get/set */
43 
sms_write_reg(u32 val,u16 reg)44 static inline void sms_write_reg(u32 val, u16 reg)
45 {
46 	writel_relaxed(val, OMAP_SMS_REGADDR(reg));
47 }
48 
sms_read_reg(u16 reg)49 static inline u32 sms_read_reg(u16 reg)
50 {
51 	return readl_relaxed(OMAP_SMS_REGADDR(reg));
52 }
53 
54 extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms);
55 
56 
57 /**
58  * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
59  * @rate: SDRC clock rate (in Hz)
60  * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
61  * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
62  * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
63  * @mr: Value to program to SDRC_MR for this rate
64  *
65  * This structure holds a pre-computed set of register values for the
66  * SDRC for a given SDRC clock rate and SDRAM chip.  These are
67  * intended to be pre-computed and specified in an array in the board-*.c
68  * files.  The structure is keyed off the 'rate' field.
69  */
70 struct omap_sdrc_params {
71 	unsigned long rate;
72 	u32 actim_ctrla;
73 	u32 actim_ctrlb;
74 	u32 rfr_ctrl;
75 	u32 mr;
76 };
77 
78 #ifdef CONFIG_SOC_HAS_OMAP2_SDRC
79 void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
80 			    struct omap_sdrc_params *sdrc_cs1);
81 #else
omap2_sdrc_init(struct omap_sdrc_params * sdrc_cs0,struct omap_sdrc_params * sdrc_cs1)82 static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
83 					  struct omap_sdrc_params *sdrc_cs1) {};
84 #endif
85 
86 int omap2_sdrc_get_params(unsigned long r,
87 			  struct omap_sdrc_params **sdrc_cs0,
88 			  struct omap_sdrc_params **sdrc_cs1);
89 void omap2_sms_save_context(void);
90 void omap2_sms_restore_context(void);
91 
92 struct memory_timings {
93 	u32 m_type;		/* ddr = 1, sdr = 0 */
94 	u32 dll_mode;		/* use lock mode = 1, unlock mode = 0 */
95 	u32 slow_dll_ctrl;	/* unlock mode, dll value for slow speed */
96 	u32 fast_dll_ctrl;	/* unlock mode, dll value for fast speed */
97 	u32 base_cs;		/* base chip select to use for calculations */
98 };
99 
100 extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
101 struct omap_sdrc_params *rx51_get_sdram_timings(void);
102 
103 u32 omap2xxx_sdrc_dll_is_unlocked(void);
104 u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
105 
106 
107 #else
108 #define OMAP242X_SDRC_REGADDR(reg)					\
109 			OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
110 #define OMAP243X_SDRC_REGADDR(reg)					\
111 			OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
112 #define OMAP34XX_SDRC_REGADDR(reg)					\
113 			OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
114 
115 #endif	/* __ASSEMBLER__ */
116 
117 /* Minimum frequency that the SDRC DLL can lock at */
118 #define MIN_SDRC_DLL_LOCK_FREQ		83000000
119 
120 /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
121 #define SDRC_MPURATE_SCALE		8
122 
123 /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
124 #define SDRC_MPURATE_BASE_SHIFT		9
125 
126 /*
127  * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
128  * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
129  */
130 #define SDRC_MPURATE_LOOPS		96
131 
132 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
133 
134 #define SDRC_SYSCONFIG		0x010
135 #define SDRC_CS_CFG		0x040
136 #define SDRC_SHARING		0x044
137 #define SDRC_ERR_TYPE		0x04C
138 #define SDRC_DLLA_CTRL		0x060
139 #define SDRC_DLLA_STATUS	0x064
140 #define SDRC_DLLB_CTRL		0x068
141 #define SDRC_DLLB_STATUS	0x06C
142 #define SDRC_POWER		0x070
143 #define SDRC_MCFG_0		0x080
144 #define SDRC_MR_0		0x084
145 #define SDRC_EMR2_0		0x08c
146 #define SDRC_ACTIM_CTRL_A_0	0x09c
147 #define SDRC_ACTIM_CTRL_B_0	0x0a0
148 #define SDRC_RFR_CTRL_0		0x0a4
149 #define SDRC_MANUAL_0		0x0a8
150 #define SDRC_MCFG_1		0x0B0
151 #define SDRC_MR_1		0x0B4
152 #define SDRC_EMR2_1		0x0BC
153 #define SDRC_ACTIM_CTRL_A_1	0x0C4
154 #define SDRC_ACTIM_CTRL_B_1	0x0C8
155 #define SDRC_RFR_CTRL_1		0x0D4
156 #define SDRC_MANUAL_1		0x0D8
157 
158 #define SDRC_POWER_AUTOCOUNT_SHIFT	8
159 #define SDRC_POWER_AUTOCOUNT_MASK	(0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
160 #define SDRC_POWER_CLKCTRL_SHIFT	4
161 #define SDRC_POWER_CLKCTRL_MASK		(0x3 << SDRC_POWER_CLKCTRL_SHIFT)
162 #define SDRC_SELF_REFRESH_ON_AUTOCOUNT	(0x2 << SDRC_POWER_CLKCTRL_SHIFT)
163 
164 /*
165  * These values represent the number of memory clock cycles between
166  * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
167  * rows per device, and include a subtraction of a 50 cycle window in the
168  * event that the autorefresh command is delayed due to other SDRC activity.
169  * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
170  * counter reaches 0.
171  *
172  * These represent optimal values for common parts, it won't work for all.
173  * As long as you scale down, most parameters are still work, they just
174  * become sub-optimal. The RFR value goes in the opposite direction. If you
175  * don't adjust it down as your clock period increases the refresh interval
176  * will not be met. Setting all parameters for complete worst case may work,
177  * but may cut memory performance by 2x. Due to errata the DLLs need to be
178  * unlocked and their value needs run time calibration.	A dynamic call is
179  * need for that as no single right value exists acorss production samples.
180  *
181  * Only the FULL speed values are given. Current code is such that rate
182  * changes must be made at DPLLoutx2. The actual value adjustment for low
183  * frequency operation will be handled by omap_set_performance()
184  *
185  * By having the boot loader boot up in the fastest L4 speed available likely
186  * will result in something which you can switch between.
187  */
188 #define SDRC_RFR_CTRL_165MHz	(0x00044c00 | 1)
189 #define SDRC_RFR_CTRL_133MHz	(0x0003de00 | 1)
190 #define SDRC_RFR_CTRL_100MHz	(0x0002da01 | 1)
191 #define SDRC_RFR_CTRL_110MHz	(0x0002da01 | 1) /* Need to calc */
192 #define SDRC_RFR_CTRL_BYPASS	(0x00005000 | 1) /* Need to calc */
193 
194 
195 /*
196  * SMS register access
197  */
198 
199 #define OMAP242X_SMS_REGADDR(reg)					\
200 		(void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
201 #define OMAP243X_SMS_REGADDR(reg)					\
202 		(void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
203 #define OMAP343X_SMS_REGADDR(reg)					\
204 		(void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
205 
206 /* SMS register offsets - read/write with sms_{read,write}_reg() */
207 
208 #define SMS_SYSCONFIG			0x010
209 /* REVISIT: fill in other SMS registers here */
210 
211 
212 
213 #endif
214