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1 /*
2  * Copyright 2011 Analog Devices Inc.
3  *
4  * Licensed under the Clear BSD license or the GPL-2 (or later)
5  */
6 
7 #ifndef _DEF_BF60X_H
8 #define _DEF_BF60X_H
9 
10 
11 /* ************************************************************** */
12 /*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x    */
13 /* ************************************************************** */
14 
15 
16 /* =========================
17         CNT Registers
18    ========================= */
19 
20 /* =========================
21         CNT0
22    ========================= */
23 #define CNT_CONFIG                 0xFFC00400         /* CNT0 Configuration Register */
24 #define CNT_IMASK                  0xFFC00404         /* CNT0 Interrupt Mask Register */
25 #define CNT_STATUS                 0xFFC00408         /* CNT0 Status Register */
26 #define CNT_COMMAND                0xFFC0040C         /* CNT0 Command Register */
27 #define CNT_DEBOUNCE               0xFFC00410         /* CNT0 Debounce Register */
28 #define CNT_COUNTER                0xFFC00414         /* CNT0 Counter Register */
29 #define CNT_MAX                    0xFFC00418         /* CNT0 Maximum Count Register */
30 #define CNT_MIN                    0xFFC0041C         /* CNT0 Minimum Count Register */
31 
32 
33 /* =========================
34         RSI Registers
35    ========================= */
36 
37 #define RSI_CLK_CONTROL            0xFFC00604         /* RSI0 Clock Control Register */
38 #define RSI_ARGUMENT               0xFFC00608         /* RSI0 Argument Register */
39 #define RSI_COMMAND                0xFFC0060C         /* RSI0 Command Register */
40 #define RSI_RESP_CMD               0xFFC00610         /* RSI0 Response Command Register */
41 #define RSI_RESPONSE0              0xFFC00614         /* RSI0 Response 0 Register */
42 #define RSI_RESPONSE1              0xFFC00618         /* RSI0 Response 1 Register */
43 #define RSI_RESPONSE2              0xFFC0061C         /* RSI0 Response 2 Register */
44 #define RSI_RESPONSE3              0xFFC00620         /* RSI0 Response 3 Register */
45 #define RSI_DATA_TIMER             0xFFC00624         /* RSI0 Data Timer Register */
46 #define RSI_DATA_LGTH              0xFFC00628         /* RSI0 Data Length Register */
47 #define RSI_DATA_CONTROL           0xFFC0062C         /* RSI0 Data Control Register */
48 #define RSI_DATA_CNT               0xFFC00630         /* RSI0 Data Count Register */
49 #define RSI_STATUS                 0xFFC00634         /* RSI0 Status Register */
50 #define RSI_STATUSCL               0xFFC00638         /* RSI0 Status Clear Register */
51 #define RSI_MASK0                  0xFFC0063C         /* RSI0 Interrupt 0 Mask Register */
52 #define RSI_MASK1                  0xFFC00640         /* RSI0 Interrupt 1 Mask Register */
53 #define RSI_FIFO_CNT               0xFFC00648         /* RSI0 FIFO Counter Register */
54 #define RSI_CEATA_CONTROL          0xFFC0064C         /* RSI0 This register contains bit to dis CCS gen */
55 #define RSI_BOOT_TCNTR             0xFFC00650         /* RSI0 Boot Timing Counter Register */
56 #define RSI_BACK_TOUT              0xFFC00654         /* RSI0 Boot Acknowledge Timeout Register */
57 #define RSI_SLP_WKUP_TOUT          0xFFC00658         /* RSI0 Sleep Wakeup Timeout Register */
58 #define RSI_BLKSZ                  0xFFC0065C         /* RSI0 Block Size Register */
59 #define RSI_FIFO                   0xFFC00680         /* RSI0 Data FIFO Register */
60 #define RSI_ESTAT                  0xFFC006C0         /* RSI0 Exception Status Register */
61 #define RSI_EMASK                  0xFFC006C4         /* RSI0 Exception Mask Register */
62 #define RSI_CONFIG                 0xFFC006C8         /* RSI0 Configuration Register */
63 #define RSI_RD_WAIT_EN             0xFFC006CC         /* RSI0 Read Wait Enable Register */
64 #define RSI_PID0                   0xFFC006D0         /* RSI0 Peripheral Identification Register */
65 #define RSI_PID1                   0xFFC006D4         /* RSI0 Peripheral Identification Register */
66 #define RSI_PID2                   0xFFC006D8         /* RSI0 Peripheral Identification Register */
67 #define RSI_PID3                   0xFFC006DC         /* RSI0 Peripheral Identification Register */
68 
69 /* =========================
70         CAN Registers
71    ========================= */
72 
73 /* =========================
74         CAN0
75    ========================= */
76 #define CAN0_MC1                    0xFFC00A00         /* CAN0 Mailbox Configuration Register 1 */
77 #define CAN0_MD1                    0xFFC00A04         /* CAN0 Mailbox Direction Register 1 */
78 #define CAN0_TRS1                   0xFFC00A08         /* CAN0 Transmission Request Set Register 1 */
79 #define CAN0_TRR1                   0xFFC00A0C         /* CAN0 Transmission Request Reset Register 1 */
80 #define CAN0_TA1                    0xFFC00A10         /* CAN0 Transmission Acknowledge Register 1 */
81 #define CAN0_AA1                    0xFFC00A14         /* CAN0 Abort Acknowledge Register 1 */
82 #define CAN0_RMP1                   0xFFC00A18         /* CAN0 Receive Message Pending Register 1 */
83 #define CAN0_RML1                   0xFFC00A1C         /* CAN0 Receive Message Lost Register 1 */
84 #define CAN0_MBTIF1                 0xFFC00A20         /* CAN0 Mailbox Transmit Interrupt Flag Register 1 */
85 #define CAN0_MBRIF1                 0xFFC00A24         /* CAN0 Mailbox Receive Interrupt Flag Register 1 */
86 #define CAN0_MBIM1                  0xFFC00A28         /* CAN0 Mailbox Interrupt Mask Register 1 */
87 #define CAN0_RFH1                   0xFFC00A2C         /* CAN0 Remote Frame Handling Register 1 */
88 #define CAN0_OPSS1                  0xFFC00A30         /* CAN0 Overwrite Protection/Single Shot Transmission Register 1 */
89 #define CAN0_MC2                    0xFFC00A40         /* CAN0 Mailbox Configuration Register 2 */
90 #define CAN0_MD2                    0xFFC00A44         /* CAN0 Mailbox Direction Register 2 */
91 #define CAN0_TRS2                   0xFFC00A48         /* CAN0 Transmission Request Set Register 2 */
92 #define CAN0_TRR2                   0xFFC00A4C         /* CAN0 Transmission Request Reset Register 2 */
93 #define CAN0_TA2                    0xFFC00A50         /* CAN0 Transmission Acknowledge Register 2 */
94 #define CAN0_AA2                    0xFFC00A54         /* CAN0 Abort Acknowledge Register 2 */
95 #define CAN0_RMP2                   0xFFC00A58         /* CAN0 Receive Message Pending Register 2 */
96 #define CAN0_RML2                   0xFFC00A5C         /* CAN0 Receive Message Lost Register 2 */
97 #define CAN0_MBTIF2                 0xFFC00A60         /* CAN0 Mailbox Transmit Interrupt Flag Register 2 */
98 #define CAN0_MBRIF2                 0xFFC00A64         /* CAN0 Mailbox Receive Interrupt Flag Register 2 */
99 #define CAN0_MBIM2                  0xFFC00A68         /* CAN0 Mailbox Interrupt Mask Register 2 */
100 #define CAN0_RFH2                   0xFFC00A6C         /* CAN0 Remote Frame Handling Register 2 */
101 #define CAN0_OPSS2                  0xFFC00A70         /* CAN0 Overwrite Protection/Single Shot Transmission Register 2 */
102 #define CAN0_CLOCK                    0xFFC00A80         /* CAN0 Clock Register */
103 #define CAN0_TIMING                 0xFFC00A84         /* CAN0 Timing Register */
104 #define CAN0_DEBUG                    0xFFC00A88         /* CAN0 Debug Register */
105 #define CAN0_STATUS                   0xFFC00A8C         /* CAN0 Status Register */
106 #define CAN0_CEC                    0xFFC00A90         /* CAN0 Error Counter Register */
107 #define CAN0_GIS                    0xFFC00A94         /* CAN0 Global CAN Interrupt Status */
108 #define CAN0_GIM                    0xFFC00A98         /* CAN0 Global CAN Interrupt Mask */
109 #define CAN0_GIF                    0xFFC00A9C         /* CAN0 Global CAN Interrupt Flag */
110 #define CAN0_CONTROL                    0xFFC00AA0         /* CAN0 CAN Master Control Register */
111 #define CAN0_INTR                    0xFFC00AA4         /* CAN0 Interrupt Pending Register */
112 #define CAN0_MBTD                   0xFFC00AAC         /* CAN0 Temporary Mailbox Disable Register */
113 #define CAN0_EWR                    0xFFC00AB0         /* CAN0 Error Counter Warning Level Register */
114 #define CAN0_ESR                    0xFFC00AB4         /* CAN0 Error Status Register */
115 #define CAN0_UCCNT                  0xFFC00AC4         /* CAN0 Universal Counter Register */
116 #define CAN0_UCRC                   0xFFC00AC8         /* CAN0 Universal Counter Reload/Capture Register */
117 #define CAN0_UCCNF                  0xFFC00ACC         /* CAN0 Universal Counter Configuration Mode Register */
118 #define CAN0_AM00L                  0xFFC00B00         /* CAN0 Acceptance Mask Register (L) */
119 #define CAN0_AM01L                  0xFFC00B08         /* CAN0 Acceptance Mask Register (L) */
120 #define CAN0_AM02L                  0xFFC00B10         /* CAN0 Acceptance Mask Register (L) */
121 #define CAN0_AM03L                  0xFFC00B18         /* CAN0 Acceptance Mask Register (L) */
122 #define CAN0_AM04L                  0xFFC00B20         /* CAN0 Acceptance Mask Register (L) */
123 #define CAN0_AM05L                  0xFFC00B28         /* CAN0 Acceptance Mask Register (L) */
124 #define CAN0_AM06L                  0xFFC00B30         /* CAN0 Acceptance Mask Register (L) */
125 #define CAN0_AM07L                  0xFFC00B38         /* CAN0 Acceptance Mask Register (L) */
126 #define CAN0_AM08L                  0xFFC00B40         /* CAN0 Acceptance Mask Register (L) */
127 #define CAN0_AM09L                  0xFFC00B48         /* CAN0 Acceptance Mask Register (L) */
128 #define CAN0_AM10L                  0xFFC00B50         /* CAN0 Acceptance Mask Register (L) */
129 #define CAN0_AM11L                  0xFFC00B58         /* CAN0 Acceptance Mask Register (L) */
130 #define CAN0_AM12L                  0xFFC00B60         /* CAN0 Acceptance Mask Register (L) */
131 #define CAN0_AM13L                  0xFFC00B68         /* CAN0 Acceptance Mask Register (L) */
132 #define CAN0_AM14L                  0xFFC00B70         /* CAN0 Acceptance Mask Register (L) */
133 #define CAN0_AM15L                  0xFFC00B78         /* CAN0 Acceptance Mask Register (L) */
134 #define CAN0_AM16L                  0xFFC00B80         /* CAN0 Acceptance Mask Register (L) */
135 #define CAN0_AM17L                  0xFFC00B88         /* CAN0 Acceptance Mask Register (L) */
136 #define CAN0_AM18L                  0xFFC00B90         /* CAN0 Acceptance Mask Register (L) */
137 #define CAN0_AM19L                  0xFFC00B98         /* CAN0 Acceptance Mask Register (L) */
138 #define CAN0_AM20L                  0xFFC00BA0         /* CAN0 Acceptance Mask Register (L) */
139 #define CAN0_AM21L                  0xFFC00BA8         /* CAN0 Acceptance Mask Register (L) */
140 #define CAN0_AM22L                  0xFFC00BB0         /* CAN0 Acceptance Mask Register (L) */
141 #define CAN0_AM23L                  0xFFC00BB8         /* CAN0 Acceptance Mask Register (L) */
142 #define CAN0_AM24L                  0xFFC00BC0         /* CAN0 Acceptance Mask Register (L) */
143 #define CAN0_AM25L                  0xFFC00BC8         /* CAN0 Acceptance Mask Register (L) */
144 #define CAN0_AM26L                  0xFFC00BD0         /* CAN0 Acceptance Mask Register (L) */
145 #define CAN0_AM27L                  0xFFC00BD8         /* CAN0 Acceptance Mask Register (L) */
146 #define CAN0_AM28L                  0xFFC00BE0         /* CAN0 Acceptance Mask Register (L) */
147 #define CAN0_AM29L                  0xFFC00BE8         /* CAN0 Acceptance Mask Register (L) */
148 #define CAN0_AM30L                  0xFFC00BF0         /* CAN0 Acceptance Mask Register (L) */
149 #define CAN0_AM31L                  0xFFC00BF8         /* CAN0 Acceptance Mask Register (L) */
150 #define CAN0_AM00H                  0xFFC00B04         /* CAN0 Acceptance Mask Register (H) */
151 #define CAN0_AM01H                  0xFFC00B0C         /* CAN0 Acceptance Mask Register (H) */
152 #define CAN0_AM02H                  0xFFC00B14         /* CAN0 Acceptance Mask Register (H) */
153 #define CAN0_AM03H                  0xFFC00B1C         /* CAN0 Acceptance Mask Register (H) */
154 #define CAN0_AM04H                  0xFFC00B24         /* CAN0 Acceptance Mask Register (H) */
155 #define CAN0_AM05H                  0xFFC00B2C         /* CAN0 Acceptance Mask Register (H) */
156 #define CAN0_AM06H                  0xFFC00B34         /* CAN0 Acceptance Mask Register (H) */
157 #define CAN0_AM07H                  0xFFC00B3C         /* CAN0 Acceptance Mask Register (H) */
158 #define CAN0_AM08H                  0xFFC00B44         /* CAN0 Acceptance Mask Register (H) */
159 #define CAN0_AM09H                  0xFFC00B4C         /* CAN0 Acceptance Mask Register (H) */
160 #define CAN0_AM10H                  0xFFC00B54         /* CAN0 Acceptance Mask Register (H) */
161 #define CAN0_AM11H                  0xFFC00B5C         /* CAN0 Acceptance Mask Register (H) */
162 #define CAN0_AM12H                  0xFFC00B64         /* CAN0 Acceptance Mask Register (H) */
163 #define CAN0_AM13H                  0xFFC00B6C         /* CAN0 Acceptance Mask Register (H) */
164 #define CAN0_AM14H                  0xFFC00B74         /* CAN0 Acceptance Mask Register (H) */
165 #define CAN0_AM15H                  0xFFC00B7C         /* CAN0 Acceptance Mask Register (H) */
166 #define CAN0_AM16H                  0xFFC00B84         /* CAN0 Acceptance Mask Register (H) */
167 #define CAN0_AM17H                  0xFFC00B8C         /* CAN0 Acceptance Mask Register (H) */
168 #define CAN0_AM18H                  0xFFC00B94         /* CAN0 Acceptance Mask Register (H) */
169 #define CAN0_AM19H                  0xFFC00B9C         /* CAN0 Acceptance Mask Register (H) */
170 #define CAN0_AM20H                  0xFFC00BA4         /* CAN0 Acceptance Mask Register (H) */
171 #define CAN0_AM21H                  0xFFC00BAC         /* CAN0 Acceptance Mask Register (H) */
172 #define CAN0_AM22H                  0xFFC00BB4         /* CAN0 Acceptance Mask Register (H) */
173 #define CAN0_AM23H                  0xFFC00BBC         /* CAN0 Acceptance Mask Register (H) */
174 #define CAN0_AM24H                  0xFFC00BC4         /* CAN0 Acceptance Mask Register (H) */
175 #define CAN0_AM25H                  0xFFC00BCC         /* CAN0 Acceptance Mask Register (H) */
176 #define CAN0_AM26H                  0xFFC00BD4         /* CAN0 Acceptance Mask Register (H) */
177 #define CAN0_AM27H                  0xFFC00BDC         /* CAN0 Acceptance Mask Register (H) */
178 #define CAN0_AM28H                  0xFFC00BE4         /* CAN0 Acceptance Mask Register (H) */
179 #define CAN0_AM29H                  0xFFC00BEC         /* CAN0 Acceptance Mask Register (H) */
180 #define CAN0_AM30H                  0xFFC00BF4         /* CAN0 Acceptance Mask Register (H) */
181 #define CAN0_AM31H                  0xFFC00BFC         /* CAN0 Acceptance Mask Register (H) */
182 #define CAN0_MB00_DATA0             0xFFC00C00         /* CAN0 Mailbox Word 0 Register */
183 #define CAN0_MB01_DATA0             0xFFC00C20         /* CAN0 Mailbox Word 0 Register */
184 #define CAN0_MB02_DATA0             0xFFC00C40         /* CAN0 Mailbox Word 0 Register */
185 #define CAN0_MB03_DATA0             0xFFC00C60         /* CAN0 Mailbox Word 0 Register */
186 #define CAN0_MB04_DATA0             0xFFC00C80         /* CAN0 Mailbox Word 0 Register */
187 #define CAN0_MB05_DATA0             0xFFC00CA0         /* CAN0 Mailbox Word 0 Register */
188 #define CAN0_MB06_DATA0             0xFFC00CC0         /* CAN0 Mailbox Word 0 Register */
189 #define CAN0_MB07_DATA0             0xFFC00CE0         /* CAN0 Mailbox Word 0 Register */
190 #define CAN0_MB08_DATA0             0xFFC00D00         /* CAN0 Mailbox Word 0 Register */
191 #define CAN0_MB09_DATA0             0xFFC00D20         /* CAN0 Mailbox Word 0 Register */
192 #define CAN0_MB10_DATA0             0xFFC00D40         /* CAN0 Mailbox Word 0 Register */
193 #define CAN0_MB11_DATA0             0xFFC00D60         /* CAN0 Mailbox Word 0 Register */
194 #define CAN0_MB12_DATA0             0xFFC00D80         /* CAN0 Mailbox Word 0 Register */
195 #define CAN0_MB13_DATA0             0xFFC00DA0         /* CAN0 Mailbox Word 0 Register */
196 #define CAN0_MB14_DATA0             0xFFC00DC0         /* CAN0 Mailbox Word 0 Register */
197 #define CAN0_MB15_DATA0             0xFFC00DE0         /* CAN0 Mailbox Word 0 Register */
198 #define CAN0_MB16_DATA0             0xFFC00E00         /* CAN0 Mailbox Word 0 Register */
199 #define CAN0_MB17_DATA0             0xFFC00E20         /* CAN0 Mailbox Word 0 Register */
200 #define CAN0_MB18_DATA0             0xFFC00E40         /* CAN0 Mailbox Word 0 Register */
201 #define CAN0_MB19_DATA0             0xFFC00E60         /* CAN0 Mailbox Word 0 Register */
202 #define CAN0_MB20_DATA0             0xFFC00E80         /* CAN0 Mailbox Word 0 Register */
203 #define CAN0_MB21_DATA0             0xFFC00EA0         /* CAN0 Mailbox Word 0 Register */
204 #define CAN0_MB22_DATA0             0xFFC00EC0         /* CAN0 Mailbox Word 0 Register */
205 #define CAN0_MB23_DATA0             0xFFC00EE0         /* CAN0 Mailbox Word 0 Register */
206 #define CAN0_MB24_DATA0             0xFFC00F00         /* CAN0 Mailbox Word 0 Register */
207 #define CAN0_MB25_DATA0             0xFFC00F20         /* CAN0 Mailbox Word 0 Register */
208 #define CAN0_MB26_DATA0             0xFFC00F40         /* CAN0 Mailbox Word 0 Register */
209 #define CAN0_MB27_DATA0             0xFFC00F60         /* CAN0 Mailbox Word 0 Register */
210 #define CAN0_MB28_DATA0             0xFFC00F80         /* CAN0 Mailbox Word 0 Register */
211 #define CAN0_MB29_DATA0             0xFFC00FA0         /* CAN0 Mailbox Word 0 Register */
212 #define CAN0_MB30_DATA0             0xFFC00FC0         /* CAN0 Mailbox Word 0 Register */
213 #define CAN0_MB31_DATA0             0xFFC00FE0         /* CAN0 Mailbox Word 0 Register */
214 #define CAN0_MB00_DATA1             0xFFC00C04         /* CAN0 Mailbox Word 1 Register */
215 #define CAN0_MB01_DATA1             0xFFC00C24         /* CAN0 Mailbox Word 1 Register */
216 #define CAN0_MB02_DATA1             0xFFC00C44         /* CAN0 Mailbox Word 1 Register */
217 #define CAN0_MB03_DATA1             0xFFC00C64         /* CAN0 Mailbox Word 1 Register */
218 #define CAN0_MB04_DATA1             0xFFC00C84         /* CAN0 Mailbox Word 1 Register */
219 #define CAN0_MB05_DATA1             0xFFC00CA4         /* CAN0 Mailbox Word 1 Register */
220 #define CAN0_MB06_DATA1             0xFFC00CC4         /* CAN0 Mailbox Word 1 Register */
221 #define CAN0_MB07_DATA1             0xFFC00CE4         /* CAN0 Mailbox Word 1 Register */
222 #define CAN0_MB08_DATA1             0xFFC00D04         /* CAN0 Mailbox Word 1 Register */
223 #define CAN0_MB09_DATA1             0xFFC00D24         /* CAN0 Mailbox Word 1 Register */
224 #define CAN0_MB10_DATA1             0xFFC00D44         /* CAN0 Mailbox Word 1 Register */
225 #define CAN0_MB11_DATA1             0xFFC00D64         /* CAN0 Mailbox Word 1 Register */
226 #define CAN0_MB12_DATA1             0xFFC00D84         /* CAN0 Mailbox Word 1 Register */
227 #define CAN0_MB13_DATA1             0xFFC00DA4         /* CAN0 Mailbox Word 1 Register */
228 #define CAN0_MB14_DATA1             0xFFC00DC4         /* CAN0 Mailbox Word 1 Register */
229 #define CAN0_MB15_DATA1             0xFFC00DE4         /* CAN0 Mailbox Word 1 Register */
230 #define CAN0_MB16_DATA1             0xFFC00E04         /* CAN0 Mailbox Word 1 Register */
231 #define CAN0_MB17_DATA1             0xFFC00E24         /* CAN0 Mailbox Word 1 Register */
232 #define CAN0_MB18_DATA1             0xFFC00E44         /* CAN0 Mailbox Word 1 Register */
233 #define CAN0_MB19_DATA1             0xFFC00E64         /* CAN0 Mailbox Word 1 Register */
234 #define CAN0_MB20_DATA1             0xFFC00E84         /* CAN0 Mailbox Word 1 Register */
235 #define CAN0_MB21_DATA1             0xFFC00EA4         /* CAN0 Mailbox Word 1 Register */
236 #define CAN0_MB22_DATA1             0xFFC00EC4         /* CAN0 Mailbox Word 1 Register */
237 #define CAN0_MB23_DATA1             0xFFC00EE4         /* CAN0 Mailbox Word 1 Register */
238 #define CAN0_MB24_DATA1             0xFFC00F04         /* CAN0 Mailbox Word 1 Register */
239 #define CAN0_MB25_DATA1             0xFFC00F24         /* CAN0 Mailbox Word 1 Register */
240 #define CAN0_MB26_DATA1             0xFFC00F44         /* CAN0 Mailbox Word 1 Register */
241 #define CAN0_MB27_DATA1             0xFFC00F64         /* CAN0 Mailbox Word 1 Register */
242 #define CAN0_MB28_DATA1             0xFFC00F84         /* CAN0 Mailbox Word 1 Register */
243 #define CAN0_MB29_DATA1             0xFFC00FA4         /* CAN0 Mailbox Word 1 Register */
244 #define CAN0_MB30_DATA1             0xFFC00FC4         /* CAN0 Mailbox Word 1 Register */
245 #define CAN0_MB31_DATA1             0xFFC00FE4         /* CAN0 Mailbox Word 1 Register */
246 #define CAN0_MB00_DATA2             0xFFC00C08         /* CAN0 Mailbox Word 2 Register */
247 #define CAN0_MB01_DATA2             0xFFC00C28         /* CAN0 Mailbox Word 2 Register */
248 #define CAN0_MB02_DATA2             0xFFC00C48         /* CAN0 Mailbox Word 2 Register */
249 #define CAN0_MB03_DATA2             0xFFC00C68         /* CAN0 Mailbox Word 2 Register */
250 #define CAN0_MB04_DATA2             0xFFC00C88         /* CAN0 Mailbox Word 2 Register */
251 #define CAN0_MB05_DATA2             0xFFC00CA8         /* CAN0 Mailbox Word 2 Register */
252 #define CAN0_MB06_DATA2             0xFFC00CC8         /* CAN0 Mailbox Word 2 Register */
253 #define CAN0_MB07_DATA2             0xFFC00CE8         /* CAN0 Mailbox Word 2 Register */
254 #define CAN0_MB08_DATA2             0xFFC00D08         /* CAN0 Mailbox Word 2 Register */
255 #define CAN0_MB09_DATA2             0xFFC00D28         /* CAN0 Mailbox Word 2 Register */
256 #define CAN0_MB10_DATA2             0xFFC00D48         /* CAN0 Mailbox Word 2 Register */
257 #define CAN0_MB11_DATA2             0xFFC00D68         /* CAN0 Mailbox Word 2 Register */
258 #define CAN0_MB12_DATA2             0xFFC00D88         /* CAN0 Mailbox Word 2 Register */
259 #define CAN0_MB13_DATA2             0xFFC00DA8         /* CAN0 Mailbox Word 2 Register */
260 #define CAN0_MB14_DATA2             0xFFC00DC8         /* CAN0 Mailbox Word 2 Register */
261 #define CAN0_MB15_DATA2             0xFFC00DE8         /* CAN0 Mailbox Word 2 Register */
262 #define CAN0_MB16_DATA2             0xFFC00E08         /* CAN0 Mailbox Word 2 Register */
263 #define CAN0_MB17_DATA2             0xFFC00E28         /* CAN0 Mailbox Word 2 Register */
264 #define CAN0_MB18_DATA2             0xFFC00E48         /* CAN0 Mailbox Word 2 Register */
265 #define CAN0_MB19_DATA2             0xFFC00E68         /* CAN0 Mailbox Word 2 Register */
266 #define CAN0_MB20_DATA2             0xFFC00E88         /* CAN0 Mailbox Word 2 Register */
267 #define CAN0_MB21_DATA2             0xFFC00EA8         /* CAN0 Mailbox Word 2 Register */
268 #define CAN0_MB22_DATA2             0xFFC00EC8         /* CAN0 Mailbox Word 2 Register */
269 #define CAN0_MB23_DATA2             0xFFC00EE8         /* CAN0 Mailbox Word 2 Register */
270 #define CAN0_MB24_DATA2             0xFFC00F08         /* CAN0 Mailbox Word 2 Register */
271 #define CAN0_MB25_DATA2             0xFFC00F28         /* CAN0 Mailbox Word 2 Register */
272 #define CAN0_MB26_DATA2             0xFFC00F48         /* CAN0 Mailbox Word 2 Register */
273 #define CAN0_MB27_DATA2             0xFFC00F68         /* CAN0 Mailbox Word 2 Register */
274 #define CAN0_MB28_DATA2             0xFFC00F88         /* CAN0 Mailbox Word 2 Register */
275 #define CAN0_MB29_DATA2             0xFFC00FA8         /* CAN0 Mailbox Word 2 Register */
276 #define CAN0_MB30_DATA2             0xFFC00FC8         /* CAN0 Mailbox Word 2 Register */
277 #define CAN0_MB31_DATA2             0xFFC00FE8         /* CAN0 Mailbox Word 2 Register */
278 #define CAN0_MB00_DATA3             0xFFC00C0C         /* CAN0 Mailbox Word 3 Register */
279 #define CAN0_MB01_DATA3             0xFFC00C2C         /* CAN0 Mailbox Word 3 Register */
280 #define CAN0_MB02_DATA3             0xFFC00C4C         /* CAN0 Mailbox Word 3 Register */
281 #define CAN0_MB03_DATA3             0xFFC00C6C         /* CAN0 Mailbox Word 3 Register */
282 #define CAN0_MB04_DATA3             0xFFC00C8C         /* CAN0 Mailbox Word 3 Register */
283 #define CAN0_MB05_DATA3             0xFFC00CAC         /* CAN0 Mailbox Word 3 Register */
284 #define CAN0_MB06_DATA3             0xFFC00CCC         /* CAN0 Mailbox Word 3 Register */
285 #define CAN0_MB07_DATA3             0xFFC00CEC         /* CAN0 Mailbox Word 3 Register */
286 #define CAN0_MB08_DATA3             0xFFC00D0C         /* CAN0 Mailbox Word 3 Register */
287 #define CAN0_MB09_DATA3             0xFFC00D2C         /* CAN0 Mailbox Word 3 Register */
288 #define CAN0_MB10_DATA3             0xFFC00D4C         /* CAN0 Mailbox Word 3 Register */
289 #define CAN0_MB11_DATA3             0xFFC00D6C         /* CAN0 Mailbox Word 3 Register */
290 #define CAN0_MB12_DATA3             0xFFC00D8C         /* CAN0 Mailbox Word 3 Register */
291 #define CAN0_MB13_DATA3             0xFFC00DAC         /* CAN0 Mailbox Word 3 Register */
292 #define CAN0_MB14_DATA3             0xFFC00DCC         /* CAN0 Mailbox Word 3 Register */
293 #define CAN0_MB15_DATA3             0xFFC00DEC         /* CAN0 Mailbox Word 3 Register */
294 #define CAN0_MB16_DATA3             0xFFC00E0C         /* CAN0 Mailbox Word 3 Register */
295 #define CAN0_MB17_DATA3             0xFFC00E2C         /* CAN0 Mailbox Word 3 Register */
296 #define CAN0_MB18_DATA3             0xFFC00E4C         /* CAN0 Mailbox Word 3 Register */
297 #define CAN0_MB19_DATA3             0xFFC00E6C         /* CAN0 Mailbox Word 3 Register */
298 #define CAN0_MB20_DATA3             0xFFC00E8C         /* CAN0 Mailbox Word 3 Register */
299 #define CAN0_MB21_DATA3             0xFFC00EAC         /* CAN0 Mailbox Word 3 Register */
300 #define CAN0_MB22_DATA3             0xFFC00ECC         /* CAN0 Mailbox Word 3 Register */
301 #define CAN0_MB23_DATA3             0xFFC00EEC         /* CAN0 Mailbox Word 3 Register */
302 #define CAN0_MB24_DATA3             0xFFC00F0C         /* CAN0 Mailbox Word 3 Register */
303 #define CAN0_MB25_DATA3             0xFFC00F2C         /* CAN0 Mailbox Word 3 Register */
304 #define CAN0_MB26_DATA3             0xFFC00F4C         /* CAN0 Mailbox Word 3 Register */
305 #define CAN0_MB27_DATA3             0xFFC00F6C         /* CAN0 Mailbox Word 3 Register */
306 #define CAN0_MB28_DATA3             0xFFC00F8C         /* CAN0 Mailbox Word 3 Register */
307 #define CAN0_MB29_DATA3             0xFFC00FAC         /* CAN0 Mailbox Word 3 Register */
308 #define CAN0_MB30_DATA3             0xFFC00FCC         /* CAN0 Mailbox Word 3 Register */
309 #define CAN0_MB31_DATA3             0xFFC00FEC         /* CAN0 Mailbox Word 3 Register */
310 #define CAN0_MB00_LENGTH            0xFFC00C10         /* CAN0 Mailbox Word 4 Register */
311 #define CAN0_MB01_LENGTH            0xFFC00C30         /* CAN0 Mailbox Word 4 Register */
312 #define CAN0_MB02_LENGTH            0xFFC00C50         /* CAN0 Mailbox Word 4 Register */
313 #define CAN0_MB03_LENGTH            0xFFC00C70         /* CAN0 Mailbox Word 4 Register */
314 #define CAN0_MB04_LENGTH            0xFFC00C90         /* CAN0 Mailbox Word 4 Register */
315 #define CAN0_MB05_LENGTH            0xFFC00CB0         /* CAN0 Mailbox Word 4 Register */
316 #define CAN0_MB06_LENGTH            0xFFC00CD0         /* CAN0 Mailbox Word 4 Register */
317 #define CAN0_MB07_LENGTH            0xFFC00CF0         /* CAN0 Mailbox Word 4 Register */
318 #define CAN0_MB08_LENGTH            0xFFC00D10         /* CAN0 Mailbox Word 4 Register */
319 #define CAN0_MB09_LENGTH            0xFFC00D30         /* CAN0 Mailbox Word 4 Register */
320 #define CAN0_MB10_LENGTH            0xFFC00D50         /* CAN0 Mailbox Word 4 Register */
321 #define CAN0_MB11_LENGTH            0xFFC00D70         /* CAN0 Mailbox Word 4 Register */
322 #define CAN0_MB12_LENGTH            0xFFC00D90         /* CAN0 Mailbox Word 4 Register */
323 #define CAN0_MB13_LENGTH            0xFFC00DB0         /* CAN0 Mailbox Word 4 Register */
324 #define CAN0_MB14_LENGTH            0xFFC00DD0         /* CAN0 Mailbox Word 4 Register */
325 #define CAN0_MB15_LENGTH            0xFFC00DF0         /* CAN0 Mailbox Word 4 Register */
326 #define CAN0_MB16_LENGTH            0xFFC00E10         /* CAN0 Mailbox Word 4 Register */
327 #define CAN0_MB17_LENGTH            0xFFC00E30         /* CAN0 Mailbox Word 4 Register */
328 #define CAN0_MB18_LENGTH            0xFFC00E50         /* CAN0 Mailbox Word 4 Register */
329 #define CAN0_MB19_LENGTH            0xFFC00E70         /* CAN0 Mailbox Word 4 Register */
330 #define CAN0_MB20_LENGTH            0xFFC00E90         /* CAN0 Mailbox Word 4 Register */
331 #define CAN0_MB21_LENGTH            0xFFC00EB0         /* CAN0 Mailbox Word 4 Register */
332 #define CAN0_MB22_LENGTH            0xFFC00ED0         /* CAN0 Mailbox Word 4 Register */
333 #define CAN0_MB23_LENGTH            0xFFC00EF0         /* CAN0 Mailbox Word 4 Register */
334 #define CAN0_MB24_LENGTH            0xFFC00F10         /* CAN0 Mailbox Word 4 Register */
335 #define CAN0_MB25_LENGTH            0xFFC00F30         /* CAN0 Mailbox Word 4 Register */
336 #define CAN0_MB26_LENGTH            0xFFC00F50         /* CAN0 Mailbox Word 4 Register */
337 #define CAN0_MB27_LENGTH            0xFFC00F70         /* CAN0 Mailbox Word 4 Register */
338 #define CAN0_MB28_LENGTH            0xFFC00F90         /* CAN0 Mailbox Word 4 Register */
339 #define CAN0_MB29_LENGTH            0xFFC00FB0         /* CAN0 Mailbox Word 4 Register */
340 #define CAN0_MB30_LENGTH            0xFFC00FD0         /* CAN0 Mailbox Word 4 Register */
341 #define CAN0_MB31_LENGTH            0xFFC00FF0         /* CAN0 Mailbox Word 4 Register */
342 #define CAN0_MB00_TIMESTAMP         0xFFC00C14         /* CAN0 Mailbox Word 5 Register */
343 #define CAN0_MB01_TIMESTAMP         0xFFC00C34         /* CAN0 Mailbox Word 5 Register */
344 #define CAN0_MB02_TIMESTAMP         0xFFC00C54         /* CAN0 Mailbox Word 5 Register */
345 #define CAN0_MB03_TIMESTAMP         0xFFC00C74         /* CAN0 Mailbox Word 5 Register */
346 #define CAN0_MB04_TIMESTAMP         0xFFC00C94         /* CAN0 Mailbox Word 5 Register */
347 #define CAN0_MB05_TIMESTAMP         0xFFC00CB4         /* CAN0 Mailbox Word 5 Register */
348 #define CAN0_MB06_TIMESTAMP         0xFFC00CD4         /* CAN0 Mailbox Word 5 Register */
349 #define CAN0_MB07_TIMESTAMP         0xFFC00CF4         /* CAN0 Mailbox Word 5 Register */
350 #define CAN0_MB08_TIMESTAMP         0xFFC00D14         /* CAN0 Mailbox Word 5 Register */
351 #define CAN0_MB09_TIMESTAMP         0xFFC00D34         /* CAN0 Mailbox Word 5 Register */
352 #define CAN0_MB10_TIMESTAMP         0xFFC00D54         /* CAN0 Mailbox Word 5 Register */
353 #define CAN0_MB11_TIMESTAMP         0xFFC00D74         /* CAN0 Mailbox Word 5 Register */
354 #define CAN0_MB12_TIMESTAMP         0xFFC00D94         /* CAN0 Mailbox Word 5 Register */
355 #define CAN0_MB13_TIMESTAMP         0xFFC00DB4         /* CAN0 Mailbox Word 5 Register */
356 #define CAN0_MB14_TIMESTAMP         0xFFC00DD4         /* CAN0 Mailbox Word 5 Register */
357 #define CAN0_MB15_TIMESTAMP         0xFFC00DF4         /* CAN0 Mailbox Word 5 Register */
358 #define CAN0_MB16_TIMESTAMP         0xFFC00E14         /* CAN0 Mailbox Word 5 Register */
359 #define CAN0_MB17_TIMESTAMP         0xFFC00E34         /* CAN0 Mailbox Word 5 Register */
360 #define CAN0_MB18_TIMESTAMP         0xFFC00E54         /* CAN0 Mailbox Word 5 Register */
361 #define CAN0_MB19_TIMESTAMP         0xFFC00E74         /* CAN0 Mailbox Word 5 Register */
362 #define CAN0_MB20_TIMESTAMP         0xFFC00E94         /* CAN0 Mailbox Word 5 Register */
363 #define CAN0_MB21_TIMESTAMP         0xFFC00EB4         /* CAN0 Mailbox Word 5 Register */
364 #define CAN0_MB22_TIMESTAMP         0xFFC00ED4         /* CAN0 Mailbox Word 5 Register */
365 #define CAN0_MB23_TIMESTAMP         0xFFC00EF4         /* CAN0 Mailbox Word 5 Register */
366 #define CAN0_MB24_TIMESTAMP         0xFFC00F14         /* CAN0 Mailbox Word 5 Register */
367 #define CAN0_MB25_TIMESTAMP         0xFFC00F34         /* CAN0 Mailbox Word 5 Register */
368 #define CAN0_MB26_TIMESTAMP         0xFFC00F54         /* CAN0 Mailbox Word 5 Register */
369 #define CAN0_MB27_TIMESTAMP         0xFFC00F74         /* CAN0 Mailbox Word 5 Register */
370 #define CAN0_MB28_TIMESTAMP         0xFFC00F94         /* CAN0 Mailbox Word 5 Register */
371 #define CAN0_MB29_TIMESTAMP         0xFFC00FB4         /* CAN0 Mailbox Word 5 Register */
372 #define CAN0_MB30_TIMESTAMP         0xFFC00FD4         /* CAN0 Mailbox Word 5 Register */
373 #define CAN0_MB31_TIMESTAMP         0xFFC00FF4         /* CAN0 Mailbox Word 5 Register */
374 #define CAN0_MB00_ID0               0xFFC00C18         /* CAN0 Mailbox Word 6 Register */
375 #define CAN0_MB01_ID0               0xFFC00C38         /* CAN0 Mailbox Word 6 Register */
376 #define CAN0_MB02_ID0               0xFFC00C58         /* CAN0 Mailbox Word 6 Register */
377 #define CAN0_MB03_ID0               0xFFC00C78         /* CAN0 Mailbox Word 6 Register */
378 #define CAN0_MB04_ID0               0xFFC00C98         /* CAN0 Mailbox Word 6 Register */
379 #define CAN0_MB05_ID0               0xFFC00CB8         /* CAN0 Mailbox Word 6 Register */
380 #define CAN0_MB06_ID0               0xFFC00CD8         /* CAN0 Mailbox Word 6 Register */
381 #define CAN0_MB07_ID0               0xFFC00CF8         /* CAN0 Mailbox Word 6 Register */
382 #define CAN0_MB08_ID0               0xFFC00D18         /* CAN0 Mailbox Word 6 Register */
383 #define CAN0_MB09_ID0               0xFFC00D38         /* CAN0 Mailbox Word 6 Register */
384 #define CAN0_MB10_ID0               0xFFC00D58         /* CAN0 Mailbox Word 6 Register */
385 #define CAN0_MB11_ID0               0xFFC00D78         /* CAN0 Mailbox Word 6 Register */
386 #define CAN0_MB12_ID0               0xFFC00D98         /* CAN0 Mailbox Word 6 Register */
387 #define CAN0_MB13_ID0               0xFFC00DB8         /* CAN0 Mailbox Word 6 Register */
388 #define CAN0_MB14_ID0               0xFFC00DD8         /* CAN0 Mailbox Word 6 Register */
389 #define CAN0_MB15_ID0               0xFFC00DF8         /* CAN0 Mailbox Word 6 Register */
390 #define CAN0_MB16_ID0               0xFFC00E18         /* CAN0 Mailbox Word 6 Register */
391 #define CAN0_MB17_ID0               0xFFC00E38         /* CAN0 Mailbox Word 6 Register */
392 #define CAN0_MB18_ID0               0xFFC00E58         /* CAN0 Mailbox Word 6 Register */
393 #define CAN0_MB19_ID0               0xFFC00E78         /* CAN0 Mailbox Word 6 Register */
394 #define CAN0_MB20_ID0               0xFFC00E98         /* CAN0 Mailbox Word 6 Register */
395 #define CAN0_MB21_ID0               0xFFC00EB8         /* CAN0 Mailbox Word 6 Register */
396 #define CAN0_MB22_ID0               0xFFC00ED8         /* CAN0 Mailbox Word 6 Register */
397 #define CAN0_MB23_ID0               0xFFC00EF8         /* CAN0 Mailbox Word 6 Register */
398 #define CAN0_MB24_ID0               0xFFC00F18         /* CAN0 Mailbox Word 6 Register */
399 #define CAN0_MB25_ID0               0xFFC00F38         /* CAN0 Mailbox Word 6 Register */
400 #define CAN0_MB26_ID0               0xFFC00F58         /* CAN0 Mailbox Word 6 Register */
401 #define CAN0_MB27_ID0               0xFFC00F78         /* CAN0 Mailbox Word 6 Register */
402 #define CAN0_MB28_ID0               0xFFC00F98         /* CAN0 Mailbox Word 6 Register */
403 #define CAN0_MB29_ID0               0xFFC00FB8         /* CAN0 Mailbox Word 6 Register */
404 #define CAN0_MB30_ID0               0xFFC00FD8         /* CAN0 Mailbox Word 6 Register */
405 #define CAN0_MB31_ID0               0xFFC00FF8         /* CAN0 Mailbox Word 6 Register */
406 #define CAN0_MB00_ID1               0xFFC00C1C         /* CAN0 Mailbox Word 7 Register */
407 #define CAN0_MB01_ID1               0xFFC00C3C         /* CAN0 Mailbox Word 7 Register */
408 #define CAN0_MB02_ID1               0xFFC00C5C         /* CAN0 Mailbox Word 7 Register */
409 #define CAN0_MB03_ID1               0xFFC00C7C         /* CAN0 Mailbox Word 7 Register */
410 #define CAN0_MB04_ID1               0xFFC00C9C         /* CAN0 Mailbox Word 7 Register */
411 #define CAN0_MB05_ID1               0xFFC00CBC         /* CAN0 Mailbox Word 7 Register */
412 #define CAN0_MB06_ID1               0xFFC00CDC         /* CAN0 Mailbox Word 7 Register */
413 #define CAN0_MB07_ID1               0xFFC00CFC         /* CAN0 Mailbox Word 7 Register */
414 #define CAN0_MB08_ID1               0xFFC00D1C         /* CAN0 Mailbox Word 7 Register */
415 #define CAN0_MB09_ID1               0xFFC00D3C         /* CAN0 Mailbox Word 7 Register */
416 #define CAN0_MB10_ID1               0xFFC00D5C         /* CAN0 Mailbox Word 7 Register */
417 #define CAN0_MB11_ID1               0xFFC00D7C         /* CAN0 Mailbox Word 7 Register */
418 #define CAN0_MB12_ID1               0xFFC00D9C         /* CAN0 Mailbox Word 7 Register */
419 #define CAN0_MB13_ID1               0xFFC00DBC         /* CAN0 Mailbox Word 7 Register */
420 #define CAN0_MB14_ID1               0xFFC00DDC         /* CAN0 Mailbox Word 7 Register */
421 #define CAN0_MB15_ID1               0xFFC00DFC         /* CAN0 Mailbox Word 7 Register */
422 #define CAN0_MB16_ID1               0xFFC00E1C         /* CAN0 Mailbox Word 7 Register */
423 #define CAN0_MB17_ID1               0xFFC00E3C         /* CAN0 Mailbox Word 7 Register */
424 #define CAN0_MB18_ID1               0xFFC00E5C         /* CAN0 Mailbox Word 7 Register */
425 #define CAN0_MB19_ID1               0xFFC00E7C         /* CAN0 Mailbox Word 7 Register */
426 #define CAN0_MB20_ID1               0xFFC00E9C         /* CAN0 Mailbox Word 7 Register */
427 #define CAN0_MB21_ID1               0xFFC00EBC         /* CAN0 Mailbox Word 7 Register */
428 #define CAN0_MB22_ID1               0xFFC00EDC         /* CAN0 Mailbox Word 7 Register */
429 #define CAN0_MB23_ID1               0xFFC00EFC         /* CAN0 Mailbox Word 7 Register */
430 #define CAN0_MB24_ID1               0xFFC00F1C         /* CAN0 Mailbox Word 7 Register */
431 #define CAN0_MB25_ID1               0xFFC00F3C         /* CAN0 Mailbox Word 7 Register */
432 #define CAN0_MB26_ID1               0xFFC00F5C         /* CAN0 Mailbox Word 7 Register */
433 #define CAN0_MB27_ID1               0xFFC00F7C         /* CAN0 Mailbox Word 7 Register */
434 #define CAN0_MB28_ID1               0xFFC00F9C         /* CAN0 Mailbox Word 7 Register */
435 #define CAN0_MB29_ID1               0xFFC00FBC         /* CAN0 Mailbox Word 7 Register */
436 #define CAN0_MB30_ID1               0xFFC00FDC         /* CAN0 Mailbox Word 7 Register */
437 #define CAN0_MB31_ID1               0xFFC00FFC         /* CAN0 Mailbox Word 7 Register */
438 
439 /* =========================
440 	LINK PORT Registers
441    ========================= */
442 #define LP0_CTL                     0xFFC01000         /* LP0 Control Register */
443 #define LP0_STAT                    0xFFC01004         /* LP0 Status Register */
444 #define LP0_DIV                     0xFFC01008         /* LP0 Clock Divider Value */
445 #define LP0_CNT                     0xFFC0100C         /* LP0 Current Count Value of Clock Divider */
446 #define LP0_TX                      0xFFC01010         /* LP0 Transmit Buffer */
447 #define LP0_RX                      0xFFC01014         /* LP0 Receive Buffer */
448 #define LP0_TXIN_SHDW               0xFFC01018         /* LP0 Shadow Input Transmit Buffer */
449 #define LP0_TXOUT_SHDW              0xFFC0101C         /* LP0 Shadow Output Transmit Buffer */
450 #define LP1_CTL                     0xFFC01100         /* LP1 Control Register */
451 #define LP1_STAT                    0xFFC01104         /* LP1 Status Register */
452 #define LP1_DIV                     0xFFC01108         /* LP1 Clock Divider Value */
453 #define LP1_CNT                     0xFFC0110C         /* LP1 Current Count Value of Clock Divider */
454 #define LP1_TX                      0xFFC01110         /* LP1 Transmit Buffer */
455 #define LP1_RX                      0xFFC01114         /* LP1 Receive Buffer */
456 #define LP1_TXIN_SHDW               0xFFC01118         /* LP1 Shadow Input Transmit Buffer */
457 #define LP1_TXOUT_SHDW              0xFFC0111C         /* LP1 Shadow Output Transmit Buffer */
458 #define LP2_CTL                     0xFFC01200         /* LP2 Control Register */
459 #define LP2_STAT                    0xFFC01204         /* LP2 Status Register */
460 #define LP2_DIV                     0xFFC01208         /* LP2 Clock Divider Value */
461 #define LP2_CNT                     0xFFC0120C         /* LP2 Current Count Value of Clock Divider */
462 #define LP2_TX                      0xFFC01210         /* LP2 Transmit Buffer */
463 #define LP2_RX                      0xFFC01214         /* LP2 Receive Buffer */
464 #define LP2_TXIN_SHDW               0xFFC01218         /* LP2 Shadow Input Transmit Buffer */
465 #define LP2_TXOUT_SHDW              0xFFC0121C         /* LP2 Shadow Output Transmit Buffer */
466 #define LP3_CTL                     0xFFC01300         /* LP3 Control Register */
467 #define LP3_STAT                    0xFFC01304         /* LP3 Status Register */
468 #define LP3_DIV                     0xFFC01308         /* LP3 Clock Divider Value */
469 #define LP3_CNT                     0xFFC0130C         /* LP3 Current Count Value of Clock Divider */
470 #define LP3_TX                      0xFFC01310         /* LP3 Transmit Buffer */
471 #define LP3_RX                      0xFFC01314         /* LP3 Receive Buffer */
472 #define LP3_TXIN_SHDW               0xFFC01318         /* LP3 Shadow Input Transmit Buffer */
473 #define LP3_TXOUT_SHDW              0xFFC0131C         /* LP3 Shadow Output Transmit Buffer */
474 
475 /* =========================
476         TIMER Registers
477    ========================= */
478 #define TIMER_REVID                0xFFC01400         /* GPTIMER Timer IP Version ID */
479 #define TIMER_RUN                  0xFFC01404         /* GPTIMER Timer Run Register */
480 #define TIMER_RUN_SET              0xFFC01408         /* GPTIMER Run Register Alias to Set */
481 #define TIMER_RUN_CLR              0xFFC0140C         /* GPTIMER Run Register Alias to Clear */
482 #define TIMER_STOP_CFG             0xFFC01410         /* GPTIMER Stop Config Register */
483 #define TIMER_STOP_CFG_SET         0xFFC01414         /* GPTIMER Stop Config Alias to Set */
484 #define TIMER_STOP_CFG_CLR         0xFFC01418         /* GPTIMER Stop Config Alias to Clear */
485 #define TIMER_DATA_IMSK            0xFFC0141C         /* GPTIMER Data Interrupt Mask register */
486 #define TIMER_STAT_IMSK            0xFFC01420         /* GPTIMER Status Interrupt Mask register */
487 #define TIMER_TRG_MSK              0xFFC01424         /* GPTIMER Output Trigger Mask register */
488 #define TIMER_TRG_IE               0xFFC01428         /* GPTIMER Slave Trigger Enable register */
489 #define TIMER_DATA_ILAT            0xFFC0142C         /* GPTIMER Data Interrupt Register */
490 #define TIMER_STAT_ILAT            0xFFC01430         /* GPTIMER Status (Error) Interrupt Register */
491 #define TIMER_ERR_TYPE             0xFFC01434         /* GPTIMER Register Indicating Type of Error */
492 #define TIMER_BCAST_PER            0xFFC01438         /* GPTIMER Broadcast Period */
493 #define TIMER_BCAST_WID            0xFFC0143C         /* GPTIMER Broadcast Width */
494 #define TIMER_BCAST_DLY            0xFFC01440         /* GPTIMER Broadcast Delay */
495 
496 /* =========================
497 	TIMER0~7
498    ========================= */
499 #define TIMER0_CONFIG             0xFFC01460         /* TIMER0 Per Timer Config Register */
500 #define TIMER0_COUNTER            0xFFC01464         /* TIMER0 Per Timer Counter Register */
501 #define TIMER0_PERIOD             0xFFC01468         /* TIMER0 Per Timer Period Register */
502 #define TIMER0_WIDTH              0xFFC0146C         /* TIMER0 Per Timer Width Register */
503 #define TIMER0_DELAY              0xFFC01470         /* TIMER0 Per Timer Delay Register */
504 
505 #define TIMER1_CONFIG             0xFFC01480         /* TIMER1 Per Timer Config Register */
506 #define TIMER1_COUNTER            0xFFC01484         /* TIMER1 Per Timer Counter Register */
507 #define TIMER1_PERIOD             0xFFC01488         /* TIMER1 Per Timer Period Register */
508 #define TIMER1_WIDTH              0xFFC0148C         /* TIMER1 Per Timer Width Register */
509 #define TIMER1_DELAY              0xFFC01490         /* TIMER1 Per Timer Delay Register */
510 
511 #define TIMER2_CONFIG             0xFFC014A0         /* TIMER2 Per Timer Config Register */
512 #define TIMER2_COUNTER            0xFFC014A4         /* TIMER2 Per Timer Counter Register */
513 #define TIMER2_PERIOD             0xFFC014A8         /* TIMER2 Per Timer Period Register */
514 #define TIMER2_WIDTH              0xFFC014AC         /* TIMER2 Per Timer Width Register */
515 #define TIMER2_DELAY              0xFFC014B0         /* TIMER2 Per Timer Delay Register */
516 
517 #define TIMER3_CONFIG             0xFFC014C0         /* TIMER3 Per Timer Config Register */
518 #define TIMER3_COUNTER            0xFFC014C4         /* TIMER3 Per Timer Counter Register */
519 #define TIMER3_PERIOD             0xFFC014C8         /* TIMER3 Per Timer Period Register */
520 #define TIMER3_WIDTH              0xFFC014CC         /* TIMER3 Per Timer Width Register */
521 #define TIMER3_DELAY              0xFFC014D0         /* TIMER3 Per Timer Delay Register */
522 
523 #define TIMER4_CONFIG             0xFFC014E0         /* TIMER4 Per Timer Config Register */
524 #define TIMER4_COUNTER            0xFFC014E4         /* TIMER4 Per Timer Counter Register */
525 #define TIMER4_PERIOD             0xFFC014E8         /* TIMER4 Per Timer Period Register */
526 #define TIMER4_WIDTH              0xFFC014EC         /* TIMER4 Per Timer Width Register */
527 #define TIMER4_DELAY              0xFFC014F0         /* TIMER4 Per Timer Delay Register */
528 
529 #define TIMER5_CONFIG             0xFFC01500         /* TIMER5 Per Timer Config Register */
530 #define TIMER5_COUNTER            0xFFC01504         /* TIMER5 Per Timer Counter Register */
531 #define TIMER5_PERIOD             0xFFC01508         /* TIMER5 Per Timer Period Register */
532 #define TIMER5_WIDTH              0xFFC0150C         /* TIMER5 Per Timer Width Register */
533 #define TIMER5_DELAY              0xFFC01510         /* TIMER5 Per Timer Delay Register */
534 
535 #define TIMER6_CONFIG             0xFFC01520         /* TIMER6 Per Timer Config Register */
536 #define TIMER6_COUNTER            0xFFC01524         /* TIMER6 Per Timer Counter Register */
537 #define TIMER6_PERIOD             0xFFC01528         /* TIMER6 Per Timer Period Register */
538 #define TIMER6_WIDTH              0xFFC0152C         /* TIMER6 Per Timer Width Register */
539 #define TIMER6_DELAY              0xFFC01530         /* TIMER6 Per Timer Delay Register */
540 
541 #define TIMER7_CONFIG             0xFFC01540         /* TIMER7 Per Timer Config Register */
542 #define TIMER7_COUNTER            0xFFC01544         /* TIMER7 Per Timer Counter Register */
543 #define TIMER7_PERIOD             0xFFC01548         /* TIMER7 Per Timer Period Register */
544 #define TIMER7_WIDTH              0xFFC0154C         /* TIMER7 Per Timer Width Register */
545 #define TIMER7_DELAY              0xFFC01550         /* TIMER7 Per Timer Delay Register */
546 
547 /* =========================
548 	CRC Registers
549    ========================= */
550 
551 /* =========================
552 	CRC0
553    ========================= */
554 #define REG_CRC0_CTL                    0xFFC01C00         /* CRC0 Control Register */
555 #define REG_CRC0_DCNT                   0xFFC01C04         /* CRC0 Data Word Count Register */
556 #define REG_CRC0_DCNTRLD                0xFFC01C08         /* CRC0 Data Word Count Reload Register */
557 #define REG_CRC0_COMP                   0xFFC01C14         /* CRC0 DATA Compare Register */
558 #define REG_CRC0_FILLVAL                0xFFC01C18         /* CRC0 Fill Value Register */
559 #define REG_CRC0_DFIFO                  0xFFC01C1C         /* CRC0 DATA FIFO Register */
560 #define REG_CRC0_INEN                   0xFFC01C20         /* CRC0 Interrupt Enable Register */
561 #define REG_CRC0_INEN_SET               0xFFC01C24         /* CRC0 Interrupt Enable Set Register */
562 #define REG_CRC0_INEN_CLR               0xFFC01C28         /* CRC0 Interrupt Enable Clear Register */
563 #define REG_CRC0_POLY                   0xFFC01C2C         /* CRC0 Polynomial Register */
564 #define REG_CRC0_STAT                   0xFFC01C40         /* CRC0 Status Register */
565 #define REG_CRC0_DCNTCAP                0xFFC01C44         /* CRC0 DATA Count Capture Register */
566 #define REG_CRC0_RESULT_FIN             0xFFC01C4C         /* CRC0 Final CRC Result Register */
567 #define REG_CRC0_RESULT_CUR             0xFFC01C50         /* CRC0 Current CRC Result Register */
568 #define REG_CRC0_REVID                  0xFFC01C60         /* CRC0 Revision ID Register */
569 
570 /* =========================
571 	CRC1
572    ========================= */
573 #define REG_CRC1_CTL                    0xFFC01D00         /* CRC1 Control Register */
574 #define REG_CRC1_DCNT                   0xFFC01D04         /* CRC1 Data Word Count Register */
575 #define REG_CRC1_DCNTRLD                0xFFC01D08         /* CRC1 Data Word Count Reload Register */
576 #define REG_CRC1_COMP                   0xFFC01D14         /* CRC1 DATA Compare Register */
577 #define REG_CRC1_FILLVAL                0xFFC01D18         /* CRC1 Fill Value Register */
578 #define REG_CRC1_DFIFO                  0xFFC01D1C         /* CRC1 DATA FIFO Register */
579 #define REG_CRC1_INEN                   0xFFC01D20         /* CRC1 Interrupt Enable Register */
580 #define REG_CRC1_INEN_SET               0xFFC01D24         /* CRC1 Interrupt Enable Set Register */
581 #define REG_CRC1_INEN_CLR               0xFFC01D28         /* CRC1 Interrupt Enable Clear Register */
582 #define REG_CRC1_POLY                   0xFFC01D2C         /* CRC1 Polynomial Register */
583 #define REG_CRC1_STAT                   0xFFC01D40         /* CRC1 Status Register */
584 #define REG_CRC1_DCNTCAP                0xFFC01D44         /* CRC1 DATA Count Capture Register */
585 #define REG_CRC1_RESULT_FIN             0xFFC01D4C         /* CRC1 Final CRC Result Register */
586 #define REG_CRC1_RESULT_CUR             0xFFC01D50         /* CRC1 Current CRC Result Register */
587 #define REG_CRC1_REVID                  0xFFC01D60         /* CRC1 Revision ID Register */
588 
589 /* =========================
590         TWI Registers
591    ========================= */
592 
593 /* =========================
594         TWI0
595    ========================= */
596 #define TWI0_CLKDIV                    0xFFC01E00         /* TWI0 SCL Clock Divider */
597 #define TWI0_CONTROL                   0xFFC01E04         /* TWI0 Control Register */
598 #define TWI0_SLAVE_CTL                 0xFFC01E08         /* TWI0 Slave Mode Control Register */
599 #define TWI0_SLAVE_STAT                0xFFC01E0C         /* TWI0 Slave Mode Status Register */
600 #define TWI0_SLAVE_ADDR                0xFFC01E10         /* TWI0 Slave Mode Address Register */
601 #define TWI0_MASTER_CTL                0xFFC01E14         /* TWI0 Master Mode Control Registers */
602 #define TWI0_MASTER_STAT               0xFFC01E18         /* TWI0 Master Mode Status Register */
603 #define TWI0_MASTER_ADDR               0xFFC01E1C         /* TWI0 Master Mode Address Register */
604 #define TWI0_INT_STAT                  0xFFC01E20         /* TWI0 Interrupt Status Register */
605 #define TWI0_INT_MASK                  0xFFC01E24         /* TWI0 Interrupt Mask Register */
606 #define TWI0_FIFO_CTL                  0xFFC01E28         /* TWI0 FIFO Control Register */
607 #define TWI0_FIFO_STAT                 0xFFC01E2C         /* TWI0 FIFO Status Register */
608 #define TWI0_XMT_DATA8                 0xFFC01E80         /* TWI0 FIFO Transmit Data Single-Byte Register */
609 #define TWI0_XMT_DATA16                0xFFC01E84         /* TWI0 FIFO Transmit Data Double-Byte Register */
610 #define TWI0_RCV_DATA8                 0xFFC01E88         /* TWI0 FIFO Transmit Data Single-Byte Register */
611 #define TWI0_RCV_DATA16                0xFFC01E8C         /* TWI0 FIFO Transmit Data Double-Byte Register */
612 
613 /* =========================
614         TWI1
615    ========================= */
616 #define TWI1_CLKDIV                 0xFFC01F00         /* TWI1 SCL Clock Divider */
617 #define TWI1_CONTROL                    0xFFC01F04         /* TWI1 Control Register */
618 #define TWI1_SLAVE_CTL                 0xFFC01F08         /* TWI1 Slave Mode Control Register */
619 #define TWI1_SLAVE_STAT                0xFFC01F0C         /* TWI1 Slave Mode Status Register */
620 #define TWI1_SLAVE_ADDR                0xFFC01F10         /* TWI1 Slave Mode Address Register */
621 #define TWI1_MASTER_CTL                0xFFC01F14         /* TWI1 Master Mode Control Registers */
622 #define TWI1_MASTER_STAT               0xFFC01F18         /* TWI1 Master Mode Status Register */
623 #define TWI1_MASTER_ADDR               0xFFC01F1C         /* TWI1 Master Mode Address Register */
624 #define TWI1_INT_STAT                  0xFFC01F20         /* TWI1 Interrupt Status Register */
625 #define TWI1_INT_MASK                   0xFFC01F24         /* TWI1 Interrupt Mask Register */
626 #define TWI1_FIFO_CTL                0xFFC01F28         /* TWI1 FIFO Control Register */
627 #define TWI1_FIFO_STAT               0xFFC01F2C         /* TWI1 FIFO Status Register */
628 #define TWI1_XMT_DATA8                0xFFC01F80         /* TWI1 FIFO Transmit Data Single-Byte Register */
629 #define TWI1_XMT_DATA16               0xFFC01F84         /* TWI1 FIFO Transmit Data Double-Byte Register */
630 #define TWI1_RCV_DATA8                0xFFC01F88         /* TWI1 FIFO Transmit Data Single-Byte Register */
631 #define TWI1_RCV_DATA16               0xFFC01F8C         /* TWI1 FIFO Transmit Data Double-Byte Register */
632 
633 
634 /* =========================
635         UART Registers
636    ========================= */
637 
638 /* =========================
639         UART0
640    ========================= */
641 #define UART0_REVID                 0xFFC02000         /* UART0 Revision ID Register */
642 #define UART0_CTL                   0xFFC02004         /* UART0 Control Register */
643 #define UART0_STAT                  0xFFC02008         /* UART0 Status Register */
644 #define UART0_SCR                   0xFFC0200C         /* UART0 Scratch Register */
645 #define UART0_CLK                   0xFFC02010         /* UART0 Clock Rate Register */
646 #define UART0_IER                   0xFFC02014         /* UART0 Interrupt Mask Register */
647 #define UART0_IER_SET               0xFFC02018         /* UART0 Interrupt Mask Set Register */
648 #define UART0_IER_CLR               0xFFC0201C         /* UART0 Interrupt Mask Clear Register */
649 #define UART0_RBR                   0xFFC02020         /* UART0 Receive Buffer Register */
650 #define UART0_THR                   0xFFC02024         /* UART0 Transmit Hold Register */
651 #define UART0_TAIP                  0xFFC02028         /* UART0 Transmit Address/Insert Pulse Register */
652 #define UART0_TSR                   0xFFC0202C         /* UART0 Transmit Shift Register */
653 #define UART0_RSR                   0xFFC02030         /* UART0 Receive Shift Register */
654 #define UART0_TXDIV                 0xFFC02034         /* UART0 Transmit Clock Devider Register */
655 #define UART0_RXDIV                 0xFFC02038         /* UART0 Receive Clock Devider Register */
656 
657 /* =========================
658         UART1
659    ========================= */
660 #define UART1_REVID                 0xFFC02400         /* UART1 Revision ID Register */
661 #define UART1_CTL                   0xFFC02404         /* UART1 Control Register */
662 #define UART1_STAT                  0xFFC02408         /* UART1 Status Register */
663 #define UART1_SCR                   0xFFC0240C         /* UART1 Scratch Register */
664 #define UART1_CLK                   0xFFC02410         /* UART1 Clock Rate Register */
665 #define UART1_IER                   0xFFC02414         /* UART1 Interrupt Mask Register */
666 #define UART1_IER_SET               0xFFC02418         /* UART1 Interrupt Mask Set Register */
667 #define UART1_IER_CLR               0xFFC0241C         /* UART1 Interrupt Mask Clear Register */
668 #define UART1_RBR                   0xFFC02420         /* UART1 Receive Buffer Register */
669 #define UART1_THR                   0xFFC02424         /* UART1 Transmit Hold Register */
670 #define UART1_TAIP                  0xFFC02428         /* UART1 Transmit Address/Insert Pulse Register */
671 #define UART1_TSR                   0xFFC0242C         /* UART1 Transmit Shift Register */
672 #define UART1_RSR                   0xFFC02430         /* UART1 Receive Shift Register */
673 #define UART1_TXDIV                 0xFFC02434         /* UART1 Transmit Clock Devider Register */
674 #define UART1_RXDIV                 0xFFC02438         /* UART1 Receive Clock Devider Register */
675 
676 
677 /* =========================
678         PORT Registers
679    ========================= */
680 
681 /* =========================
682         PORTA
683    ========================= */
684 #define PORTA_FER                   0xFFC03000         /* PORTA Port x Function Enable Register */
685 #define PORTA_FER_SET               0xFFC03004         /* PORTA Port x Function Enable Set Register */
686 #define PORTA_FER_CLEAR               0xFFC03008         /* PORTA Port x Function Enable Clear Register */
687 #define PORTA_DATA                  0xFFC0300C         /* PORTA Port x GPIO Data Register */
688 #define PORTA_DATA_SET              0xFFC03010         /* PORTA Port x GPIO Data Set Register */
689 #define PORTA_DATA_CLEAR              0xFFC03014         /* PORTA Port x GPIO Data Clear Register */
690 #define PORTA_DIR                   0xFFC03018         /* PORTA Port x GPIO Direction Register */
691 #define PORTA_DIR_SET               0xFFC0301C         /* PORTA Port x GPIO Direction Set Register */
692 #define PORTA_DIR_CLEAR               0xFFC03020         /* PORTA Port x GPIO Direction Clear Register */
693 #define PORTA_INEN                  0xFFC03024         /* PORTA Port x GPIO Input Enable Register */
694 #define PORTA_INEN_SET              0xFFC03028         /* PORTA Port x GPIO Input Enable Set Register */
695 #define PORTA_INEN_CLEAR              0xFFC0302C         /* PORTA Port x GPIO Input Enable Clear Register */
696 #define PORTA_MUX                   0xFFC03030         /* PORTA Port x Multiplexer Control Register */
697 #define PORTA_DATA_TGL              0xFFC03034         /* PORTA Port x GPIO Input Enable Toggle Register */
698 #define PORTA_POL                   0xFFC03038         /* PORTA Port x GPIO Programming Inversion Register */
699 #define PORTA_POL_SET               0xFFC0303C         /* PORTA Port x GPIO Programming Inversion Set Register */
700 #define PORTA_POL_CLEAR               0xFFC03040         /* PORTA Port x GPIO Programming Inversion Clear Register */
701 #define PORTA_LOCK                  0xFFC03044         /* PORTA Port x GPIO Lock Register */
702 #define PORTA_REVID                 0xFFC0307C         /* PORTA Port x GPIO Revision ID */
703 
704 /* =========================
705         PORTB
706    ========================= */
707 #define PORTB_FER                   0xFFC03080         /* PORTB Port x Function Enable Register */
708 #define PORTB_FER_SET               0xFFC03084         /* PORTB Port x Function Enable Set Register */
709 #define PORTB_FER_CLEAR               0xFFC03088         /* PORTB Port x Function Enable Clear Register */
710 #define PORTB_DATA                  0xFFC0308C         /* PORTB Port x GPIO Data Register */
711 #define PORTB_DATA_SET              0xFFC03090         /* PORTB Port x GPIO Data Set Register */
712 #define PORTB_DATA_CLEAR              0xFFC03094         /* PORTB Port x GPIO Data Clear Register */
713 #define PORTB_DIR                   0xFFC03098         /* PORTB Port x GPIO Direction Register */
714 #define PORTB_DIR_SET               0xFFC0309C         /* PORTB Port x GPIO Direction Set Register */
715 #define PORTB_DIR_CLEAR               0xFFC030A0         /* PORTB Port x GPIO Direction Clear Register */
716 #define PORTB_INEN                  0xFFC030A4         /* PORTB Port x GPIO Input Enable Register */
717 #define PORTB_INEN_SET              0xFFC030A8         /* PORTB Port x GPIO Input Enable Set Register */
718 #define PORTB_INEN_CLEAR              0xFFC030AC         /* PORTB Port x GPIO Input Enable Clear Register */
719 #define PORTB_MUX                   0xFFC030B0         /* PORTB Port x Multiplexer Control Register */
720 #define PORTB_DATA_TGL              0xFFC030B4         /* PORTB Port x GPIO Input Enable Toggle Register */
721 #define PORTB_POL                   0xFFC030B8         /* PORTB Port x GPIO Programming Inversion Register */
722 #define PORTB_POL_SET               0xFFC030BC         /* PORTB Port x GPIO Programming Inversion Set Register */
723 #define PORTB_POL_CLEAR               0xFFC030C0         /* PORTB Port x GPIO Programming Inversion Clear Register */
724 #define PORTB_LOCK                  0xFFC030C4         /* PORTB Port x GPIO Lock Register */
725 #define PORTB_REVID                 0xFFC030FC         /* PORTB Port x GPIO Revision ID */
726 
727 /* =========================
728         PORTC
729    ========================= */
730 #define PORTC_FER                   0xFFC03100         /* PORTC Port x Function Enable Register */
731 #define PORTC_FER_SET               0xFFC03104         /* PORTC Port x Function Enable Set Register */
732 #define PORTC_FER_CLEAR               0xFFC03108         /* PORTC Port x Function Enable Clear Register */
733 #define PORTC_DATA                  0xFFC0310C         /* PORTC Port x GPIO Data Register */
734 #define PORTC_DATA_SET              0xFFC03110         /* PORTC Port x GPIO Data Set Register */
735 #define PORTC_DATA_CLEAR              0xFFC03114         /* PORTC Port x GPIO Data Clear Register */
736 #define PORTC_DIR                   0xFFC03118         /* PORTC Port x GPIO Direction Register */
737 #define PORTC_DIR_SET               0xFFC0311C         /* PORTC Port x GPIO Direction Set Register */
738 #define PORTC_DIR_CLEAR               0xFFC03120         /* PORTC Port x GPIO Direction Clear Register */
739 #define PORTC_INEN                  0xFFC03124         /* PORTC Port x GPIO Input Enable Register */
740 #define PORTC_INEN_SET              0xFFC03128         /* PORTC Port x GPIO Input Enable Set Register */
741 #define PORTC_INEN_CLEAR              0xFFC0312C         /* PORTC Port x GPIO Input Enable Clear Register */
742 #define PORTC_MUX                   0xFFC03130         /* PORTC Port x Multiplexer Control Register */
743 #define PORTC_DATA_TGL              0xFFC03134         /* PORTC Port x GPIO Input Enable Toggle Register */
744 #define PORTC_POL                   0xFFC03138         /* PORTC Port x GPIO Programming Inversion Register */
745 #define PORTC_POL_SET               0xFFC0313C         /* PORTC Port x GPIO Programming Inversion Set Register */
746 #define PORTC_POL_CLEAR               0xFFC03140         /* PORTC Port x GPIO Programming Inversion Clear Register */
747 #define PORTC_LOCK                  0xFFC03144         /* PORTC Port x GPIO Lock Register */
748 #define PORTC_REVID                 0xFFC0317C         /* PORTC Port x GPIO Revision ID */
749 
750 /* =========================
751         PORTD
752    ========================= */
753 #define PORTD_FER                   0xFFC03180         /* PORTD Port x Function Enable Register */
754 #define PORTD_FER_SET               0xFFC03184         /* PORTD Port x Function Enable Set Register */
755 #define PORTD_FER_CLEAR               0xFFC03188         /* PORTD Port x Function Enable Clear Register */
756 #define PORTD_DATA                  0xFFC0318C         /* PORTD Port x GPIO Data Register */
757 #define PORTD_DATA_SET              0xFFC03190         /* PORTD Port x GPIO Data Set Register */
758 #define PORTD_DATA_CLEAR              0xFFC03194         /* PORTD Port x GPIO Data Clear Register */
759 #define PORTD_DIR                   0xFFC03198         /* PORTD Port x GPIO Direction Register */
760 #define PORTD_DIR_SET               0xFFC0319C         /* PORTD Port x GPIO Direction Set Register */
761 #define PORTD_DIR_CLEAR               0xFFC031A0         /* PORTD Port x GPIO Direction Clear Register */
762 #define PORTD_INEN                  0xFFC031A4         /* PORTD Port x GPIO Input Enable Register */
763 #define PORTD_INEN_SET              0xFFC031A8         /* PORTD Port x GPIO Input Enable Set Register */
764 #define PORTD_INEN_CLEAR              0xFFC031AC         /* PORTD Port x GPIO Input Enable Clear Register */
765 #define PORTD_MUX                   0xFFC031B0         /* PORTD Port x Multiplexer Control Register */
766 #define PORTD_DATA_TGL              0xFFC031B4         /* PORTD Port x GPIO Input Enable Toggle Register */
767 #define PORTD_POL                   0xFFC031B8         /* PORTD Port x GPIO Programming Inversion Register */
768 #define PORTD_POL_SET               0xFFC031BC         /* PORTD Port x GPIO Programming Inversion Set Register */
769 #define PORTD_POL_CLEAR               0xFFC031C0         /* PORTD Port x GPIO Programming Inversion Clear Register */
770 #define PORTD_LOCK                  0xFFC031C4         /* PORTD Port x GPIO Lock Register */
771 #define PORTD_REVID                 0xFFC031FC         /* PORTD Port x GPIO Revision ID */
772 
773 /* =========================
774         PORTE
775    ========================= */
776 #define PORTE_FER                   0xFFC03200         /* PORTE Port x Function Enable Register */
777 #define PORTE_FER_SET               0xFFC03204         /* PORTE Port x Function Enable Set Register */
778 #define PORTE_FER_CLEAR               0xFFC03208         /* PORTE Port x Function Enable Clear Register */
779 #define PORTE_DATA                  0xFFC0320C         /* PORTE Port x GPIO Data Register */
780 #define PORTE_DATA_SET              0xFFC03210         /* PORTE Port x GPIO Data Set Register */
781 #define PORTE_DATA_CLEAR              0xFFC03214         /* PORTE Port x GPIO Data Clear Register */
782 #define PORTE_DIR                   0xFFC03218         /* PORTE Port x GPIO Direction Register */
783 #define PORTE_DIR_SET               0xFFC0321C         /* PORTE Port x GPIO Direction Set Register */
784 #define PORTE_DIR_CLEAR               0xFFC03220         /* PORTE Port x GPIO Direction Clear Register */
785 #define PORTE_INEN                  0xFFC03224         /* PORTE Port x GPIO Input Enable Register */
786 #define PORTE_INEN_SET              0xFFC03228         /* PORTE Port x GPIO Input Enable Set Register */
787 #define PORTE_INEN_CLEAR              0xFFC0322C         /* PORTE Port x GPIO Input Enable Clear Register */
788 #define PORTE_MUX                   0xFFC03230         /* PORTE Port x Multiplexer Control Register */
789 #define PORTE_DATA_TGL              0xFFC03234         /* PORTE Port x GPIO Input Enable Toggle Register */
790 #define PORTE_POL                   0xFFC03238         /* PORTE Port x GPIO Programming Inversion Register */
791 #define PORTE_POL_SET               0xFFC0323C         /* PORTE Port x GPIO Programming Inversion Set Register */
792 #define PORTE_POL_CLEAR               0xFFC03240         /* PORTE Port x GPIO Programming Inversion Clear Register */
793 #define PORTE_LOCK                  0xFFC03244         /* PORTE Port x GPIO Lock Register */
794 #define PORTE_REVID                 0xFFC0327C         /* PORTE Port x GPIO Revision ID */
795 
796 /* =========================
797         PORTF
798    ========================= */
799 #define PORTF_FER                   0xFFC03280         /* PORTF Port x Function Enable Register */
800 #define PORTF_FER_SET               0xFFC03284         /* PORTF Port x Function Enable Set Register */
801 #define PORTF_FER_CLEAR               0xFFC03288         /* PORTF Port x Function Enable Clear Register */
802 #define PORTF_DATA                  0xFFC0328C         /* PORTF Port x GPIO Data Register */
803 #define PORTF_DATA_SET              0xFFC03290         /* PORTF Port x GPIO Data Set Register */
804 #define PORTF_DATA_CLEAR              0xFFC03294         /* PORTF Port x GPIO Data Clear Register */
805 #define PORTF_DIR                   0xFFC03298         /* PORTF Port x GPIO Direction Register */
806 #define PORTF_DIR_SET               0xFFC0329C         /* PORTF Port x GPIO Direction Set Register */
807 #define PORTF_DIR_CLEAR               0xFFC032A0         /* PORTF Port x GPIO Direction Clear Register */
808 #define PORTF_INEN                  0xFFC032A4         /* PORTF Port x GPIO Input Enable Register */
809 #define PORTF_INEN_SET              0xFFC032A8         /* PORTF Port x GPIO Input Enable Set Register */
810 #define PORTF_INEN_CLEAR              0xFFC032AC         /* PORTF Port x GPIO Input Enable Clear Register */
811 #define PORTF_MUX                   0xFFC032B0         /* PORTF Port x Multiplexer Control Register */
812 #define PORTF_DATA_TGL              0xFFC032B4         /* PORTF Port x GPIO Input Enable Toggle Register */
813 #define PORTF_POL                   0xFFC032B8         /* PORTF Port x GPIO Programming Inversion Register */
814 #define PORTF_POL_SET               0xFFC032BC         /* PORTF Port x GPIO Programming Inversion Set Register */
815 #define PORTF_POL_CLEAR               0xFFC032C0         /* PORTF Port x GPIO Programming Inversion Clear Register */
816 #define PORTF_LOCK                  0xFFC032C4         /* PORTF Port x GPIO Lock Register */
817 #define PORTF_REVID                 0xFFC032FC         /* PORTF Port x GPIO Revision ID */
818 
819 /* =========================
820         PORTG
821    ========================= */
822 #define PORTG_FER                   0xFFC03300         /* PORTG Port x Function Enable Register */
823 #define PORTG_FER_SET               0xFFC03304         /* PORTG Port x Function Enable Set Register */
824 #define PORTG_FER_CLEAR               0xFFC03308         /* PORTG Port x Function Enable Clear Register */
825 #define PORTG_DATA                  0xFFC0330C         /* PORTG Port x GPIO Data Register */
826 #define PORTG_DATA_SET              0xFFC03310         /* PORTG Port x GPIO Data Set Register */
827 #define PORTG_DATA_CLEAR              0xFFC03314         /* PORTG Port x GPIO Data Clear Register */
828 #define PORTG_DIR                   0xFFC03318         /* PORTG Port x GPIO Direction Register */
829 #define PORTG_DIR_SET               0xFFC0331C         /* PORTG Port x GPIO Direction Set Register */
830 #define PORTG_DIR_CLEAR               0xFFC03320         /* PORTG Port x GPIO Direction Clear Register */
831 #define PORTG_INEN                  0xFFC03324         /* PORTG Port x GPIO Input Enable Register */
832 #define PORTG_INEN_SET              0xFFC03328         /* PORTG Port x GPIO Input Enable Set Register */
833 #define PORTG_INEN_CLEAR              0xFFC0332C         /* PORTG Port x GPIO Input Enable Clear Register */
834 #define PORTG_MUX                   0xFFC03330         /* PORTG Port x Multiplexer Control Register */
835 #define PORTG_DATA_TGL              0xFFC03334         /* PORTG Port x GPIO Input Enable Toggle Register */
836 #define PORTG_POL                   0xFFC03338         /* PORTG Port x GPIO Programming Inversion Register */
837 #define PORTG_POL_SET               0xFFC0333C         /* PORTG Port x GPIO Programming Inversion Set Register */
838 #define PORTG_POL_CLEAR               0xFFC03340         /* PORTG Port x GPIO Programming Inversion Clear Register */
839 #define PORTG_LOCK                  0xFFC03344         /* PORTG Port x GPIO Lock Register */
840 #define PORTG_REVID                 0xFFC0337C         /* PORTG Port x GPIO Revision ID */
841 
842 /* ==================================================
843         Pads Controller Registers
844    ================================================== */
845 
846 /* =========================
847         PADS0
848    ========================= */
849 #define PADS0_EMAC_PTP_CLKSEL	    0xFFC03404         /* PADS0 Clock Selection for EMAC and PTP */
850 #define PADS0_TWI_VSEL		    0xFFC03408         /* PADS0 TWI Voltage Selection */
851 #define PADS0_PORTS_HYST	    0xFFC03440         /* PADS0 Hysteresis Enable Register */
852 
853 /* =========================
854         PINT Registers
855    ========================= */
856 
857 /* =========================
858         PINT0
859    ========================= */
860 #define PINT0_MASK_SET              0xFFC04000         /* PINT0 Pint Mask Set Register */
861 #define PINT0_MASK_CLEAR            0xFFC04004         /* PINT0 Pint Mask Clear Register */
862 #define PINT0_REQUEST               0xFFC04008         /* PINT0 Pint Request Register */
863 #define PINT0_ASSIGN                0xFFC0400C         /* PINT0 Pint Assign Register */
864 #define PINT0_EDGE_SET              0xFFC04010         /* PINT0 Pint Edge Set Register */
865 #define PINT0_EDGE_CLEAR            0xFFC04014         /* PINT0 Pint Edge Clear Register */
866 #define PINT0_INVERT_SET            0xFFC04018         /* PINT0 Pint Invert Set Register */
867 #define PINT0_INVERT_CLEAR          0xFFC0401C         /* PINT0 Pint Invert Clear Register */
868 #define PINT0_PINSTATE              0xFFC04020         /* PINT0 Pint Pinstate Register */
869 #define PINT0_LATCH                 0xFFC04024         /* PINT0 Pint Latch Register */
870 
871 /* =========================
872         PINT1
873    ========================= */
874 #define PINT1_MASK_SET              0xFFC04100         /* PINT1 Pint Mask Set Register */
875 #define PINT1_MASK_CLEAR            0xFFC04104         /* PINT1 Pint Mask Clear Register */
876 #define PINT1_REQUEST               0xFFC04108         /* PINT1 Pint Request Register */
877 #define PINT1_ASSIGN                0xFFC0410C         /* PINT1 Pint Assign Register */
878 #define PINT1_EDGE_SET              0xFFC04110         /* PINT1 Pint Edge Set Register */
879 #define PINT1_EDGE_CLEAR            0xFFC04114         /* PINT1 Pint Edge Clear Register */
880 #define PINT1_INVERT_SET            0xFFC04118         /* PINT1 Pint Invert Set Register */
881 #define PINT1_INVERT_CLEAR          0xFFC0411C         /* PINT1 Pint Invert Clear Register */
882 #define PINT1_PINSTATE              0xFFC04120         /* PINT1 Pint Pinstate Register */
883 #define PINT1_LATCH                 0xFFC04124         /* PINT1 Pint Latch Register */
884 
885 /* =========================
886         PINT2
887    ========================= */
888 #define PINT2_MASK_SET              0xFFC04200         /* PINT2 Pint Mask Set Register */
889 #define PINT2_MASK_CLEAR            0xFFC04204         /* PINT2 Pint Mask Clear Register */
890 #define PINT2_REQUEST               0xFFC04208         /* PINT2 Pint Request Register */
891 #define PINT2_ASSIGN                0xFFC0420C         /* PINT2 Pint Assign Register */
892 #define PINT2_EDGE_SET              0xFFC04210         /* PINT2 Pint Edge Set Register */
893 #define PINT2_EDGE_CLEAR            0xFFC04214         /* PINT2 Pint Edge Clear Register */
894 #define PINT2_INVERT_SET            0xFFC04218         /* PINT2 Pint Invert Set Register */
895 #define PINT2_INVERT_CLEAR          0xFFC0421C         /* PINT2 Pint Invert Clear Register */
896 #define PINT2_PINSTATE              0xFFC04220         /* PINT2 Pint Pinstate Register */
897 #define PINT2_LATCH                 0xFFC04224         /* PINT2 Pint Latch Register */
898 
899 /* =========================
900         PINT3
901    ========================= */
902 #define PINT3_MASK_SET              0xFFC04300         /* PINT3 Pint Mask Set Register */
903 #define PINT3_MASK_CLEAR            0xFFC04304         /* PINT3 Pint Mask Clear Register */
904 #define PINT3_REQUEST               0xFFC04308         /* PINT3 Pint Request Register */
905 #define PINT3_ASSIGN                0xFFC0430C         /* PINT3 Pint Assign Register */
906 #define PINT3_EDGE_SET              0xFFC04310         /* PINT3 Pint Edge Set Register */
907 #define PINT3_EDGE_CLEAR            0xFFC04314         /* PINT3 Pint Edge Clear Register */
908 #define PINT3_INVERT_SET            0xFFC04318         /* PINT3 Pint Invert Set Register */
909 #define PINT3_INVERT_CLEAR          0xFFC0431C         /* PINT3 Pint Invert Clear Register */
910 #define PINT3_PINSTATE              0xFFC04320         /* PINT3 Pint Pinstate Register */
911 #define PINT3_LATCH                 0xFFC04324         /* PINT3 Pint Latch Register */
912 
913 /* =========================
914         PINT4
915    ========================= */
916 #define PINT4_MASK_SET              0xFFC04400         /* PINT4 Pint Mask Set Register */
917 #define PINT4_MASK_CLEAR            0xFFC04404         /* PINT4 Pint Mask Clear Register */
918 #define PINT4_REQUEST               0xFFC04408         /* PINT4 Pint Request Register */
919 #define PINT4_ASSIGN                0xFFC0440C         /* PINT4 Pint Assign Register */
920 #define PINT4_EDGE_SET              0xFFC04410         /* PINT4 Pint Edge Set Register */
921 #define PINT4_EDGE_CLEAR            0xFFC04414         /* PINT4 Pint Edge Clear Register */
922 #define PINT4_INVERT_SET            0xFFC04418         /* PINT4 Pint Invert Set Register */
923 #define PINT4_INVERT_CLEAR          0xFFC0441C         /* PINT4 Pint Invert Clear Register */
924 #define PINT4_PINSTATE              0xFFC04420         /* PINT4 Pint Pinstate Register */
925 #define PINT4_LATCH                 0xFFC04424         /* PINT4 Pint Latch Register */
926 
927 /* =========================
928         PINT5
929    ========================= */
930 #define PINT5_MASK_SET              0xFFC04500         /* PINT5 Pint Mask Set Register */
931 #define PINT5_MASK_CLEAR            0xFFC04504         /* PINT5 Pint Mask Clear Register */
932 #define PINT5_REQUEST               0xFFC04508         /* PINT5 Pint Request Register */
933 #define PINT5_ASSIGN                0xFFC0450C         /* PINT5 Pint Assign Register */
934 #define PINT5_EDGE_SET              0xFFC04510         /* PINT5 Pint Edge Set Register */
935 #define PINT5_EDGE_CLEAR            0xFFC04514         /* PINT5 Pint Edge Clear Register */
936 #define PINT5_INVERT_SET            0xFFC04518         /* PINT5 Pint Invert Set Register */
937 #define PINT5_INVERT_CLEAR          0xFFC0451C         /* PINT5 Pint Invert Clear Register */
938 #define PINT5_PINSTATE              0xFFC04520         /* PINT5 Pint Pinstate Register */
939 #define PINT5_LATCH                 0xFFC04524         /* PINT5 Pint Latch Register */
940 
941 
942 /* =========================
943         SMC Registers
944    ========================= */
945 
946 /* =========================
947         SMC0
948    ========================= */
949 #define SMC_GCTL                   0xFFC16004         /* SMC0 SMC Control Register */
950 #define SMC_GSTAT                  0xFFC16008         /* SMC0 SMC Status Register */
951 #define SMC_B0CTL                  0xFFC1600C         /* SMC0 SMC Bank0 Control Register */
952 #define SMC_B0TIM                  0xFFC16010         /* SMC0 SMC Bank0 Timing Register */
953 #define SMC_B0ETIM                 0xFFC16014         /* SMC0 SMC Bank0 Extended Timing Register */
954 #define SMC_B1CTL                  0xFFC1601C         /* SMC0 SMC BANK1 Control Register */
955 #define SMC_B1TIM                  0xFFC16020         /* SMC0 SMC BANK1 Timing Register */
956 #define SMC_B1ETIM                 0xFFC16024         /* SMC0 SMC BANK1 Extended Timing Register */
957 #define SMC_B2CTL                  0xFFC1602C         /* SMC0 SMC BANK2 Control Register */
958 #define SMC_B2TIM                  0xFFC16030         /* SMC0 SMC BANK2 Timing Register */
959 #define SMC_B2ETIM                 0xFFC16034         /* SMC0 SMC BANK2 Extended Timing Register */
960 #define SMC_B3CTL                  0xFFC1603C         /* SMC0 SMC BANK3 Control Register */
961 #define SMC_B3TIM                  0xFFC16040         /* SMC0 SMC BANK3 Timing Register */
962 #define SMC_B3ETIM                 0xFFC16044         /* SMC0 SMC BANK3 Extended Timing Register */
963 
964 
965 /* =========================
966         WDOG Registers
967    ========================= */
968 
969 /* =========================
970         WDOG0
971    ========================= */
972 #define WDOG0_CTL                   0xFFC17000         /* WDOG0 Control Register */
973 #define WDOG0_CNT                   0xFFC17004         /* WDOG0 Count Register */
974 #define WDOG0_STAT                  0xFFC17008         /* WDOG0 Watchdog Timer Status Register */
975 #define WDOG_CTL		WDOG0_CTL
976 #define WDOG_CNT		WDOG0_CNT
977 #define WDOG_STAT		WDOG0_STAT
978 
979 /* =========================
980         WDOG1
981    ========================= */
982 #define WDOG1_CTL                   0xFFC17800         /* WDOG1 Control Register */
983 #define WDOG1_CNT                   0xFFC17804         /* WDOG1 Count Register */
984 #define WDOG1_STAT                  0xFFC17808         /* WDOG1 Watchdog Timer Status Register */
985 
986 
987 /* =========================
988         SDU Registers
989    ========================= */
990 
991 /* =========================
992         SDU0
993    ========================= */
994 #define SDU0_IDCODE                 0xFFC1F020         /* SDU0 ID Code Register */
995 #define SDU0_CTL                    0xFFC1F050         /* SDU0 Control Register */
996 #define SDU0_STAT                   0xFFC1F054         /* SDU0 Status Register */
997 #define SDU0_MACCTL                 0xFFC1F058         /* SDU0 Memory Access Control Register */
998 #define SDU0_MACADDR                0xFFC1F05C         /* SDU0 Memory Access Address Register */
999 #define SDU0_MACDATA                0xFFC1F060         /* SDU0 Memory Access Data Register */
1000 #define SDU0_DMARD                  0xFFC1F064         /* SDU0 DMA Read Data Register */
1001 #define SDU0_DMAWD                  0xFFC1F068         /* SDU0 DMA Write Data Register */
1002 #define SDU0_MSG                    0xFFC1F080         /* SDU0 Message Register */
1003 #define SDU0_MSG_SET                0xFFC1F084         /* SDU0 Message Set Register */
1004 #define SDU0_MSG_CLR                0xFFC1F088         /* SDU0 Message Clear Register */
1005 #define SDU0_GHLT                   0xFFC1F08C         /* SDU0 Group Halt Register */
1006 
1007 
1008 /* =========================
1009         EMAC Registers
1010    ========================= */
1011 /* =========================
1012         EMAC0
1013    ========================= */
1014 #define EMAC0_MACCFG                0xFFC20000         /* EMAC0 MAC Configuration Register */
1015 #define EMAC0_MACFRMFILT            0xFFC20004         /* EMAC0 Filter Register for filtering Received Frames */
1016 #define EMAC0_HASHTBL_HI            0xFFC20008         /* EMAC0 Contains the Upper 32 bits of the hash table */
1017 #define EMAC0_HASHTBL_LO            0xFFC2000C         /* EMAC0 Contains the lower 32 bits of the hash table */
1018 #define EMAC0_GMII_ADDR             0xFFC20010         /* EMAC0 Management Address Register */
1019 #define EMAC0_GMII_DATA             0xFFC20014         /* EMAC0 Management Data Register */
1020 #define EMAC0_FLOWCTL               0xFFC20018         /* EMAC0 MAC FLow Control Register */
1021 #define EMAC0_VLANTAG               0xFFC2001C         /* EMAC0 VLAN Tag Register */
1022 #define EMAC0_VER                   0xFFC20020         /* EMAC0 EMAC Version Register */
1023 #define EMAC0_DBG                   0xFFC20024         /* EMAC0 EMAC Debug Register */
1024 #define EMAC0_RMTWKUP               0xFFC20028         /* EMAC0 Remote wake up frame register */
1025 #define EMAC0_PMT_CTLSTAT           0xFFC2002C         /* EMAC0 PMT Control and Status Register */
1026 #define EMAC0_ISTAT                 0xFFC20038         /* EMAC0 EMAC Interrupt Status Register */
1027 #define EMAC0_IMSK                  0xFFC2003C         /* EMAC0 EMAC Interrupt Mask Register */
1028 #define EMAC0_ADDR0_HI              0xFFC20040         /* EMAC0 EMAC Address0 High Register */
1029 #define EMAC0_ADDR0_LO              0xFFC20044         /* EMAC0 EMAC Address0 Low Register */
1030 #define EMAC0_MMC_CTL               0xFFC20100         /* EMAC0 MMC Control Register */
1031 #define EMAC0_MMC_RXINT             0xFFC20104         /* EMAC0 MMC RX Interrupt Register */
1032 #define EMAC0_MMC_TXINT             0xFFC20108         /* EMAC0 MMC TX Interrupt Register */
1033 #define EMAC0_MMC_RXIMSK            0xFFC2010C         /* EMAC0 MMC RX Interrupt Mask Register */
1034 #define EMAC0_MMC_TXIMSK            0xFFC20110         /* EMAC0 MMC TX Interrupt Mask Register */
1035 #define EMAC0_TXOCTCNT_GB           0xFFC20114         /* EMAC0 Num bytes transmitted exclusive of preamble */
1036 #define EMAC0_TXFRMCNT_GB           0xFFC20118         /* EMAC0 Num frames transmitted exclusive of retired */
1037 #define EMAC0_TXBCASTFRM_G          0xFFC2011C         /* EMAC0 Number of good broadcast frames transmitted. */
1038 #define EMAC0_TXMCASTFRM_G          0xFFC20120         /* EMAC0 Number of good multicast frames transmitted. */
1039 #define EMAC0_TX64_GB               0xFFC20124         /* EMAC0 Number of 64 byte length frames */
1040 #define EMAC0_TX65TO127_GB          0xFFC20128         /* EMAC0 Number of frames of length b/w 65-127 (inclusive) bytes */
1041 #define EMAC0_TX128TO255_GB         0xFFC2012C         /* EMAC0 Number of frames of length b/w 128-255 (inclusive) bytes */
1042 #define EMAC0_TX256TO511_GB         0xFFC20130         /* EMAC0 Number of frames of length b/w 256-511 (inclusive) bytes */
1043 #define EMAC0_TX512TO1023_GB        0xFFC20134         /* EMAC0 Number of frames of length b/w 512-1023 (inclusive) bytes */
1044 #define EMAC0_TX1024TOMAX_GB        0xFFC20138         /* EMAC0 Number of frames of length b/w 1024-max (inclusive) bytes */
1045 #define EMAC0_TXUCASTFRM_GB         0xFFC2013C         /* EMAC0 Number of good and bad unicast frames transmitted */
1046 #define EMAC0_TXMCASTFRM_GB         0xFFC20140         /* EMAC0 Number of good and bad multicast frames transmitted */
1047 #define EMAC0_TXBCASTFRM_GB         0xFFC20144         /* EMAC0 Number of good and bad broadcast frames transmitted */
1048 #define EMAC0_TXUNDR_ERR            0xFFC20148         /* EMAC0 Number of frames aborted due to frame underflow error */
1049 #define EMAC0_TXSNGCOL_G            0xFFC2014C         /* EMAC0 Number of transmitted frames after single collision */
1050 #define EMAC0_TXMULTCOL_G           0xFFC20150         /* EMAC0 Number of transmitted frames with more than one collision */
1051 #define EMAC0_TXDEFERRED            0xFFC20154         /* EMAC0 Number of transmitted frames after deferral */
1052 #define EMAC0_TXLATECOL             0xFFC20158         /* EMAC0 Number of frames aborted due to late collision error */
1053 #define EMAC0_TXEXCESSCOL           0xFFC2015C         /* EMAC0 Number of aborted frames due to excessive collisions */
1054 #define EMAC0_TXCARR_ERR            0xFFC20160         /* EMAC0 Number of aborted frames due to carrier sense error */
1055 #define EMAC0_TXOCTCNT_G            0xFFC20164         /* EMAC0 Number of bytes transmitted in good frames only */
1056 #define EMAC0_TXFRMCNT_G            0xFFC20168         /* EMAC0 Number of good frames transmitted. */
1057 #define EMAC0_TXEXCESSDEF           0xFFC2016C         /* EMAC0 Number of frames aborted due to excessive deferral */
1058 #define EMAC0_TXPAUSEFRM            0xFFC20170         /* EMAC0 Number of good PAUSE frames transmitted. */
1059 #define EMAC0_TXVLANFRM_G           0xFFC20174         /* EMAC0 Number of VLAN frames transmitted */
1060 #define EMAC0_RXFRMCNT_GB           0xFFC20180         /* EMAC0 Number of good and bad frames received. */
1061 #define EMAC0_RXOCTCNT_GB           0xFFC20184         /* EMAC0 Number of bytes received in good and bad frames */
1062 #define EMAC0_RXOCTCNT_G            0xFFC20188         /* EMAC0 Number of bytes received only in good frames */
1063 #define EMAC0_RXBCASTFRM_G          0xFFC2018C         /* EMAC0 Number of good broadcast frames received. */
1064 #define EMAC0_RXMCASTFRM_G          0xFFC20190         /* EMAC0 Number of good multicast frames received */
1065 #define EMAC0_RXCRC_ERR             0xFFC20194         /* EMAC0 Number of frames received with CRC error */
1066 #define EMAC0_RXALIGN_ERR           0xFFC20198         /* EMAC0 Number of frames with alignment error */
1067 #define EMAC0_RXRUNT_ERR            0xFFC2019C         /* EMAC0 Number of frames received with runt error. */
1068 #define EMAC0_RXJAB_ERR             0xFFC201A0         /* EMAC0 Number of frames received with length greater than 1518 */
1069 #define EMAC0_RXUSIZE_G             0xFFC201A4         /* EMAC0 Number of frames received with length 64 */
1070 #define EMAC0_RXOSIZE_G             0xFFC201A8         /* EMAC0 Number of frames received with length greater than maxium */
1071 #define EMAC0_RX64_GB               0xFFC201AC         /* EMAC0 Number of good and bad frames of lengh 64 bytes */
1072 #define EMAC0_RX65TO127_GB          0xFFC201B0         /* EMAC0 Number of good and bad frame between 64-127(inclusive) */
1073 #define EMAC0_RX128TO255_GB         0xFFC201B4         /* EMAC0 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
1074 #define EMAC0_RX256TO511_GB         0xFFC201B8         /* EMAC0 Number of good and bad frames between 256-511(inclusive) */
1075 #define EMAC0_RX512TO1023_GB        0xFFC201BC         /* EMAC0 Number of good and bad frames received between 512-1023 */
1076 #define EMAC0_RX1024TOMAX_GB        0xFFC201C0         /* EMAC0 Number of frames received between 1024 and maxsize */
1077 #define EMAC0_RXUCASTFRM_G          0xFFC201C4         /* EMAC0 Number of good unicast frames received. */
1078 #define EMAC0_RXLEN_ERR             0xFFC201C8         /* EMAC0 Number of frames received with length error */
1079 #define EMAC0_RXOORTYPE             0xFFC201CC         /* EMAC0 Number of frames with length not equal to valid frame size */
1080 #define EMAC0_RXPAUSEFRM            0xFFC201D0         /* EMAC0 Number of good and valid PAUSE frames received. */
1081 #define EMAC0_RXFIFO_OVF            0xFFC201D4         /* EMAC0 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
1082 #define EMAC0_RXVLANFRM_GB          0xFFC201D8         /* EMAC0 Number of good and bad VLAN frames received. */
1083 #define EMAC0_RXWDOG_ERR            0xFFC201DC         /* EMAC0 Frames received with error due to watchdog timeout */
1084 #define EMAC0_IPC_RXIMSK            0xFFC20200         /* EMAC0 MMC IPC RX Interrupt Mask Register */
1085 #define EMAC0_IPC_RXINT             0xFFC20208         /* EMAC0 MMC IPC RX Interrupt Register */
1086 #define EMAC0_RXIPV4_GD_FRM         0xFFC20210         /* EMAC0 Number of good IPv4 datagrams */
1087 #define EMAC0_RXIPV4_HDR_ERR_FRM    0xFFC20214         /* EMAC0 Number of IPv4 datagrams with header errors */
1088 #define EMAC0_RXIPV4_NOPAY_FRM      0xFFC20218         /* EMAC0 Number of IPv4 datagrams without checksum */
1089 #define EMAC0_RXIPV4_FRAG_FRM       0xFFC2021C         /* EMAC0 Number of good IPv4 datagrams with fragmentation */
1090 #define EMAC0_RXIPV4_UDSBL_FRM      0xFFC20220         /* EMAC0 Number of IPv4 UDP datagrams with disabled checksum */
1091 #define EMAC0_RXIPV6_GD_FRM         0xFFC20224         /* EMAC0 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
1092 #define EMAC0_RXIPV6_HDR_ERR_FRM    0xFFC20228         /* EMAC0 Number of IPv6 datagrams with header errors */
1093 #define EMAC0_RXIPV6_NOPAY_FRM      0xFFC2022C         /* EMAC0 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
1094 #define EMAC0_RXUDP_GD_FRM          0xFFC20230         /* EMAC0 Number of good IP datagrames with good UDP payload */
1095 #define EMAC0_RXUDP_ERR_FRM         0xFFC20234         /* EMAC0 Number of good IP datagrams with UDP checksum errors */
1096 #define EMAC0_RXTCP_GD_FRM          0xFFC20238         /* EMAC0 Number of good IP datagrams with a good TCP payload */
1097 #define EMAC0_RXTCP_ERR_FRM         0xFFC2023C         /* EMAC0 Number of good IP datagrams with TCP checksum errors */
1098 #define EMAC0_RXICMP_GD_FRM         0xFFC20240         /* EMAC0 Number of good IP datagrams with a good ICMP payload */
1099 #define EMAC0_RXICMP_ERR_FRM        0xFFC20244         /* EMAC0 Number of good IP datagrams with ICMP checksum errors */
1100 #define EMAC0_RXIPV4_GD_OCT         0xFFC20250         /* EMAC0 Bytes received in IPv4 datagrams including tcp,udp or icmp */
1101 #define EMAC0_RXIPV4_HDR_ERR_OCT    0xFFC20254         /* EMAC0 Bytes received in IPv4 datagrams with header errors */
1102 #define EMAC0_RXIPV4_NOPAY_OCT      0xFFC20258         /* EMAC0 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
1103 #define EMAC0_RXIPV4_FRAG_OCT       0xFFC2025C         /* EMAC0 Bytes received in fragmented IPv4 datagrams */
1104 #define EMAC0_RXIPV4_UDSBL_OCT      0xFFC20260         /* EMAC0 Bytes received in UDP segment with checksum disabled */
1105 #define EMAC0_RXIPV6_GD_OCT         0xFFC20264         /* EMAC0 Bytes received in good IPv6  including tcp,udp or icmp load */
1106 #define EMAC0_RXIPV6_HDR_ERR_OCT    0xFFC20268         /* EMAC0 Number of bytes received in IPv6 with header errors */
1107 #define EMAC0_RXIPV6_NOPAY_OCT      0xFFC2026C         /* EMAC0 Bytes received in IPv6 without tcp,udp or icmp load */
1108 #define EMAC0_RXUDP_GD_OCT          0xFFC20270         /* EMAC0 Number of bytes received in good UDP segments */
1109 #define EMAC0_RXUDP_ERR_OCT         0xFFC20274         /* EMAC0 Number of bytes received in UDP segment with checksum err */
1110 #define EMAC0_RXTCP_GD_OCT          0xFFC20278         /* EMAC0 Number of bytes received in a good TCP segment */
1111 #define EMAC0_RXTCP_ERR_OCT         0xFFC2027C         /* EMAC0 Number of bytes received in TCP segment with checksum err */
1112 #define EMAC0_RXICMP_GD_OCT         0xFFC20280         /* EMAC0 Number of bytes received in a good ICMP segment */
1113 #define EMAC0_RXICMP_ERR_OCT        0xFFC20284         /* EMAC0 Bytes received in an ICMP segment with checksum errors */
1114 #define EMAC0_TM_CTL                0xFFC20700         /* EMAC0 EMAC Time Stamp Control Register */
1115 #define EMAC0_TM_SUBSEC             0xFFC20704         /* EMAC0 EMAC Time Stamp Sub Second Increment */
1116 #define EMAC0_TM_SEC                0xFFC20708         /* EMAC0 EMAC Time Stamp Second Register */
1117 #define EMAC0_TM_NSEC               0xFFC2070C         /* EMAC0 EMAC Time Stamp Nano Second Register */
1118 #define EMAC0_TM_SECUPDT            0xFFC20710         /* EMAC0 EMAC Time Stamp Seconds Update */
1119 #define EMAC0_TM_NSECUPDT           0xFFC20714         /* EMAC0 EMAC Time Stamp Nano Seconds Update */
1120 #define EMAC0_TM_ADDEND             0xFFC20718         /* EMAC0 EMAC Time Stamp Addend Register */
1121 #define EMAC0_TM_TGTM               0xFFC2071C         /* EMAC0 EMAC Time Stamp Target Time Sec. */
1122 #define EMAC0_TM_NTGTM              0xFFC20720         /* EMAC0 EMAC Time Stamp Target Time Nanosec. */
1123 #define EMAC0_TM_HISEC              0xFFC20724         /* EMAC0 EMAC Time Stamp High Second Register */
1124 #define EMAC0_TM_STMPSTAT           0xFFC20728         /* EMAC0 EMAC Time Stamp Status Register */
1125 #define EMAC0_TM_PPSCTL             0xFFC2072C         /* EMAC0 EMAC PPS Control Register */
1126 #define EMAC0_TM_AUXSTMP_NSEC       0xFFC20730         /* EMAC0 EMAC Auxillary Time Stamp Nano Register */
1127 #define EMAC0_TM_AUXSTMP_SEC        0xFFC20734         /* EMAC0 EMAC Auxillary Time Stamp Sec Register */
1128 #define EMAC0_DMA_BUSMODE           0xFFC21000         /* EMAC0 Bus Operating Modes for EMAC DMA */
1129 #define EMAC0_DMA_TXPOLL            0xFFC21004         /* EMAC0 TX DMA Poll demand register */
1130 #define EMAC0_DMA_RXPOLL            0xFFC21008         /* EMAC0 RX DMA Poll demand register */
1131 #define EMAC0_DMA_RXDSC_ADDR        0xFFC2100C         /* EMAC0 RX Descriptor List Address */
1132 #define EMAC0_DMA_TXDSC_ADDR        0xFFC21010         /* EMAC0 TX Descriptor List Address */
1133 #define EMAC0_DMA_STAT              0xFFC21014         /* EMAC0 DMA Status Register */
1134 #define EMAC0_DMA_OPMODE            0xFFC21018         /* EMAC0 DMA Operation Mode Register */
1135 #define EMAC0_DMA_IEN               0xFFC2101C         /* EMAC0 DMA Interrupt Enable Register */
1136 #define EMAC0_DMA_MISS_FRM          0xFFC21020         /* EMAC0 DMA missed frame and buffer overflow counter */
1137 #define EMAC0_DMA_RXIWDOG           0xFFC21024         /* EMAC0 DMA RX Interrupt Watch Dog timer */
1138 #define EMAC0_DMA_BMMODE            0xFFC21028         /* EMAC0 AXI Bus Mode Register */
1139 #define EMAC0_DMA_BMSTAT            0xFFC2102C         /* EMAC0 AXI Status Register */
1140 #define EMAC0_DMA_TXDSC_CUR         0xFFC21048         /* EMAC0 TX current descriptor register */
1141 #define EMAC0_DMA_RXDSC_CUR         0xFFC2104C         /* EMAC0 RX current descriptor register */
1142 #define EMAC0_DMA_TXBUF_CUR         0xFFC21050         /* EMAC0 TX current buffer pointer register */
1143 #define EMAC0_DMA_RXBUF_CUR         0xFFC21054         /* EMAC0 RX current buffer pointer register */
1144 #define EMAC0_HWFEAT                0xFFC21058         /* EMAC0 Hardware Feature Register */
1145 
1146 /* =========================
1147         EMAC1
1148    ========================= */
1149 #define EMAC1_MACCFG                0xFFC22000         /* EMAC1 MAC Configuration Register */
1150 #define EMAC1_MACFRMFILT            0xFFC22004         /* EMAC1 Filter Register for filtering Received Frames */
1151 #define EMAC1_HASHTBL_HI            0xFFC22008         /* EMAC1 Contains the Upper 32 bits of the hash table */
1152 #define EMAC1_HASHTBL_LO            0xFFC2200C         /* EMAC1 Contains the lower 32 bits of the hash table */
1153 #define EMAC1_GMII_ADDR             0xFFC22010         /* EMAC1 Management Address Register */
1154 #define EMAC1_GMII_DATA             0xFFC22014         /* EMAC1 Management Data Register */
1155 #define EMAC1_FLOWCTL               0xFFC22018         /* EMAC1 MAC FLow Control Register */
1156 #define EMAC1_VLANTAG               0xFFC2201C         /* EMAC1 VLAN Tag Register */
1157 #define EMAC1_VER                   0xFFC22020         /* EMAC1 EMAC Version Register */
1158 #define EMAC1_DBG                   0xFFC22024         /* EMAC1 EMAC Debug Register */
1159 #define EMAC1_RMTWKUP               0xFFC22028         /* EMAC1 Remote wake up frame register */
1160 #define EMAC1_PMT_CTLSTAT           0xFFC2202C         /* EMAC1 PMT Control and Status Register */
1161 #define EMAC1_ISTAT                 0xFFC22038         /* EMAC1 EMAC Interrupt Status Register */
1162 #define EMAC1_IMSK                  0xFFC2203C         /* EMAC1 EMAC Interrupt Mask Register */
1163 #define EMAC1_ADDR0_HI              0xFFC22040         /* EMAC1 EMAC Address0 High Register */
1164 #define EMAC1_ADDR0_LO              0xFFC22044         /* EMAC1 EMAC Address0 Low Register */
1165 #define EMAC1_MMC_CTL               0xFFC22100         /* EMAC1 MMC Control Register */
1166 #define EMAC1_MMC_RXINT             0xFFC22104         /* EMAC1 MMC RX Interrupt Register */
1167 #define EMAC1_MMC_TXINT             0xFFC22108         /* EMAC1 MMC TX Interrupt Register */
1168 #define EMAC1_MMC_RXIMSK            0xFFC2210C         /* EMAC1 MMC RX Interrupt Mask Register */
1169 #define EMAC1_MMC_TXIMSK            0xFFC22110         /* EMAC1 MMC TX Interrupt Mask Register */
1170 #define EMAC1_TXOCTCNT_GB           0xFFC22114         /* EMAC1 Num bytes transmitted exclusive of preamble */
1171 #define EMAC1_TXFRMCNT_GB           0xFFC22118         /* EMAC1 Num frames transmitted exclusive of retired */
1172 #define EMAC1_TXBCASTFRM_G          0xFFC2211C         /* EMAC1 Number of good broadcast frames transmitted. */
1173 #define EMAC1_TXMCASTFRM_G          0xFFC22120         /* EMAC1 Number of good multicast frames transmitted. */
1174 #define EMAC1_TX64_GB               0xFFC22124         /* EMAC1 Number of 64 byte length frames */
1175 #define EMAC1_TX65TO127_GB          0xFFC22128         /* EMAC1 Number of frames of length b/w 65-127 (inclusive) bytes */
1176 #define EMAC1_TX128TO255_GB         0xFFC2212C         /* EMAC1 Number of frames of length b/w 128-255 (inclusive) bytes */
1177 #define EMAC1_TX256TO511_GB         0xFFC22130         /* EMAC1 Number of frames of length b/w 256-511 (inclusive) bytes */
1178 #define EMAC1_TX512TO1023_GB        0xFFC22134         /* EMAC1 Number of frames of length b/w 512-1023 (inclusive) bytes */
1179 #define EMAC1_TX1024TOMAX_GB        0xFFC22138         /* EMAC1 Number of frames of length b/w 1024-max (inclusive) bytes */
1180 #define EMAC1_TXUCASTFRM_GB         0xFFC2213C         /* EMAC1 Number of good and bad unicast frames transmitted */
1181 #define EMAC1_TXMCASTFRM_GB         0xFFC22140         /* EMAC1 Number of good and bad multicast frames transmitted */
1182 #define EMAC1_TXBCASTFRM_GB         0xFFC22144         /* EMAC1 Number of good and bad broadcast frames transmitted */
1183 #define EMAC1_TXUNDR_ERR            0xFFC22148         /* EMAC1 Number of frames aborted due to frame underflow error */
1184 #define EMAC1_TXSNGCOL_G            0xFFC2214C         /* EMAC1 Number of transmitted frames after single collision */
1185 #define EMAC1_TXMULTCOL_G           0xFFC22150         /* EMAC1 Number of transmitted frames with more than one collision */
1186 #define EMAC1_TXDEFERRED            0xFFC22154         /* EMAC1 Number of transmitted frames after deferral */
1187 #define EMAC1_TXLATECOL             0xFFC22158         /* EMAC1 Number of frames aborted due to late collision error */
1188 #define EMAC1_TXEXCESSCOL           0xFFC2215C         /* EMAC1 Number of aborted frames due to excessive collisions */
1189 #define EMAC1_TXCARR_ERR            0xFFC22160         /* EMAC1 Number of aborted frames due to carrier sense error */
1190 #define EMAC1_TXOCTCNT_G            0xFFC22164         /* EMAC1 Number of bytes transmitted in good frames only */
1191 #define EMAC1_TXFRMCNT_G            0xFFC22168         /* EMAC1 Number of good frames transmitted. */
1192 #define EMAC1_TXEXCESSDEF           0xFFC2216C         /* EMAC1 Number of frames aborted due to excessive deferral */
1193 #define EMAC1_TXPAUSEFRM            0xFFC22170         /* EMAC1 Number of good PAUSE frames transmitted. */
1194 #define EMAC1_TXVLANFRM_G           0xFFC22174         /* EMAC1 Number of VLAN frames transmitted */
1195 #define EMAC1_RXFRMCNT_GB           0xFFC22180         /* EMAC1 Number of good and bad frames received. */
1196 #define EMAC1_RXOCTCNT_GB           0xFFC22184         /* EMAC1 Number of bytes received in good and bad frames */
1197 #define EMAC1_RXOCTCNT_G            0xFFC22188         /* EMAC1 Number of bytes received only in good frames */
1198 #define EMAC1_RXBCASTFRM_G          0xFFC2218C         /* EMAC1 Number of good broadcast frames received. */
1199 #define EMAC1_RXMCASTFRM_G          0xFFC22190         /* EMAC1 Number of good multicast frames received */
1200 #define EMAC1_RXCRC_ERR             0xFFC22194         /* EMAC1 Number of frames received with CRC error */
1201 #define EMAC1_RXALIGN_ERR           0xFFC22198         /* EMAC1 Number of frames with alignment error */
1202 #define EMAC1_RXRUNT_ERR            0xFFC2219C         /* EMAC1 Number of frames received with runt error. */
1203 #define EMAC1_RXJAB_ERR             0xFFC221A0         /* EMAC1 Number of frames received with length greater than 1518 */
1204 #define EMAC1_RXUSIZE_G             0xFFC221A4         /* EMAC1 Number of frames received with length 64 */
1205 #define EMAC1_RXOSIZE_G             0xFFC221A8         /* EMAC1 Number of frames received with length greater than maxium */
1206 #define EMAC1_RX64_GB               0xFFC221AC         /* EMAC1 Number of good and bad frames of lengh 64 bytes */
1207 #define EMAC1_RX65TO127_GB          0xFFC221B0         /* EMAC1 Number of good and bad frame between 64-127(inclusive) */
1208 #define EMAC1_RX128TO255_GB         0xFFC221B4         /* EMAC1 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
1209 #define EMAC1_RX256TO511_GB         0xFFC221B8         /* EMAC1 Number of good and bad frames between 256-511(inclusive) */
1210 #define EMAC1_RX512TO1023_GB        0xFFC221BC         /* EMAC1 Number of good and bad frames received between 512-1023 */
1211 #define EMAC1_RX1024TOMAX_GB        0xFFC221C0         /* EMAC1 Number of frames received between 1024 and maxsize */
1212 #define EMAC1_RXUCASTFRM_G          0xFFC221C4         /* EMAC1 Number of good unicast frames received. */
1213 #define EMAC1_RXLEN_ERR             0xFFC221C8         /* EMAC1 Number of frames received with length error */
1214 #define EMAC1_RXOORTYPE             0xFFC221CC         /* EMAC1 Number of frames with length not equal to valid frame size */
1215 #define EMAC1_RXPAUSEFRM            0xFFC221D0         /* EMAC1 Number of good and valid PAUSE frames received. */
1216 #define EMAC1_RXFIFO_OVF            0xFFC221D4         /* EMAC1 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
1217 #define EMAC1_RXVLANFRM_GB          0xFFC221D8         /* EMAC1 Number of good and bad VLAN frames received. */
1218 #define EMAC1_RXWDOG_ERR            0xFFC221DC         /* EMAC1 Frames received with error due to watchdog timeout */
1219 #define EMAC1_IPC_RXIMSK            0xFFC22200         /* EMAC1 MMC IPC RX Interrupt Mask Register */
1220 #define EMAC1_IPC_RXINT             0xFFC22208         /* EMAC1 MMC IPC RX Interrupt Register */
1221 #define EMAC1_RXIPV4_GD_FRM         0xFFC22210         /* EMAC1 Number of good IPv4 datagrams */
1222 #define EMAC1_RXIPV4_HDR_ERR_FRM    0xFFC22214         /* EMAC1 Number of IPv4 datagrams with header errors */
1223 #define EMAC1_RXIPV4_NOPAY_FRM      0xFFC22218         /* EMAC1 Number of IPv4 datagrams without checksum */
1224 #define EMAC1_RXIPV4_FRAG_FRM       0xFFC2221C         /* EMAC1 Number of good IPv4 datagrams with fragmentation */
1225 #define EMAC1_RXIPV4_UDSBL_FRM      0xFFC22220         /* EMAC1 Number of IPv4 UDP datagrams with disabled checksum */
1226 #define EMAC1_RXIPV6_GD_FRM         0xFFC22224         /* EMAC1 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
1227 #define EMAC1_RXIPV6_HDR_ERR_FRM    0xFFC22228         /* EMAC1 Number of IPv6 datagrams with header errors */
1228 #define EMAC1_RXIPV6_NOPAY_FRM      0xFFC2222C         /* EMAC1 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
1229 #define EMAC1_RXUDP_GD_FRM          0xFFC22230         /* EMAC1 Number of good IP datagrames with good UDP payload */
1230 #define EMAC1_RXUDP_ERR_FRM         0xFFC22234         /* EMAC1 Number of good IP datagrams with UDP checksum errors */
1231 #define EMAC1_RXTCP_GD_FRM          0xFFC22238         /* EMAC1 Number of good IP datagrams with a good TCP payload */
1232 #define EMAC1_RXTCP_ERR_FRM         0xFFC2223C         /* EMAC1 Number of good IP datagrams with TCP checksum errors */
1233 #define EMAC1_RXICMP_GD_FRM         0xFFC22240         /* EMAC1 Number of good IP datagrams with a good ICMP payload */
1234 #define EMAC1_RXICMP_ERR_FRM        0xFFC22244         /* EMAC1 Number of good IP datagrams with ICMP checksum errors */
1235 #define EMAC1_RXIPV4_GD_OCT         0xFFC22250         /* EMAC1 Bytes received in IPv4 datagrams including tcp,udp or icmp */
1236 #define EMAC1_RXIPV4_HDR_ERR_OCT    0xFFC22254         /* EMAC1 Bytes received in IPv4 datagrams with header errors */
1237 #define EMAC1_RXIPV4_NOPAY_OCT      0xFFC22258         /* EMAC1 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
1238 #define EMAC1_RXIPV4_FRAG_OCT       0xFFC2225C         /* EMAC1 Bytes received in fragmented IPv4 datagrams */
1239 #define EMAC1_RXIPV4_UDSBL_OCT      0xFFC22260         /* EMAC1 Bytes received in UDP segment with checksum disabled */
1240 #define EMAC1_RXIPV6_GD_OCT         0xFFC22264         /* EMAC1 Bytes received in good IPv6  including tcp,udp or icmp load */
1241 #define EMAC1_RXIPV6_HDR_ERR_OCT    0xFFC22268         /* EMAC1 Number of bytes received in IPv6 with header errors */
1242 #define EMAC1_RXIPV6_NOPAY_OCT      0xFFC2226C         /* EMAC1 Bytes received in IPv6 without tcp,udp or icmp load */
1243 #define EMAC1_RXUDP_GD_OCT          0xFFC22270         /* EMAC1 Number of bytes received in good UDP segments */
1244 #define EMAC1_RXUDP_ERR_OCT         0xFFC22274         /* EMAC1 Number of bytes received in UDP segment with checksum err */
1245 #define EMAC1_RXTCP_GD_OCT          0xFFC22278         /* EMAC1 Number of bytes received in a good TCP segment */
1246 #define EMAC1_RXTCP_ERR_OCT         0xFFC2227C         /* EMAC1 Number of bytes received in TCP segment with checksum err */
1247 #define EMAC1_RXICMP_GD_OCT         0xFFC22280         /* EMAC1 Number of bytes received in a good ICMP segment */
1248 #define EMAC1_RXICMP_ERR_OCT        0xFFC22284         /* EMAC1 Bytes received in an ICMP segment with checksum errors */
1249 #define EMAC1_TM_CTL                0xFFC22700         /* EMAC1 EMAC Time Stamp Control Register */
1250 #define EMAC1_TM_SUBSEC             0xFFC22704         /* EMAC1 EMAC Time Stamp Sub Second Increment */
1251 #define EMAC1_TM_SEC                0xFFC22708         /* EMAC1 EMAC Time Stamp Second Register */
1252 #define EMAC1_TM_NSEC               0xFFC2270C         /* EMAC1 EMAC Time Stamp Nano Second Register */
1253 #define EMAC1_TM_SECUPDT            0xFFC22710         /* EMAC1 EMAC Time Stamp Seconds Update */
1254 #define EMAC1_TM_NSECUPDT           0xFFC22714         /* EMAC1 EMAC Time Stamp Nano Seconds Update */
1255 #define EMAC1_TM_ADDEND             0xFFC22718         /* EMAC1 EMAC Time Stamp Addend Register */
1256 #define EMAC1_TM_TGTM               0xFFC2271C         /* EMAC1 EMAC Time Stamp Target Time Sec. */
1257 #define EMAC1_TM_NTGTM              0xFFC22720         /* EMAC1 EMAC Time Stamp Target Time Nanosec. */
1258 #define EMAC1_TM_HISEC              0xFFC22724         /* EMAC1 EMAC Time Stamp High Second Register */
1259 #define EMAC1_TM_STMPSTAT           0xFFC22728         /* EMAC1 EMAC Time Stamp Status Register */
1260 #define EMAC1_TM_PPSCTL             0xFFC2272C         /* EMAC1 EMAC PPS Control Register */
1261 #define EMAC1_TM_AUXSTMP_NSEC       0xFFC22730         /* EMAC1 EMAC Auxillary Time Stamp Nano Register */
1262 #define EMAC1_TM_AUXSTMP_SEC        0xFFC22734         /* EMAC1 EMAC Auxillary Time Stamp Sec Register */
1263 #define EMAC1_DMA_BUSMODE           0xFFC23000         /* EMAC1 Bus Operating Modes for EMAC DMA */
1264 #define EMAC1_DMA_TXPOLL            0xFFC23004         /* EMAC1 TX DMA Poll demand register */
1265 #define EMAC1_DMA_RXPOLL            0xFFC23008         /* EMAC1 RX DMA Poll demand register */
1266 #define EMAC1_DMA_RXDSC_ADDR        0xFFC2300C         /* EMAC1 RX Descriptor List Address */
1267 #define EMAC1_DMA_TXDSC_ADDR        0xFFC23010         /* EMAC1 TX Descriptor List Address */
1268 #define EMAC1_DMA_STAT              0xFFC23014         /* EMAC1 DMA Status Register */
1269 #define EMAC1_DMA_OPMODE            0xFFC23018         /* EMAC1 DMA Operation Mode Register */
1270 #define EMAC1_DMA_IEN               0xFFC2301C         /* EMAC1 DMA Interrupt Enable Register */
1271 #define EMAC1_DMA_MISS_FRM          0xFFC23020         /* EMAC1 DMA missed frame and buffer overflow counter */
1272 #define EMAC1_DMA_RXIWDOG           0xFFC23024         /* EMAC1 DMA RX Interrupt Watch Dog timer */
1273 #define EMAC1_DMA_BMMODE            0xFFC23028         /* EMAC1 AXI Bus Mode Register */
1274 #define EMAC1_DMA_BMSTAT            0xFFC2302C         /* EMAC1 AXI Status Register */
1275 #define EMAC1_DMA_TXDSC_CUR         0xFFC23048         /* EMAC1 TX current descriptor register */
1276 #define EMAC1_DMA_RXDSC_CUR         0xFFC2304C         /* EMAC1 RX current descriptor register */
1277 #define EMAC1_DMA_TXBUF_CUR         0xFFC23050         /* EMAC1 TX current buffer pointer register */
1278 #define EMAC1_DMA_RXBUF_CUR         0xFFC23054         /* EMAC1 RX current buffer pointer register */
1279 #define EMAC1_HWFEAT                0xFFC23058         /* EMAC1 Hardware Feature Register */
1280 
1281 
1282 /* =========================
1283         SPI Registers
1284    ========================= */
1285 
1286 /* =========================
1287         SPI0
1288    ========================= */
1289 #define SPI0_REGBASE                0xFFC40400
1290 #define SPI0_CTL                    0xFFC40404         /* SPI0 Control Register */
1291 #define SPI0_RXCTL                  0xFFC40408         /* SPI0 RX Control Register */
1292 #define SPI0_TXCTL                  0xFFC4040C         /* SPI0 TX Control Register */
1293 #define SPI0_CLK                    0xFFC40410         /* SPI0 Clock Rate Register */
1294 #define SPI0_DLY                    0xFFC40414         /* SPI0 Delay Register */
1295 #define SPI0_SLVSEL                 0xFFC40418         /* SPI0 Slave Select Register */
1296 #define SPI0_RWC                    0xFFC4041C         /* SPI0 Received Word-Count Register */
1297 #define SPI0_RWCR                   0xFFC40420         /* SPI0 Received Word-Count Reload Register */
1298 #define SPI0_TWC                    0xFFC40424         /* SPI0 Transmitted Word-Count Register */
1299 #define SPI0_TWCR                   0xFFC40428         /* SPI0 Transmitted Word-Count Reload Register */
1300 #define SPI0_IMSK                   0xFFC40430         /* SPI0 Interrupt Mask Register */
1301 #define SPI0_IMSK_CLR               0xFFC40434         /* SPI0 Interrupt Mask Clear Register */
1302 #define SPI0_IMSK_SET               0xFFC40438         /* SPI0 Interrupt Mask Set Register */
1303 #define SPI0_STAT                   0xFFC40440         /* SPI0 Status Register */
1304 #define SPI0_ILAT                   0xFFC40444         /* SPI0 Masked Interrupt Condition Register */
1305 #define SPI0_ILAT_CLR               0xFFC40448         /* SPI0 Masked Interrupt Clear Register */
1306 #define SPI0_RFIFO                  0xFFC40450         /* SPI0 Receive FIFO Data Register */
1307 #define SPI0_TFIFO                  0xFFC40458         /* SPI0 Transmit FIFO Data Register */
1308 
1309 /* =========================
1310         SPI1
1311    ========================= */
1312 #define SPI1_REGBASE                0xFFC40500
1313 #define SPI1_CTL                    0xFFC40504         /* SPI1 Control Register */
1314 #define SPI1_RXCTL                  0xFFC40508         /* SPI1 RX Control Register */
1315 #define SPI1_TXCTL                  0xFFC4050C         /* SPI1 TX Control Register */
1316 #define SPI1_CLK                    0xFFC40510         /* SPI1 Clock Rate Register */
1317 #define SPI1_DLY                    0xFFC40514         /* SPI1 Delay Register */
1318 #define SPI1_SLVSEL                 0xFFC40518         /* SPI1 Slave Select Register */
1319 #define SPI1_RWC                    0xFFC4051C         /* SPI1 Received Word-Count Register */
1320 #define SPI1_RWCR                   0xFFC40520         /* SPI1 Received Word-Count Reload Register */
1321 #define SPI1_TWC                    0xFFC40524         /* SPI1 Transmitted Word-Count Register */
1322 #define SPI1_TWCR                   0xFFC40528         /* SPI1 Transmitted Word-Count Reload Register */
1323 #define SPI1_IMSK                   0xFFC40530         /* SPI1 Interrupt Mask Register */
1324 #define SPI1_IMSK_CLR               0xFFC40534         /* SPI1 Interrupt Mask Clear Register */
1325 #define SPI1_IMSK_SET               0xFFC40538         /* SPI1 Interrupt Mask Set Register */
1326 #define SPI1_STAT                   0xFFC40540         /* SPI1 Status Register */
1327 #define SPI1_ILAT                   0xFFC40544         /* SPI1 Masked Interrupt Condition Register */
1328 #define SPI1_ILAT_CLR               0xFFC40548         /* SPI1 Masked Interrupt Clear Register */
1329 #define SPI1_RFIFO                  0xFFC40550         /* SPI1 Receive FIFO Data Register */
1330 #define SPI1_TFIFO                  0xFFC40558         /* SPI1 Transmit FIFO Data Register */
1331 
1332 /* =========================
1333 	SPORT Registers
1334    ========================= */
1335 
1336 /* =========================
1337 	SPORT0
1338    ========================= */
1339 #define SPORT0_CTL_A                0xFFC40000         /* SPORT0 'A' Control Register */
1340 #define SPORT0_DIV_A                0xFFC40004         /* SPORT0 'A' Clock and FS Divide Register */
1341 #define SPORT0_MCTL_A               0xFFC40008         /* SPORT0 'A' Multichannel Control Register */
1342 #define SPORT0_CS0_A                0xFFC4000C         /* SPORT0 'A' Multichannel Select Register (Channels 0-31) */
1343 #define SPORT0_CS1_A                0xFFC40010         /* SPORT0 'A' Multichannel Select Register (Channels 32-63) */
1344 #define SPORT0_CS2_A                0xFFC40014         /* SPORT0 'A' Multichannel Select Register (Channels 64-95) */
1345 #define SPORT0_CS3_A                0xFFC40018         /* SPORT0 'A' Multichannel Select Register (Channels 96-127) */
1346 #define SPORT0_CNT_A                0xFFC4001C         /* SPORT0 'A' Frame Sync And Clock Divisor Current Count */
1347 #define SPORT0_ERR_A                0xFFC40020         /* SPORT0 'A' Error Register */
1348 #define SPORT0_MSTAT_A              0xFFC40024         /* SPORT0 'A' Multichannel Mode Status Register */
1349 #define SPORT0_CTL2_A               0xFFC40028         /* SPORT0 'A' Control Register 2 */
1350 #define SPORT0_TXPRI_A              0xFFC40040         /* SPORT0 'A' Primary Channel Transmit Buffer Register */
1351 #define SPORT0_RXPRI_A              0xFFC40044         /* SPORT0 'A' Primary Channel Receive Buffer Register */
1352 #define SPORT0_TXSEC_A              0xFFC40048         /* SPORT0 'A' Secondary Channel Transmit Buffer Register */
1353 #define SPORT0_RXSEC_A              0xFFC4004C         /* SPORT0 'A' Secondary Channel Receive Buffer Register */
1354 #define SPORT0_CTL_B                0xFFC40080         /* SPORT0 'B' Control Register */
1355 #define SPORT0_DIV_B                0xFFC40084         /* SPORT0 'B' Clock and FS Divide Register */
1356 #define SPORT0_MCTL_B               0xFFC40088         /* SPORT0 'B' Multichannel Control Register */
1357 #define SPORT0_CS0_B                0xFFC4008C         /* SPORT0 'B' Multichannel Select Register (Channels 0-31) */
1358 #define SPORT0_CS1_B                0xFFC40090         /* SPORT0 'B' Multichannel Select Register (Channels 32-63) */
1359 #define SPORT0_CS2_B                0xFFC40094         /* SPORT0 'B' Multichannel Select Register (Channels 64-95) */
1360 #define SPORT0_CS3_B                0xFFC40098         /* SPORT0 'B' Multichannel Select Register (Channels 96-127) */
1361 #define SPORT0_CNT_B                0xFFC4009C         /* SPORT0 'B' Frame Sync And Clock Divisor Current Count */
1362 #define SPORT0_ERR_B                0xFFC400A0         /* SPORT0 'B' Error Register */
1363 #define SPORT0_MSTAT_B              0xFFC400A4         /* SPORT0 'B' Multichannel Mode Status Register */
1364 #define SPORT0_CTL2_B               0xFFC400A8         /* SPORT0 'B' Control Register 2 */
1365 #define SPORT0_TXPRI_B              0xFFC400C0         /* SPORT0 'B' Primary Channel Transmit Buffer Register */
1366 #define SPORT0_RXPRI_B              0xFFC400C4         /* SPORT0 'B' Primary Channel Receive Buffer Register */
1367 #define SPORT0_TXSEC_B              0xFFC400C8         /* SPORT0 'B' Secondary Channel Transmit Buffer Register */
1368 #define SPORT0_RXSEC_B              0xFFC400CC         /* SPORT0 'B' Secondary Channel Receive Buffer Register */
1369 
1370 /* =========================
1371 	SPORT1
1372    ========================= */
1373 #define SPORT1_CTL_A                0xFFC40100         /* SPORT1 'A' Control Register */
1374 #define SPORT1_DIV_A                0xFFC40104         /* SPORT1 'A' Clock and FS Divide Register */
1375 #define SPORT1_MCTL_A               0xFFC40108         /* SPORT1 'A' Multichannel Control Register */
1376 #define SPORT1_CS0_A                0xFFC4010C         /* SPORT1 'A' Multichannel Select Register (Channels 0-31) */
1377 #define SPORT1_CS1_A                0xFFC40110         /* SPORT1 'A' Multichannel Select Register (Channels 32-63) */
1378 #define SPORT1_CS2_A                0xFFC40114         /* SPORT1 'A' Multichannel Select Register (Channels 64-95) */
1379 #define SPORT1_CS3_A                0xFFC40118         /* SPORT1 'A' Multichannel Select Register (Channels 96-127) */
1380 #define SPORT1_CNT_A                0xFFC4011C         /* SPORT1 'A' Frame Sync And Clock Divisor Current Count */
1381 #define SPORT1_ERR_A                0xFFC40120         /* SPORT1 'A' Error Register */
1382 #define SPORT1_MSTAT_A              0xFFC40124         /* SPORT1 'A' Multichannel Mode Status Register */
1383 #define SPORT1_CTL2_A               0xFFC40128         /* SPORT1 'A' Control Register 2 */
1384 #define SPORT1_TXPRI_A              0xFFC40140         /* SPORT1 'A' Primary Channel Transmit Buffer Register */
1385 #define SPORT1_RXPRI_A              0xFFC40144         /* SPORT1 'A' Primary Channel Receive Buffer Register */
1386 #define SPORT1_TXSEC_A              0xFFC40148         /* SPORT1 'A' Secondary Channel Transmit Buffer Register */
1387 #define SPORT1_RXSEC_A              0xFFC4014C         /* SPORT1 'A' Secondary Channel Receive Buffer Register */
1388 #define SPORT1_CTL_B                0xFFC40180         /* SPORT1 'B' Control Register */
1389 #define SPORT1_DIV_B                0xFFC40184         /* SPORT1 'B' Clock and FS Divide Register */
1390 #define SPORT1_MCTL_B               0xFFC40188         /* SPORT1 'B' Multichannel Control Register */
1391 #define SPORT1_CS0_B                0xFFC4018C         /* SPORT1 'B' Multichannel Select Register (Channels 0-31) */
1392 #define SPORT1_CS1_B                0xFFC40190         /* SPORT1 'B' Multichannel Select Register (Channels 32-63) */
1393 #define SPORT1_CS2_B                0xFFC40194         /* SPORT1 'B' Multichannel Select Register (Channels 64-95) */
1394 #define SPORT1_CS3_B                0xFFC40198         /* SPORT1 'B' Multichannel Select Register (Channels 96-127) */
1395 #define SPORT1_CNT_B                0xFFC4019C         /* SPORT1 'B' Frame Sync And Clock Divisor Current Count */
1396 #define SPORT1_ERR_B                0xFFC401A0         /* SPORT1 'B' Error Register */
1397 #define SPORT1_MSTAT_B              0xFFC401A4         /* SPORT1 'B' Multichannel Mode Status Register */
1398 #define SPORT1_CTL2_B               0xFFC401A8         /* SPORT1 'B' Control Register 2 */
1399 #define SPORT1_TXPRI_B              0xFFC401C0         /* SPORT1 'B' Primary Channel Transmit Buffer Register */
1400 #define SPORT1_RXPRI_B              0xFFC401C4         /* SPORT1 'B' Primary Channel Receive Buffer Register */
1401 #define SPORT1_TXSEC_B              0xFFC401C8         /* SPORT1 'B' Secondary Channel Transmit Buffer Register */
1402 #define SPORT1_RXSEC_B              0xFFC401CC         /* SPORT1 'B' Secondary Channel Receive Buffer Register */
1403 
1404 /* =========================
1405 	SPORT2
1406    ========================= */
1407 #define SPORT2_CTL_A                0xFFC40200         /* SPORT2 'A' Control Register */
1408 #define SPORT2_DIV_A                0xFFC40204         /* SPORT2 'A' Clock and FS Divide Register */
1409 #define SPORT2_MCTL_A               0xFFC40208         /* SPORT2 'A' Multichannel Control Register */
1410 #define SPORT2_CS0_A                0xFFC4020C         /* SPORT2 'A' Multichannel Select Register (Channels 0-31) */
1411 #define SPORT2_CS1_A                0xFFC40210         /* SPORT2 'A' Multichannel Select Register (Channels 32-63) */
1412 #define SPORT2_CS2_A                0xFFC40214         /* SPORT2 'A' Multichannel Select Register (Channels 64-95) */
1413 #define SPORT2_CS3_A                0xFFC40218         /* SPORT2 'A' Multichannel Select Register (Channels 96-127) */
1414 #define SPORT2_CNT_A                0xFFC4021C         /* SPORT2 'A' Frame Sync And Clock Divisor Current Count */
1415 #define SPORT2_ERR_A                0xFFC40220         /* SPORT2 'A' Error Register */
1416 #define SPORT2_MSTAT_A              0xFFC40224         /* SPORT2 'A' Multichannel Mode Status Register */
1417 #define SPORT2_CTL2_A               0xFFC40228         /* SPORT2 'A' Control Register 2 */
1418 #define SPORT2_TXPRI_A              0xFFC40240         /* SPORT2 'A' Primary Channel Transmit Buffer Register */
1419 #define SPORT2_RXPRI_A              0xFFC40244         /* SPORT2 'A' Primary Channel Receive Buffer Register */
1420 #define SPORT2_TXSEC_A              0xFFC40248         /* SPORT2 'A' Secondary Channel Transmit Buffer Register */
1421 #define SPORT2_RXSEC_A              0xFFC4024C         /* SPORT2 'A' Secondary Channel Receive Buffer Register */
1422 #define SPORT2_CTL_B                0xFFC40280         /* SPORT2 'B' Control Register */
1423 #define SPORT2_DIV_B                0xFFC40284         /* SPORT2 'B' Clock and FS Divide Register */
1424 #define SPORT2_MCTL_B               0xFFC40288         /* SPORT2 'B' Multichannel Control Register */
1425 #define SPORT2_CS0_B                0xFFC4028C         /* SPORT2 'B' Multichannel Select Register (Channels 0-31) */
1426 #define SPORT2_CS1_B                0xFFC40290         /* SPORT2 'B' Multichannel Select Register (Channels 32-63) */
1427 #define SPORT2_CS2_B                0xFFC40294         /* SPORT2 'B' Multichannel Select Register (Channels 64-95) */
1428 #define SPORT2_CS3_B                0xFFC40298         /* SPORT2 'B' Multichannel Select Register (Channels 96-127) */
1429 #define SPORT2_CNT_B                0xFFC4029C         /* SPORT2 'B' Frame Sync And Clock Divisor Current Count */
1430 #define SPORT2_ERR_B                0xFFC402A0         /* SPORT2 'B' Error Register */
1431 #define SPORT2_MSTAT_B              0xFFC402A4         /* SPORT2 'B' Multichannel Mode Status Register */
1432 #define SPORT2_CTL2_B               0xFFC402A8         /* SPORT2 'B' Control Register 2 */
1433 #define SPORT2_TXPRI_B              0xFFC402C0         /* SPORT2 'B' Primary Channel Transmit Buffer Register */
1434 #define SPORT2_RXPRI_B              0xFFC402C4         /* SPORT2 'B' Primary Channel Receive Buffer Register */
1435 #define SPORT2_TXSEC_B              0xFFC402C8         /* SPORT2 'B' Secondary Channel Transmit Buffer Register */
1436 #define SPORT2_RXSEC_B              0xFFC402CC         /* SPORT2 'B' Secondary Channel Receive Buffer Register */
1437 
1438 /* =========================
1439 	EPPI Registers
1440    ========================= */
1441 
1442 /* =========================
1443 	EPPI0
1444    ========================= */
1445 #define EPPI0_STAT                  0xFFC18000         /* EPPI0 Status Register */
1446 #define EPPI0_HCNT                  0xFFC18004         /* EPPI0 Horizontal Transfer Count Register */
1447 #define EPPI0_HDLY                  0xFFC18008         /* EPPI0 Horizontal Delay Count Register */
1448 #define EPPI0_VCNT                  0xFFC1800C         /* EPPI0 Vertical Transfer Count Register */
1449 #define EPPI0_VDLY                  0xFFC18010         /* EPPI0 Vertical Delay Count Register */
1450 #define EPPI0_FRAME                 0xFFC18014         /* EPPI0 Lines Per Frame Register */
1451 #define EPPI0_LINE                  0xFFC18018         /* EPPI0 Samples Per Line Register */
1452 #define EPPI0_CLKDIV                0xFFC1801C         /* EPPI0 Clock Divide Register */
1453 #define EPPI0_CTL                   0xFFC18020         /* EPPI0 Control Register */
1454 #define EPPI0_FS1_WLHB              0xFFC18024         /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
1455 #define EPPI0_FS1_PASPL             0xFFC18028         /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
1456 #define EPPI0_FS2_WLVB              0xFFC1802C         /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
1457 #define EPPI0_FS2_PALPF             0xFFC18030         /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
1458 #define EPPI0_IMSK                  0xFFC18034         /* EPPI0 Interrupt Mask Register */
1459 #define EPPI0_ODDCLIP               0xFFC1803C         /* EPPI0 Clipping Register for ODD (Chroma) Data */
1460 #define EPPI0_EVENCLIP              0xFFC18040         /* EPPI0 Clipping Register for EVEN (Luma) Data */
1461 #define EPPI0_FS1_DLY               0xFFC18044         /* EPPI0 Frame Sync 1 Delay Value */
1462 #define EPPI0_FS2_DLY               0xFFC18048         /* EPPI0 Frame Sync 2 Delay Value */
1463 #define EPPI0_CTL2                  0xFFC1804C         /* EPPI0 Control Register 2 */
1464 
1465 /* =========================
1466 	EPPI1
1467    ========================= */
1468 #define EPPI1_STAT                  0xFFC18400         /* EPPI1 Status Register */
1469 #define EPPI1_HCNT                  0xFFC18404         /* EPPI1 Horizontal Transfer Count Register */
1470 #define EPPI1_HDLY                  0xFFC18408         /* EPPI1 Horizontal Delay Count Register */
1471 #define EPPI1_VCNT                  0xFFC1840C         /* EPPI1 Vertical Transfer Count Register */
1472 #define EPPI1_VDLY                  0xFFC18410         /* EPPI1 Vertical Delay Count Register */
1473 #define EPPI1_FRAME                 0xFFC18414         /* EPPI1 Lines Per Frame Register */
1474 #define EPPI1_LINE                  0xFFC18418         /* EPPI1 Samples Per Line Register */
1475 #define EPPI1_CLKDIV                0xFFC1841C         /* EPPI1 Clock Divide Register */
1476 #define EPPI1_CTL                   0xFFC18420         /* EPPI1 Control Register */
1477 #define EPPI1_FS1_WLHB              0xFFC18424         /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
1478 #define EPPI1_FS1_PASPL             0xFFC18428         /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
1479 #define EPPI1_FS2_WLVB              0xFFC1842C         /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
1480 #define EPPI1_FS2_PALPF             0xFFC18430         /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
1481 #define EPPI1_IMSK                  0xFFC18434         /* EPPI1 Interrupt Mask Register */
1482 #define EPPI1_ODDCLIP               0xFFC1843C         /* EPPI1 Clipping Register for ODD (Chroma) Data */
1483 #define EPPI1_EVENCLIP              0xFFC18440         /* EPPI1 Clipping Register for EVEN (Luma) Data */
1484 #define EPPI1_FS1_DLY               0xFFC18444         /* EPPI1 Frame Sync 1 Delay Value */
1485 #define EPPI1_FS2_DLY               0xFFC18448         /* EPPI1 Frame Sync 2 Delay Value */
1486 #define EPPI1_CTL2                  0xFFC1844C         /* EPPI1 Control Register 2 */
1487 
1488 /* =========================
1489 	EPPI2
1490    ========================= */
1491 #define EPPI2_STAT                  0xFFC18800         /* EPPI2 Status Register */
1492 #define EPPI2_HCNT                  0xFFC18804         /* EPPI2 Horizontal Transfer Count Register */
1493 #define EPPI2_HDLY                  0xFFC18808         /* EPPI2 Horizontal Delay Count Register */
1494 #define EPPI2_VCNT                  0xFFC1880C         /* EPPI2 Vertical Transfer Count Register */
1495 #define EPPI2_VDLY                  0xFFC18810         /* EPPI2 Vertical Delay Count Register */
1496 #define EPPI2_FRAME                 0xFFC18814         /* EPPI2 Lines Per Frame Register */
1497 #define EPPI2_LINE                  0xFFC18818         /* EPPI2 Samples Per Line Register */
1498 #define EPPI2_CLKDIV                0xFFC1881C         /* EPPI2 Clock Divide Register */
1499 #define EPPI2_CTL                   0xFFC18820         /* EPPI2 Control Register */
1500 #define EPPI2_FS1_WLHB              0xFFC18824         /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
1501 #define EPPI2_FS1_PASPL             0xFFC18828         /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
1502 #define EPPI2_FS2_WLVB              0xFFC1882C         /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
1503 #define EPPI2_FS2_PALPF             0xFFC18830         /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
1504 #define EPPI2_IMSK                  0xFFC18834         /* EPPI2 Interrupt Mask Register */
1505 #define EPPI2_ODDCLIP               0xFFC1883C         /* EPPI2 Clipping Register for ODD (Chroma) Data */
1506 #define EPPI2_EVENCLIP              0xFFC18840         /* EPPI2 Clipping Register for EVEN (Luma) Data */
1507 #define EPPI2_FS1_DLY               0xFFC18844         /* EPPI2 Frame Sync 1 Delay Value */
1508 #define EPPI2_FS2_DLY               0xFFC18848         /* EPPI2 Frame Sync 2 Delay Value */
1509 #define EPPI2_CTL2                  0xFFC1884C         /* EPPI2 Control Register 2 */
1510 
1511 
1512 
1513 /* =========================
1514         DDE Registers
1515    ========================= */
1516 
1517 /* =========================
1518         DMA0
1519    ========================= */
1520 #define DMA0_NEXT_DESC_PTR          0xFFC41000         /* DMA0 Pointer to Next Initial Descriptor */
1521 #define DMA0_START_ADDR             0xFFC41004         /* DMA0 Start Address of Current Buffer */
1522 #define DMA0_CONFIG                 0xFFC41008         /* DMA0 Configuration Register */
1523 #define DMA0_X_COUNT                0xFFC4100C         /* DMA0 Inner Loop Count Start Value */
1524 #define DMA0_X_MODIFY               0xFFC41010         /* DMA0 Inner Loop Address Increment */
1525 #define DMA0_Y_COUNT                0xFFC41014         /* DMA0 Outer Loop Count Start Value (2D only) */
1526 #define DMA0_Y_MODIFY               0xFFC41018         /* DMA0 Outer Loop Address Increment (2D only) */
1527 #define DMA0_CURR_DESC_PTR          0xFFC41024         /* DMA0 Current Descriptor Pointer */
1528 #define DMA0_PREV_DESC_PTR          0xFFC41028         /* DMA0 Previous Initial Descriptor Pointer */
1529 #define DMA0_CURR_ADDR              0xFFC4102C         /* DMA0 Current Address */
1530 #define DMA0_IRQ_STATUS             0xFFC41030         /* DMA0 Status Register */
1531 #define DMA0_CURR_X_COUNT           0xFFC41034         /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
1532 #define DMA0_CURR_Y_COUNT           0xFFC41038         /* DMA0 Current Row Count (2D only) */
1533 #define DMA0_BWL_COUNT              0xFFC41040         /* DMA0 Bandwidth Limit Count */
1534 #define DMA0_CURR_BWL_COUNT         0xFFC41044         /* DMA0 Bandwidth Limit Count Current */
1535 #define DMA0_BWM_COUNT              0xFFC41048         /* DMA0 Bandwidth Monitor Count */
1536 #define DMA0_CURR_BWM_COUNT         0xFFC4104C         /* DMA0 Bandwidth Monitor Count Current */
1537 
1538 /* =========================
1539         DMA1
1540    ========================= */
1541 #define DMA1_NEXT_DESC_PTR             0xFFC41080         /* DMA1 Pointer to Next Initial Descriptor */
1542 #define DMA1_START_ADDR              0xFFC41084         /* DMA1 Start Address of Current Buffer */
1543 #define DMA1_CONFIG                    0xFFC41088         /* DMA1 Configuration Register */
1544 #define DMA1_X_COUNT                   0xFFC4108C         /* DMA1 Inner Loop Count Start Value */
1545 #define DMA1_X_MODIFY                   0xFFC41090         /* DMA1 Inner Loop Address Increment */
1546 #define DMA1_Y_COUNT                   0xFFC41094         /* DMA1 Outer Loop Count Start Value (2D only) */
1547 #define DMA1_Y_MODIFY                   0xFFC41098         /* DMA1 Outer Loop Address Increment (2D only) */
1548 #define DMA1_CURR_DESC_PTR             0xFFC410A4         /* DMA1 Current Descriptor Pointer */
1549 #define DMA1_PREV_DESC_PTR             0xFFC410A8         /* DMA1 Previous Initial Descriptor Pointer */
1550 #define DMA1_CURR_ADDR               0xFFC410AC         /* DMA1 Current Address */
1551 #define DMA1_IRQ_STATUS                   0xFFC410B0         /* DMA1 Status Register */
1552 #define DMA1_CURR_X_COUNT               0xFFC410B4         /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
1553 #define DMA1_CURR_Y_COUNT               0xFFC410B8         /* DMA1 Current Row Count (2D only) */
1554 #define DMA1_BWL_COUNT                 0xFFC410C0         /* DMA1 Bandwidth Limit Count */
1555 #define DMA1_CURR_BWL_COUNT             0xFFC410C4         /* DMA1 Bandwidth Limit Count Current */
1556 #define DMA1_BWM_COUNT                 0xFFC410C8         /* DMA1 Bandwidth Monitor Count */
1557 #define DMA1_CURR_BWM_COUNT             0xFFC410CC         /* DMA1 Bandwidth Monitor Count Current */
1558 
1559 /* =========================
1560         DMA2
1561    ========================= */
1562 #define DMA2_NEXT_DESC_PTR             0xFFC41100         /* DMA2 Pointer to Next Initial Descriptor */
1563 #define DMA2_START_ADDR              0xFFC41104         /* DMA2 Start Address of Current Buffer */
1564 #define DMA2_CONFIG                    0xFFC41108         /* DMA2 Configuration Register */
1565 #define DMA2_X_COUNT                   0xFFC4110C         /* DMA2 Inner Loop Count Start Value */
1566 #define DMA2_X_MODIFY                   0xFFC41110         /* DMA2 Inner Loop Address Increment */
1567 #define DMA2_Y_COUNT                   0xFFC41114         /* DMA2 Outer Loop Count Start Value (2D only) */
1568 #define DMA2_Y_MODIFY                   0xFFC41118         /* DMA2 Outer Loop Address Increment (2D only) */
1569 #define DMA2_CURR_DESC_PTR             0xFFC41124         /* DMA2 Current Descriptor Pointer */
1570 #define DMA2_PREV_DESC_PTR             0xFFC41128         /* DMA2 Previous Initial Descriptor Pointer */
1571 #define DMA2_CURR_ADDR               0xFFC4112C         /* DMA2 Current Address */
1572 #define DMA2_IRQ_STATUS                   0xFFC41130         /* DMA2 Status Register */
1573 #define DMA2_CURR_X_COUNT               0xFFC41134         /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
1574 #define DMA2_CURR_Y_COUNT               0xFFC41138         /* DMA2 Current Row Count (2D only) */
1575 #define DMA2_BWL_COUNT                 0xFFC41140         /* DMA2 Bandwidth Limit Count */
1576 #define DMA2_CURR_BWL_COUNT             0xFFC41144         /* DMA2 Bandwidth Limit Count Current */
1577 #define DMA2_BWM_COUNT                 0xFFC41148         /* DMA2 Bandwidth Monitor Count */
1578 #define DMA2_CURR_BWM_COUNT             0xFFC4114C         /* DMA2 Bandwidth Monitor Count Current */
1579 
1580 /* =========================
1581         DMA3
1582    ========================= */
1583 #define DMA3_NEXT_DESC_PTR             0xFFC41180         /* DMA3 Pointer to Next Initial Descriptor */
1584 #define DMA3_START_ADDR              0xFFC41184         /* DMA3 Start Address of Current Buffer */
1585 #define DMA3_CONFIG                    0xFFC41188         /* DMA3 Configuration Register */
1586 #define DMA3_X_COUNT                   0xFFC4118C         /* DMA3 Inner Loop Count Start Value */
1587 #define DMA3_X_MODIFY                   0xFFC41190         /* DMA3 Inner Loop Address Increment */
1588 #define DMA3_Y_COUNT                   0xFFC41194         /* DMA3 Outer Loop Count Start Value (2D only) */
1589 #define DMA3_Y_MODIFY                   0xFFC41198         /* DMA3 Outer Loop Address Increment (2D only) */
1590 #define DMA3_CURR_DESC_PTR             0xFFC411A4         /* DMA3 Current Descriptor Pointer */
1591 #define DMA3_PREV_DESC_PTR             0xFFC411A8         /* DMA3 Previous Initial Descriptor Pointer */
1592 #define DMA3_CURR_ADDR               0xFFC411AC         /* DMA3 Current Address */
1593 #define DMA3_IRQ_STATUS                   0xFFC411B0         /* DMA3 Status Register */
1594 #define DMA3_CURR_X_COUNT               0xFFC411B4         /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
1595 #define DMA3_CURR_Y_COUNT               0xFFC411B8         /* DMA3 Current Row Count (2D only) */
1596 #define DMA3_BWL_COUNT                 0xFFC411C0         /* DMA3 Bandwidth Limit Count */
1597 #define DMA3_CURR_BWL_COUNT             0xFFC411C4         /* DMA3 Bandwidth Limit Count Current */
1598 #define DMA3_BWM_COUNT                 0xFFC411C8         /* DMA3 Bandwidth Monitor Count */
1599 #define DMA3_CURR_BWM_COUNT             0xFFC411CC         /* DMA3 Bandwidth Monitor Count Current */
1600 
1601 /* =========================
1602         DMA4
1603    ========================= */
1604 #define DMA4_NEXT_DESC_PTR             0xFFC41200         /* DMA4 Pointer to Next Initial Descriptor */
1605 #define DMA4_START_ADDR              0xFFC41204         /* DMA4 Start Address of Current Buffer */
1606 #define DMA4_CONFIG                    0xFFC41208         /* DMA4 Configuration Register */
1607 #define DMA4_X_COUNT                   0xFFC4120C         /* DMA4 Inner Loop Count Start Value */
1608 #define DMA4_X_MODIFY                   0xFFC41210         /* DMA4 Inner Loop Address Increment */
1609 #define DMA4_Y_COUNT                   0xFFC41214         /* DMA4 Outer Loop Count Start Value (2D only) */
1610 #define DMA4_Y_MODIFY                   0xFFC41218         /* DMA4 Outer Loop Address Increment (2D only) */
1611 #define DMA4_CURR_DESC_PTR             0xFFC41224         /* DMA4 Current Descriptor Pointer */
1612 #define DMA4_PREV_DESC_PTR             0xFFC41228         /* DMA4 Previous Initial Descriptor Pointer */
1613 #define DMA4_CURR_ADDR               0xFFC4122C         /* DMA4 Current Address */
1614 #define DMA4_IRQ_STATUS                   0xFFC41230         /* DMA4 Status Register */
1615 #define DMA4_CURR_X_COUNT               0xFFC41234         /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
1616 #define DMA4_CURR_Y_COUNT               0xFFC41238         /* DMA4 Current Row Count (2D only) */
1617 #define DMA4_BWL_COUNT                 0xFFC41240         /* DMA4 Bandwidth Limit Count */
1618 #define DMA4_CURR_BWL_COUNT             0xFFC41244         /* DMA4 Bandwidth Limit Count Current */
1619 #define DMA4_BWM_COUNT                 0xFFC41248         /* DMA4 Bandwidth Monitor Count */
1620 #define DMA4_CURR_BWM_COUNT             0xFFC4124C         /* DMA4 Bandwidth Monitor Count Current */
1621 
1622 /* =========================
1623         DMA5
1624    ========================= */
1625 #define DMA5_NEXT_DESC_PTR             0xFFC41280         /* DMA5 Pointer to Next Initial Descriptor */
1626 #define DMA5_START_ADDR              0xFFC41284         /* DMA5 Start Address of Current Buffer */
1627 #define DMA5_CONFIG                    0xFFC41288         /* DMA5 Configuration Register */
1628 #define DMA5_X_COUNT                   0xFFC4128C         /* DMA5 Inner Loop Count Start Value */
1629 #define DMA5_X_MODIFY                   0xFFC41290         /* DMA5 Inner Loop Address Increment */
1630 #define DMA5_Y_COUNT                   0xFFC41294         /* DMA5 Outer Loop Count Start Value (2D only) */
1631 #define DMA5_Y_MODIFY                   0xFFC41298         /* DMA5 Outer Loop Address Increment (2D only) */
1632 #define DMA5_CURR_DESC_PTR             0xFFC412A4         /* DMA5 Current Descriptor Pointer */
1633 #define DMA5_PREV_DESC_PTR             0xFFC412A8         /* DMA5 Previous Initial Descriptor Pointer */
1634 #define DMA5_CURR_ADDR               0xFFC412AC         /* DMA5 Current Address */
1635 #define DMA5_IRQ_STATUS                   0xFFC412B0         /* DMA5 Status Register */
1636 #define DMA5_CURR_X_COUNT               0xFFC412B4         /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
1637 #define DMA5_CURR_Y_COUNT               0xFFC412B8         /* DMA5 Current Row Count (2D only) */
1638 #define DMA5_BWL_COUNT                 0xFFC412C0         /* DMA5 Bandwidth Limit Count */
1639 #define DMA5_CURR_BWL_COUNT             0xFFC412C4         /* DMA5 Bandwidth Limit Count Current */
1640 #define DMA5_BWM_COUNT                 0xFFC412C8         /* DMA5 Bandwidth Monitor Count */
1641 #define DMA5_CURR_BWM_COUNT             0xFFC412CC         /* DMA5 Bandwidth Monitor Count Current */
1642 
1643 /* =========================
1644         DMA6
1645    ========================= */
1646 #define DMA6_NEXT_DESC_PTR             0xFFC41300         /* DMA6 Pointer to Next Initial Descriptor */
1647 #define DMA6_START_ADDR              0xFFC41304         /* DMA6 Start Address of Current Buffer */
1648 #define DMA6_CONFIG                    0xFFC41308         /* DMA6 Configuration Register */
1649 #define DMA6_X_COUNT                   0xFFC4130C         /* DMA6 Inner Loop Count Start Value */
1650 #define DMA6_X_MODIFY                   0xFFC41310         /* DMA6 Inner Loop Address Increment */
1651 #define DMA6_Y_COUNT                   0xFFC41314         /* DMA6 Outer Loop Count Start Value (2D only) */
1652 #define DMA6_Y_MODIFY                   0xFFC41318         /* DMA6 Outer Loop Address Increment (2D only) */
1653 #define DMA6_CURR_DESC_PTR             0xFFC41324         /* DMA6 Current Descriptor Pointer */
1654 #define DMA6_PREV_DESC_PTR             0xFFC41328         /* DMA6 Previous Initial Descriptor Pointer */
1655 #define DMA6_CURR_ADDR               0xFFC4132C         /* DMA6 Current Address */
1656 #define DMA6_IRQ_STATUS                   0xFFC41330         /* DMA6 Status Register */
1657 #define DMA6_CURR_X_COUNT               0xFFC41334         /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
1658 #define DMA6_CURR_Y_COUNT               0xFFC41338         /* DMA6 Current Row Count (2D only) */
1659 #define DMA6_BWL_COUNT                 0xFFC41340         /* DMA6 Bandwidth Limit Count */
1660 #define DMA6_CURR_BWL_COUNT             0xFFC41344         /* DMA6 Bandwidth Limit Count Current */
1661 #define DMA6_BWM_COUNT                 0xFFC41348         /* DMA6 Bandwidth Monitor Count */
1662 #define DMA6_CURR_BWM_COUNT             0xFFC4134C         /* DMA6 Bandwidth Monitor Count Current */
1663 
1664 /* =========================
1665         DMA7
1666    ========================= */
1667 #define DMA7_NEXT_DESC_PTR             0xFFC41380         /* DMA7 Pointer to Next Initial Descriptor */
1668 #define DMA7_START_ADDR              0xFFC41384         /* DMA7 Start Address of Current Buffer */
1669 #define DMA7_CONFIG                    0xFFC41388         /* DMA7 Configuration Register */
1670 #define DMA7_X_COUNT                   0xFFC4138C         /* DMA7 Inner Loop Count Start Value */
1671 #define DMA7_X_MODIFY                   0xFFC41390         /* DMA7 Inner Loop Address Increment */
1672 #define DMA7_Y_COUNT                   0xFFC41394         /* DMA7 Outer Loop Count Start Value (2D only) */
1673 #define DMA7_Y_MODIFY                   0xFFC41398         /* DMA7 Outer Loop Address Increment (2D only) */
1674 #define DMA7_CURR_DESC_PTR             0xFFC413A4         /* DMA7 Current Descriptor Pointer */
1675 #define DMA7_PREV_DESC_PTR             0xFFC413A8         /* DMA7 Previous Initial Descriptor Pointer */
1676 #define DMA7_CURR_ADDR               0xFFC413AC         /* DMA7 Current Address */
1677 #define DMA7_IRQ_STATUS                   0xFFC413B0         /* DMA7 Status Register */
1678 #define DMA7_CURR_X_COUNT               0xFFC413B4         /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
1679 #define DMA7_CURR_Y_COUNT               0xFFC413B8         /* DMA7 Current Row Count (2D only) */
1680 #define DMA7_BWL_COUNT                 0xFFC413C0         /* DMA7 Bandwidth Limit Count */
1681 #define DMA7_CURR_BWL_COUNT             0xFFC413C4         /* DMA7 Bandwidth Limit Count Current */
1682 #define DMA7_BWM_COUNT                 0xFFC413C8         /* DMA7 Bandwidth Monitor Count */
1683 #define DMA7_CURR_BWM_COUNT             0xFFC413CC         /* DMA7 Bandwidth Monitor Count Current */
1684 
1685 /* =========================
1686         DMA8
1687    ========================= */
1688 #define DMA8_NEXT_DESC_PTR             0xFFC41400         /* DMA8 Pointer to Next Initial Descriptor */
1689 #define DMA8_START_ADDR              0xFFC41404         /* DMA8 Start Address of Current Buffer */
1690 #define DMA8_CONFIG                    0xFFC41408         /* DMA8 Configuration Register */
1691 #define DMA8_X_COUNT                   0xFFC4140C         /* DMA8 Inner Loop Count Start Value */
1692 #define DMA8_X_MODIFY                   0xFFC41410         /* DMA8 Inner Loop Address Increment */
1693 #define DMA8_Y_COUNT                   0xFFC41414         /* DMA8 Outer Loop Count Start Value (2D only) */
1694 #define DMA8_Y_MODIFY                   0xFFC41418         /* DMA8 Outer Loop Address Increment (2D only) */
1695 #define DMA8_CURR_DESC_PTR             0xFFC41424         /* DMA8 Current Descriptor Pointer */
1696 #define DMA8_PREV_DESC_PTR             0xFFC41428         /* DMA8 Previous Initial Descriptor Pointer */
1697 #define DMA8_CURR_ADDR               0xFFC4142C         /* DMA8 Current Address */
1698 #define DMA8_IRQ_STATUS                   0xFFC41430         /* DMA8 Status Register */
1699 #define DMA8_CURR_X_COUNT               0xFFC41434         /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
1700 #define DMA8_CURR_Y_COUNT               0xFFC41438         /* DMA8 Current Row Count (2D only) */
1701 #define DMA8_BWL_COUNT                 0xFFC41440         /* DMA8 Bandwidth Limit Count */
1702 #define DMA8_CURR_BWL_COUNT             0xFFC41444         /* DMA8 Bandwidth Limit Count Current */
1703 #define DMA8_BWM_COUNT                 0xFFC41448         /* DMA8 Bandwidth Monitor Count */
1704 #define DMA8_CURR_BWM_COUNT             0xFFC4144C         /* DMA8 Bandwidth Monitor Count Current */
1705 
1706 /* =========================
1707         DMA9
1708    ========================= */
1709 #define DMA9_NEXT_DESC_PTR             0xFFC41480         /* DMA9 Pointer to Next Initial Descriptor */
1710 #define DMA9_START_ADDR              0xFFC41484         /* DMA9 Start Address of Current Buffer */
1711 #define DMA9_CONFIG                    0xFFC41488         /* DMA9 Configuration Register */
1712 #define DMA9_X_COUNT                   0xFFC4148C         /* DMA9 Inner Loop Count Start Value */
1713 #define DMA9_X_MODIFY                   0xFFC41490         /* DMA9 Inner Loop Address Increment */
1714 #define DMA9_Y_COUNT                   0xFFC41494         /* DMA9 Outer Loop Count Start Value (2D only) */
1715 #define DMA9_Y_MODIFY                   0xFFC41498         /* DMA9 Outer Loop Address Increment (2D only) */
1716 #define DMA9_CURR_DESC_PTR             0xFFC414A4         /* DMA9 Current Descriptor Pointer */
1717 #define DMA9_PREV_DESC_PTR             0xFFC414A8         /* DMA9 Previous Initial Descriptor Pointer */
1718 #define DMA9_CURR_ADDR               0xFFC414AC         /* DMA9 Current Address */
1719 #define DMA9_IRQ_STATUS                   0xFFC414B0         /* DMA9 Status Register */
1720 #define DMA9_CURR_X_COUNT               0xFFC414B4         /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
1721 #define DMA9_CURR_Y_COUNT               0xFFC414B8         /* DMA9 Current Row Count (2D only) */
1722 #define DMA9_BWL_COUNT                 0xFFC414C0         /* DMA9 Bandwidth Limit Count */
1723 #define DMA9_CURR_BWL_COUNT             0xFFC414C4         /* DMA9 Bandwidth Limit Count Current */
1724 #define DMA9_BWM_COUNT                 0xFFC414C8         /* DMA9 Bandwidth Monitor Count */
1725 #define DMA9_CURR_BWM_COUNT             0xFFC414CC         /* DMA9 Bandwidth Monitor Count Current */
1726 
1727 /* =========================
1728         DMA10
1729    ========================= */
1730 #define DMA10_NEXT_DESC_PTR            0xFFC05000         /* DMA10 Pointer to Next Initial Descriptor */
1731 #define DMA10_START_ADDR             0xFFC05004         /* DMA10 Start Address of Current Buffer */
1732 #define DMA10_CONFIG                   0xFFC05008         /* DMA10 Configuration Register */
1733 #define DMA10_X_COUNT                  0xFFC0500C         /* DMA10 Inner Loop Count Start Value */
1734 #define DMA10_X_MODIFY                  0xFFC05010         /* DMA10 Inner Loop Address Increment */
1735 #define DMA10_Y_COUNT                  0xFFC05014         /* DMA10 Outer Loop Count Start Value (2D only) */
1736 #define DMA10_Y_MODIFY                  0xFFC05018         /* DMA10 Outer Loop Address Increment (2D only) */
1737 #define DMA10_CURR_DESC_PTR            0xFFC05024         /* DMA10 Current Descriptor Pointer */
1738 #define DMA10_PREV_DESC_PTR            0xFFC05028         /* DMA10 Previous Initial Descriptor Pointer */
1739 #define DMA10_CURR_ADDR              0xFFC0502C         /* DMA10 Current Address */
1740 #define DMA10_IRQ_STATUS                  0xFFC05030         /* DMA10 Status Register */
1741 #define DMA10_CURR_X_COUNT              0xFFC05034         /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
1742 #define DMA10_CURR_Y_COUNT              0xFFC05038         /* DMA10 Current Row Count (2D only) */
1743 #define DMA10_BWL_COUNT                0xFFC05040         /* DMA10 Bandwidth Limit Count */
1744 #define DMA10_CURR_BWL_COUNT            0xFFC05044         /* DMA10 Bandwidth Limit Count Current */
1745 #define DMA10_BWM_COUNT                0xFFC05048         /* DMA10 Bandwidth Monitor Count */
1746 #define DMA10_CURR_BWM_COUNT            0xFFC0504C         /* DMA10 Bandwidth Monitor Count Current */
1747 
1748 /* =========================
1749         DMA11
1750    ========================= */
1751 #define DMA11_NEXT_DESC_PTR            0xFFC05080         /* DMA11 Pointer to Next Initial Descriptor */
1752 #define DMA11_START_ADDR             0xFFC05084         /* DMA11 Start Address of Current Buffer */
1753 #define DMA11_CONFIG                   0xFFC05088         /* DMA11 Configuration Register */
1754 #define DMA11_X_COUNT                  0xFFC0508C         /* DMA11 Inner Loop Count Start Value */
1755 #define DMA11_X_MODIFY                  0xFFC05090         /* DMA11 Inner Loop Address Increment */
1756 #define DMA11_Y_COUNT                  0xFFC05094         /* DMA11 Outer Loop Count Start Value (2D only) */
1757 #define DMA11_Y_MODIFY                  0xFFC05098         /* DMA11 Outer Loop Address Increment (2D only) */
1758 #define DMA11_CURR_DESC_PTR            0xFFC050A4         /* DMA11 Current Descriptor Pointer */
1759 #define DMA11_PREV_DESC_PTR            0xFFC050A8         /* DMA11 Previous Initial Descriptor Pointer */
1760 #define DMA11_CURR_ADDR              0xFFC050AC         /* DMA11 Current Address */
1761 #define DMA11_IRQ_STATUS                  0xFFC050B0         /* DMA11 Status Register */
1762 #define DMA11_CURR_X_COUNT              0xFFC050B4         /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
1763 #define DMA11_CURR_Y_COUNT              0xFFC050B8         /* DMA11 Current Row Count (2D only) */
1764 #define DMA11_BWL_COUNT                0xFFC050C0         /* DMA11 Bandwidth Limit Count */
1765 #define DMA11_CURR_BWL_COUNT            0xFFC050C4         /* DMA11 Bandwidth Limit Count Current */
1766 #define DMA11_BWM_COUNT                0xFFC050C8         /* DMA11 Bandwidth Monitor Count */
1767 #define DMA11_CURR_BWM_COUNT            0xFFC050CC         /* DMA11 Bandwidth Monitor Count Current */
1768 
1769 /* =========================
1770         DMA12
1771    ========================= */
1772 #define DMA12_NEXT_DESC_PTR            0xFFC05100         /* DMA12 Pointer to Next Initial Descriptor */
1773 #define DMA12_START_ADDR             0xFFC05104         /* DMA12 Start Address of Current Buffer */
1774 #define DMA12_CONFIG                   0xFFC05108         /* DMA12 Configuration Register */
1775 #define DMA12_X_COUNT                  0xFFC0510C         /* DMA12 Inner Loop Count Start Value */
1776 #define DMA12_X_MODIFY                  0xFFC05110         /* DMA12 Inner Loop Address Increment */
1777 #define DMA12_Y_COUNT                  0xFFC05114         /* DMA12 Outer Loop Count Start Value (2D only) */
1778 #define DMA12_Y_MODIFY                  0xFFC05118         /* DMA12 Outer Loop Address Increment (2D only) */
1779 #define DMA12_CURR_DESC_PTR            0xFFC05124         /* DMA12 Current Descriptor Pointer */
1780 #define DMA12_PREV_DESC_PTR            0xFFC05128         /* DMA12 Previous Initial Descriptor Pointer */
1781 #define DMA12_CURR_ADDR              0xFFC0512C         /* DMA12 Current Address */
1782 #define DMA12_IRQ_STATUS                  0xFFC05130         /* DMA12 Status Register */
1783 #define DMA12_CURR_X_COUNT              0xFFC05134         /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
1784 #define DMA12_CURR_Y_COUNT              0xFFC05138         /* DMA12 Current Row Count (2D only) */
1785 #define DMA12_BWL_COUNT                0xFFC05140         /* DMA12 Bandwidth Limit Count */
1786 #define DMA12_CURR_BWL_COUNT            0xFFC05144         /* DMA12 Bandwidth Limit Count Current */
1787 #define DMA12_BWM_COUNT                0xFFC05148         /* DMA12 Bandwidth Monitor Count */
1788 #define DMA12_CURR_BWM_COUNT            0xFFC0514C         /* DMA12 Bandwidth Monitor Count Current */
1789 
1790 /* =========================
1791         DMA13
1792    ========================= */
1793 #define DMA13_NEXT_DESC_PTR            0xFFC07000         /* DMA13 Pointer to Next Initial Descriptor */
1794 #define DMA13_START_ADDR             0xFFC07004         /* DMA13 Start Address of Current Buffer */
1795 #define DMA13_CONFIG                   0xFFC07008         /* DMA13 Configuration Register */
1796 #define DMA13_X_COUNT                  0xFFC0700C         /* DMA13 Inner Loop Count Start Value */
1797 #define DMA13_X_MODIFY                  0xFFC07010         /* DMA13 Inner Loop Address Increment */
1798 #define DMA13_Y_COUNT                  0xFFC07014         /* DMA13 Outer Loop Count Start Value (2D only) */
1799 #define DMA13_Y_MODIFY                  0xFFC07018         /* DMA13 Outer Loop Address Increment (2D only) */
1800 #define DMA13_CURR_DESC_PTR            0xFFC07024         /* DMA13 Current Descriptor Pointer */
1801 #define DMA13_PREV_DESC_PTR            0xFFC07028         /* DMA13 Previous Initial Descriptor Pointer */
1802 #define DMA13_CURR_ADDR              0xFFC0702C         /* DMA13 Current Address */
1803 #define DMA13_IRQ_STATUS                  0xFFC07030         /* DMA13 Status Register */
1804 #define DMA13_CURR_X_COUNT              0xFFC07034         /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
1805 #define DMA13_CURR_Y_COUNT              0xFFC07038         /* DMA13 Current Row Count (2D only) */
1806 #define DMA13_BWL_COUNT                0xFFC07040         /* DMA13 Bandwidth Limit Count */
1807 #define DMA13_CURR_BWL_COUNT            0xFFC07044         /* DMA13 Bandwidth Limit Count Current */
1808 #define DMA13_BWM_COUNT                0xFFC07048         /* DMA13 Bandwidth Monitor Count */
1809 #define DMA13_CURR_BWM_COUNT            0xFFC0704C         /* DMA13 Bandwidth Monitor Count Current */
1810 
1811 /* =========================
1812         DMA14
1813    ========================= */
1814 #define DMA14_NEXT_DESC_PTR            0xFFC07080         /* DMA14 Pointer to Next Initial Descriptor */
1815 #define DMA14_START_ADDR             0xFFC07084         /* DMA14 Start Address of Current Buffer */
1816 #define DMA14_CONFIG                   0xFFC07088         /* DMA14 Configuration Register */
1817 #define DMA14_X_COUNT                  0xFFC0708C         /* DMA14 Inner Loop Count Start Value */
1818 #define DMA14_X_MODIFY                  0xFFC07090         /* DMA14 Inner Loop Address Increment */
1819 #define DMA14_Y_COUNT                  0xFFC07094         /* DMA14 Outer Loop Count Start Value (2D only) */
1820 #define DMA14_Y_MODIFY                  0xFFC07098         /* DMA14 Outer Loop Address Increment (2D only) */
1821 #define DMA14_CURR_DESC_PTR            0xFFC070A4         /* DMA14 Current Descriptor Pointer */
1822 #define DMA14_PREV_DESC_PTR            0xFFC070A8         /* DMA14 Previous Initial Descriptor Pointer */
1823 #define DMA14_CURR_ADDR              0xFFC070AC         /* DMA14 Current Address */
1824 #define DMA14_IRQ_STATUS                  0xFFC070B0         /* DMA14 Status Register */
1825 #define DMA14_CURR_X_COUNT              0xFFC070B4         /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
1826 #define DMA14_CURR_Y_COUNT              0xFFC070B8         /* DMA14 Current Row Count (2D only) */
1827 #define DMA14_BWL_COUNT                0xFFC070C0         /* DMA14 Bandwidth Limit Count */
1828 #define DMA14_CURR_BWL_COUNT            0xFFC070C4         /* DMA14 Bandwidth Limit Count Current */
1829 #define DMA14_BWM_COUNT                0xFFC070C8         /* DMA14 Bandwidth Monitor Count */
1830 #define DMA14_CURR_BWM_COUNT            0xFFC070CC         /* DMA14 Bandwidth Monitor Count Current */
1831 
1832 /* =========================
1833         DMA15
1834    ========================= */
1835 #define DMA15_NEXT_DESC_PTR            0xFFC07100         /* DMA15 Pointer to Next Initial Descriptor */
1836 #define DMA15_START_ADDR             0xFFC07104         /* DMA15 Start Address of Current Buffer */
1837 #define DMA15_CONFIG                   0xFFC07108         /* DMA15 Configuration Register */
1838 #define DMA15_X_COUNT                  0xFFC0710C         /* DMA15 Inner Loop Count Start Value */
1839 #define DMA15_X_MODIFY                  0xFFC07110         /* DMA15 Inner Loop Address Increment */
1840 #define DMA15_Y_COUNT                  0xFFC07114         /* DMA15 Outer Loop Count Start Value (2D only) */
1841 #define DMA15_Y_MODIFY                  0xFFC07118         /* DMA15 Outer Loop Address Increment (2D only) */
1842 #define DMA15_CURR_DESC_PTR            0xFFC07124         /* DMA15 Current Descriptor Pointer */
1843 #define DMA15_PREV_DESC_PTR            0xFFC07128         /* DMA15 Previous Initial Descriptor Pointer */
1844 #define DMA15_CURR_ADDR              0xFFC0712C         /* DMA15 Current Address */
1845 #define DMA15_IRQ_STATUS                  0xFFC07130         /* DMA15 Status Register */
1846 #define DMA15_CURR_X_COUNT              0xFFC07134         /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
1847 #define DMA15_CURR_Y_COUNT              0xFFC07138         /* DMA15 Current Row Count (2D only) */
1848 #define DMA15_BWL_COUNT                0xFFC07140         /* DMA15 Bandwidth Limit Count */
1849 #define DMA15_CURR_BWL_COUNT            0xFFC07144         /* DMA15 Bandwidth Limit Count Current */
1850 #define DMA15_BWM_COUNT                0xFFC07148         /* DMA15 Bandwidth Monitor Count */
1851 #define DMA15_CURR_BWM_COUNT            0xFFC0714C         /* DMA15 Bandwidth Monitor Count Current */
1852 
1853 /* =========================
1854         DMA16
1855    ========================= */
1856 #define DMA16_NEXT_DESC_PTR            0xFFC07180         /* DMA16 Pointer to Next Initial Descriptor */
1857 #define DMA16_START_ADDR             0xFFC07184         /* DMA16 Start Address of Current Buffer */
1858 #define DMA16_CONFIG                   0xFFC07188         /* DMA16 Configuration Register */
1859 #define DMA16_X_COUNT                  0xFFC0718C         /* DMA16 Inner Loop Count Start Value */
1860 #define DMA16_X_MODIFY                  0xFFC07190         /* DMA16 Inner Loop Address Increment */
1861 #define DMA16_Y_COUNT                  0xFFC07194         /* DMA16 Outer Loop Count Start Value (2D only) */
1862 #define DMA16_Y_MODIFY                  0xFFC07198         /* DMA16 Outer Loop Address Increment (2D only) */
1863 #define DMA16_CURR_DESC_PTR            0xFFC071A4         /* DMA16 Current Descriptor Pointer */
1864 #define DMA16_PREV_DESC_PTR            0xFFC071A8         /* DMA16 Previous Initial Descriptor Pointer */
1865 #define DMA16_CURR_ADDR              0xFFC071AC         /* DMA16 Current Address */
1866 #define DMA16_IRQ_STATUS                  0xFFC071B0         /* DMA16 Status Register */
1867 #define DMA16_CURR_X_COUNT              0xFFC071B4         /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
1868 #define DMA16_CURR_Y_COUNT              0xFFC071B8         /* DMA16 Current Row Count (2D only) */
1869 #define DMA16_BWL_COUNT                0xFFC071C0         /* DMA16 Bandwidth Limit Count */
1870 #define DMA16_CURR_BWL_COUNT            0xFFC071C4         /* DMA16 Bandwidth Limit Count Current */
1871 #define DMA16_BWM_COUNT                0xFFC071C8         /* DMA16 Bandwidth Monitor Count */
1872 #define DMA16_CURR_BWM_COUNT            0xFFC071CC         /* DMA16 Bandwidth Monitor Count Current */
1873 
1874 /* =========================
1875         DMA17
1876    ========================= */
1877 #define DMA17_NEXT_DESC_PTR            0xFFC07200         /* DMA17 Pointer to Next Initial Descriptor */
1878 #define DMA17_START_ADDR             0xFFC07204         /* DMA17 Start Address of Current Buffer */
1879 #define DMA17_CONFIG                   0xFFC07208         /* DMA17 Configuration Register */
1880 #define DMA17_X_COUNT                  0xFFC0720C         /* DMA17 Inner Loop Count Start Value */
1881 #define DMA17_X_MODIFY                  0xFFC07210         /* DMA17 Inner Loop Address Increment */
1882 #define DMA17_Y_COUNT                  0xFFC07214         /* DMA17 Outer Loop Count Start Value (2D only) */
1883 #define DMA17_Y_MODIFY                  0xFFC07218         /* DMA17 Outer Loop Address Increment (2D only) */
1884 #define DMA17_CURR_DESC_PTR            0xFFC07224         /* DMA17 Current Descriptor Pointer */
1885 #define DMA17_PREV_DESC_PTR            0xFFC07228         /* DMA17 Previous Initial Descriptor Pointer */
1886 #define DMA17_CURR_ADDR              0xFFC0722C         /* DMA17 Current Address */
1887 #define DMA17_IRQ_STATUS                  0xFFC07230         /* DMA17 Status Register */
1888 #define DMA17_CURR_X_COUNT              0xFFC07234         /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
1889 #define DMA17_CURR_Y_COUNT              0xFFC07238         /* DMA17 Current Row Count (2D only) */
1890 #define DMA17_BWL_COUNT                0xFFC07240         /* DMA17 Bandwidth Limit Count */
1891 #define DMA17_CURR_BWL_COUNT            0xFFC07244         /* DMA17 Bandwidth Limit Count Current */
1892 #define DMA17_BWM_COUNT                0xFFC07248         /* DMA17 Bandwidth Monitor Count */
1893 #define DMA17_CURR_BWM_COUNT            0xFFC0724C         /* DMA17 Bandwidth Monitor Count Current */
1894 
1895 /* =========================
1896         DMA18
1897    ========================= */
1898 #define DMA18_NEXT_DESC_PTR            0xFFC07280         /* DMA18 Pointer to Next Initial Descriptor */
1899 #define DMA18_START_ADDR             0xFFC07284         /* DMA18 Start Address of Current Buffer */
1900 #define DMA18_CONFIG                   0xFFC07288         /* DMA18 Configuration Register */
1901 #define DMA18_X_COUNT                  0xFFC0728C         /* DMA18 Inner Loop Count Start Value */
1902 #define DMA18_X_MODIFY                  0xFFC07290         /* DMA18 Inner Loop Address Increment */
1903 #define DMA18_Y_COUNT                  0xFFC07294         /* DMA18 Outer Loop Count Start Value (2D only) */
1904 #define DMA18_Y_MODIFY                  0xFFC07298         /* DMA18 Outer Loop Address Increment (2D only) */
1905 #define DMA18_CURR_DESC_PTR            0xFFC072A4         /* DMA18 Current Descriptor Pointer */
1906 #define DMA18_PREV_DESC_PTR            0xFFC072A8         /* DMA18 Previous Initial Descriptor Pointer */
1907 #define DMA18_CURR_ADDR              0xFFC072AC         /* DMA18 Current Address */
1908 #define DMA18_IRQ_STATUS                  0xFFC072B0         /* DMA18 Status Register */
1909 #define DMA18_CURR_X_COUNT              0xFFC072B4         /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
1910 #define DMA18_CURR_Y_COUNT              0xFFC072B8         /* DMA18 Current Row Count (2D only) */
1911 #define DMA18_BWL_COUNT                0xFFC072C0         /* DMA18 Bandwidth Limit Count */
1912 #define DMA18_CURR_BWL_COUNT            0xFFC072C4         /* DMA18 Bandwidth Limit Count Current */
1913 #define DMA18_BWM_COUNT                0xFFC072C8         /* DMA18 Bandwidth Monitor Count */
1914 #define DMA18_CURR_BWM_COUNT            0xFFC072CC         /* DMA18 Bandwidth Monitor Count Current */
1915 
1916 /* =========================
1917         DMA19
1918    ========================= */
1919 #define DMA19_NEXT_DESC_PTR            0xFFC07300         /* DMA19 Pointer to Next Initial Descriptor */
1920 #define DMA19_START_ADDR             0xFFC07304         /* DMA19 Start Address of Current Buffer */
1921 #define DMA19_CONFIG                   0xFFC07308         /* DMA19 Configuration Register */
1922 #define DMA19_X_COUNT                  0xFFC0730C         /* DMA19 Inner Loop Count Start Value */
1923 #define DMA19_X_MODIFY                  0xFFC07310         /* DMA19 Inner Loop Address Increment */
1924 #define DMA19_Y_COUNT                  0xFFC07314         /* DMA19 Outer Loop Count Start Value (2D only) */
1925 #define DMA19_Y_MODIFY                  0xFFC07318         /* DMA19 Outer Loop Address Increment (2D only) */
1926 #define DMA19_CURR_DESC_PTR            0xFFC07324         /* DMA19 Current Descriptor Pointer */
1927 #define DMA19_PREV_DESC_PTR            0xFFC07328         /* DMA19 Previous Initial Descriptor Pointer */
1928 #define DMA19_CURR_ADDR              0xFFC0732C         /* DMA19 Current Address */
1929 #define DMA19_IRQ_STATUS                  0xFFC07330         /* DMA19 Status Register */
1930 #define DMA19_CURR_X_COUNT              0xFFC07334         /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
1931 #define DMA19_CURR_Y_COUNT              0xFFC07338         /* DMA19 Current Row Count (2D only) */
1932 #define DMA19_BWL_COUNT                0xFFC07340         /* DMA19 Bandwidth Limit Count */
1933 #define DMA19_CURR_BWL_COUNT            0xFFC07344         /* DMA19 Bandwidth Limit Count Current */
1934 #define DMA19_BWM_COUNT                0xFFC07348         /* DMA19 Bandwidth Monitor Count */
1935 #define DMA19_CURR_BWM_COUNT            0xFFC0734C         /* DMA19 Bandwidth Monitor Count Current */
1936 
1937 /* =========================
1938         DMA20
1939    ========================= */
1940 #define DMA20_NEXT_DESC_PTR            0xFFC07380         /* DMA20 Pointer to Next Initial Descriptor */
1941 #define DMA20_START_ADDR             0xFFC07384         /* DMA20 Start Address of Current Buffer */
1942 #define DMA20_CONFIG                   0xFFC07388         /* DMA20 Configuration Register */
1943 #define DMA20_X_COUNT                  0xFFC0738C         /* DMA20 Inner Loop Count Start Value */
1944 #define DMA20_X_MODIFY                  0xFFC07390         /* DMA20 Inner Loop Address Increment */
1945 #define DMA20_Y_COUNT                  0xFFC07394         /* DMA20 Outer Loop Count Start Value (2D only) */
1946 #define DMA20_Y_MODIFY                  0xFFC07398         /* DMA20 Outer Loop Address Increment (2D only) */
1947 #define DMA20_CURR_DESC_PTR            0xFFC073A4         /* DMA20 Current Descriptor Pointer */
1948 #define DMA20_PREV_DESC_PTR            0xFFC073A8         /* DMA20 Previous Initial Descriptor Pointer */
1949 #define DMA20_CURR_ADDR              0xFFC073AC         /* DMA20 Current Address */
1950 #define DMA20_IRQ_STATUS                  0xFFC073B0         /* DMA20 Status Register */
1951 #define DMA20_CURR_X_COUNT              0xFFC073B4         /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
1952 #define DMA20_CURR_Y_COUNT              0xFFC073B8         /* DMA20 Current Row Count (2D only) */
1953 #define DMA20_BWL_COUNT                0xFFC073C0         /* DMA20 Bandwidth Limit Count */
1954 #define DMA20_CURR_BWL_COUNT            0xFFC073C4         /* DMA20 Bandwidth Limit Count Current */
1955 #define DMA20_BWM_COUNT                0xFFC073C8         /* DMA20 Bandwidth Monitor Count */
1956 #define DMA20_CURR_BWM_COUNT            0xFFC073CC         /* DMA20 Bandwidth Monitor Count Current */
1957 
1958 /* =========================
1959         DMA21
1960    ========================= */
1961 #define DMA21_NEXT_DESC_PTR            0xFFC09000         /* DMA21 Pointer to Next Initial Descriptor */
1962 #define DMA21_START_ADDR             0xFFC09004         /* DMA21 Start Address of Current Buffer */
1963 #define DMA21_CONFIG                   0xFFC09008         /* DMA21 Configuration Register */
1964 #define DMA21_X_COUNT                  0xFFC0900C         /* DMA21 Inner Loop Count Start Value */
1965 #define DMA21_X_MODIFY                  0xFFC09010         /* DMA21 Inner Loop Address Increment */
1966 #define DMA21_Y_COUNT                  0xFFC09014         /* DMA21 Outer Loop Count Start Value (2D only) */
1967 #define DMA21_Y_MODIFY                  0xFFC09018         /* DMA21 Outer Loop Address Increment (2D only) */
1968 #define DMA21_CURR_DESC_PTR            0xFFC09024         /* DMA21 Current Descriptor Pointer */
1969 #define DMA21_PREV_DESC_PTR            0xFFC09028         /* DMA21 Previous Initial Descriptor Pointer */
1970 #define DMA21_CURR_ADDR              0xFFC0902C         /* DMA21 Current Address */
1971 #define DMA21_IRQ_STATUS                  0xFFC09030         /* DMA21 Status Register */
1972 #define DMA21_CURR_X_COUNT              0xFFC09034         /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
1973 #define DMA21_CURR_Y_COUNT              0xFFC09038         /* DMA21 Current Row Count (2D only) */
1974 #define DMA21_BWL_COUNT                0xFFC09040         /* DMA21 Bandwidth Limit Count */
1975 #define DMA21_CURR_BWL_COUNT            0xFFC09044         /* DMA21 Bandwidth Limit Count Current */
1976 #define DMA21_BWM_COUNT                0xFFC09048         /* DMA21 Bandwidth Monitor Count */
1977 #define DMA21_CURR_BWM_COUNT            0xFFC0904C         /* DMA21 Bandwidth Monitor Count Current */
1978 
1979 /* =========================
1980         DMA22
1981    ========================= */
1982 #define DMA22_NEXT_DESC_PTR            0xFFC09080         /* DMA22 Pointer to Next Initial Descriptor */
1983 #define DMA22_START_ADDR             0xFFC09084         /* DMA22 Start Address of Current Buffer */
1984 #define DMA22_CONFIG                   0xFFC09088         /* DMA22 Configuration Register */
1985 #define DMA22_X_COUNT                  0xFFC0908C         /* DMA22 Inner Loop Count Start Value */
1986 #define DMA22_X_MODIFY                  0xFFC09090         /* DMA22 Inner Loop Address Increment */
1987 #define DMA22_Y_COUNT                  0xFFC09094         /* DMA22 Outer Loop Count Start Value (2D only) */
1988 #define DMA22_Y_MODIFY                  0xFFC09098         /* DMA22 Outer Loop Address Increment (2D only) */
1989 #define DMA22_CURR_DESC_PTR            0xFFC090A4         /* DMA22 Current Descriptor Pointer */
1990 #define DMA22_PREV_DESC_PTR            0xFFC090A8         /* DMA22 Previous Initial Descriptor Pointer */
1991 #define DMA22_CURR_ADDR              0xFFC090AC         /* DMA22 Current Address */
1992 #define DMA22_IRQ_STATUS                  0xFFC090B0         /* DMA22 Status Register */
1993 #define DMA22_CURR_X_COUNT              0xFFC090B4         /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
1994 #define DMA22_CURR_Y_COUNT              0xFFC090B8         /* DMA22 Current Row Count (2D only) */
1995 #define DMA22_BWL_COUNT                0xFFC090C0         /* DMA22 Bandwidth Limit Count */
1996 #define DMA22_CURR_BWL_COUNT            0xFFC090C4         /* DMA22 Bandwidth Limit Count Current */
1997 #define DMA22_BWM_COUNT                0xFFC090C8         /* DMA22 Bandwidth Monitor Count */
1998 #define DMA22_CURR_BWM_COUNT            0xFFC090CC         /* DMA22 Bandwidth Monitor Count Current */
1999 
2000 /* =========================
2001         DMA23
2002    ========================= */
2003 #define DMA23_NEXT_DESC_PTR            0xFFC09100         /* DMA23 Pointer to Next Initial Descriptor */
2004 #define DMA23_START_ADDR             0xFFC09104         /* DMA23 Start Address of Current Buffer */
2005 #define DMA23_CONFIG                   0xFFC09108         /* DMA23 Configuration Register */
2006 #define DMA23_X_COUNT                  0xFFC0910C         /* DMA23 Inner Loop Count Start Value */
2007 #define DMA23_X_MODIFY                  0xFFC09110         /* DMA23 Inner Loop Address Increment */
2008 #define DMA23_Y_COUNT                  0xFFC09114         /* DMA23 Outer Loop Count Start Value (2D only) */
2009 #define DMA23_Y_MODIFY                  0xFFC09118         /* DMA23 Outer Loop Address Increment (2D only) */
2010 #define DMA23_CURR_DESC_PTR            0xFFC09124         /* DMA23 Current Descriptor Pointer */
2011 #define DMA23_PREV_DESC_PTR            0xFFC09128         /* DMA23 Previous Initial Descriptor Pointer */
2012 #define DMA23_CURR_ADDR              0xFFC0912C         /* DMA23 Current Address */
2013 #define DMA23_IRQ_STATUS                  0xFFC09130         /* DMA23 Status Register */
2014 #define DMA23_CURR_X_COUNT              0xFFC09134         /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
2015 #define DMA23_CURR_Y_COUNT              0xFFC09138         /* DMA23 Current Row Count (2D only) */
2016 #define DMA23_BWL_COUNT                0xFFC09140         /* DMA23 Bandwidth Limit Count */
2017 #define DMA23_CURR_BWL_COUNT            0xFFC09144         /* DMA23 Bandwidth Limit Count Current */
2018 #define DMA23_BWM_COUNT                0xFFC09148         /* DMA23 Bandwidth Monitor Count */
2019 #define DMA23_CURR_BWM_COUNT            0xFFC0914C         /* DMA23 Bandwidth Monitor Count Current */
2020 
2021 /* =========================
2022         DMA24
2023    ========================= */
2024 #define DMA24_NEXT_DESC_PTR            0xFFC09180         /* DMA24 Pointer to Next Initial Descriptor */
2025 #define DMA24_START_ADDR             0xFFC09184         /* DMA24 Start Address of Current Buffer */
2026 #define DMA24_CONFIG                   0xFFC09188         /* DMA24 Configuration Register */
2027 #define DMA24_X_COUNT                  0xFFC0918C         /* DMA24 Inner Loop Count Start Value */
2028 #define DMA24_X_MODIFY                  0xFFC09190         /* DMA24 Inner Loop Address Increment */
2029 #define DMA24_Y_COUNT                  0xFFC09194         /* DMA24 Outer Loop Count Start Value (2D only) */
2030 #define DMA24_Y_MODIFY                  0xFFC09198         /* DMA24 Outer Loop Address Increment (2D only) */
2031 #define DMA24_CURR_DESC_PTR            0xFFC091A4         /* DMA24 Current Descriptor Pointer */
2032 #define DMA24_PREV_DESC_PTR            0xFFC091A8         /* DMA24 Previous Initial Descriptor Pointer */
2033 #define DMA24_CURR_ADDR              0xFFC091AC         /* DMA24 Current Address */
2034 #define DMA24_IRQ_STATUS                  0xFFC091B0         /* DMA24 Status Register */
2035 #define DMA24_CURR_X_COUNT              0xFFC091B4         /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
2036 #define DMA24_CURR_Y_COUNT              0xFFC091B8         /* DMA24 Current Row Count (2D only) */
2037 #define DMA24_BWL_COUNT                0xFFC091C0         /* DMA24 Bandwidth Limit Count */
2038 #define DMA24_CURR_BWL_COUNT            0xFFC091C4         /* DMA24 Bandwidth Limit Count Current */
2039 #define DMA24_BWM_COUNT                0xFFC091C8         /* DMA24 Bandwidth Monitor Count */
2040 #define DMA24_CURR_BWM_COUNT            0xFFC091CC         /* DMA24 Bandwidth Monitor Count Current */
2041 
2042 /* =========================
2043         DMA25
2044    ========================= */
2045 #define DMA25_NEXT_DESC_PTR            0xFFC09200         /* DMA25 Pointer to Next Initial Descriptor */
2046 #define DMA25_START_ADDR             0xFFC09204         /* DMA25 Start Address of Current Buffer */
2047 #define DMA25_CONFIG                   0xFFC09208         /* DMA25 Configuration Register */
2048 #define DMA25_X_COUNT                  0xFFC0920C         /* DMA25 Inner Loop Count Start Value */
2049 #define DMA25_X_MODIFY                  0xFFC09210         /* DMA25 Inner Loop Address Increment */
2050 #define DMA25_Y_COUNT                  0xFFC09214         /* DMA25 Outer Loop Count Start Value (2D only) */
2051 #define DMA25_Y_MODIFY                  0xFFC09218         /* DMA25 Outer Loop Address Increment (2D only) */
2052 #define DMA25_CURR_DESC_PTR            0xFFC09224         /* DMA25 Current Descriptor Pointer */
2053 #define DMA25_PREV_DESC_PTR            0xFFC09228         /* DMA25 Previous Initial Descriptor Pointer */
2054 #define DMA25_CURR_ADDR              0xFFC0922C         /* DMA25 Current Address */
2055 #define DMA25_IRQ_STATUS                  0xFFC09230         /* DMA25 Status Register */
2056 #define DMA25_CURR_X_COUNT              0xFFC09234         /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
2057 #define DMA25_CURR_Y_COUNT              0xFFC09238         /* DMA25 Current Row Count (2D only) */
2058 #define DMA25_BWL_COUNT                0xFFC09240         /* DMA25 Bandwidth Limit Count */
2059 #define DMA25_CURR_BWL_COUNT            0xFFC09244         /* DMA25 Bandwidth Limit Count Current */
2060 #define DMA25_BWM_COUNT                0xFFC09248         /* DMA25 Bandwidth Monitor Count */
2061 #define DMA25_CURR_BWM_COUNT            0xFFC0924C         /* DMA25 Bandwidth Monitor Count Current */
2062 
2063 /* =========================
2064         DMA26
2065    ========================= */
2066 #define DMA26_NEXT_DESC_PTR            0xFFC09280         /* DMA26 Pointer to Next Initial Descriptor */
2067 #define DMA26_START_ADDR             0xFFC09284         /* DMA26 Start Address of Current Buffer */
2068 #define DMA26_CONFIG                   0xFFC09288         /* DMA26 Configuration Register */
2069 #define DMA26_X_COUNT                  0xFFC0928C         /* DMA26 Inner Loop Count Start Value */
2070 #define DMA26_X_MODIFY                  0xFFC09290         /* DMA26 Inner Loop Address Increment */
2071 #define DMA26_Y_COUNT                  0xFFC09294         /* DMA26 Outer Loop Count Start Value (2D only) */
2072 #define DMA26_Y_MODIFY                  0xFFC09298         /* DMA26 Outer Loop Address Increment (2D only) */
2073 #define DMA26_CURR_DESC_PTR            0xFFC092A4         /* DMA26 Current Descriptor Pointer */
2074 #define DMA26_PREV_DESC_PTR            0xFFC092A8         /* DMA26 Previous Initial Descriptor Pointer */
2075 #define DMA26_CURR_ADDR              0xFFC092AC         /* DMA26 Current Address */
2076 #define DMA26_IRQ_STATUS                  0xFFC092B0         /* DMA26 Status Register */
2077 #define DMA26_CURR_X_COUNT              0xFFC092B4         /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
2078 #define DMA26_CURR_Y_COUNT              0xFFC092B8         /* DMA26 Current Row Count (2D only) */
2079 #define DMA26_BWL_COUNT                0xFFC092C0         /* DMA26 Bandwidth Limit Count */
2080 #define DMA26_CURR_BWL_COUNT            0xFFC092C4         /* DMA26 Bandwidth Limit Count Current */
2081 #define DMA26_BWM_COUNT                0xFFC092C8         /* DMA26 Bandwidth Monitor Count */
2082 #define DMA26_CURR_BWM_COUNT            0xFFC092CC         /* DMA26 Bandwidth Monitor Count Current */
2083 
2084 /* =========================
2085         DMA27
2086    ========================= */
2087 #define DMA27_NEXT_DESC_PTR            0xFFC09300         /* DMA27 Pointer to Next Initial Descriptor */
2088 #define DMA27_START_ADDR             0xFFC09304         /* DMA27 Start Address of Current Buffer */
2089 #define DMA27_CONFIG                   0xFFC09308         /* DMA27 Configuration Register */
2090 #define DMA27_X_COUNT                  0xFFC0930C         /* DMA27 Inner Loop Count Start Value */
2091 #define DMA27_X_MODIFY                  0xFFC09310         /* DMA27 Inner Loop Address Increment */
2092 #define DMA27_Y_COUNT                  0xFFC09314         /* DMA27 Outer Loop Count Start Value (2D only) */
2093 #define DMA27_Y_MODIFY                  0xFFC09318         /* DMA27 Outer Loop Address Increment (2D only) */
2094 #define DMA27_CURR_DESC_PTR            0xFFC09324         /* DMA27 Current Descriptor Pointer */
2095 #define DMA27_PREV_DESC_PTR            0xFFC09328         /* DMA27 Previous Initial Descriptor Pointer */
2096 #define DMA27_CURR_ADDR              0xFFC0932C         /* DMA27 Current Address */
2097 #define DMA27_IRQ_STATUS                  0xFFC09330         /* DMA27 Status Register */
2098 #define DMA27_CURR_X_COUNT              0xFFC09334         /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
2099 #define DMA27_CURR_Y_COUNT              0xFFC09338         /* DMA27 Current Row Count (2D only) */
2100 #define DMA27_BWL_COUNT                0xFFC09340         /* DMA27 Bandwidth Limit Count */
2101 #define DMA27_CURR_BWL_COUNT            0xFFC09344         /* DMA27 Bandwidth Limit Count Current */
2102 #define DMA27_BWM_COUNT                0xFFC09348         /* DMA27 Bandwidth Monitor Count */
2103 #define DMA27_CURR_BWM_COUNT            0xFFC0934C         /* DMA27 Bandwidth Monitor Count Current */
2104 
2105 /* =========================
2106         DMA28
2107    ========================= */
2108 #define DMA28_NEXT_DESC_PTR            0xFFC09380         /* DMA28 Pointer to Next Initial Descriptor */
2109 #define DMA28_START_ADDR             0xFFC09384         /* DMA28 Start Address of Current Buffer */
2110 #define DMA28_CONFIG                   0xFFC09388         /* DMA28 Configuration Register */
2111 #define DMA28_X_COUNT                  0xFFC0938C         /* DMA28 Inner Loop Count Start Value */
2112 #define DMA28_X_MODIFY                  0xFFC09390         /* DMA28 Inner Loop Address Increment */
2113 #define DMA28_Y_COUNT                  0xFFC09394         /* DMA28 Outer Loop Count Start Value (2D only) */
2114 #define DMA28_Y_MODIFY                  0xFFC09398         /* DMA28 Outer Loop Address Increment (2D only) */
2115 #define DMA28_CURR_DESC_PTR            0xFFC093A4         /* DMA28 Current Descriptor Pointer */
2116 #define DMA28_PREV_DESC_PTR            0xFFC093A8         /* DMA28 Previous Initial Descriptor Pointer */
2117 #define DMA28_CURR_ADDR              0xFFC093AC         /* DMA28 Current Address */
2118 #define DMA28_IRQ_STATUS                  0xFFC093B0         /* DMA28 Status Register */
2119 #define DMA28_CURR_X_COUNT              0xFFC093B4         /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
2120 #define DMA28_CURR_Y_COUNT              0xFFC093B8         /* DMA28 Current Row Count (2D only) */
2121 #define DMA28_BWL_COUNT                0xFFC093C0         /* DMA28 Bandwidth Limit Count */
2122 #define DMA28_CURR_BWL_COUNT            0xFFC093C4         /* DMA28 Bandwidth Limit Count Current */
2123 #define DMA28_BWM_COUNT                0xFFC093C8         /* DMA28 Bandwidth Monitor Count */
2124 #define DMA28_CURR_BWM_COUNT            0xFFC093CC         /* DMA28 Bandwidth Monitor Count Current */
2125 
2126 /* =========================
2127         DMA29
2128    ========================= */
2129 #define DMA29_NEXT_DESC_PTR            0xFFC0B000         /* DMA29 Pointer to Next Initial Descriptor */
2130 #define DMA29_START_ADDR             0xFFC0B004         /* DMA29 Start Address of Current Buffer */
2131 #define DMA29_CONFIG                   0xFFC0B008         /* DMA29 Configuration Register */
2132 #define DMA29_X_COUNT                  0xFFC0B00C         /* DMA29 Inner Loop Count Start Value */
2133 #define DMA29_X_MODIFY                  0xFFC0B010         /* DMA29 Inner Loop Address Increment */
2134 #define DMA29_Y_COUNT                  0xFFC0B014         /* DMA29 Outer Loop Count Start Value (2D only) */
2135 #define DMA29_Y_MODIFY                  0xFFC0B018         /* DMA29 Outer Loop Address Increment (2D only) */
2136 #define DMA29_CURR_DESC_PTR            0xFFC0B024         /* DMA29 Current Descriptor Pointer */
2137 #define DMA29_PREV_DESC_PTR            0xFFC0B028         /* DMA29 Previous Initial Descriptor Pointer */
2138 #define DMA29_CURR_ADDR              0xFFC0B02C         /* DMA29 Current Address */
2139 #define DMA29_IRQ_STATUS                  0xFFC0B030         /* DMA29 Status Register */
2140 #define DMA29_CURR_X_COUNT              0xFFC0B034         /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
2141 #define DMA29_CURR_Y_COUNT              0xFFC0B038         /* DMA29 Current Row Count (2D only) */
2142 #define DMA29_BWL_COUNT                0xFFC0B040         /* DMA29 Bandwidth Limit Count */
2143 #define DMA29_CURR_BWL_COUNT            0xFFC0B044         /* DMA29 Bandwidth Limit Count Current */
2144 #define DMA29_BWM_COUNT                0xFFC0B048         /* DMA29 Bandwidth Monitor Count */
2145 #define DMA29_CURR_BWM_COUNT            0xFFC0B04C         /* DMA29 Bandwidth Monitor Count Current */
2146 
2147 /* =========================
2148         DMA30
2149    ========================= */
2150 #define DMA30_NEXT_DESC_PTR            0xFFC0B080         /* DMA30 Pointer to Next Initial Descriptor */
2151 #define DMA30_START_ADDR             0xFFC0B084         /* DMA30 Start Address of Current Buffer */
2152 #define DMA30_CONFIG                   0xFFC0B088         /* DMA30 Configuration Register */
2153 #define DMA30_X_COUNT                  0xFFC0B08C         /* DMA30 Inner Loop Count Start Value */
2154 #define DMA30_X_MODIFY                  0xFFC0B090         /* DMA30 Inner Loop Address Increment */
2155 #define DMA30_Y_COUNT                  0xFFC0B094         /* DMA30 Outer Loop Count Start Value (2D only) */
2156 #define DMA30_Y_MODIFY                  0xFFC0B098         /* DMA30 Outer Loop Address Increment (2D only) */
2157 #define DMA30_CURR_DESC_PTR            0xFFC0B0A4         /* DMA30 Current Descriptor Pointer */
2158 #define DMA30_PREV_DESC_PTR            0xFFC0B0A8         /* DMA30 Previous Initial Descriptor Pointer */
2159 #define DMA30_CURR_ADDR              0xFFC0B0AC         /* DMA30 Current Address */
2160 #define DMA30_IRQ_STATUS                  0xFFC0B0B0         /* DMA30 Status Register */
2161 #define DMA30_CURR_X_COUNT              0xFFC0B0B4         /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
2162 #define DMA30_CURR_Y_COUNT              0xFFC0B0B8         /* DMA30 Current Row Count (2D only) */
2163 #define DMA30_BWL_COUNT                0xFFC0B0C0         /* DMA30 Bandwidth Limit Count */
2164 #define DMA30_CURR_BWL_COUNT            0xFFC0B0C4         /* DMA30 Bandwidth Limit Count Current */
2165 #define DMA30_BWM_COUNT                0xFFC0B0C8         /* DMA30 Bandwidth Monitor Count */
2166 #define DMA30_CURR_BWM_COUNT            0xFFC0B0CC         /* DMA30 Bandwidth Monitor Count Current */
2167 
2168 /* =========================
2169         DMA31
2170    ========================= */
2171 #define DMA31_NEXT_DESC_PTR            0xFFC0B100         /* DMA31 Pointer to Next Initial Descriptor */
2172 #define DMA31_START_ADDR             0xFFC0B104         /* DMA31 Start Address of Current Buffer */
2173 #define DMA31_CONFIG                   0xFFC0B108         /* DMA31 Configuration Register */
2174 #define DMA31_X_COUNT                  0xFFC0B10C         /* DMA31 Inner Loop Count Start Value */
2175 #define DMA31_X_MODIFY                  0xFFC0B110         /* DMA31 Inner Loop Address Increment */
2176 #define DMA31_Y_COUNT                  0xFFC0B114         /* DMA31 Outer Loop Count Start Value (2D only) */
2177 #define DMA31_Y_MODIFY                  0xFFC0B118         /* DMA31 Outer Loop Address Increment (2D only) */
2178 #define DMA31_CURR_DESC_PTR            0xFFC0B124         /* DMA31 Current Descriptor Pointer */
2179 #define DMA31_PREV_DESC_PTR            0xFFC0B128         /* DMA31 Previous Initial Descriptor Pointer */
2180 #define DMA31_CURR_ADDR              0xFFC0B12C         /* DMA31 Current Address */
2181 #define DMA31_IRQ_STATUS                  0xFFC0B130         /* DMA31 Status Register */
2182 #define DMA31_CURR_X_COUNT              0xFFC0B134         /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
2183 #define DMA31_CURR_Y_COUNT              0xFFC0B138         /* DMA31 Current Row Count (2D only) */
2184 #define DMA31_BWL_COUNT                0xFFC0B140         /* DMA31 Bandwidth Limit Count */
2185 #define DMA31_CURR_BWL_COUNT            0xFFC0B144         /* DMA31 Bandwidth Limit Count Current */
2186 #define DMA31_BWM_COUNT                0xFFC0B148         /* DMA31 Bandwidth Monitor Count */
2187 #define DMA31_CURR_BWM_COUNT            0xFFC0B14C         /* DMA31 Bandwidth Monitor Count Current */
2188 
2189 /* =========================
2190         DMA32
2191    ========================= */
2192 #define DMA32_NEXT_DESC_PTR            0xFFC0B180         /* DMA32 Pointer to Next Initial Descriptor */
2193 #define DMA32_START_ADDR             0xFFC0B184         /* DMA32 Start Address of Current Buffer */
2194 #define DMA32_CONFIG                   0xFFC0B188         /* DMA32 Configuration Register */
2195 #define DMA32_X_COUNT                  0xFFC0B18C         /* DMA32 Inner Loop Count Start Value */
2196 #define DMA32_X_MODIFY                  0xFFC0B190         /* DMA32 Inner Loop Address Increment */
2197 #define DMA32_Y_COUNT                  0xFFC0B194         /* DMA32 Outer Loop Count Start Value (2D only) */
2198 #define DMA32_Y_MODIFY                  0xFFC0B198         /* DMA32 Outer Loop Address Increment (2D only) */
2199 #define DMA32_CURR_DESC_PTR            0xFFC0B1A4         /* DMA32 Current Descriptor Pointer */
2200 #define DMA32_PREV_DESC_PTR            0xFFC0B1A8         /* DMA32 Previous Initial Descriptor Pointer */
2201 #define DMA32_CURR_ADDR              0xFFC0B1AC         /* DMA32 Current Address */
2202 #define DMA32_IRQ_STATUS                  0xFFC0B1B0         /* DMA32 Status Register */
2203 #define DMA32_CURR_X_COUNT              0xFFC0B1B4         /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
2204 #define DMA32_CURR_Y_COUNT              0xFFC0B1B8         /* DMA32 Current Row Count (2D only) */
2205 #define DMA32_BWL_COUNT                0xFFC0B1C0         /* DMA32 Bandwidth Limit Count */
2206 #define DMA32_CURR_BWL_COUNT            0xFFC0B1C4         /* DMA32 Bandwidth Limit Count Current */
2207 #define DMA32_BWM_COUNT                0xFFC0B1C8         /* DMA32 Bandwidth Monitor Count */
2208 #define DMA32_CURR_BWM_COUNT            0xFFC0B1CC         /* DMA32 Bandwidth Monitor Count Current */
2209 
2210 /* =========================
2211         DMA33
2212    ========================= */
2213 #define DMA33_NEXT_DESC_PTR            0xFFC0D000         /* DMA33 Pointer to Next Initial Descriptor */
2214 #define DMA33_START_ADDR             0xFFC0D004         /* DMA33 Start Address of Current Buffer */
2215 #define DMA33_CONFIG                   0xFFC0D008         /* DMA33 Configuration Register */
2216 #define DMA33_X_COUNT                  0xFFC0D00C         /* DMA33 Inner Loop Count Start Value */
2217 #define DMA33_X_MODIFY                  0xFFC0D010         /* DMA33 Inner Loop Address Increment */
2218 #define DMA33_Y_COUNT                  0xFFC0D014         /* DMA33 Outer Loop Count Start Value (2D only) */
2219 #define DMA33_Y_MODIFY                  0xFFC0D018         /* DMA33 Outer Loop Address Increment (2D only) */
2220 #define DMA33_CURR_DESC_PTR            0xFFC0D024         /* DMA33 Current Descriptor Pointer */
2221 #define DMA33_PREV_DESC_PTR            0xFFC0D028         /* DMA33 Previous Initial Descriptor Pointer */
2222 #define DMA33_CURR_ADDR              0xFFC0D02C         /* DMA33 Current Address */
2223 #define DMA33_IRQ_STATUS                  0xFFC0D030         /* DMA33 Status Register */
2224 #define DMA33_CURR_X_COUNT              0xFFC0D034         /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
2225 #define DMA33_CURR_Y_COUNT              0xFFC0D038         /* DMA33 Current Row Count (2D only) */
2226 #define DMA33_BWL_COUNT                0xFFC0D040         /* DMA33 Bandwidth Limit Count */
2227 #define DMA33_CURR_BWL_COUNT            0xFFC0D044         /* DMA33 Bandwidth Limit Count Current */
2228 #define DMA33_BWM_COUNT                0xFFC0D048         /* DMA33 Bandwidth Monitor Count */
2229 #define DMA33_CURR_BWM_COUNT            0xFFC0D04C         /* DMA33 Bandwidth Monitor Count Current */
2230 
2231 /* =========================
2232         DMA34
2233    ========================= */
2234 #define DMA34_NEXT_DESC_PTR            0xFFC0D080         /* DMA34 Pointer to Next Initial Descriptor */
2235 #define DMA34_START_ADDR             0xFFC0D084         /* DMA34 Start Address of Current Buffer */
2236 #define DMA34_CONFIG                   0xFFC0D088         /* DMA34 Configuration Register */
2237 #define DMA34_X_COUNT                  0xFFC0D08C         /* DMA34 Inner Loop Count Start Value */
2238 #define DMA34_X_MODIFY                  0xFFC0D090         /* DMA34 Inner Loop Address Increment */
2239 #define DMA34_Y_COUNT                  0xFFC0D094         /* DMA34 Outer Loop Count Start Value (2D only) */
2240 #define DMA34_Y_MODIFY                  0xFFC0D098         /* DMA34 Outer Loop Address Increment (2D only) */
2241 #define DMA34_CURR_DESC_PTR            0xFFC0D0A4         /* DMA34 Current Descriptor Pointer */
2242 #define DMA34_PREV_DESC_PTR            0xFFC0D0A8         /* DMA34 Previous Initial Descriptor Pointer */
2243 #define DMA34_CURR_ADDR              0xFFC0D0AC         /* DMA34 Current Address */
2244 #define DMA34_IRQ_STATUS                  0xFFC0D0B0         /* DMA34 Status Register */
2245 #define DMA34_CURR_X_COUNT              0xFFC0D0B4         /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
2246 #define DMA34_CURR_Y_COUNT              0xFFC0D0B8         /* DMA34 Current Row Count (2D only) */
2247 #define DMA34_BWL_COUNT                0xFFC0D0C0         /* DMA34 Bandwidth Limit Count */
2248 #define DMA34_CURR_BWL_COUNT            0xFFC0D0C4         /* DMA34 Bandwidth Limit Count Current */
2249 #define DMA34_BWM_COUNT                0xFFC0D0C8         /* DMA34 Bandwidth Monitor Count */
2250 #define DMA34_CURR_BWM_COUNT            0xFFC0D0CC         /* DMA34 Bandwidth Monitor Count Current */
2251 
2252 /* =========================
2253         DMA35
2254    ========================= */
2255 #define DMA35_NEXT_DESC_PTR            0xFFC10000         /* DMA35 Pointer to Next Initial Descriptor */
2256 #define DMA35_START_ADDR             0xFFC10004         /* DMA35 Start Address of Current Buffer */
2257 #define DMA35_CONFIG                   0xFFC10008         /* DMA35 Configuration Register */
2258 #define DMA35_X_COUNT                  0xFFC1000C         /* DMA35 Inner Loop Count Start Value */
2259 #define DMA35_X_MODIFY                  0xFFC10010         /* DMA35 Inner Loop Address Increment */
2260 #define DMA35_Y_COUNT                  0xFFC10014         /* DMA35 Outer Loop Count Start Value (2D only) */
2261 #define DMA35_Y_MODIFY                  0xFFC10018         /* DMA35 Outer Loop Address Increment (2D only) */
2262 #define DMA35_CURR_DESC_PTR            0xFFC10024         /* DMA35 Current Descriptor Pointer */
2263 #define DMA35_PREV_DESC_PTR            0xFFC10028         /* DMA35 Previous Initial Descriptor Pointer */
2264 #define DMA35_CURR_ADDR              0xFFC1002C         /* DMA35 Current Address */
2265 #define DMA35_IRQ_STATUS                  0xFFC10030         /* DMA35 Status Register */
2266 #define DMA35_CURR_X_COUNT              0xFFC10034         /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
2267 #define DMA35_CURR_Y_COUNT              0xFFC10038         /* DMA35 Current Row Count (2D only) */
2268 #define DMA35_BWL_COUNT                0xFFC10040         /* DMA35 Bandwidth Limit Count */
2269 #define DMA35_CURR_BWL_COUNT            0xFFC10044         /* DMA35 Bandwidth Limit Count Current */
2270 #define DMA35_BWM_COUNT                0xFFC10048         /* DMA35 Bandwidth Monitor Count */
2271 #define DMA35_CURR_BWM_COUNT            0xFFC1004C         /* DMA35 Bandwidth Monitor Count Current */
2272 
2273 /* =========================
2274         DMA36
2275    ========================= */
2276 #define DMA36_NEXT_DESC_PTR            0xFFC10080         /* DMA36 Pointer to Next Initial Descriptor */
2277 #define DMA36_START_ADDR             0xFFC10084         /* DMA36 Start Address of Current Buffer */
2278 #define DMA36_CONFIG                   0xFFC10088         /* DMA36 Configuration Register */
2279 #define DMA36_X_COUNT                  0xFFC1008C         /* DMA36 Inner Loop Count Start Value */
2280 #define DMA36_X_MODIFY                  0xFFC10090         /* DMA36 Inner Loop Address Increment */
2281 #define DMA36_Y_COUNT                  0xFFC10094         /* DMA36 Outer Loop Count Start Value (2D only) */
2282 #define DMA36_Y_MODIFY                  0xFFC10098         /* DMA36 Outer Loop Address Increment (2D only) */
2283 #define DMA36_CURR_DESC_PTR            0xFFC100A4         /* DMA36 Current Descriptor Pointer */
2284 #define DMA36_PREV_DESC_PTR            0xFFC100A8         /* DMA36 Previous Initial Descriptor Pointer */
2285 #define DMA36_CURR_ADDR              0xFFC100AC         /* DMA36 Current Address */
2286 #define DMA36_IRQ_STATUS                  0xFFC100B0         /* DMA36 Status Register */
2287 #define DMA36_CURR_X_COUNT              0xFFC100B4         /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
2288 #define DMA36_CURR_Y_COUNT              0xFFC100B8         /* DMA36 Current Row Count (2D only) */
2289 #define DMA36_BWL_COUNT                0xFFC100C0         /* DMA36 Bandwidth Limit Count */
2290 #define DMA36_CURR_BWL_COUNT            0xFFC100C4         /* DMA36 Bandwidth Limit Count Current */
2291 #define DMA36_BWM_COUNT                0xFFC100C8         /* DMA36 Bandwidth Monitor Count */
2292 #define DMA36_CURR_BWM_COUNT            0xFFC100CC         /* DMA36 Bandwidth Monitor Count Current */
2293 
2294 /* =========================
2295         DMA37
2296    ========================= */
2297 #define DMA37_NEXT_DESC_PTR            0xFFC10100         /* DMA37 Pointer to Next Initial Descriptor */
2298 #define DMA37_START_ADDR             0xFFC10104         /* DMA37 Start Address of Current Buffer */
2299 #define DMA37_CONFIG                   0xFFC10108         /* DMA37 Configuration Register */
2300 #define DMA37_X_COUNT                  0xFFC1010C         /* DMA37 Inner Loop Count Start Value */
2301 #define DMA37_X_MODIFY                  0xFFC10110         /* DMA37 Inner Loop Address Increment */
2302 #define DMA37_Y_COUNT                  0xFFC10114         /* DMA37 Outer Loop Count Start Value (2D only) */
2303 #define DMA37_Y_MODIFY                  0xFFC10118         /* DMA37 Outer Loop Address Increment (2D only) */
2304 #define DMA37_CURR_DESC_PTR            0xFFC10124         /* DMA37 Current Descriptor Pointer */
2305 #define DMA37_PREV_DESC_PTR            0xFFC10128         /* DMA37 Previous Initial Descriptor Pointer */
2306 #define DMA37_CURR_ADDR              0xFFC1012C         /* DMA37 Current Address */
2307 #define DMA37_IRQ_STATUS                  0xFFC10130         /* DMA37 Status Register */
2308 #define DMA37_CURR_X_COUNT              0xFFC10134         /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
2309 #define DMA37_CURR_Y_COUNT              0xFFC10138         /* DMA37 Current Row Count (2D only) */
2310 #define DMA37_BWL_COUNT                0xFFC10140         /* DMA37 Bandwidth Limit Count */
2311 #define DMA37_CURR_BWL_COUNT            0xFFC10144         /* DMA37 Bandwidth Limit Count Current */
2312 #define DMA37_BWM_COUNT                0xFFC10148         /* DMA37 Bandwidth Monitor Count */
2313 #define DMA37_CURR_BWM_COUNT            0xFFC1014C         /* DMA37 Bandwidth Monitor Count Current */
2314 
2315 /* =========================
2316         DMA38
2317    ========================= */
2318 #define DMA38_NEXT_DESC_PTR            0xFFC12000         /* DMA38 Pointer to Next Initial Descriptor */
2319 #define DMA38_START_ADDR             0xFFC12004         /* DMA38 Start Address of Current Buffer */
2320 #define DMA38_CONFIG                   0xFFC12008         /* DMA38 Configuration Register */
2321 #define DMA38_X_COUNT                  0xFFC1200C         /* DMA38 Inner Loop Count Start Value */
2322 #define DMA38_X_MODIFY                  0xFFC12010         /* DMA38 Inner Loop Address Increment */
2323 #define DMA38_Y_COUNT                  0xFFC12014         /* DMA38 Outer Loop Count Start Value (2D only) */
2324 #define DMA38_Y_MODIFY                  0xFFC12018         /* DMA38 Outer Loop Address Increment (2D only) */
2325 #define DMA38_CURR_DESC_PTR            0xFFC12024         /* DMA38 Current Descriptor Pointer */
2326 #define DMA38_PREV_DESC_PTR            0xFFC12028         /* DMA38 Previous Initial Descriptor Pointer */
2327 #define DMA38_CURR_ADDR              0xFFC1202C         /* DMA38 Current Address */
2328 #define DMA38_IRQ_STATUS                  0xFFC12030         /* DMA38 Status Register */
2329 #define DMA38_CURR_X_COUNT              0xFFC12034         /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
2330 #define DMA38_CURR_Y_COUNT              0xFFC12038         /* DMA38 Current Row Count (2D only) */
2331 #define DMA38_BWL_COUNT                0xFFC12040         /* DMA38 Bandwidth Limit Count */
2332 #define DMA38_CURR_BWL_COUNT            0xFFC12044         /* DMA38 Bandwidth Limit Count Current */
2333 #define DMA38_BWM_COUNT                0xFFC12048         /* DMA38 Bandwidth Monitor Count */
2334 #define DMA38_CURR_BWM_COUNT            0xFFC1204C         /* DMA38 Bandwidth Monitor Count Current */
2335 
2336 /* =========================
2337         DMA39
2338    ========================= */
2339 #define DMA39_NEXT_DESC_PTR            0xFFC12080         /* DMA39 Pointer to Next Initial Descriptor */
2340 #define DMA39_START_ADDR             0xFFC12084         /* DMA39 Start Address of Current Buffer */
2341 #define DMA39_CONFIG                   0xFFC12088         /* DMA39 Configuration Register */
2342 #define DMA39_X_COUNT                  0xFFC1208C         /* DMA39 Inner Loop Count Start Value */
2343 #define DMA39_X_MODIFY                  0xFFC12090         /* DMA39 Inner Loop Address Increment */
2344 #define DMA39_Y_COUNT                  0xFFC12094         /* DMA39 Outer Loop Count Start Value (2D only) */
2345 #define DMA39_Y_MODIFY                  0xFFC12098         /* DMA39 Outer Loop Address Increment (2D only) */
2346 #define DMA39_CURR_DESC_PTR            0xFFC120A4         /* DMA39 Current Descriptor Pointer */
2347 #define DMA39_PREV_DESC_PTR            0xFFC120A8         /* DMA39 Previous Initial Descriptor Pointer */
2348 #define DMA39_CURR_ADDR              0xFFC120AC         /* DMA39 Current Address */
2349 #define DMA39_IRQ_STATUS                  0xFFC120B0         /* DMA39 Status Register */
2350 #define DMA39_CURR_X_COUNT              0xFFC120B4         /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
2351 #define DMA39_CURR_Y_COUNT              0xFFC120B8         /* DMA39 Current Row Count (2D only) */
2352 #define DMA39_BWL_COUNT                0xFFC120C0         /* DMA39 Bandwidth Limit Count */
2353 #define DMA39_CURR_BWL_COUNT            0xFFC120C4         /* DMA39 Bandwidth Limit Count Current */
2354 #define DMA39_BWM_COUNT                0xFFC120C8         /* DMA39 Bandwidth Monitor Count */
2355 #define DMA39_CURR_BWM_COUNT            0xFFC120CC         /* DMA39 Bandwidth Monitor Count Current */
2356 
2357 /* =========================
2358         DMA40
2359    ========================= */
2360 #define DMA40_NEXT_DESC_PTR            0xFFC12100         /* DMA40 Pointer to Next Initial Descriptor */
2361 #define DMA40_START_ADDR             0xFFC12104         /* DMA40 Start Address of Current Buffer */
2362 #define DMA40_CONFIG                   0xFFC12108         /* DMA40 Configuration Register */
2363 #define DMA40_X_COUNT                  0xFFC1210C         /* DMA40 Inner Loop Count Start Value */
2364 #define DMA40_X_MODIFY                  0xFFC12110         /* DMA40 Inner Loop Address Increment */
2365 #define DMA40_Y_COUNT                  0xFFC12114         /* DMA40 Outer Loop Count Start Value (2D only) */
2366 #define DMA40_Y_MODIFY                  0xFFC12118         /* DMA40 Outer Loop Address Increment (2D only) */
2367 #define DMA40_CURR_DESC_PTR            0xFFC12124         /* DMA40 Current Descriptor Pointer */
2368 #define DMA40_PREV_DESC_PTR            0xFFC12128         /* DMA40 Previous Initial Descriptor Pointer */
2369 #define DMA40_CURR_ADDR              0xFFC1212C         /* DMA40 Current Address */
2370 #define DMA40_IRQ_STATUS                  0xFFC12130         /* DMA40 Status Register */
2371 #define DMA40_CURR_X_COUNT              0xFFC12134         /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
2372 #define DMA40_CURR_Y_COUNT              0xFFC12138         /* DMA40 Current Row Count (2D only) */
2373 #define DMA40_BWL_COUNT                0xFFC12140         /* DMA40 Bandwidth Limit Count */
2374 #define DMA40_CURR_BWL_COUNT            0xFFC12144         /* DMA40 Bandwidth Limit Count Current */
2375 #define DMA40_BWM_COUNT                0xFFC12148         /* DMA40 Bandwidth Monitor Count */
2376 #define DMA40_CURR_BWM_COUNT            0xFFC1214C         /* DMA40 Bandwidth Monitor Count Current */
2377 
2378 /* =========================
2379         DMA41
2380    ========================= */
2381 #define DMA41_NEXT_DESC_PTR            0xFFC12180         /* DMA41 Pointer to Next Initial Descriptor */
2382 #define DMA41_START_ADDR             0xFFC12184         /* DMA41 Start Address of Current Buffer */
2383 #define DMA41_CONFIG                   0xFFC12188         /* DMA41 Configuration Register */
2384 #define DMA41_X_COUNT                  0xFFC1218C         /* DMA41 Inner Loop Count Start Value */
2385 #define DMA41_X_MODIFY                  0xFFC12190         /* DMA41 Inner Loop Address Increment */
2386 #define DMA41_Y_COUNT                  0xFFC12194         /* DMA41 Outer Loop Count Start Value (2D only) */
2387 #define DMA41_Y_MODIFY                  0xFFC12198         /* DMA41 Outer Loop Address Increment (2D only) */
2388 #define DMA41_CURR_DESC_PTR            0xFFC121A4         /* DMA41 Current Descriptor Pointer */
2389 #define DMA41_PREV_DESC_PTR            0xFFC121A8         /* DMA41 Previous Initial Descriptor Pointer */
2390 #define DMA41_CURR_ADDR              0xFFC121AC         /* DMA41 Current Address */
2391 #define DMA41_IRQ_STATUS                  0xFFC121B0         /* DMA41 Status Register */
2392 #define DMA41_CURR_X_COUNT              0xFFC121B4         /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
2393 #define DMA41_CURR_Y_COUNT              0xFFC121B8         /* DMA41 Current Row Count (2D only) */
2394 #define DMA41_BWL_COUNT                0xFFC121C0         /* DMA41 Bandwidth Limit Count */
2395 #define DMA41_CURR_BWL_COUNT            0xFFC121C4         /* DMA41 Bandwidth Limit Count Current */
2396 #define DMA41_BWM_COUNT                0xFFC121C8         /* DMA41 Bandwidth Monitor Count */
2397 #define DMA41_CURR_BWM_COUNT            0xFFC121CC         /* DMA41 Bandwidth Monitor Count Current */
2398 
2399 /* =========================
2400         DMA42
2401    ========================= */
2402 #define DMA42_NEXT_DESC_PTR            0xFFC14000         /* DMA42 Pointer to Next Initial Descriptor */
2403 #define DMA42_START_ADDR             0xFFC14004         /* DMA42 Start Address of Current Buffer */
2404 #define DMA42_CONFIG                   0xFFC14008         /* DMA42 Configuration Register */
2405 #define DMA42_X_COUNT                  0xFFC1400C         /* DMA42 Inner Loop Count Start Value */
2406 #define DMA42_X_MODIFY                  0xFFC14010         /* DMA42 Inner Loop Address Increment */
2407 #define DMA42_Y_COUNT                  0xFFC14014         /* DMA42 Outer Loop Count Start Value (2D only) */
2408 #define DMA42_Y_MODIFY                  0xFFC14018         /* DMA42 Outer Loop Address Increment (2D only) */
2409 #define DMA42_CURR_DESC_PTR            0xFFC14024         /* DMA42 Current Descriptor Pointer */
2410 #define DMA42_PREV_DESC_PTR            0xFFC14028         /* DMA42 Previous Initial Descriptor Pointer */
2411 #define DMA42_CURR_ADDR              0xFFC1402C         /* DMA42 Current Address */
2412 #define DMA42_IRQ_STATUS                  0xFFC14030         /* DMA42 Status Register */
2413 #define DMA42_CURR_X_COUNT              0xFFC14034         /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
2414 #define DMA42_CURR_Y_COUNT              0xFFC14038         /* DMA42 Current Row Count (2D only) */
2415 #define DMA42_BWL_COUNT                0xFFC14040         /* DMA42 Bandwidth Limit Count */
2416 #define DMA42_CURR_BWL_COUNT            0xFFC14044         /* DMA42 Bandwidth Limit Count Current */
2417 #define DMA42_BWM_COUNT                0xFFC14048         /* DMA42 Bandwidth Monitor Count */
2418 #define DMA42_CURR_BWM_COUNT            0xFFC1404C         /* DMA42 Bandwidth Monitor Count Current */
2419 
2420 /* =========================
2421         DMA43
2422    ========================= */
2423 #define DMA43_NEXT_DESC_PTR            0xFFC14080         /* DMA43 Pointer to Next Initial Descriptor */
2424 #define DMA43_START_ADDR             0xFFC14084         /* DMA43 Start Address of Current Buffer */
2425 #define DMA43_CONFIG                   0xFFC14088         /* DMA43 Configuration Register */
2426 #define DMA43_X_COUNT                  0xFFC1408C         /* DMA43 Inner Loop Count Start Value */
2427 #define DMA43_X_MODIFY                  0xFFC14090         /* DMA43 Inner Loop Address Increment */
2428 #define DMA43_Y_COUNT                  0xFFC14094         /* DMA43 Outer Loop Count Start Value (2D only) */
2429 #define DMA43_Y_MODIFY                  0xFFC14098         /* DMA43 Outer Loop Address Increment (2D only) */
2430 #define DMA43_CURR_DESC_PTR            0xFFC140A4         /* DMA43 Current Descriptor Pointer */
2431 #define DMA43_PREV_DESC_PTR            0xFFC140A8         /* DMA43 Previous Initial Descriptor Pointer */
2432 #define DMA43_CURR_ADDR              0xFFC140AC         /* DMA43 Current Address */
2433 #define DMA43_IRQ_STATUS                  0xFFC140B0         /* DMA43 Status Register */
2434 #define DMA43_CURR_X_COUNT              0xFFC140B4         /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
2435 #define DMA43_CURR_Y_COUNT              0xFFC140B8         /* DMA43 Current Row Count (2D only) */
2436 #define DMA43_BWL_COUNT                0xFFC140C0         /* DMA43 Bandwidth Limit Count */
2437 #define DMA43_CURR_BWL_COUNT            0xFFC140C4         /* DMA43 Bandwidth Limit Count Current */
2438 #define DMA43_BWM_COUNT                0xFFC140C8         /* DMA43 Bandwidth Monitor Count */
2439 #define DMA43_CURR_BWM_COUNT            0xFFC140CC         /* DMA43 Bandwidth Monitor Count Current */
2440 
2441 /* =========================
2442         DMA44
2443    ========================= */
2444 #define DMA44_NEXT_DESC_PTR            0xFFC14100         /* DMA44 Pointer to Next Initial Descriptor */
2445 #define DMA44_START_ADDR             0xFFC14104         /* DMA44 Start Address of Current Buffer */
2446 #define DMA44_CONFIG                   0xFFC14108         /* DMA44 Configuration Register */
2447 #define DMA44_X_COUNT                  0xFFC1410C         /* DMA44 Inner Loop Count Start Value */
2448 #define DMA44_X_MODIFY                  0xFFC14110         /* DMA44 Inner Loop Address Increment */
2449 #define DMA44_Y_COUNT                  0xFFC14114         /* DMA44 Outer Loop Count Start Value (2D only) */
2450 #define DMA44_Y_MODIFY                  0xFFC14118         /* DMA44 Outer Loop Address Increment (2D only) */
2451 #define DMA44_CURR_DESC_PTR            0xFFC14124         /* DMA44 Current Descriptor Pointer */
2452 #define DMA44_PREV_DESC_PTR            0xFFC14128         /* DMA44 Previous Initial Descriptor Pointer */
2453 #define DMA44_CURR_ADDR              0xFFC1412C         /* DMA44 Current Address */
2454 #define DMA44_IRQ_STATUS                  0xFFC14130         /* DMA44 Status Register */
2455 #define DMA44_CURR_X_COUNT              0xFFC14134         /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
2456 #define DMA44_CURR_Y_COUNT              0xFFC14138         /* DMA44 Current Row Count (2D only) */
2457 #define DMA44_BWL_COUNT                0xFFC14140         /* DMA44 Bandwidth Limit Count */
2458 #define DMA44_CURR_BWL_COUNT            0xFFC14144         /* DMA44 Bandwidth Limit Count Current */
2459 #define DMA44_BWM_COUNT                0xFFC14148         /* DMA44 Bandwidth Monitor Count */
2460 #define DMA44_CURR_BWM_COUNT            0xFFC1414C         /* DMA44 Bandwidth Monitor Count Current */
2461 
2462 /* =========================
2463         DMA45
2464    ========================= */
2465 #define DMA45_NEXT_DESC_PTR            0xFFC14180         /* DMA45 Pointer to Next Initial Descriptor */
2466 #define DMA45_START_ADDR             0xFFC14184         /* DMA45 Start Address of Current Buffer */
2467 #define DMA45_CONFIG                   0xFFC14188         /* DMA45 Configuration Register */
2468 #define DMA45_X_COUNT                  0xFFC1418C         /* DMA45 Inner Loop Count Start Value */
2469 #define DMA45_X_MODIFY                  0xFFC14190         /* DMA45 Inner Loop Address Increment */
2470 #define DMA45_Y_COUNT                  0xFFC14194         /* DMA45 Outer Loop Count Start Value (2D only) */
2471 #define DMA45_Y_MODIFY                  0xFFC14198         /* DMA45 Outer Loop Address Increment (2D only) */
2472 #define DMA45_CURR_DESC_PTR            0xFFC141A4         /* DMA45 Current Descriptor Pointer */
2473 #define DMA45_PREV_DESC_PTR            0xFFC141A8         /* DMA45 Previous Initial Descriptor Pointer */
2474 #define DMA45_CURR_ADDR              0xFFC141AC         /* DMA45 Current Address */
2475 #define DMA45_IRQ_STATUS                  0xFFC141B0         /* DMA45 Status Register */
2476 #define DMA45_CURR_X_COUNT              0xFFC141B4         /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
2477 #define DMA45_CURR_Y_COUNT              0xFFC141B8         /* DMA45 Current Row Count (2D only) */
2478 #define DMA45_BWL_COUNT                0xFFC141C0         /* DMA45 Bandwidth Limit Count */
2479 #define DMA45_CURR_BWL_COUNT            0xFFC141C4         /* DMA45 Bandwidth Limit Count Current */
2480 #define DMA45_BWM_COUNT                0xFFC141C8         /* DMA45 Bandwidth Monitor Count */
2481 #define DMA45_CURR_BWM_COUNT            0xFFC141CC         /* DMA45 Bandwidth Monitor Count Current */
2482 
2483 /* =========================
2484         DMA46
2485    ========================= */
2486 #define DMA46_NEXT_DESC_PTR            0xFFC14200         /* DMA46 Pointer to Next Initial Descriptor */
2487 #define DMA46_START_ADDR             0xFFC14204         /* DMA46 Start Address of Current Buffer */
2488 #define DMA46_CONFIG                   0xFFC14208         /* DMA46 Configuration Register */
2489 #define DMA46_X_COUNT                  0xFFC1420C         /* DMA46 Inner Loop Count Start Value */
2490 #define DMA46_X_MODIFY                  0xFFC14210         /* DMA46 Inner Loop Address Increment */
2491 #define DMA46_Y_COUNT                  0xFFC14214         /* DMA46 Outer Loop Count Start Value (2D only) */
2492 #define DMA46_Y_MODIFY                  0xFFC14218         /* DMA46 Outer Loop Address Increment (2D only) */
2493 #define DMA46_CURR_DESC_PTR            0xFFC14224         /* DMA46 Current Descriptor Pointer */
2494 #define DMA46_PREV_DESC_PTR            0xFFC14228         /* DMA46 Previous Initial Descriptor Pointer */
2495 #define DMA46_CURR_ADDR              0xFFC1422C         /* DMA46 Current Address */
2496 #define DMA46_IRQ_STATUS                  0xFFC14230         /* DMA46 Status Register */
2497 #define DMA46_CURR_X_COUNT              0xFFC14234         /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
2498 #define DMA46_CURR_Y_COUNT              0xFFC14238         /* DMA46 Current Row Count (2D only) */
2499 #define DMA46_BWL_COUNT                0xFFC14240         /* DMA46 Bandwidth Limit Count */
2500 #define DMA46_CURR_BWL_COUNT            0xFFC14244         /* DMA46 Bandwidth Limit Count Current */
2501 #define DMA46_BWM_COUNT                0xFFC14248         /* DMA46 Bandwidth Monitor Count */
2502 #define DMA46_CURR_BWM_COUNT            0xFFC1424C         /* DMA46 Bandwidth Monitor Count Current */
2503 
2504 
2505 /********************************************************************************
2506     DMA Alias Definitions
2507  ********************************************************************************/
2508 #define MDMA0_DEST_CRC0_NEXT_DESC_PTR   (DMA22_NEXT_DESC_PTR)
2509 #define MDMA0_DEST_CRC0_START_ADDR    (DMA22_START_ADDR)
2510 #define MDMA0_DEST_CRC0_CONFIG          (DMA22_CONFIG)
2511 #define MDMA0_DEST_CRC0_X_COUNT         (DMA22_X_COUNT)
2512 #define MDMA0_DEST_CRC0_X_MODIFY         (DMA22_X_MODIFY)
2513 #define MDMA0_DEST_CRC0_Y_COUNT         (DMA22_Y_COUNT)
2514 #define MDMA0_DEST_CRC0_Y_MODIFY         (DMA22_Y_MODIFY)
2515 #define MDMA0_DEST_CRC0_CURR_DESC_PTR   (DMA22_CURR_DESC_PTR)
2516 #define MDMA0_DEST_CRC0_PREV_DESC_PTR   (DMA22_PREV_DESC_PTR)
2517 #define MDMA0_DEST_CRC0_CURR_ADDR     (DMA22_CURR_ADDR)
2518 #define MDMA0_DEST_CRC0_IRQ_STATUS         (DMA22_IRQ_STATUS)
2519 #define MDMA0_DEST_CRC0_CURR_X_COUNT     (DMA22_CURR_X_COUNT)
2520 #define MDMA0_DEST_CRC0_CURR_Y_COUNT     (DMA22_CURR_Y_COUNT)
2521 #define MDMA0_DEST_CRC0_BWL_COUNT       (DMA22_BWL_COUNT)
2522 #define MDMA0_DEST_CRC0_CURR_BWL_COUNT   (DMA22_CURR_BWL_COUNT)
2523 #define MDMA0_DEST_CRC0_BWM_COUNT       (DMA22_BWM_COUNT)
2524 #define MDMA0_DEST_CRC0_CURR_BWM_COUNT   (DMA22_CURR_BWM_COUNT)
2525 #define MDMA0_SRC_CRC0_NEXT_DESC_PTR    (DMA21_NEXT_DESC_PTR)
2526 #define MDMA0_SRC_CRC0_START_ADDR     (DMA21_START_ADDR)
2527 #define MDMA0_SRC_CRC0_CONFIG           (DMA21_CONFIG)
2528 #define MDMA0_SRC_CRC0_X_COUNT          (DMA21_X_COUNT)
2529 #define MDMA0_SRC_CRC0_X_MODIFY          (DMA21_X_MODIFY)
2530 #define MDMA0_SRC_CRC0_Y_COUNT          (DMA21_Y_COUNT)
2531 #define MDMA0_SRC_CRC0_Y_MODIFY          (DMA21_Y_MODIFY)
2532 #define MDMA0_SRC_CRC0_CURR_DESC_PTR    (DMA21_CURR_DESC_PTR)
2533 #define MDMA0_SRC_CRC0_PREV_DESC_PTR    (DMA21_PREV_DESC_PTR)
2534 #define MDMA0_SRC_CRC0_CURR_ADDR      (DMA21_CURR_ADDR)
2535 #define MDMA0_SRC_CRC0_IRQ_STATUS          (DMA21_IRQ_STATUS)
2536 #define MDMA0_SRC_CRC0_CURR_X_COUNT      (DMA21_CURR_X_COUNT)
2537 #define MDMA0_SRC_CRC0_CURR_Y_COUNT      (DMA21_CURR_Y_COUNT)
2538 #define MDMA0_SRC_CRC0_BWL_COUNT        (DMA21_BWL_COUNT)
2539 #define MDMA0_SRC_CRC0_CURR_BWL_COUNT    (DMA21_CURR_BWL_COUNT)
2540 #define MDMA0_SRC_CRC0_BWM_COUNT        (DMA21_BWM_COUNT)
2541 #define MDMA0_SRC_CRC0_CURR_BWM_COUNT    (DMA21_CURR_BWM_COUNT)
2542 #define MDMA1_DEST_CRC1_NEXT_DESC_PTR   (DMA24_NEXT_DESC_PTR)
2543 #define MDMA1_DEST_CRC1_START_ADDR    (DMA24_START_ADDR)
2544 #define MDMA1_DEST_CRC1_CONFIG          (DMA24_CONFIG)
2545 #define MDMA1_DEST_CRC1_X_COUNT         (DMA24_X_COUNT)
2546 #define MDMA1_DEST_CRC1_X_MODIFY         (DMA24_X_MODIFY)
2547 #define MDMA1_DEST_CRC1_Y_COUNT         (DMA24_Y_COUNT)
2548 #define MDMA1_DEST_CRC1_Y_MODIFY         (DMA24_Y_MODIFY)
2549 #define MDMA1_DEST_CRC1_CURR_DESC_PTR   (DMA24_CURR_DESC_PTR)
2550 #define MDMA1_DEST_CRC1_PREV_DESC_PTR   (DMA24_PREV_DESC_PTR)
2551 #define MDMA1_DEST_CRC1_CURR_ADDR     (DMA24_CURR_ADDR)
2552 #define MDMA1_DEST_CRC1_IRQ_STATUS         (DMA24_IRQ_STATUS)
2553 #define MDMA1_DEST_CRC1_CURR_X_COUNT     (DMA24_CURR_X_COUNT)
2554 #define MDMA1_DEST_CRC1_CURR_Y_COUNT     (DMA24_CURR_Y_COUNT)
2555 #define MDMA1_DEST_CRC1_BWL_COUNT       (DMA24_BWL_COUNT)
2556 #define MDMA1_DEST_CRC1_CURR_BWL_COUNT   (DMA24_CURR_BWL_COUNT)
2557 #define MDMA1_DEST_CRC1_BWM_COUNT       (DMA24_BWM_COUNT)
2558 #define MDMA1_DEST_CRC1_CURR_BWM_COUNT   (DMA24_CURR_BWM_COUNT)
2559 #define MDMA1_SRC_CRC1_NEXT_DESC_PTR    (DMA23_NEXT_DESC_PTR)
2560 #define MDMA1_SRC_CRC1_START_ADDR     (DMA23_START_ADDR)
2561 #define MDMA1_SRC_CRC1_CONFIG           (DMA23_CONFIG)
2562 #define MDMA1_SRC_CRC1_X_COUNT          (DMA23_X_COUNT)
2563 #define MDMA1_SRC_CRC1_X_MODIFY          (DMA23_X_MODIFY)
2564 #define MDMA1_SRC_CRC1_Y_COUNT          (DMA23_Y_COUNT)
2565 #define MDMA1_SRC_CRC1_Y_MODIFY          (DMA23_Y_MODIFY)
2566 #define MDMA1_SRC_CRC1_CURR_DESC_PTR    (DMA23_CURR_DESC_PTR)
2567 #define MDMA1_SRC_CRC1_PREV_DESC_PTR    (DMA23_PREV_DESC_PTR)
2568 #define MDMA1_SRC_CRC1_CURR_ADDR      (DMA23_CURR_ADDR)
2569 #define MDMA1_SRC_CRC1_IRQ_STATUS          (DMA23_IRQ_STATUS)
2570 #define MDMA1_SRC_CRC1_CURR_X_COUNT      (DMA23_CURR_X_COUNT)
2571 #define MDMA1_SRC_CRC1_CURR_Y_COUNT      (DMA23_CURR_Y_COUNT)
2572 #define MDMA1_SRC_CRC1_BWL_COUNT        (DMA23_BWL_COUNT)
2573 #define MDMA1_SRC_CRC1_CURR_BWL_COUNT    (DMA23_CURR_BWL_COUNT)
2574 #define MDMA1_SRC_CRC1_BWM_COUNT        (DMA23_BWM_COUNT)
2575 #define MDMA1_SRC_CRC1_CURR_BWM_COUNT    (DMA23_CURR_BWM_COUNT)
2576 #define MDMA2_DEST_NEXT_DESC_PTR            (DMA26_NEXT_DESC_PTR)
2577 #define MDMA2_DEST_START_ADDR             (DMA26_START_ADDR)
2578 #define MDMA2_DEST_CONFIG                   (DMA26_CONFIG)
2579 #define MDMA2_DEST_X_COUNT                  (DMA26_X_COUNT)
2580 #define MDMA2_DEST_X_MODIFY                  (DMA26_X_MODIFY)
2581 #define MDMA2_DEST_Y_COUNT                  (DMA26_Y_COUNT)
2582 #define MDMA2_DEST_Y_MODIFY                  (DMA26_Y_MODIFY)
2583 #define MDMA2_DEST_CURR_DESC_PTR            (DMA26_CURR_DESC_PTR)
2584 #define MDMA2_DEST_PREV_DESC_PTR            (DMA26_PREV_DESC_PTR)
2585 #define MDMA2_DEST_CURR_ADDR              (DMA26_CURR_ADDR)
2586 #define MDMA2_DEST_IRQ_STATUS                  (DMA26_IRQ_STATUS)
2587 #define MDMA2_DEST_CURR_X_COUNT              (DMA26_CURR_X_COUNT)
2588 #define MDMA2_DEST_CURR_Y_COUNT              (DMA26_CURR_Y_COUNT)
2589 #define MDMA2_DEST_BWL_COUNT                (DMA26_BWL_COUNT)
2590 #define MDMA2_DEST_CURR_BWL_COUNT            (DMA26_CURR_BWL_COUNT)
2591 #define MDMA2_DEST_BWM_COUNT                (DMA26_BWM_COUNT)
2592 #define MDMA2_DEST_CURR_BWM_COUNT            (DMA26_CURR_BWM_COUNT)
2593 #define MDMA2_SRC_NEXT_DESC_PTR            (DMA25_NEXT_DESC_PTR)
2594 #define MDMA2_SRC_START_ADDR             (DMA25_START_ADDR)
2595 #define MDMA2_SRC_CONFIG                   (DMA25_CONFIG)
2596 #define MDMA2_SRC_X_COUNT                  (DMA25_X_COUNT)
2597 #define MDMA2_SRC_X_MODIFY                  (DMA25_X_MODIFY)
2598 #define MDMA2_SRC_Y_COUNT                  (DMA25_Y_COUNT)
2599 #define MDMA2_SRC_Y_MODIFY                  (DMA25_Y_MODIFY)
2600 #define MDMA2_SRC_CURR_DESC_PTR            (DMA25_CURR_DESC_PTR)
2601 #define MDMA2_SRC_PREV_DESC_PTR            (DMA25_PREV_DESC_PTR)
2602 #define MDMA2_SRC_CURR_ADDR              (DMA25_CURR_ADDR)
2603 #define MDMA2_SRC_IRQ_STATUS                  (DMA25_IRQ_STATUS)
2604 #define MDMA2_SRC_CURR_X_COUNT              (DMA25_CURR_X_COUNT)
2605 #define MDMA2_SRC_CURR_Y_COUNT              (DMA25_CURR_Y_COUNT)
2606 #define MDMA2_SRC_BWL_COUNT                (DMA25_BWL_COUNT)
2607 #define MDMA2_SRC_CURR_BWL_COUNT            (DMA25_CURR_BWL_COUNT)
2608 #define MDMA2_SRC_BWM_COUNT                (DMA25_BWM_COUNT)
2609 #define MDMA2_SRC_CURR_BWM_COUNT            (DMA25_CURR_BWM_COUNT)
2610 #define MDMA3_DEST_NEXT_DESC_PTR            (DMA28_NEXT_DESC_PTR)
2611 #define MDMA3_DEST_START_ADDR             (DMA28_START_ADDR)
2612 #define MDMA3_DEST_CONFIG                   (DMA28_CONFIG)
2613 #define MDMA3_DEST_X_COUNT                  (DMA28_X_COUNT)
2614 #define MDMA3_DEST_X_MODIFY                  (DMA28_X_MODIFY)
2615 #define MDMA3_DEST_Y_COUNT                  (DMA28_Y_COUNT)
2616 #define MDMA3_DEST_Y_MODIFY                  (DMA28_Y_MODIFY)
2617 #define MDMA3_DEST_CURR_DESC_PTR            (DMA28_CURR_DESC_PTR)
2618 #define MDMA3_DEST_PREV_DESC_PTR            (DMA28_PREV_DESC_PTR)
2619 #define MDMA3_DEST_CURR_ADDR              (DMA28_CURR_ADDR)
2620 #define MDMA3_DEST_IRQ_STATUS                  (DMA28_IRQ_STATUS)
2621 #define MDMA3_DEST_CURR_X_COUNT              (DMA28_CURR_X_COUNT)
2622 #define MDMA3_DEST_CURR_Y_COUNT              (DMA28_CURR_Y_COUNT)
2623 #define MDMA3_DEST_BWL_COUNT                (DMA28_BWL_COUNT)
2624 #define MDMA3_DEST_CURR_BWL_COUNT            (DMA28_CURR_BWL_COUNT)
2625 #define MDMA3_DEST_BWM_COUNT                (DMA28_BWM_COUNT)
2626 #define MDMA3_DEST_CURR_BWM_COUNT            (DMA28_CURR_BWM_COUNT)
2627 #define MDMA3_SRC_NEXT_DESC_PTR            (DMA27_NEXT_DESC_PTR)
2628 #define MDMA3_SRC_START_ADDR             (DMA27_START_ADDR)
2629 #define MDMA3_SRC_CONFIG                   (DMA27_CONFIG)
2630 #define MDMA3_SRC_X_COUNT                  (DMA27_X_COUNT)
2631 #define MDMA3_SRC_X_MODIFY                  (DMA27_X_MODIFY)
2632 #define MDMA3_SRC_Y_COUNT                  (DMA27_Y_COUNT)
2633 #define MDMA3_SRC_Y_MODIFY                  (DMA27_Y_MODIFY)
2634 #define MDMA3_SRC_CURR_DESC_PTR            (DMA27_CURR_DESC_PTR)
2635 #define MDMA3_SRC_PREV_DESC_PTR            (DMA27_PREV_DESC_PTR)
2636 #define MDMA3_SRC_CURR_ADDR              (DMA27_CURR_ADDR)
2637 #define MDMA3_SRC_IRQ_STATUS                  (DMA27_IRQ_STATUS)
2638 #define MDMA3_SRC_CURR_X_COUNT              (DMA27_CURR_X_COUNT)
2639 #define MDMA3_SRC_CURR_Y_COUNT              (DMA27_CURR_Y_COUNT)
2640 #define MDMA3_SRC_BWL_COUNT                (DMA27_BWL_COUNT)
2641 #define MDMA3_SRC_CURR_BWL_COUNT            (DMA27_CURR_BWL_COUNT)
2642 #define MDMA3_SRC_BWM_COUNT                (DMA27_BWM_COUNT)
2643 #define MDMA3_SRC_CURR_BWM_COUNT            (DMA27_CURR_BWM_COUNT)
2644 
2645 
2646 /* =========================
2647         DMC Registers
2648    ========================= */
2649 
2650 /* =========================
2651         DMC0
2652    ========================= */
2653 #define DMC0_ID                     0xFFC80000         /* DMC0 Identification Register */
2654 #define DMC0_CTL                    0xFFC80004         /* DMC0 Control Register */
2655 #define DMC0_STAT                   0xFFC80008         /* DMC0 Status Register */
2656 #define DMC0_EFFCTL                 0xFFC8000C         /* DMC0 Efficiency Controller */
2657 #define DMC0_PRIO                   0xFFC80010         /* DMC0 Priority ID Register */
2658 #define DMC0_PRIOMSK                0xFFC80014         /* DMC0 Priority ID Mask */
2659 #define DMC0_CFG                    0xFFC80040         /* DMC0 SDRAM Configuration */
2660 #define DMC0_TR0                    0xFFC80044         /* DMC0 Timing Register 0 */
2661 #define DMC0_TR1                    0xFFC80048         /* DMC0 Timing Register 1 */
2662 #define DMC0_TR2                    0xFFC8004C         /* DMC0 Timing Register 2 */
2663 #define DMC0_MSK                    0xFFC8005C         /* DMC0 Mode Register Mask */
2664 #define DMC0_MR                     0xFFC80060         /* DMC0 Mode Shadow register */
2665 #define DMC0_EMR1                   0xFFC80064         /* DMC0 EMR1 Shadow Register */
2666 #define DMC0_EMR2                   0xFFC80068         /* DMC0 EMR2 Shadow Register */
2667 #define DMC0_EMR3                   0xFFC8006C         /* DMC0 EMR3 Shadow Register */
2668 #define DMC0_DLLCTL                 0xFFC80080         /* DMC0 DLL Control Register */
2669 #define DMC0_PADCTL                 0xFFC800C0         /* DMC0 PAD Control Register 0 */
2670 
2671 #define DEVSZ_64                0x000         /* DMC External Bank Size = 64Mbit */
2672 #define DEVSZ_128               0x100         /* DMC External Bank Size = 128Mbit */
2673 #define DEVSZ_256               0x200         /* DMC External Bank Size = 256Mbit */
2674 #define DEVSZ_512               0x300         /* DMC External Bank Size = 512Mbit */
2675 #define DEVSZ_1G                0x400         /* DMC External Bank Size = 1Gbit */
2676 #define DEVSZ_2G                0x500         /* DMC External Bank Size = 2Gbit */
2677 
2678 /* =========================
2679         L2CTL Registers
2680    ========================= */
2681 
2682 /* =========================
2683         L2CTL0
2684    ========================= */
2685 #define L2CTL0_CTL                  0xFFCA3000         /* L2CTL0 L2 Control Register */
2686 #define L2CTL0_ACTL_C0              0xFFCA3004         /* L2CTL0 L2 Core 0 Access Control Register */
2687 #define L2CTL0_ACTL_C1              0xFFCA3008         /* L2CTL0 L2 Core 1 Access Control Register */
2688 #define L2CTL0_ACTL_SYS             0xFFCA300C         /* L2CTL0 L2 System Access Control Register */
2689 #define L2CTL0_STAT                 0xFFCA3010         /* L2CTL0 L2 Status Register */
2690 #define L2CTL0_RPCR                 0xFFCA3014         /* L2CTL0 L2 Read Priority Count Register */
2691 #define L2CTL0_WPCR                 0xFFCA3018         /* L2CTL0 L2 Write Priority Count Register */
2692 #define L2CTL0_RFA                  0xFFCA3024         /* L2CTL0 L2 Refresh Address Regsiter */
2693 #define L2CTL0_ERRADDR0             0xFFCA3040         /* L2CTL0 L2 Bank 0 ECC Error Address Register */
2694 #define L2CTL0_ERRADDR1             0xFFCA3044         /* L2CTL0 L2 Bank 1 ECC Error Address Register */
2695 #define L2CTL0_ERRADDR2             0xFFCA3048         /* L2CTL0 L2 Bank 2 ECC Error Address Register */
2696 #define L2CTL0_ERRADDR3             0xFFCA304C         /* L2CTL0 L2 Bank 3 ECC Error Address Register */
2697 #define L2CTL0_ERRADDR4             0xFFCA3050         /* L2CTL0 L2 Bank 4 ECC Error Address Register */
2698 #define L2CTL0_ERRADDR5             0xFFCA3054         /* L2CTL0 L2 Bank 5 ECC Error Address Register */
2699 #define L2CTL0_ERRADDR6             0xFFCA3058         /* L2CTL0 L2 Bank 6 ECC Error Address Register */
2700 #define L2CTL0_ERRADDR7             0xFFCA305C         /* L2CTL0 L2 Bank 7 ECC Error Address Register */
2701 #define L2CTL0_ET0                  0xFFCA3080         /* L2CTL0 L2 AXI Error 0 Type Register */
2702 #define L2CTL0_EADDR0               0xFFCA3084         /* L2CTL0 L2 AXI Error 0 Address Register */
2703 #define L2CTL0_ET1                  0xFFCA3088         /* L2CTL0 L2 AXI Error 1 Type Register */
2704 #define L2CTL0_EADDR1               0xFFCA308C         /* L2CTL0 L2 AXI Error 1 Address Register */
2705 
2706 
2707 /* =========================
2708         SEC Registers
2709    ========================= */
2710 /* ------------------------------------------------------------------------------------------------------------------------
2711        SEC Core Interface (SCI) Register Definitions
2712    ------------------------------------------------------------------------------------------------------------------------ */
2713 
2714 #define SEC_SCI_BASE 0xFFCA4400
2715 #define SEC_SCI_OFF 0x40
2716 #define SEC_CCTL 0x0         /* SEC Core Control Register n */
2717 #define SEC_CSTAT 0x4         /* SEC Core Status Register n */
2718 #define SEC_CPND 0x8         /* SEC Core Pending IRQ Register n */
2719 #define SEC_CACT 0xC         /* SEC Core Active IRQ Register n */
2720 #define SEC_CPMSK 0x10         /* SEC Core IRQ Priority Mask Register n */
2721 #define SEC_CGMSK 0x14         /* SEC Core IRQ Group Mask Register n */
2722 #define SEC_CPLVL 0x18         /* SEC Core IRQ Priority Level Register n */
2723 #define SEC_CSID 0x1C         /* SEC Core IRQ Source ID Register n */
2724 
2725 #define bfin_read_SEC_SCI(n, reg) bfin_read32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg)
2726 #define bfin_write_SEC_SCI(n, reg, val) \
2727 	bfin_write32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg, val)
2728 
2729 /* ------------------------------------------------------------------------------------------------------------------------
2730        SEC Fault Management Interface (SFI) Register Definitions
2731    ------------------------------------------------------------------------------------------------------------------------ */
2732 #define SEC_FCTL                   0xFFCA4010         /* SEC Fault Control Register */
2733 #define SEC_FSTAT                  0xFFCA4014         /* SEC Fault Status Register */
2734 #define SEC_FSID                   0xFFCA4018         /* SEC Fault Source ID Register */
2735 #define SEC_FEND                   0xFFCA401C         /* SEC Fault End Register */
2736 #define SEC_FDLY                   0xFFCA4020         /* SEC Fault Delay Register */
2737 #define SEC_FDLY_CUR               0xFFCA4024         /* SEC Fault Delay Current Register */
2738 #define SEC_FSRDLY                 0xFFCA4028         /* SEC Fault System Reset Delay Register */
2739 #define SEC_FSRDLY_CUR             0xFFCA402C         /* SEC Fault System Reset Delay Current Register */
2740 #define SEC_FCOPP                  0xFFCA4030         /* SEC Fault COP Period Register */
2741 #define SEC_FCOPP_CUR              0xFFCA4034         /* SEC Fault COP Period Current Register */
2742 
2743 /* ------------------------------------------------------------------------------------------------------------------------
2744        SEC Global Register Definitions
2745    ------------------------------------------------------------------------------------------------------------------------ */
2746 #define SEC_GCTL                   0xFFCA4000         /* SEC Global Control Register */
2747 #define SEC_GSTAT                  0xFFCA4004         /* SEC Global Status Register */
2748 #define SEC_RAISE                  0xFFCA4008         /* SEC Global Raise Register */
2749 #define SEC_END                    0xFFCA400C         /* SEC Global End Register */
2750 
2751 /* ------------------------------------------------------------------------------------------------------------------------
2752        SEC Source Interface (SSI) Register Definitions
2753    ------------------------------------------------------------------------------------------------------------------------ */
2754 #define SEC_SCTL0                  0xFFCA4800         /* SEC IRQ Source Control Register n */
2755 #define SEC_SCTL1                  0xFFCA4808         /* SEC IRQ Source Control Register n */
2756 #define SEC_SCTL2                  0xFFCA4810         /* SEC IRQ Source Control Register n */
2757 #define SEC_SCTL3                  0xFFCA4818         /* SEC IRQ Source Control Register n */
2758 #define SEC_SCTL4                  0xFFCA4820         /* SEC IRQ Source Control Register n */
2759 #define SEC_SCTL5                  0xFFCA4828         /* SEC IRQ Source Control Register n */
2760 #define SEC_SCTL6                  0xFFCA4830         /* SEC IRQ Source Control Register n */
2761 #define SEC_SCTL7                  0xFFCA4838         /* SEC IRQ Source Control Register n */
2762 #define SEC_SCTL8                  0xFFCA4840         /* SEC IRQ Source Control Register n */
2763 #define SEC_SCTL9                  0xFFCA4848         /* SEC IRQ Source Control Register n */
2764 #define SEC_SCTL10                 0xFFCA4850         /* SEC IRQ Source Control Register n */
2765 #define SEC_SCTL11                 0xFFCA4858         /* SEC IRQ Source Control Register n */
2766 #define SEC_SCTL12                 0xFFCA4860         /* SEC IRQ Source Control Register n */
2767 #define SEC_SCTL13                 0xFFCA4868         /* SEC IRQ Source Control Register n */
2768 #define SEC_SCTL14                 0xFFCA4870         /* SEC IRQ Source Control Register n */
2769 #define SEC_SCTL15                 0xFFCA4878         /* SEC IRQ Source Control Register n */
2770 #define SEC_SCTL16                 0xFFCA4880         /* SEC IRQ Source Control Register n */
2771 #define SEC_SCTL17                 0xFFCA4888         /* SEC IRQ Source Control Register n */
2772 #define SEC_SCTL18                 0xFFCA4890         /* SEC IRQ Source Control Register n */
2773 #define SEC_SCTL19                 0xFFCA4898         /* SEC IRQ Source Control Register n */
2774 #define SEC_SCTL20                 0xFFCA48A0         /* SEC IRQ Source Control Register n */
2775 #define SEC_SCTL21                 0xFFCA48A8         /* SEC IRQ Source Control Register n */
2776 #define SEC_SCTL22                 0xFFCA48B0         /* SEC IRQ Source Control Register n */
2777 #define SEC_SCTL23                 0xFFCA48B8         /* SEC IRQ Source Control Register n */
2778 #define SEC_SCTL24                 0xFFCA48C0         /* SEC IRQ Source Control Register n */
2779 #define SEC_SCTL25                 0xFFCA48C8         /* SEC IRQ Source Control Register n */
2780 #define SEC_SCTL26                 0xFFCA48D0         /* SEC IRQ Source Control Register n */
2781 #define SEC_SCTL27                 0xFFCA48D8         /* SEC IRQ Source Control Register n */
2782 #define SEC_SCTL28                 0xFFCA48E0         /* SEC IRQ Source Control Register n */
2783 #define SEC_SCTL29                 0xFFCA48E8         /* SEC IRQ Source Control Register n */
2784 #define SEC_SCTL30                 0xFFCA48F0         /* SEC IRQ Source Control Register n */
2785 #define SEC_SCTL31                 0xFFCA48F8         /* SEC IRQ Source Control Register n */
2786 #define SEC_SCTL32                 0xFFCA4900         /* SEC IRQ Source Control Register n */
2787 #define SEC_SCTL33                 0xFFCA4908         /* SEC IRQ Source Control Register n */
2788 #define SEC_SCTL34                 0xFFCA4910         /* SEC IRQ Source Control Register n */
2789 #define SEC_SCTL35                 0xFFCA4918         /* SEC IRQ Source Control Register n */
2790 #define SEC_SCTL36                 0xFFCA4920         /* SEC IRQ Source Control Register n */
2791 #define SEC_SCTL37                 0xFFCA4928         /* SEC IRQ Source Control Register n */
2792 #define SEC_SCTL38                 0xFFCA4930         /* SEC IRQ Source Control Register n */
2793 #define SEC_SCTL39                 0xFFCA4938         /* SEC IRQ Source Control Register n */
2794 #define SEC_SCTL40                 0xFFCA4940         /* SEC IRQ Source Control Register n */
2795 #define SEC_SCTL41                 0xFFCA4948         /* SEC IRQ Source Control Register n */
2796 #define SEC_SCTL42                 0xFFCA4950         /* SEC IRQ Source Control Register n */
2797 #define SEC_SCTL43                 0xFFCA4958         /* SEC IRQ Source Control Register n */
2798 #define SEC_SCTL44                 0xFFCA4960         /* SEC IRQ Source Control Register n */
2799 #define SEC_SCTL45                 0xFFCA4968         /* SEC IRQ Source Control Register n */
2800 #define SEC_SCTL46                 0xFFCA4970         /* SEC IRQ Source Control Register n */
2801 #define SEC_SCTL47                 0xFFCA4978         /* SEC IRQ Source Control Register n */
2802 #define SEC_SCTL48                 0xFFCA4980         /* SEC IRQ Source Control Register n */
2803 #define SEC_SCTL49                 0xFFCA4988         /* SEC IRQ Source Control Register n */
2804 #define SEC_SCTL50                 0xFFCA4990         /* SEC IRQ Source Control Register n */
2805 #define SEC_SCTL51                 0xFFCA4998         /* SEC IRQ Source Control Register n */
2806 #define SEC_SCTL52                 0xFFCA49A0         /* SEC IRQ Source Control Register n */
2807 #define SEC_SCTL53                 0xFFCA49A8         /* SEC IRQ Source Control Register n */
2808 #define SEC_SCTL54                 0xFFCA49B0         /* SEC IRQ Source Control Register n */
2809 #define SEC_SCTL55                 0xFFCA49B8         /* SEC IRQ Source Control Register n */
2810 #define SEC_SCTL56                 0xFFCA49C0         /* SEC IRQ Source Control Register n */
2811 #define SEC_SCTL57                 0xFFCA49C8         /* SEC IRQ Source Control Register n */
2812 #define SEC_SCTL58                 0xFFCA49D0         /* SEC IRQ Source Control Register n */
2813 #define SEC_SCTL59                 0xFFCA49D8         /* SEC IRQ Source Control Register n */
2814 #define SEC_SCTL60                 0xFFCA49E0         /* SEC IRQ Source Control Register n */
2815 #define SEC_SCTL61                 0xFFCA49E8         /* SEC IRQ Source Control Register n */
2816 #define SEC_SCTL62                 0xFFCA49F0         /* SEC IRQ Source Control Register n */
2817 #define SEC_SCTL63                 0xFFCA49F8         /* SEC IRQ Source Control Register n */
2818 #define SEC_SCTL64                 0xFFCA4A00         /* SEC IRQ Source Control Register n */
2819 #define SEC_SCTL65                 0xFFCA4A08         /* SEC IRQ Source Control Register n */
2820 #define SEC_SCTL66                 0xFFCA4A10         /* SEC IRQ Source Control Register n */
2821 #define SEC_SCTL67                 0xFFCA4A18         /* SEC IRQ Source Control Register n */
2822 #define SEC_SCTL68                 0xFFCA4A20         /* SEC IRQ Source Control Register n */
2823 #define SEC_SCTL69                 0xFFCA4A28         /* SEC IRQ Source Control Register n */
2824 #define SEC_SCTL70                 0xFFCA4A30         /* SEC IRQ Source Control Register n */
2825 #define SEC_SCTL71                 0xFFCA4A38         /* SEC IRQ Source Control Register n */
2826 #define SEC_SCTL72                 0xFFCA4A40         /* SEC IRQ Source Control Register n */
2827 #define SEC_SCTL73                 0xFFCA4A48         /* SEC IRQ Source Control Register n */
2828 #define SEC_SCTL74                 0xFFCA4A50         /* SEC IRQ Source Control Register n */
2829 #define SEC_SCTL75                 0xFFCA4A58         /* SEC IRQ Source Control Register n */
2830 #define SEC_SCTL76                 0xFFCA4A60         /* SEC IRQ Source Control Register n */
2831 #define SEC_SCTL77                 0xFFCA4A68         /* SEC IRQ Source Control Register n */
2832 #define SEC_SCTL78                 0xFFCA4A70         /* SEC IRQ Source Control Register n */
2833 #define SEC_SCTL79                 0xFFCA4A78         /* SEC IRQ Source Control Register n */
2834 #define SEC_SCTL80                 0xFFCA4A80         /* SEC IRQ Source Control Register n */
2835 #define SEC_SCTL81                 0xFFCA4A88         /* SEC IRQ Source Control Register n */
2836 #define SEC_SCTL82                 0xFFCA4A90         /* SEC IRQ Source Control Register n */
2837 #define SEC_SCTL83                 0xFFCA4A98         /* SEC IRQ Source Control Register n */
2838 #define SEC_SCTL84                 0xFFCA4AA0         /* SEC IRQ Source Control Register n */
2839 #define SEC_SCTL85                 0xFFCA4AA8         /* SEC IRQ Source Control Register n */
2840 #define SEC_SCTL86                 0xFFCA4AB0         /* SEC IRQ Source Control Register n */
2841 #define SEC_SCTL87                 0xFFCA4AB8         /* SEC IRQ Source Control Register n */
2842 #define SEC_SCTL88                 0xFFCA4AC0         /* SEC IRQ Source Control Register n */
2843 #define SEC_SCTL89                 0xFFCA4AC8         /* SEC IRQ Source Control Register n */
2844 #define SEC_SCTL90                 0xFFCA4AD0         /* SEC IRQ Source Control Register n */
2845 #define SEC_SCTL91                 0xFFCA4AD8         /* SEC IRQ Source Control Register n */
2846 #define SEC_SCTL92                 0xFFCA4AE0         /* SEC IRQ Source Control Register n */
2847 #define SEC_SCTL93                 0xFFCA4AE8         /* SEC IRQ Source Control Register n */
2848 #define SEC_SCTL94                 0xFFCA4AF0         /* SEC IRQ Source Control Register n */
2849 #define SEC_SCTL95                 0xFFCA4AF8         /* SEC IRQ Source Control Register n */
2850 #define SEC_SCTL96                 0xFFCA4B00         /* SEC IRQ Source Control Register n */
2851 #define SEC_SCTL97                 0xFFCA4B08         /* SEC IRQ Source Control Register n */
2852 #define SEC_SCTL98                 0xFFCA4B10         /* SEC IRQ Source Control Register n */
2853 #define SEC_SCTL99                 0xFFCA4B18         /* SEC IRQ Source Control Register n */
2854 #define SEC_SCTL100                0xFFCA4B20         /* SEC IRQ Source Control Register n */
2855 #define SEC_SCTL101                0xFFCA4B28         /* SEC IRQ Source Control Register n */
2856 #define SEC_SCTL102                0xFFCA4B30         /* SEC IRQ Source Control Register n */
2857 #define SEC_SCTL103                0xFFCA4B38         /* SEC IRQ Source Control Register n */
2858 #define SEC_SCTL104                0xFFCA4B40         /* SEC IRQ Source Control Register n */
2859 #define SEC_SCTL105                0xFFCA4B48         /* SEC IRQ Source Control Register n */
2860 #define SEC_SCTL106                0xFFCA4B50         /* SEC IRQ Source Control Register n */
2861 #define SEC_SCTL107                0xFFCA4B58         /* SEC IRQ Source Control Register n */
2862 #define SEC_SCTL108                0xFFCA4B60         /* SEC IRQ Source Control Register n */
2863 #define SEC_SCTL109                0xFFCA4B68         /* SEC IRQ Source Control Register n */
2864 #define SEC_SCTL110                0xFFCA4B70         /* SEC IRQ Source Control Register n */
2865 #define SEC_SCTL111                0xFFCA4B78         /* SEC IRQ Source Control Register n */
2866 #define SEC_SCTL112                0xFFCA4B80         /* SEC IRQ Source Control Register n */
2867 #define SEC_SCTL113                0xFFCA4B88         /* SEC IRQ Source Control Register n */
2868 #define SEC_SCTL114                0xFFCA4B90         /* SEC IRQ Source Control Register n */
2869 #define SEC_SCTL115                0xFFCA4B98         /* SEC IRQ Source Control Register n */
2870 #define SEC_SCTL116                0xFFCA4BA0         /* SEC IRQ Source Control Register n */
2871 #define SEC_SCTL117                0xFFCA4BA8         /* SEC IRQ Source Control Register n */
2872 #define SEC_SCTL118                0xFFCA4BB0         /* SEC IRQ Source Control Register n */
2873 #define SEC_SCTL119                0xFFCA4BB8         /* SEC IRQ Source Control Register n */
2874 #define SEC_SCTL120                0xFFCA4BC0         /* SEC IRQ Source Control Register n */
2875 #define SEC_SCTL121                0xFFCA4BC8         /* SEC IRQ Source Control Register n */
2876 #define SEC_SCTL122                0xFFCA4BD0         /* SEC IRQ Source Control Register n */
2877 #define SEC_SCTL123                0xFFCA4BD8         /* SEC IRQ Source Control Register n */
2878 #define SEC_SCTL124                0xFFCA4BE0         /* SEC IRQ Source Control Register n */
2879 #define SEC_SCTL125                0xFFCA4BE8         /* SEC IRQ Source Control Register n */
2880 #define SEC_SCTL126                0xFFCA4BF0         /* SEC IRQ Source Control Register n */
2881 #define SEC_SCTL127                0xFFCA4BF8         /* SEC IRQ Source Control Register n */
2882 #define SEC_SCTL128                0xFFCA4C00         /* SEC IRQ Source Control Register n */
2883 #define SEC_SCTL129                0xFFCA4C08         /* SEC IRQ Source Control Register n */
2884 #define SEC_SCTL130                0xFFCA4C10         /* SEC IRQ Source Control Register n */
2885 #define SEC_SCTL131                0xFFCA4C18         /* SEC IRQ Source Control Register n */
2886 #define SEC_SCTL132                0xFFCA4C20         /* SEC IRQ Source Control Register n */
2887 #define SEC_SCTL133                0xFFCA4C28         /* SEC IRQ Source Control Register n */
2888 #define SEC_SCTL134                0xFFCA4C30         /* SEC IRQ Source Control Register n */
2889 #define SEC_SCTL135                0xFFCA4C38         /* SEC IRQ Source Control Register n */
2890 #define SEC_SCTL136                0xFFCA4C40         /* SEC IRQ Source Control Register n */
2891 #define SEC_SCTL137                0xFFCA4C48         /* SEC IRQ Source Control Register n */
2892 #define SEC_SCTL138                0xFFCA4C50         /* SEC IRQ Source Control Register n */
2893 #define SEC_SCTL139                0xFFCA4C58         /* SEC IRQ Source Control Register n */
2894 #define SEC_SSTAT0                 0xFFCA4804         /* SEC IRQ Source Status Register n */
2895 #define SEC_SSTAT1                 0xFFCA480C         /* SEC IRQ Source Status Register n */
2896 #define SEC_SSTAT2                 0xFFCA4814         /* SEC IRQ Source Status Register n */
2897 #define SEC_SSTAT3                 0xFFCA481C         /* SEC IRQ Source Status Register n */
2898 #define SEC_SSTAT4                 0xFFCA4824         /* SEC IRQ Source Status Register n */
2899 #define SEC_SSTAT5                 0xFFCA482C         /* SEC IRQ Source Status Register n */
2900 #define SEC_SSTAT6                 0xFFCA4834         /* SEC IRQ Source Status Register n */
2901 #define SEC_SSTAT7                 0xFFCA483C         /* SEC IRQ Source Status Register n */
2902 #define SEC_SSTAT8                 0xFFCA4844         /* SEC IRQ Source Status Register n */
2903 #define SEC_SSTAT9                 0xFFCA484C         /* SEC IRQ Source Status Register n */
2904 #define SEC_SSTAT10                0xFFCA4854         /* SEC IRQ Source Status Register n */
2905 #define SEC_SSTAT11                0xFFCA485C         /* SEC IRQ Source Status Register n */
2906 #define SEC_SSTAT12                0xFFCA4864         /* SEC IRQ Source Status Register n */
2907 #define SEC_SSTAT13                0xFFCA486C         /* SEC IRQ Source Status Register n */
2908 #define SEC_SSTAT14                0xFFCA4874         /* SEC IRQ Source Status Register n */
2909 #define SEC_SSTAT15                0xFFCA487C         /* SEC IRQ Source Status Register n */
2910 #define SEC_SSTAT16                0xFFCA4884         /* SEC IRQ Source Status Register n */
2911 #define SEC_SSTAT17                0xFFCA488C         /* SEC IRQ Source Status Register n */
2912 #define SEC_SSTAT18                0xFFCA4894         /* SEC IRQ Source Status Register n */
2913 #define SEC_SSTAT19                0xFFCA489C         /* SEC IRQ Source Status Register n */
2914 #define SEC_SSTAT20                0xFFCA48A4         /* SEC IRQ Source Status Register n */
2915 #define SEC_SSTAT21                0xFFCA48AC         /* SEC IRQ Source Status Register n */
2916 #define SEC_SSTAT22                0xFFCA48B4         /* SEC IRQ Source Status Register n */
2917 #define SEC_SSTAT23                0xFFCA48BC         /* SEC IRQ Source Status Register n */
2918 #define SEC_SSTAT24                0xFFCA48C4         /* SEC IRQ Source Status Register n */
2919 #define SEC_SSTAT25                0xFFCA48CC         /* SEC IRQ Source Status Register n */
2920 #define SEC_SSTAT26                0xFFCA48D4         /* SEC IRQ Source Status Register n */
2921 #define SEC_SSTAT27                0xFFCA48DC         /* SEC IRQ Source Status Register n */
2922 #define SEC_SSTAT28                0xFFCA48E4         /* SEC IRQ Source Status Register n */
2923 #define SEC_SSTAT29                0xFFCA48EC         /* SEC IRQ Source Status Register n */
2924 #define SEC_SSTAT30                0xFFCA48F4         /* SEC IRQ Source Status Register n */
2925 #define SEC_SSTAT31                0xFFCA48FC         /* SEC IRQ Source Status Register n */
2926 #define SEC_SSTAT32                0xFFCA4904         /* SEC IRQ Source Status Register n */
2927 #define SEC_SSTAT33                0xFFCA490C         /* SEC IRQ Source Status Register n */
2928 #define SEC_SSTAT34                0xFFCA4914         /* SEC IRQ Source Status Register n */
2929 #define SEC_SSTAT35                0xFFCA491C         /* SEC IRQ Source Status Register n */
2930 #define SEC_SSTAT36                0xFFCA4924         /* SEC IRQ Source Status Register n */
2931 #define SEC_SSTAT37                0xFFCA492C         /* SEC IRQ Source Status Register n */
2932 #define SEC_SSTAT38                0xFFCA4934         /* SEC IRQ Source Status Register n */
2933 #define SEC_SSTAT39                0xFFCA493C         /* SEC IRQ Source Status Register n */
2934 #define SEC_SSTAT40                0xFFCA4944         /* SEC IRQ Source Status Register n */
2935 #define SEC_SSTAT41                0xFFCA494C         /* SEC IRQ Source Status Register n */
2936 #define SEC_SSTAT42                0xFFCA4954         /* SEC IRQ Source Status Register n */
2937 #define SEC_SSTAT43                0xFFCA495C         /* SEC IRQ Source Status Register n */
2938 #define SEC_SSTAT44                0xFFCA4964         /* SEC IRQ Source Status Register n */
2939 #define SEC_SSTAT45                0xFFCA496C         /* SEC IRQ Source Status Register n */
2940 #define SEC_SSTAT46                0xFFCA4974         /* SEC IRQ Source Status Register n */
2941 #define SEC_SSTAT47                0xFFCA497C         /* SEC IRQ Source Status Register n */
2942 #define SEC_SSTAT48                0xFFCA4984         /* SEC IRQ Source Status Register n */
2943 #define SEC_SSTAT49                0xFFCA498C         /* SEC IRQ Source Status Register n */
2944 #define SEC_SSTAT50                0xFFCA4994         /* SEC IRQ Source Status Register n */
2945 #define SEC_SSTAT51                0xFFCA499C         /* SEC IRQ Source Status Register n */
2946 #define SEC_SSTAT52                0xFFCA49A4         /* SEC IRQ Source Status Register n */
2947 #define SEC_SSTAT53                0xFFCA49AC         /* SEC IRQ Source Status Register n */
2948 #define SEC_SSTAT54                0xFFCA49B4         /* SEC IRQ Source Status Register n */
2949 #define SEC_SSTAT55                0xFFCA49BC         /* SEC IRQ Source Status Register n */
2950 #define SEC_SSTAT56                0xFFCA49C4         /* SEC IRQ Source Status Register n */
2951 #define SEC_SSTAT57                0xFFCA49CC         /* SEC IRQ Source Status Register n */
2952 #define SEC_SSTAT58                0xFFCA49D4         /* SEC IRQ Source Status Register n */
2953 #define SEC_SSTAT59                0xFFCA49DC         /* SEC IRQ Source Status Register n */
2954 #define SEC_SSTAT60                0xFFCA49E4         /* SEC IRQ Source Status Register n */
2955 #define SEC_SSTAT61                0xFFCA49EC         /* SEC IRQ Source Status Register n */
2956 #define SEC_SSTAT62                0xFFCA49F4         /* SEC IRQ Source Status Register n */
2957 #define SEC_SSTAT63                0xFFCA49FC         /* SEC IRQ Source Status Register n */
2958 #define SEC_SSTAT64                0xFFCA4A04         /* SEC IRQ Source Status Register n */
2959 #define SEC_SSTAT65                0xFFCA4A0C         /* SEC IRQ Source Status Register n */
2960 #define SEC_SSTAT66                0xFFCA4A14         /* SEC IRQ Source Status Register n */
2961 #define SEC_SSTAT67                0xFFCA4A1C         /* SEC IRQ Source Status Register n */
2962 #define SEC_SSTAT68                0xFFCA4A24         /* SEC IRQ Source Status Register n */
2963 #define SEC_SSTAT69                0xFFCA4A2C         /* SEC IRQ Source Status Register n */
2964 #define SEC_SSTAT70                0xFFCA4A34         /* SEC IRQ Source Status Register n */
2965 #define SEC_SSTAT71                0xFFCA4A3C         /* SEC IRQ Source Status Register n */
2966 #define SEC_SSTAT72                0xFFCA4A44         /* SEC IRQ Source Status Register n */
2967 #define SEC_SSTAT73                0xFFCA4A4C         /* SEC IRQ Source Status Register n */
2968 #define SEC_SSTAT74                0xFFCA4A54         /* SEC IRQ Source Status Register n */
2969 #define SEC_SSTAT75                0xFFCA4A5C         /* SEC IRQ Source Status Register n */
2970 #define SEC_SSTAT76                0xFFCA4A64         /* SEC IRQ Source Status Register n */
2971 #define SEC_SSTAT77                0xFFCA4A6C         /* SEC IRQ Source Status Register n */
2972 #define SEC_SSTAT78                0xFFCA4A74         /* SEC IRQ Source Status Register n */
2973 #define SEC_SSTAT79                0xFFCA4A7C         /* SEC IRQ Source Status Register n */
2974 #define SEC_SSTAT80                0xFFCA4A84         /* SEC IRQ Source Status Register n */
2975 #define SEC_SSTAT81                0xFFCA4A8C         /* SEC IRQ Source Status Register n */
2976 #define SEC_SSTAT82                0xFFCA4A94         /* SEC IRQ Source Status Register n */
2977 #define SEC_SSTAT83                0xFFCA4A9C         /* SEC IRQ Source Status Register n */
2978 #define SEC_SSTAT84                0xFFCA4AA4         /* SEC IRQ Source Status Register n */
2979 #define SEC_SSTAT85                0xFFCA4AAC         /* SEC IRQ Source Status Register n */
2980 #define SEC_SSTAT86                0xFFCA4AB4         /* SEC IRQ Source Status Register n */
2981 #define SEC_SSTAT87                0xFFCA4ABC         /* SEC IRQ Source Status Register n */
2982 #define SEC_SSTAT88                0xFFCA4AC4         /* SEC IRQ Source Status Register n */
2983 #define SEC_SSTAT89                0xFFCA4ACC         /* SEC IRQ Source Status Register n */
2984 #define SEC_SSTAT90                0xFFCA4AD4         /* SEC IRQ Source Status Register n */
2985 #define SEC_SSTAT91                0xFFCA4ADC         /* SEC IRQ Source Status Register n */
2986 #define SEC_SSTAT92                0xFFCA4AE4         /* SEC IRQ Source Status Register n */
2987 #define SEC_SSTAT93                0xFFCA4AEC         /* SEC IRQ Source Status Register n */
2988 #define SEC_SSTAT94                0xFFCA4AF4         /* SEC IRQ Source Status Register n */
2989 #define SEC_SSTAT95                0xFFCA4AFC         /* SEC IRQ Source Status Register n */
2990 #define SEC_SSTAT96                0xFFCA4B04         /* SEC IRQ Source Status Register n */
2991 #define SEC_SSTAT97                0xFFCA4B0C         /* SEC IRQ Source Status Register n */
2992 #define SEC_SSTAT98                0xFFCA4B14         /* SEC IRQ Source Status Register n */
2993 #define SEC_SSTAT99                0xFFCA4B1C         /* SEC IRQ Source Status Register n */
2994 #define SEC_SSTAT100               0xFFCA4B24         /* SEC IRQ Source Status Register n */
2995 #define SEC_SSTAT101               0xFFCA4B2C         /* SEC IRQ Source Status Register n */
2996 #define SEC_SSTAT102               0xFFCA4B34         /* SEC IRQ Source Status Register n */
2997 #define SEC_SSTAT103               0xFFCA4B3C         /* SEC IRQ Source Status Register n */
2998 #define SEC_SSTAT104               0xFFCA4B44         /* SEC IRQ Source Status Register n */
2999 #define SEC_SSTAT105               0xFFCA4B4C         /* SEC IRQ Source Status Register n */
3000 #define SEC_SSTAT106               0xFFCA4B54         /* SEC IRQ Source Status Register n */
3001 #define SEC_SSTAT107               0xFFCA4B5C         /* SEC IRQ Source Status Register n */
3002 #define SEC_SSTAT108               0xFFCA4B64         /* SEC IRQ Source Status Register n */
3003 #define SEC_SSTAT109               0xFFCA4B6C         /* SEC IRQ Source Status Register n */
3004 #define SEC_SSTAT110               0xFFCA4B74         /* SEC IRQ Source Status Register n */
3005 #define SEC_SSTAT111               0xFFCA4B7C         /* SEC IRQ Source Status Register n */
3006 #define SEC_SSTAT112               0xFFCA4B84         /* SEC IRQ Source Status Register n */
3007 #define SEC_SSTAT113               0xFFCA4B8C         /* SEC IRQ Source Status Register n */
3008 #define SEC_SSTAT114               0xFFCA4B94         /* SEC IRQ Source Status Register n */
3009 #define SEC_SSTAT115               0xFFCA4B9C         /* SEC IRQ Source Status Register n */
3010 #define SEC_SSTAT116               0xFFCA4BA4         /* SEC IRQ Source Status Register n */
3011 #define SEC_SSTAT117               0xFFCA4BAC         /* SEC IRQ Source Status Register n */
3012 #define SEC_SSTAT118               0xFFCA4BB4         /* SEC IRQ Source Status Register n */
3013 #define SEC_SSTAT119               0xFFCA4BBC         /* SEC IRQ Source Status Register n */
3014 #define SEC_SSTAT120               0xFFCA4BC4         /* SEC IRQ Source Status Register n */
3015 #define SEC_SSTAT121               0xFFCA4BCC         /* SEC IRQ Source Status Register n */
3016 #define SEC_SSTAT122               0xFFCA4BD4         /* SEC IRQ Source Status Register n */
3017 #define SEC_SSTAT123               0xFFCA4BDC         /* SEC IRQ Source Status Register n */
3018 #define SEC_SSTAT124               0xFFCA4BE4         /* SEC IRQ Source Status Register n */
3019 #define SEC_SSTAT125               0xFFCA4BEC         /* SEC IRQ Source Status Register n */
3020 #define SEC_SSTAT126               0xFFCA4BF4         /* SEC IRQ Source Status Register n */
3021 #define SEC_SSTAT127               0xFFCA4BFC         /* SEC IRQ Source Status Register n */
3022 #define SEC_SSTAT128               0xFFCA4C04         /* SEC IRQ Source Status Register n */
3023 #define SEC_SSTAT129               0xFFCA4C0C         /* SEC IRQ Source Status Register n */
3024 #define SEC_SSTAT130               0xFFCA4C14         /* SEC IRQ Source Status Register n */
3025 #define SEC_SSTAT131               0xFFCA4C1C         /* SEC IRQ Source Status Register n */
3026 #define SEC_SSTAT132               0xFFCA4C24         /* SEC IRQ Source Status Register n */
3027 #define SEC_SSTAT133               0xFFCA4C2C         /* SEC IRQ Source Status Register n */
3028 #define SEC_SSTAT134               0xFFCA4C34         /* SEC IRQ Source Status Register n */
3029 #define SEC_SSTAT135               0xFFCA4C3C         /* SEC IRQ Source Status Register n */
3030 #define SEC_SSTAT136               0xFFCA4C44         /* SEC IRQ Source Status Register n */
3031 #define SEC_SSTAT137               0xFFCA4C4C         /* SEC IRQ Source Status Register n */
3032 #define SEC_SSTAT138               0xFFCA4C54         /* SEC IRQ Source Status Register n */
3033 #define SEC_SSTAT139               0xFFCA4C5C         /* SEC IRQ Source Status Register n */
3034 
3035 /* ------------------------------------------------------------------------------------------------------------------------
3036         SEC_CCTL                             Pos/Masks     Description
3037    ------------------------------------------------------------------------------------------------------------------------ */
3038 #define SEC_CCTL_LOCK                   0x80000000    /* LOCK: Lock */
3039 #define SEC_CCTL_NMI_EN                 0x00010000    /* NMIEN: Enable */
3040 #define SEC_CCTL_WAITIDLE               0x00001000    /* WFI: Wait for Idle */
3041 #define SEC_CCTL_RESET                  0x00000002    /* RESET: Reset */
3042 #define SEC_CCTL_EN                     0x00000001    /* EN: Enable */
3043 
3044 /* ------------------------------------------------------------------------------------------------------------------------
3045         SEC_CSTAT                            Pos/Masks     Description
3046    ------------------------------------------------------------------------------------------------------------------------ */
3047 #define SEC_CSTAT_NMI                   0x00010000    /* NMI Status */
3048 #define SEC_CSTAT_WAITING               0x00001000    /* WFI: Waiting */
3049 #define SEC_CSTAT_VALID_SID             0x00000400    /* SIDV: Valid */
3050 #define SEC_CSTAT_VALID_ACT             0x00000200    /* ACTV: Valid */
3051 #define SEC_CSTAT_VALID_PND             0x00000100    /* PNDV: Valid */
3052 #define SEC_CSTAT_ERRC                  0x00000030    /* Error Cause */
3053 #define SEC_CSTAT_ACKERR                0x00000010    /* ERRC: Acknowledge Error */
3054 #define SEC_CSTAT_ERR                   0x00000002    /* ERR: Error Occurred */
3055 
3056 /* ------------------------------------------------------------------------------------------------------------------------
3057         SEC_CPND                             Pos/Masks     Description
3058    ------------------------------------------------------------------------------------------------------------------------ */
3059 #define SEC_CPND_PRIO                   0x0000FF00    /* Highest Pending IRQ Priority */
3060 #define SEC_CPND_SID                    0x000000FF    /* Highest Pending IRQ Source ID */
3061 
3062 /* ------------------------------------------------------------------------------------------------------------------------
3063         SEC_CACT                             Pos/Masks     Description
3064    ------------------------------------------------------------------------------------------------------------------------ */
3065 #define SEC_CACT_PRIO                   0x0000FF00    /* Highest Active IRQ Priority */
3066 #define SEC_CACT_SID                    0x000000FF    /* Highest Active IRQ Source ID */
3067 
3068 /* ------------------------------------------------------------------------------------------------------------------------
3069         SEC_CPMSK                            Pos/Masks     Description
3070    ------------------------------------------------------------------------------------------------------------------------ */
3071 #define SEC_CPMSK_LOCK                  0x80000000    /* LOCK: Lock */
3072 #define SEC_CPMSK_PRIO                  0x000000FF    /* IRQ Priority Mask */
3073 
3074 /* ------------------------------------------------------------------------------------------------------------------------
3075         SEC_CGMSK                            Pos/Masks     Description
3076    ------------------------------------------------------------------------------------------------------------------------ */
3077 #define SEC_CGMSK_LOCK                  0x80000000    /* LOCK: Lock */
3078 #define SEC_CGMSK_MASK                  0x00000100    /* UGRP: Mask Ungrouped Sources */
3079 #define SEC_CGMSK_GRP                   0x0000000F    /* Grouped Mask */
3080 
3081 /* ------------------------------------------------------------------------------------------------------------------------
3082         SEC_CPLVL                            Pos/Masks     Description
3083    ------------------------------------------------------------------------------------------------------------------------ */
3084 #define SEC_CPLVL_LOCK                  0x80000000    /* LOCK: Lock */
3085 #define SEC_CPLVL_PLVL                  0x00000007    /* Priority Levels */
3086 
3087 /* ------------------------------------------------------------------------------------------------------------------------
3088         SEC_CSID                             Pos/Masks     Description
3089    ------------------------------------------------------------------------------------------------------------------------ */
3090 #define SEC_CSID_SID                    0x000000FF    /* Source ID */
3091 
3092 
3093 /* ------------------------------------------------------------------------------------------------------------------------
3094         SEC_FCTL                             Pos/Masks     Description
3095    ------------------------------------------------------------------------------------------------------------------------ */
3096 #define SEC_FCTL_LOCK                   0x80000000    /* LOCK: Lock */
3097 #define SEC_FCTL_FLTPND_MODE            0x00002000    /* TES: Fault Pending Mode */
3098 #define SEC_FCTL_COP_MODE               0x00001000    /* CMS: COP Mode */
3099 #define SEC_FCTL_FLTIN_EN               0x00000080    /* FIEN: Enable */
3100 #define SEC_FCTL_SYSRST_EN              0x00000040    /* SREN: Enable */
3101 #define SEC_FCTL_TRGOUT_EN              0x00000020    /* TOEN: Enable */
3102 #define SEC_FCTL_FLTOUT_EN              0x00000010    /* FOEN: Enable */
3103 #define SEC_FCTL_RESET                  0x00000002    /* RESET: Reset */
3104 #define SEC_FCTL_EN                     0x00000001    /* EN: Enable */
3105 
3106 /* ------------------------------------------------------------------------------------------------------------------------
3107         SEC_FSTAT                            Pos/Masks     Description
3108    ------------------------------------------------------------------------------------------------------------------------ */
3109 #define SEC_FSTAT_NXTFLT                0x00000400    /* NPND: Pending */
3110 #define SEC_FSTAT_FLTACT                0x00000200    /* ACT: Active Fault */
3111 #define SEC_FSTAT_FLTPND                0x00000100    /* PND: Pending */
3112 #define SEC_FSTAT_ERRC                  0x00000030    /* Error Cause */
3113 #define SEC_FSTAT_ENDERR                0x00000020    /* ERRC: End Error */
3114 #define SEC_FSTAT_ERR                   0x00000002    /* ERR: Error Occurred */
3115 
3116 /* ------------------------------------------------------------------------------------------------------------------------
3117         SEC_FSID                             Pos/Masks     Description
3118    ------------------------------------------------------------------------------------------------------------------------ */
3119 #define SEC_FSID_SRC_EXTFLT             0x00010000    /* FEXT: Fault External */
3120 #define SEC_FSID_SID                    0x000000FF    /* Source ID */
3121 
3122 /* ------------------------------------------------------------------------------------------------------------------------
3123         SEC_FEND                             Pos/Masks     Description
3124    ------------------------------------------------------------------------------------------------------------------------ */
3125 #define SEC_FEND_END_EXTFLT             0x00010000    /* FEXT: Fault External */
3126 #define SEC_FEND_SID                    0x000000FF    /* Source ID */
3127 
3128 
3129 /* ------------------------------------------------------------------------------------------------------------------------
3130         SEC_GCTL                             Pos/Masks     Description
3131    ------------------------------------------------------------------------------------------------------------------------ */
3132 #define SEC_GCTL_LOCK                   0x80000000    /* Lock */
3133 #define SEC_GCTL_RESET                  0x00000002    /* Reset */
3134 #define SEC_GCTL_EN                     0x00000001    /* Enable */
3135 
3136 /* ------------------------------------------------------------------------------------------------------------------------
3137         SEC_GSTAT                            Pos/Masks     Description
3138    ------------------------------------------------------------------------------------------------------------------------ */
3139 #define SEC_GSTAT_LWERR                 0x80000000    /* LWERR: Error Occurred */
3140 #define SEC_GSTAT_ADRERR                0x40000000    /* ADRERR: Error Occurred */
3141 #define SEC_GSTAT_SID                   0x00FF0000    /* Source ID for SSI Error */
3142 #define SEC_GSTAT_SCI                   0x00000F00    /* SCI ID for SCI Error */
3143 #define SEC_GSTAT_ERRC                  0x00000030    /* Error Cause */
3144 #define SEC_GSTAT_SCIERR                0x00000010    /* ERRC: SCI Error */
3145 #define SEC_GSTAT_SSIERR                0x00000020    /* ERRC: SSI Error */
3146 #define SEC_GSTAT_ERR                   0x00000002    /* ERR: Error Occurred */
3147 
3148 /* ------------------------------------------------------------------------------------------------------------------------
3149         SEC_RAISE                            Pos/Masks     Description
3150    ------------------------------------------------------------------------------------------------------------------------ */
3151 #define SEC_RAISE_SID                   0x000000FF    /* Source ID IRQ Set to Pending */
3152 
3153 /* ------------------------------------------------------------------------------------------------------------------------
3154         SEC_END                              Pos/Masks     Description
3155    ------------------------------------------------------------------------------------------------------------------------ */
3156 #define SEC_END_SID                     0x000000FF    /* Source ID IRQ to End */
3157 
3158 
3159 /* ------------------------------------------------------------------------------------------------------------------------
3160         SEC_SCTL                             Pos/Masks     Description
3161    ------------------------------------------------------------------------------------------------------------------------ */
3162 #define SEC_SCTL_LOCK                   0x80000000    /* Lock */
3163 #define SEC_SCTL_CTG                    0x0F000000    /* Core Target Select */
3164 #define SEC_SCTL_GRP                    0x000F0000    /* Group Select */
3165 #define SEC_SCTL_PRIO                   0x0000FF00    /* Priority Level Select */
3166 #define SEC_SCTL_ERR_EN                 0x00000010    /* ERREN: Enable */
3167 #define SEC_SCTL_EDGE                   0x00000008    /* ES: Edge Sensitive */
3168 #define SEC_SCTL_SRC_EN                 0x00000004    /* SEN: Enable */
3169 #define SEC_SCTL_FAULT_EN               0x00000002    /* FEN: Enable */
3170 #define SEC_SCTL_INT_EN                 0x00000001    /* IEN: Enable */
3171 
3172 /* ------------------------------------------------------------------------------------------------------------------------
3173         SEC_SSTAT                            Pos/Masks     Description
3174    ------------------------------------------------------------------------------------------------------------------------ */
3175 #define SEC_SSTAT_CHID                  0x00FF0000    /* Channel ID */
3176 #define SEC_SSTAT_ACTIVE_SRC            0x00000200    /* ACT: Active Source */
3177 #define SEC_SSTAT_PENDING               0x00000100    /* PND: Pending */
3178 #define SEC_SSTAT_ERRC                  0x00000030    /* Error Cause */
3179 #define SEC_SSTAT_ENDERR                0x00000020    /* ERRC: End Error */
3180 #define SEC_SSTAT_ERR                   0x00000002    /* Error */
3181 
3182 
3183 /* =========================
3184         RCU Registers
3185    ========================= */
3186 
3187 /* =========================
3188         RCU0
3189    ========================= */
3190 #define RCU0_CTL                    0xFFCA6000         /* RCU0 Control Register */
3191 #define RCU0_STAT                   0xFFCA6004         /* RCU0 Status Register */
3192 #define RCU0_CRCTL                  0xFFCA6008         /* RCU0 Core Reset Control Register */
3193 #define RCU0_CRSTAT                 0xFFCA600C         /* RCU0 Core Reset Status Register */
3194 #define RCU0_SIDIS                  0xFFCA6010         /* RCU0 System Interface Disable Register */
3195 #define RCU0_SISTAT                 0xFFCA6014         /* RCU0 System Interface Status Register */
3196 #define RCU0_SVECT_LCK              0xFFCA6018         /* RCU0 SVECT Lock Register */
3197 #define RCU0_BCODE                  0xFFCA601C         /* RCU0 Boot Code Register */
3198 #define RCU0_SVECT0                 0xFFCA6020         /* RCU0 Software Vector Register n */
3199 #define RCU0_SVECT1                 0xFFCA6024         /* RCU0 Software Vector Register n */
3200 
3201 
3202 /* =========================
3203         CGU0
3204    ========================= */
3205 #define CGU0_CTL                    0xFFCA8000         /* CGU0 Control Register */
3206 #define CGU0_STAT                   0xFFCA8004         /* CGU0 Status Register */
3207 #define CGU0_DIV                    0xFFCA8008         /* CGU0 Divisor Register */
3208 #define CGU0_CLKOUTSEL              0xFFCA800C         /* CGU0 CLKOUT Select Register */
3209 
3210 
3211 /* =========================
3212         DPM Registers
3213    ========================= */
3214 
3215 /* =========================
3216         DPM0
3217    ========================= */
3218 #define DPM0_CTL                    0xFFCA9000         /* DPM0 Control Register */
3219 #define DPM0_STAT                   0xFFCA9004         /* DPM0 Status Register */
3220 #define DPM0_CCBF_DIS               0xFFCA9008         /* DPM0 Core Clock Buffer Disable Register */
3221 #define DPM0_CCBF_EN                0xFFCA900C         /* DPM0 Core Clock Buffer Enable Register */
3222 #define DPM0_CCBF_STAT              0xFFCA9010         /* DPM0 Core Clock Buffer Status Register */
3223 #define DPM0_CCBF_STAT_STKY         0xFFCA9014         /* DPM0 Core Clock Buffer Status Sticky Register */
3224 #define DPM0_SCBF_DIS               0xFFCA9018         /* DPM0 System Clock Buffer Disable Register */
3225 #define DPM0_WAKE_EN                0xFFCA901C         /* DPM0 Wakeup Enable Register */
3226 #define DPM0_WAKE_POL               0xFFCA9020         /* DPM0 Wakeup Polarity Register */
3227 #define DPM0_WAKE_STAT              0xFFCA9024         /* DPM0 Wakeup Status Register */
3228 #define DPM0_HIB_DIS                0xFFCA9028         /* DPM0 Hibernate Disable Register */
3229 #define DPM0_PGCNTR                 0xFFCA902C         /* DPM0 Power Good Counter Register */
3230 #define DPM0_RESTORE0               0xFFCA9030         /* DPM0 Restore Register */
3231 #define DPM0_RESTORE1               0xFFCA9034         /* DPM0 Restore Register */
3232 #define DPM0_RESTORE2               0xFFCA9038         /* DPM0 Restore Register */
3233 #define DPM0_RESTORE3               0xFFCA903C         /* DPM0 Restore Register */
3234 #define DPM0_RESTORE4               0xFFCA9040         /* DPM0 Restore Register */
3235 #define DPM0_RESTORE5               0xFFCA9044         /* DPM0 Restore Register */
3236 #define DPM0_RESTORE6               0xFFCA9048         /* DPM0 Restore Register */
3237 #define DPM0_RESTORE7               0xFFCA904C         /* DPM0 Restore Register */
3238 #define DPM0_RESTORE8               0xFFCA9050         /* DPM0 Restore Register */
3239 #define DPM0_RESTORE9               0xFFCA9054         /* DPM0 Restore Register */
3240 #define DPM0_RESTORE10              0xFFCA9058         /* DPM0 Restore Register */
3241 #define DPM0_RESTORE11              0xFFCA905C         /* DPM0 Restore Register */
3242 #define DPM0_RESTORE12              0xFFCA9060         /* DPM0 Restore Register */
3243 #define DPM0_RESTORE13              0xFFCA9064         /* DPM0 Restore Register */
3244 #define DPM0_RESTORE14              0xFFCA9068         /* DPM0 Restore Register */
3245 #define DPM0_RESTORE15              0xFFCA906C         /* DPM0 Restore Register */
3246 
3247 
3248 /* =========================
3249         DBG Registers
3250    ========================= */
3251 
3252 /* USB register */
3253 #define USB_FADDR                  0xFFCC1000         /* USB Device Address in Peripheral Mode */
3254 #define USB_POWER                  0xFFCC1001         /* USB Power and Device Control */
3255 #define USB_INTRTX                 0xFFCC1002         /* USB Transmit Interrupt */
3256 #define USB_INTRRX                 0xFFCC1004         /* USB Receive Interrupts */
3257 #define USB_INTRTXE                0xFFCC1006         /* USB Transmit Interrupt Enable */
3258 #define USB_INTRRXE                0xFFCC1008         /* USB Receive Interrupt Enable */
3259 #define USB_INTRUSB                    0xFFCC100A         /* USB USB Interrupts */
3260 #define USB_INTRUSBE                    0xFFCC100B         /* USB USB Interrupt Enable */
3261 #define USB_FRAME                  0xFFCC100C         /* USB Frame Number */
3262 #define USB_INDEX                  0xFFCC100E         /* USB Index */
3263 #define USB_TESTMODE               0xFFCC100F         /* USB Testmodes */
3264 #define USB_EPI_TXMAXP0            0xFFCC1010         /* USB Transmit Maximum Packet Length */
3265 #define USB_EP_NI0_TXMAXP          0xFFCC1010
3266 #define USB_EP0I_CSR0_H            0xFFCC1012         /* USB Config and Status EP0 */
3267 #define USB_EPI_TXCSR0_H           0xFFCC1012         /* USB Transmit Configuration and Status */
3268 #define USB_EP0I_CSR0_P            0xFFCC1012         /* USB Config and Status EP0 */
3269 #define USB_EPI_TXCSR0_P           0xFFCC1012         /* USB Transmit Configuration and Status */
3270 #define USB_EPI_RXMAXP0            0xFFCC1014         /* USB Receive Maximum Packet Length */
3271 #define USB_EPI_RXCSR0_H           0xFFCC1016         /* USB Receive Configuration and Status Register */
3272 #define USB_EPI_RXCSR0_P           0xFFCC1016         /* USB Receive Configuration and Status Register */
3273 #define USB_EP0I_CNT0              0xFFCC1018         /* USB Number of Received Bytes for Endpoint 0 */
3274 #define USB_EPI_RXCNT0             0xFFCC1018         /* USB Number of Byte Received */
3275 #define USB_EP0I_TYPE0             0xFFCC101A         /* USB Speed for Endpoint 0 */
3276 #define USB_EPI_TXTYPE0            0xFFCC101A         /* USB Transmit Type */
3277 #define USB_EP0I_NAKLIMIT0         0xFFCC101B         /* USB NAK Response Timeout for Endpoint 0 */
3278 #define USB_EPI_TXINTERVAL0        0xFFCC101B         /* USB Transmit Polling Interval */
3279 #define USB_EPI_RXTYPE0            0xFFCC101C         /* USB Receive Type */
3280 #define USB_EPI_RXINTERVAL0        0xFFCC101D         /* USB Receive Polling Interval */
3281 #define USB_EP0I_CFGDATA0          0xFFCC101F         /* USB Configuration Information */
3282 #define USB_FIFOB0                 0xFFCC1020         /* USB FIFO Data */
3283 #define USB_FIFOB1                 0xFFCC1024         /* USB FIFO Data */
3284 #define USB_FIFOB2                 0xFFCC1028         /* USB FIFO Data */
3285 #define USB_FIFOB3                 0xFFCC102C         /* USB FIFO Data */
3286 #define USB_FIFOB4                 0xFFCC1030         /* USB FIFO Data */
3287 #define USB_FIFOB5                 0xFFCC1034         /* USB FIFO Data */
3288 #define USB_FIFOB6                 0xFFCC1038         /* USB FIFO Data */
3289 #define USB_FIFOB7                 0xFFCC103C         /* USB FIFO Data */
3290 #define USB_FIFOB8                 0xFFCC1040         /* USB FIFO Data */
3291 #define USB_FIFOB9                 0xFFCC1044         /* USB FIFO Data */
3292 #define USB_FIFOB10                0xFFCC1048         /* USB FIFO Data */
3293 #define USB_FIFOB11                0xFFCC104C         /* USB FIFO Data */
3294 #define USB_FIFOH0                 0xFFCC1020         /* USB FIFO Data */
3295 #define USB_FIFOH1                 0xFFCC1024         /* USB FIFO Data */
3296 #define USB_FIFOH2                 0xFFCC1028         /* USB FIFO Data */
3297 #define USB_FIFOH3                 0xFFCC102C         /* USB FIFO Data */
3298 #define USB_FIFOH4                 0xFFCC1030         /* USB FIFO Data */
3299 #define USB_FIFOH5                 0xFFCC1034         /* USB FIFO Data */
3300 #define USB_FIFOH6                 0xFFCC1038         /* USB FIFO Data */
3301 #define USB_FIFOH7                 0xFFCC103C         /* USB FIFO Data */
3302 #define USB_FIFOH8                 0xFFCC1040         /* USB FIFO Data */
3303 #define USB_FIFOH9                 0xFFCC1044         /* USB FIFO Data */
3304 #define USB_FIFOH10                0xFFCC1048         /* USB FIFO Data */
3305 #define USB_FIFOH11                0xFFCC104C         /* USB FIFO Data */
3306 #define USB_FIFO0                  0xFFCC1020         /* USB FIFO Data */
3307 #define USB_EP0_FIFO               0xFFCC1020
3308 #define USB_FIFO1                  0xFFCC1024         /* USB FIFO Data */
3309 #define USB_FIFO2                  0xFFCC1028         /* USB FIFO Data */
3310 #define USB_FIFO3                  0xFFCC102C         /* USB FIFO Data */
3311 #define USB_FIFO4                  0xFFCC1030         /* USB FIFO Data */
3312 #define USB_FIFO5                  0xFFCC1034         /* USB FIFO Data */
3313 #define USB_FIFO6                  0xFFCC1038         /* USB FIFO Data */
3314 #define USB_FIFO7                  0xFFCC103C         /* USB FIFO Data */
3315 #define USB_FIFO8                  0xFFCC1040         /* USB FIFO Data */
3316 #define USB_FIFO9                  0xFFCC1044         /* USB FIFO Data */
3317 #define USB_FIFO10                 0xFFCC1048         /* USB FIFO Data */
3318 #define USB_FIFO11                 0xFFCC104C         /* USB FIFO Data */
3319 #define USB_OTG_DEV_CTL                0xFFCC1060         /* USB Device Control */
3320 #define USB_TXFIFOSZ               0xFFCC1062         /* USB Transmit FIFO Size */
3321 #define USB_RXFIFOSZ               0xFFCC1063         /* USB Receive FIFO Size */
3322 #define USB_TXFIFOADDR             0xFFCC1064         /* USB Transmit FIFO Address */
3323 #define USB_RXFIFOADDR             0xFFCC1066         /* USB Receive FIFO Address */
3324 #define USB_VENDSTAT               0xFFCC1068         /* USB Vendor Status */
3325 #define USB_HWVERS                 0xFFCC106C         /* USB Hardware Version */
3326 #define USB_EPINFO                 0xFFCC1078         /* USB Endpoint Info */
3327 #define USB_RAMINFO                0xFFCC1079         /* USB Ram Information */
3328 #define USB_LINKINFO               0xFFCC107A         /* USB Programmable Delay Values */
3329 #define USB_VPLEN                  0xFFCC107B         /* USB VBus Pulse Duration */
3330 #define USB_HS_EOF1                0xFFCC107C         /* USB High Speed End of Frame Remaining */
3331 #define USB_FS_EOF1                0xFFCC107D         /* USB Full Speed End of Frame Remaining */
3332 #define USB_LS_EOF1                0xFFCC107E         /* USB Low Speed End of Frame Remaining */
3333 #define USB_SOFT_RST               0xFFCC107F         /* USB Software Reset */
3334 #define USB_TXFUNCADDR0            0xFFCC1080         /* USB Transmit Function Address */
3335 #define USB_TXFUNCADDR1            0xFFCC1088         /* USB Transmit Function Address */
3336 #define USB_TXFUNCADDR2            0xFFCC1090         /* USB Transmit Function Address */
3337 #define USB_TXFUNCADDR3            0xFFCC1098         /* USB Transmit Function Address */
3338 #define USB_TXFUNCADDR4            0xFFCC10A0         /* USB Transmit Function Address */
3339 #define USB_TXFUNCADDR5            0xFFCC10A8         /* USB Transmit Function Address */
3340 #define USB_TXFUNCADDR6            0xFFCC10B0         /* USB Transmit Function Address */
3341 #define USB_TXFUNCADDR7            0xFFCC10B8         /* USB Transmit Function Address */
3342 #define USB_TXFUNCADDR8            0xFFCC10C0         /* USB Transmit Function Address */
3343 #define USB_TXFUNCADDR9            0xFFCC10C8         /* USB Transmit Function Address */
3344 #define USB_TXFUNCADDR10           0xFFCC10D0         /* USB Transmit Function Address */
3345 #define USB_TXFUNCADDR11           0xFFCC10D8         /* USB Transmit Function Address */
3346 #define USB_TXHUBADDR0             0xFFCC1082         /* USB Transmit Hub Address */
3347 #define USB_TXHUBADDR1             0xFFCC108A         /* USB Transmit Hub Address */
3348 #define USB_TXHUBADDR2             0xFFCC1092         /* USB Transmit Hub Address */
3349 #define USB_TXHUBADDR3             0xFFCC109A         /* USB Transmit Hub Address */
3350 #define USB_TXHUBADDR4             0xFFCC10A2         /* USB Transmit Hub Address */
3351 #define USB_TXHUBADDR5             0xFFCC10AA         /* USB Transmit Hub Address */
3352 #define USB_TXHUBADDR6             0xFFCC10B2         /* USB Transmit Hub Address */
3353 #define USB_TXHUBADDR7             0xFFCC10BA         /* USB Transmit Hub Address */
3354 #define USB_TXHUBADDR8             0xFFCC10C2         /* USB Transmit Hub Address */
3355 #define USB_TXHUBADDR9             0xFFCC10CA         /* USB Transmit Hub Address */
3356 #define USB_TXHUBADDR10            0xFFCC10D2         /* USB Transmit Hub Address */
3357 #define USB_TXHUBADDR11            0xFFCC10DA         /* USB Transmit Hub Address */
3358 #define USB_TXHUBPORT0             0xFFCC1083         /* USB Transmit Hub Port */
3359 #define USB_TXHUBPORT1             0xFFCC108B         /* USB Transmit Hub Port */
3360 #define USB_TXHUBPORT2             0xFFCC1093         /* USB Transmit Hub Port */
3361 #define USB_TXHUBPORT3             0xFFCC109B         /* USB Transmit Hub Port */
3362 #define USB_TXHUBPORT4             0xFFCC10A3         /* USB Transmit Hub Port */
3363 #define USB_TXHUBPORT5             0xFFCC10AB         /* USB Transmit Hub Port */
3364 #define USB_TXHUBPORT6             0xFFCC10B3         /* USB Transmit Hub Port */
3365 #define USB_TXHUBPORT7             0xFFCC10BB         /* USB Transmit Hub Port */
3366 #define USB_TXHUBPORT8             0xFFCC10C3         /* USB Transmit Hub Port */
3367 #define USB_TXHUBPORT9             0xFFCC10CB         /* USB Transmit Hub Port */
3368 #define USB_TXHUBPORT10            0xFFCC10D3         /* USB Transmit Hub Port */
3369 #define USB_TXHUBPORT11            0xFFCC10DB         /* USB Transmit Hub Port */
3370 #define USB_RXFUNCADDR0            0xFFCC1084         /* USB Receive Function Address */
3371 #define USB_RXFUNCADDR1            0xFFCC108C         /* USB Receive Function Address */
3372 #define USB_RXFUNCADDR2            0xFFCC1094         /* USB Receive Function Address */
3373 #define USB_RXFUNCADDR3            0xFFCC109C         /* USB Receive Function Address */
3374 #define USB_RXFUNCADDR4            0xFFCC10A4         /* USB Receive Function Address */
3375 #define USB_RXFUNCADDR5            0xFFCC10AC         /* USB Receive Function Address */
3376 #define USB_RXFUNCADDR6            0xFFCC10B4         /* USB Receive Function Address */
3377 #define USB_RXFUNCADDR7            0xFFCC10BC         /* USB Receive Function Address */
3378 #define USB_RXFUNCADDR8            0xFFCC10C4         /* USB Receive Function Address */
3379 #define USB_RXFUNCADDR9            0xFFCC10CC         /* USB Receive Function Address */
3380 #define USB_RXFUNCADDR10           0xFFCC10D4         /* USB Receive Function Address */
3381 #define USB_RXFUNCADDR11           0xFFCC10DC         /* USB Receive Function Address */
3382 #define USB_RXHUBADDR0             0xFFCC1086         /* USB Receive Hub Address */
3383 #define USB_RXHUBADDR1             0xFFCC108E         /* USB Receive Hub Address */
3384 #define USB_RXHUBADDR2             0xFFCC1096         /* USB Receive Hub Address */
3385 #define USB_RXHUBADDR3             0xFFCC109E         /* USB Receive Hub Address */
3386 #define USB_RXHUBADDR4             0xFFCC10A6         /* USB Receive Hub Address */
3387 #define USB_RXHUBADDR5             0xFFCC10AE         /* USB Receive Hub Address */
3388 #define USB_RXHUBADDR6             0xFFCC10B6         /* USB Receive Hub Address */
3389 #define USB_RXHUBADDR7             0xFFCC10BE         /* USB Receive Hub Address */
3390 #define USB_RXHUBADDR8             0xFFCC10C6         /* USB Receive Hub Address */
3391 #define USB_RXHUBADDR9             0xFFCC10CE         /* USB Receive Hub Address */
3392 #define USB_RXHUBADDR10            0xFFCC10D6         /* USB Receive Hub Address */
3393 #define USB_RXHUBADDR11            0xFFCC10DE         /* USB Receive Hub Address */
3394 #define USB_RXHUBPORT0             0xFFCC1087         /* USB Receive Hub Port */
3395 #define USB_RXHUBPORT1             0xFFCC108F         /* USB Receive Hub Port */
3396 #define USB_RXHUBPORT2             0xFFCC1097         /* USB Receive Hub Port */
3397 #define USB_RXHUBPORT3             0xFFCC109F         /* USB Receive Hub Port */
3398 #define USB_RXHUBPORT4             0xFFCC10A7         /* USB Receive Hub Port */
3399 #define USB_RXHUBPORT5             0xFFCC10AF         /* USB Receive Hub Port */
3400 #define USB_RXHUBPORT6             0xFFCC10B7         /* USB Receive Hub Port */
3401 #define USB_RXHUBPORT7             0xFFCC10BF         /* USB Receive Hub Port */
3402 #define USB_RXHUBPORT8             0xFFCC10C7         /* USB Receive Hub Port */
3403 #define USB_RXHUBPORT9             0xFFCC10CF         /* USB Receive Hub Port */
3404 #define USB_RXHUBPORT10            0xFFCC10D7         /* USB Receive Hub Port */
3405 #define USB_RXHUBPORT11            0xFFCC10DF         /* USB Receive Hub Port */
3406 #define USB_EP0_CSR0_H             0xFFCC1102         /* USB Config and Status EP0 */
3407 #define USB_EP0_CSR0_P             0xFFCC1102         /* USB Config and Status EP0 */
3408 #define USB_EP0_CNT0               0xFFCC1108         /* USB Number of Received Bytes for Endpoint 0 */
3409 #define USB_EP0_TYPE0              0xFFCC110A         /* USB Speed for Endpoint 0 */
3410 #define USB_EP0_NAKLIMIT0          0xFFCC110B         /* USB NAK Response Timeout for Endpoint 0 */
3411 #define USB_EP0_CFGDATA0           0xFFCC110F         /* USB Configuration Information */
3412 #define USB_EP_TXMAXP0             0xFFCC1110         /* USB Transmit Maximum Packet Length */
3413 #define USB_EP_TXMAXP1             0xFFCC1120         /* USB Transmit Maximum Packet Length */
3414 #define USB_EP_TXMAXP2             0xFFCC1130         /* USB Transmit Maximum Packet Length */
3415 #define USB_EP_TXMAXP3             0xFFCC1140         /* USB Transmit Maximum Packet Length */
3416 #define USB_EP_TXMAXP4             0xFFCC1150         /* USB Transmit Maximum Packet Length */
3417 #define USB_EP_TXMAXP5             0xFFCC1160         /* USB Transmit Maximum Packet Length */
3418 #define USB_EP_TXMAXP6             0xFFCC1170         /* USB Transmit Maximum Packet Length */
3419 #define USB_EP_TXMAXP7             0xFFCC1180         /* USB Transmit Maximum Packet Length */
3420 #define USB_EP_TXMAXP8             0xFFCC1190         /* USB Transmit Maximum Packet Length */
3421 #define USB_EP_TXMAXP9             0xFFCC11A0         /* USB Transmit Maximum Packet Length */
3422 #define USB_EP_TXMAXP10            0xFFCC11B0         /* USB Transmit Maximum Packet Length */
3423 #define USB_EP_TXCSR0_H            0xFFCC1112         /* USB Transmit Configuration and Status */
3424 #define USB_EP_TXCSR1_H            0xFFCC1122         /* USB Transmit Configuration and Status */
3425 #define USB_EP_TXCSR2_H            0xFFCC1132         /* USB Transmit Configuration and Status */
3426 #define USB_EP_TXCSR3_H            0xFFCC1142         /* USB Transmit Configuration and Status */
3427 #define USB_EP_TXCSR4_H            0xFFCC1152         /* USB Transmit Configuration and Status */
3428 #define USB_EP_TXCSR5_H            0xFFCC1162         /* USB Transmit Configuration and Status */
3429 #define USB_EP_TXCSR6_H            0xFFCC1172         /* USB Transmit Configuration and Status */
3430 #define USB_EP_TXCSR7_H            0xFFCC1182         /* USB Transmit Configuration and Status */
3431 #define USB_EP_TXCSR8_H            0xFFCC1192         /* USB Transmit Configuration and Status */
3432 #define USB_EP_TXCSR9_H            0xFFCC11A2         /* USB Transmit Configuration and Status */
3433 #define USB_EP_TXCSR10_H           0xFFCC11B2         /* USB Transmit Configuration and Status */
3434 #define USB_EP_TXCSR0_P            0xFFCC1112         /* USB Transmit Configuration and Status */
3435 #define USB_EP_TXCSR1_P            0xFFCC1122         /* USB Transmit Configuration and Status */
3436 #define USB_EP_TXCSR2_P            0xFFCC1132         /* USB Transmit Configuration and Status */
3437 #define USB_EP_TXCSR3_P            0xFFCC1142         /* USB Transmit Configuration and Status */
3438 #define USB_EP_TXCSR4_P            0xFFCC1152         /* USB Transmit Configuration and Status */
3439 #define USB_EP_TXCSR5_P            0xFFCC1162         /* USB Transmit Configuration and Status */
3440 #define USB_EP_TXCSR6_P            0xFFCC1172         /* USB Transmit Configuration and Status */
3441 #define USB_EP_TXCSR7_P            0xFFCC1182         /* USB Transmit Configuration and Status */
3442 #define USB_EP_TXCSR8_P            0xFFCC1192         /* USB Transmit Configuration and Status */
3443 #define USB_EP_TXCSR9_P            0xFFCC11A2         /* USB Transmit Configuration and Status */
3444 #define USB_EP_TXCSR10_P           0xFFCC11B2         /* USB Transmit Configuration and Status */
3445 #define USB_EP_RXMAXP0             0xFFCC1114         /* USB Receive Maximum Packet Length */
3446 #define USB_EP_RXMAXP1             0xFFCC1124         /* USB Receive Maximum Packet Length */
3447 #define USB_EP_RXMAXP2             0xFFCC1134         /* USB Receive Maximum Packet Length */
3448 #define USB_EP_RXMAXP3             0xFFCC1144         /* USB Receive Maximum Packet Length */
3449 #define USB_EP_RXMAXP4             0xFFCC1154         /* USB Receive Maximum Packet Length */
3450 #define USB_EP_RXMAXP5             0xFFCC1164         /* USB Receive Maximum Packet Length */
3451 #define USB_EP_RXMAXP6             0xFFCC1174         /* USB Receive Maximum Packet Length */
3452 #define USB_EP_RXMAXP7             0xFFCC1184         /* USB Receive Maximum Packet Length */
3453 #define USB_EP_RXMAXP8             0xFFCC1194         /* USB Receive Maximum Packet Length */
3454 #define USB_EP_RXMAXP9             0xFFCC11A4         /* USB Receive Maximum Packet Length */
3455 #define USB_EP_RXMAXP10            0xFFCC11B4         /* USB Receive Maximum Packet Length */
3456 #define USB_EP_RXCSR0_H            0xFFCC1116         /* USB Receive Configuration and Status Register */
3457 #define USB_EP_RXCSR1_H            0xFFCC1126         /* USB Receive Configuration and Status Register */
3458 #define USB_EP_RXCSR2_H            0xFFCC1136         /* USB Receive Configuration and Status Register */
3459 #define USB_EP_RXCSR3_H            0xFFCC1146         /* USB Receive Configuration and Status Register */
3460 #define USB_EP_RXCSR4_H            0xFFCC1156         /* USB Receive Configuration and Status Register */
3461 #define USB_EP_RXCSR5_H            0xFFCC1166         /* USB Receive Configuration and Status Register */
3462 #define USB_EP_RXCSR6_H            0xFFCC1176         /* USB Receive Configuration and Status Register */
3463 #define USB_EP_RXCSR7_H            0xFFCC1186         /* USB Receive Configuration and Status Register */
3464 #define USB_EP_RXCSR8_H            0xFFCC1196         /* USB Receive Configuration and Status Register */
3465 #define USB_EP_RXCSR9_H            0xFFCC11A6         /* USB Receive Configuration and Status Register */
3466 #define USB_EP_RXCSR10_H           0xFFCC11B6         /* USB Receive Configuration and Status Register */
3467 #define USB_EP_RXCSR0_P            0xFFCC1116         /* USB Receive Configuration and Status Register */
3468 #define USB_EP_RXCSR1_P            0xFFCC1126         /* USB Receive Configuration and Status Register */
3469 #define USB_EP_RXCSR2_P            0xFFCC1136         /* USB Receive Configuration and Status Register */
3470 #define USB_EP_RXCSR3_P            0xFFCC1146         /* USB Receive Configuration and Status Register */
3471 #define USB_EP_RXCSR4_P            0xFFCC1156         /* USB Receive Configuration and Status Register */
3472 #define USB_EP_RXCSR5_P            0xFFCC1166         /* USB Receive Configuration and Status Register */
3473 #define USB_EP_RXCSR6_P            0xFFCC1176         /* USB Receive Configuration and Status Register */
3474 #define USB_EP_RXCSR7_P            0xFFCC1186         /* USB Receive Configuration and Status Register */
3475 #define USB_EP_RXCSR8_P            0xFFCC1196         /* USB Receive Configuration and Status Register */
3476 #define USB_EP_RXCSR9_P            0xFFCC11A6         /* USB Receive Configuration and Status Register */
3477 #define USB_EP_RXCSR10_P           0xFFCC11B6         /* USB Receive Configuration and Status Register */
3478 #define USB_EP_RXCNT0              0xFFCC1118         /* USB Number of Byte Received */
3479 #define USB_EP_RXCNT1              0xFFCC1128         /* USB Number of Byte Received */
3480 #define USB_EP_RXCNT2              0xFFCC1138         /* USB Number of Byte Received */
3481 #define USB_EP_RXCNT3              0xFFCC1148         /* USB Number of Byte Received */
3482 #define USB_EP_RXCNT4              0xFFCC1158         /* USB Number of Byte Received */
3483 #define USB_EP_RXCNT5              0xFFCC1168         /* USB Number of Byte Received */
3484 #define USB_EP_RXCNT6              0xFFCC1178         /* USB Number of Byte Received */
3485 #define USB_EP_RXCNT7              0xFFCC1188         /* USB Number of Byte Received */
3486 #define USB_EP_RXCNT8              0xFFCC1198         /* USB Number of Byte Received */
3487 #define USB_EP_RXCNT9              0xFFCC11A8         /* USB Number of Byte Received */
3488 #define USB_EP_RXCNT10             0xFFCC11B8         /* USB Number of Byte Received */
3489 #define USB_EP_TXTYPE0             0xFFCC111A         /* USB Transmit Type */
3490 #define USB_EP_TXTYPE1             0xFFCC112A         /* USB Transmit Type */
3491 #define USB_EP_TXTYPE2             0xFFCC113A         /* USB Transmit Type */
3492 #define USB_EP_TXTYPE3             0xFFCC114A         /* USB Transmit Type */
3493 #define USB_EP_TXTYPE4             0xFFCC115A         /* USB Transmit Type */
3494 #define USB_EP_TXTYPE5             0xFFCC116A         /* USB Transmit Type */
3495 #define USB_EP_TXTYPE6             0xFFCC117A         /* USB Transmit Type */
3496 #define USB_EP_TXTYPE7             0xFFCC118A         /* USB Transmit Type */
3497 #define USB_EP_TXTYPE8             0xFFCC119A         /* USB Transmit Type */
3498 #define USB_EP_TXTYPE9             0xFFCC11AA         /* USB Transmit Type */
3499 #define USB_EP_TXTYPE10            0xFFCC11BA         /* USB Transmit Type */
3500 #define USB_EP_TXINTERVAL0         0xFFCC111B         /* USB Transmit Polling Interval */
3501 #define USB_EP_TXINTERVAL1         0xFFCC112B         /* USB Transmit Polling Interval */
3502 #define USB_EP_TXINTERVAL2         0xFFCC113B         /* USB Transmit Polling Interval */
3503 #define USB_EP_TXINTERVAL3         0xFFCC114B         /* USB Transmit Polling Interval */
3504 #define USB_EP_TXINTERVAL4         0xFFCC115B         /* USB Transmit Polling Interval */
3505 #define USB_EP_TXINTERVAL5         0xFFCC116B         /* USB Transmit Polling Interval */
3506 #define USB_EP_TXINTERVAL6         0xFFCC117B         /* USB Transmit Polling Interval */
3507 #define USB_EP_TXINTERVAL7         0xFFCC118B         /* USB Transmit Polling Interval */
3508 #define USB_EP_TXINTERVAL8         0xFFCC119B         /* USB Transmit Polling Interval */
3509 #define USB_EP_TXINTERVAL9         0xFFCC11AB         /* USB Transmit Polling Interval */
3510 #define USB_EP_TXINTERVAL10        0xFFCC11BB         /* USB Transmit Polling Interval */
3511 #define USB_EP_RXTYPE0             0xFFCC111C         /* USB Receive Type */
3512 #define USB_EP_RXTYPE1             0xFFCC112C         /* USB Receive Type */
3513 #define USB_EP_RXTYPE2             0xFFCC113C         /* USB Receive Type */
3514 #define USB_EP_RXTYPE3             0xFFCC114C         /* USB Receive Type */
3515 #define USB_EP_RXTYPE4             0xFFCC115C         /* USB Receive Type */
3516 #define USB_EP_RXTYPE5             0xFFCC116C         /* USB Receive Type */
3517 #define USB_EP_RXTYPE6             0xFFCC117C         /* USB Receive Type */
3518 #define USB_EP_RXTYPE7             0xFFCC118C         /* USB Receive Type */
3519 #define USB_EP_RXTYPE8             0xFFCC119C         /* USB Receive Type */
3520 #define USB_EP_RXTYPE9             0xFFCC11AC         /* USB Receive Type */
3521 #define USB_EP_RXTYPE10            0xFFCC11BC         /* USB Receive Type */
3522 #define USB_EP_RXINTERVAL0         0xFFCC111D         /* USB Receive Polling Interval */
3523 #define USB_EP_RXINTERVAL1         0xFFCC112D         /* USB Receive Polling Interval */
3524 #define USB_EP_RXINTERVAL2         0xFFCC113D         /* USB Receive Polling Interval */
3525 #define USB_EP_RXINTERVAL3         0xFFCC114D         /* USB Receive Polling Interval */
3526 #define USB_EP_RXINTERVAL4         0xFFCC115D         /* USB Receive Polling Interval */
3527 #define USB_EP_RXINTERVAL5         0xFFCC116D         /* USB Receive Polling Interval */
3528 #define USB_EP_RXINTERVAL6         0xFFCC117D         /* USB Receive Polling Interval */
3529 #define USB_EP_RXINTERVAL7         0xFFCC118D         /* USB Receive Polling Interval */
3530 #define USB_EP_RXINTERVAL8         0xFFCC119D         /* USB Receive Polling Interval */
3531 #define USB_EP_RXINTERVAL9         0xFFCC11AD         /* USB Receive Polling Interval */
3532 #define USB_EP_RXINTERVAL10        0xFFCC11BD         /* USB Receive Polling Interval */
3533 #define USB_DMA_IRQ                0xFFCC1200         /* USB Interrupt Register */
3534 #define USB_DMA_CTL0               0xFFCC1204         /* USB DMA Control */
3535 #define USB_DMA_CTL1               0xFFCC1214         /* USB DMA Control */
3536 #define USB_DMA_CTL2               0xFFCC1224         /* USB DMA Control */
3537 #define USB_DMA_CTL3               0xFFCC1234         /* USB DMA Control */
3538 #define USB_DMA_CTL4               0xFFCC1244         /* USB DMA Control */
3539 #define USB_DMA_CTL5               0xFFCC1254         /* USB DMA Control */
3540 #define USB_DMA_CTL6               0xFFCC1264         /* USB DMA Control */
3541 #define USB_DMA_CTL7               0xFFCC1274         /* USB DMA Control */
3542 #define USB_DMA_ADDR0              0xFFCC1208         /* USB DMA Address */
3543 #define USB_DMA_ADDR1              0xFFCC1218         /* USB DMA Address */
3544 #define USB_DMA_ADDR2              0xFFCC1228         /* USB DMA Address */
3545 #define USB_DMA_ADDR3              0xFFCC1238         /* USB DMA Address */
3546 #define USB_DMA_ADDR4              0xFFCC1248         /* USB DMA Address */
3547 #define USB_DMA_ADDR5              0xFFCC1258         /* USB DMA Address */
3548 #define USB_DMA_ADDR6              0xFFCC1268         /* USB DMA Address */
3549 #define USB_DMA_ADDR7              0xFFCC1278         /* USB DMA Address */
3550 #define USB_DMA_CNT0               0xFFCC120C         /* USB DMA Count */
3551 #define USB_DMA_CNT1               0xFFCC121C         /* USB DMA Count */
3552 #define USB_DMA_CNT2               0xFFCC122C         /* USB DMA Count */
3553 #define USB_DMA_CNT3               0xFFCC123C         /* USB DMA Count */
3554 #define USB_DMA_CNT4               0xFFCC124C         /* USB DMA Count */
3555 #define USB_DMA_CNT5               0xFFCC125C         /* USB DMA Count */
3556 #define USB_DMA_CNT6               0xFFCC126C         /* USB DMA Count */
3557 #define USB_DMA_CNT7               0xFFCC127C         /* USB DMA Count */
3558 #define USB_RQPKTCNT0              0xFFCC1300         /* USB Request Packet Count */
3559 #define USB_RQPKTCNT1              0xFFCC1304         /* USB Request Packet Count */
3560 #define USB_RQPKTCNT2              0xFFCC1308         /* USB Request Packet Count */
3561 #define USB_RQPKTCNT3              0xFFCC130C         /* USB Request Packet Count */
3562 #define USB_RQPKTCNT4              0xFFCC1310         /* USB Request Packet Count */
3563 #define USB_RQPKTCNT5              0xFFCC1314         /* USB Request Packet Count */
3564 #define USB_RQPKTCNT6              0xFFCC1318         /* USB Request Packet Count */
3565 #define USB_RQPKTCNT7              0xFFCC131C         /* USB Request Packet Count */
3566 #define USB_RQPKTCNT8              0xFFCC1320         /* USB Request Packet Count */
3567 #define USB_RQPKTCNT9              0xFFCC1324         /* USB Request Packet Count */
3568 #define USB_RQPKTCNT10             0xFFCC1328         /* USB Request Packet Count */
3569 #define USB_CT_UCH                 0xFFCC1344         /* USB Chirp Timeout */
3570 #define USB_CT_HHSRTN              0xFFCC1346         /* USB High Speed Resume Return to Normal */
3571 #define USB_CT_HSBT                0xFFCC1348         /* USB High Speed Timeout */
3572 #define USB_LPM_ATTR               0xFFCC1360         /* USB LPM Attribute */
3573 #define USB_LPM_CTL                0xFFCC1362         /* USB LPM Control */
3574 #define USB_LPM_IEN                0xFFCC1363         /* USB LPM Interrupt Enable */
3575 #define USB_LPM_IRQ                0xFFCC1364         /* USB LPM Interrupt */
3576 #define USB_LPM_FADDR              0xFFCC1365         /* USB LPM Function Address */
3577 #define USB_VBUS_CTL               0xFFCC1380         /* USB VBus Control */
3578 #define USB_BAT_CHG                0xFFCC1381         /* USB Battery Charging */
3579 #define USB_PHY_CTL                0xFFCC1394         /* USB PHY Control */
3580 #define USB_TESTCTL                0xFFCC1397         /* USB Test Control */
3581 #define USB_PLL_OSC                0xFFCC1398         /* USB PLL and Oscillator Control */
3582 
3583 
3584 
3585 /* =========================
3586         CHIPID
3587    ========================= */
3588 
3589 #define                           CHIPID  0xffc00014
3590 /* CHIPID Masks */
3591 #define                   CHIPID_VERSION  0xF0000000
3592 #define                    CHIPID_FAMILY  0x0FFFF000
3593 #define               CHIPID_MANUFACTURE  0x00000FFE
3594 
3595 
3596 #endif /* _DEF_BF60X_H */
3597