1 /*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8 #ifndef __STMPE_H
9 #define __STMPE_H
10
11 #include <linux/device.h>
12 #include <linux/mfd/core.h>
13 #include <linux/mfd/stmpe.h>
14 #include <linux/printk.h>
15 #include <linux/types.h>
16
17 extern const struct dev_pm_ops stmpe_dev_pm_ops;
18
19 #ifdef STMPE_DUMP_BYTES
stmpe_dump_bytes(const char * str,const void * buf,size_t len)20 static inline void stmpe_dump_bytes(const char *str, const void *buf,
21 size_t len)
22 {
23 print_hex_dump_bytes(str, DUMP_PREFIX_OFFSET, buf, len);
24 }
25 #else
stmpe_dump_bytes(const char * str,const void * buf,size_t len)26 static inline void stmpe_dump_bytes(const char *str, const void *buf,
27 size_t len)
28 {
29 }
30 #endif
31
32 /**
33 * struct stmpe_variant_block - information about block
34 * @cell: base mfd cell
35 * @irq: interrupt number to be added to each IORESOURCE_IRQ
36 * in the cell
37 * @block: block id; used for identification with platform data and for
38 * enable and altfunc callbacks
39 */
40 struct stmpe_variant_block {
41 const struct mfd_cell *cell;
42 int irq;
43 enum stmpe_block block;
44 };
45
46 /**
47 * struct stmpe_variant_info - variant-specific information
48 * @name: part name
49 * @id_val: content of CHIPID register
50 * @id_mask: bits valid in CHIPID register for comparison with id_val
51 * @num_gpios: number of GPIOS
52 * @af_bits: number of bits used to specify the alternate function
53 * @regs: variant specific registers.
54 * @blocks: list of blocks present on this device
55 * @num_blocks: number of blocks present on this device
56 * @num_irqs: number of internal IRQs available on this device
57 * @enable: callback to enable the specified blocks.
58 * Called with the I/O lock held.
59 * @get_altfunc: callback to get the alternate function number for the
60 * specific block
61 * @enable_autosleep: callback to configure autosleep with specified timeout
62 */
63 struct stmpe_variant_info {
64 const char *name;
65 u16 id_val;
66 u16 id_mask;
67 int num_gpios;
68 int af_bits;
69 const u8 *regs;
70 struct stmpe_variant_block *blocks;
71 int num_blocks;
72 int num_irqs;
73 int (*enable)(struct stmpe *stmpe, unsigned int blocks, bool enable);
74 int (*get_altfunc)(struct stmpe *stmpe, enum stmpe_block block);
75 int (*enable_autosleep)(struct stmpe *stmpe, int autosleep_timeout);
76 };
77
78 /**
79 * struct stmpe_client_info - i2c or spi specific routines/info
80 * @data: client specific data
81 * @read_byte: read single byte
82 * @write_byte: write single byte
83 * @read_block: read block or multiple bytes
84 * @write_block: write block or multiple bytes
85 * @init: client init routine, called during probe
86 */
87 struct stmpe_client_info {
88 void *data;
89 int irq;
90 void *client;
91 struct device *dev;
92 int (*read_byte)(struct stmpe *stmpe, u8 reg);
93 int (*write_byte)(struct stmpe *stmpe, u8 reg, u8 val);
94 int (*read_block)(struct stmpe *stmpe, u8 reg, u8 len, u8 *values);
95 int (*write_block)(struct stmpe *stmpe, u8 reg, u8 len,
96 const u8 *values);
97 void (*init)(struct stmpe *stmpe);
98 };
99
100 int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum);
101 int stmpe_remove(struct stmpe *stmpe);
102
103 #define STMPE_ICR_LSB_HIGH (1 << 2)
104 #define STMPE_ICR_LSB_EDGE (1 << 1)
105 #define STMPE_ICR_LSB_GIM (1 << 0)
106
107 /*
108 * STMPE801
109 */
110 #define STMPE801_ID 0x0108
111 #define STMPE801_NR_INTERNAL_IRQS 1
112
113 #define STMPE801_REG_CHIP_ID 0x00
114 #define STMPE801_REG_VERSION_ID 0x02
115 #define STMPE801_REG_SYS_CTRL 0x04
116 #define STMPE801_REG_GPIO_INT_EN 0x08
117 #define STMPE801_REG_GPIO_INT_STA 0x09
118 #define STMPE801_REG_GPIO_MP_STA 0x10
119 #define STMPE801_REG_GPIO_SET_PIN 0x11
120 #define STMPE801_REG_GPIO_DIR 0x12
121
122 #define STMPE801_REG_SYS_CTRL_RESET (1 << 7)
123 #define STMPE801_REG_SYS_CTRL_INT_EN (1 << 2)
124 #define STMPE801_REG_SYS_CTRL_INT_HI (1 << 0)
125
126 /*
127 * STMPE811
128 */
129
130 #define STMPE811_IRQ_TOUCH_DET 0
131 #define STMPE811_IRQ_FIFO_TH 1
132 #define STMPE811_IRQ_FIFO_OFLOW 2
133 #define STMPE811_IRQ_FIFO_FULL 3
134 #define STMPE811_IRQ_FIFO_EMPTY 4
135 #define STMPE811_IRQ_TEMP_SENS 5
136 #define STMPE811_IRQ_ADC 6
137 #define STMPE811_IRQ_GPIOC 7
138 #define STMPE811_NR_INTERNAL_IRQS 8
139
140 #define STMPE811_REG_CHIP_ID 0x00
141 #define STMPE811_REG_SYS_CTRL2 0x04
142 #define STMPE811_REG_SPI_CFG 0x08
143 #define STMPE811_REG_INT_CTRL 0x09
144 #define STMPE811_REG_INT_EN 0x0A
145 #define STMPE811_REG_INT_STA 0x0B
146 #define STMPE811_REG_GPIO_INT_EN 0x0C
147 #define STMPE811_REG_GPIO_INT_STA 0x0D
148 #define STMPE811_REG_GPIO_SET_PIN 0x10
149 #define STMPE811_REG_GPIO_CLR_PIN 0x11
150 #define STMPE811_REG_GPIO_MP_STA 0x12
151 #define STMPE811_REG_GPIO_DIR 0x13
152 #define STMPE811_REG_GPIO_ED 0x14
153 #define STMPE811_REG_GPIO_RE 0x15
154 #define STMPE811_REG_GPIO_FE 0x16
155 #define STMPE811_REG_GPIO_AF 0x17
156
157 #define STMPE811_SYS_CTRL2_ADC_OFF (1 << 0)
158 #define STMPE811_SYS_CTRL2_TSC_OFF (1 << 1)
159 #define STMPE811_SYS_CTRL2_GPIO_OFF (1 << 2)
160 #define STMPE811_SYS_CTRL2_TS_OFF (1 << 3)
161
162 /*
163 * STMPE1601
164 */
165
166 #define STMPE1601_IRQ_GPIOC 8
167 #define STMPE1601_IRQ_PWM3 7
168 #define STMPE1601_IRQ_PWM2 6
169 #define STMPE1601_IRQ_PWM1 5
170 #define STMPE1601_IRQ_PWM0 4
171 #define STMPE1601_IRQ_KEYPAD_OVER 2
172 #define STMPE1601_IRQ_KEYPAD 1
173 #define STMPE1601_IRQ_WAKEUP 0
174 #define STMPE1601_NR_INTERNAL_IRQS 9
175
176 #define STMPE1601_REG_SYS_CTRL 0x02
177 #define STMPE1601_REG_SYS_CTRL2 0x03
178 #define STMPE1601_REG_ICR_LSB 0x11
179 #define STMPE1601_REG_IER_LSB 0x13
180 #define STMPE1601_REG_ISR_MSB 0x14
181 #define STMPE1601_REG_CHIP_ID 0x80
182 #define STMPE1601_REG_INT_EN_GPIO_MASK_LSB 0x17
183 #define STMPE1601_REG_INT_STA_GPIO_MSB 0x18
184 #define STMPE1601_REG_GPIO_MP_LSB 0x87
185 #define STMPE1601_REG_GPIO_SET_LSB 0x83
186 #define STMPE1601_REG_GPIO_CLR_LSB 0x85
187 #define STMPE1601_REG_GPIO_SET_DIR_LSB 0x89
188 #define STMPE1601_REG_GPIO_ED_MSB 0x8A
189 #define STMPE1601_REG_GPIO_RE_LSB 0x8D
190 #define STMPE1601_REG_GPIO_FE_LSB 0x8F
191 #define STMPE1601_REG_GPIO_PU_LSB 0x91
192 #define STMPE1601_REG_GPIO_AF_U_MSB 0x92
193
194 #define STMPE1601_SYS_CTRL_ENABLE_GPIO (1 << 3)
195 #define STMPE1601_SYS_CTRL_ENABLE_KPC (1 << 1)
196 #define STMPE1601_SYS_CTRL_ENABLE_SPWM (1 << 0)
197
198 /* The 1601/2403 share the same masks */
199 #define STMPE1601_AUTOSLEEP_TIMEOUT_MASK (0x7)
200 #define STPME1601_AUTOSLEEP_ENABLE (1 << 3)
201
202 /*
203 * STMPE1801
204 */
205 #define STMPE1801_ID 0xc110
206 #define STMPE1801_NR_INTERNAL_IRQS 5
207 #define STMPE1801_IRQ_KEYPAD_COMBI 4
208 #define STMPE1801_IRQ_GPIOC 3
209 #define STMPE1801_IRQ_KEYPAD_OVER 2
210 #define STMPE1801_IRQ_KEYPAD 1
211 #define STMPE1801_IRQ_WAKEUP 0
212
213 #define STMPE1801_REG_CHIP_ID 0x00
214 #define STMPE1801_REG_SYS_CTRL 0x02
215 #define STMPE1801_REG_INT_CTRL_LOW 0x04
216 #define STMPE1801_REG_INT_EN_MASK_LOW 0x06
217 #define STMPE1801_REG_INT_STA_LOW 0x08
218 #define STMPE1801_REG_INT_EN_GPIO_MASK_LOW 0x0A
219 #define STMPE1801_REG_INT_EN_GPIO_MASK_MID 0x0B
220 #define STMPE1801_REG_INT_EN_GPIO_MASK_HIGH 0x0C
221 #define STMPE1801_REG_INT_STA_GPIO_LOW 0x0D
222 #define STMPE1801_REG_INT_STA_GPIO_MID 0x0E
223 #define STMPE1801_REG_INT_STA_GPIO_HIGH 0x0F
224 #define STMPE1801_REG_GPIO_SET_LOW 0x10
225 #define STMPE1801_REG_GPIO_SET_MID 0x11
226 #define STMPE1801_REG_GPIO_SET_HIGH 0x12
227 #define STMPE1801_REG_GPIO_CLR_LOW 0x13
228 #define STMPE1801_REG_GPIO_CLR_MID 0x14
229 #define STMPE1801_REG_GPIO_CLR_HIGH 0x15
230 #define STMPE1801_REG_GPIO_MP_LOW 0x16
231 #define STMPE1801_REG_GPIO_MP_MID 0x17
232 #define STMPE1801_REG_GPIO_MP_HIGH 0x18
233 #define STMPE1801_REG_GPIO_SET_DIR_LOW 0x19
234 #define STMPE1801_REG_GPIO_SET_DIR_MID 0x1A
235 #define STMPE1801_REG_GPIO_SET_DIR_HIGH 0x1B
236 #define STMPE1801_REG_GPIO_RE_LOW 0x1C
237 #define STMPE1801_REG_GPIO_RE_MID 0x1D
238 #define STMPE1801_REG_GPIO_RE_HIGH 0x1E
239 #define STMPE1801_REG_GPIO_FE_LOW 0x1F
240 #define STMPE1801_REG_GPIO_FE_MID 0x20
241 #define STMPE1801_REG_GPIO_FE_HIGH 0x21
242 #define STMPE1801_REG_GPIO_PULL_UP_LOW 0x22
243 #define STMPE1801_REG_GPIO_PULL_UP_MID 0x23
244 #define STMPE1801_REG_GPIO_PULL_UP_HIGH 0x24
245
246 #define STMPE1801_MSK_SYS_CTRL_RESET (1 << 7)
247
248 #define STMPE1801_MSK_INT_EN_KPC (1 << 1)
249 #define STMPE1801_MSK_INT_EN_GPIO (1 << 3)
250
251 /*
252 * STMPE24xx
253 */
254
255 #define STMPE24XX_IRQ_GPIOC 8
256 #define STMPE24XX_IRQ_PWM2 7
257 #define STMPE24XX_IRQ_PWM1 6
258 #define STMPE24XX_IRQ_PWM0 5
259 #define STMPE24XX_IRQ_ROT_OVER 4
260 #define STMPE24XX_IRQ_ROT 3
261 #define STMPE24XX_IRQ_KEYPAD_OVER 2
262 #define STMPE24XX_IRQ_KEYPAD 1
263 #define STMPE24XX_IRQ_WAKEUP 0
264 #define STMPE24XX_NR_INTERNAL_IRQS 9
265
266 #define STMPE24XX_REG_SYS_CTRL 0x02
267 #define STMPE24XX_REG_ICR_LSB 0x11
268 #define STMPE24XX_REG_IER_LSB 0x13
269 #define STMPE24XX_REG_ISR_MSB 0x14
270 #define STMPE24XX_REG_CHIP_ID 0x80
271 #define STMPE24XX_REG_IEGPIOR_LSB 0x18
272 #define STMPE24XX_REG_ISGPIOR_MSB 0x19
273 #define STMPE24XX_REG_GPMR_LSB 0xA4
274 #define STMPE24XX_REG_GPSR_LSB 0x85
275 #define STMPE24XX_REG_GPCR_LSB 0x88
276 #define STMPE24XX_REG_GPDR_LSB 0x8B
277 #define STMPE24XX_REG_GPEDR_MSB 0x8C
278 #define STMPE24XX_REG_GPRER_LSB 0x91
279 #define STMPE24XX_REG_GPFER_LSB 0x94
280 #define STMPE24XX_REG_GPPUR_LSB 0x97
281 #define STMPE24XX_REG_GPPDR_LSB 0x9a
282 #define STMPE24XX_REG_GPAFR_U_MSB 0x9B
283
284 #define STMPE24XX_SYS_CTRL_ENABLE_GPIO (1 << 3)
285 #define STMPE24XX_SYSCON_ENABLE_PWM (1 << 2)
286 #define STMPE24XX_SYS_CTRL_ENABLE_KPC (1 << 1)
287 #define STMPE24XX_SYSCON_ENABLE_ROT (1 << 0)
288
289 #endif
290