1 /*
2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 /*
35 * This file contains all of the code that is specific to the InfiniPath
36 * HT chip.
37 */
38
39 #include <linux/vmalloc.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
42 #include <linux/htirq.h>
43 #include <rdma/ib_verbs.h>
44
45 #include "ipath_kernel.h"
46 #include "ipath_registers.h"
47
48 static void ipath_setup_ht_setextled(struct ipath_devdata *, u64, u64);
49
50
51 /*
52 * This lists the InfiniPath registers, in the actual chip layout.
53 * This structure should never be directly accessed.
54 *
55 * The names are in InterCap form because they're taken straight from
56 * the chip specification. Since they're only used in this file, they
57 * don't pollute the rest of the source.
58 */
59
60 struct _infinipath_do_not_use_kernel_regs {
61 unsigned long long Revision;
62 unsigned long long Control;
63 unsigned long long PageAlign;
64 unsigned long long PortCnt;
65 unsigned long long DebugPortSelect;
66 unsigned long long DebugPort;
67 unsigned long long SendRegBase;
68 unsigned long long UserRegBase;
69 unsigned long long CounterRegBase;
70 unsigned long long Scratch;
71 unsigned long long ReservedMisc1;
72 unsigned long long InterruptConfig;
73 unsigned long long IntBlocked;
74 unsigned long long IntMask;
75 unsigned long long IntStatus;
76 unsigned long long IntClear;
77 unsigned long long ErrorMask;
78 unsigned long long ErrorStatus;
79 unsigned long long ErrorClear;
80 unsigned long long HwErrMask;
81 unsigned long long HwErrStatus;
82 unsigned long long HwErrClear;
83 unsigned long long HwDiagCtrl;
84 unsigned long long MDIO;
85 unsigned long long IBCStatus;
86 unsigned long long IBCCtrl;
87 unsigned long long ExtStatus;
88 unsigned long long ExtCtrl;
89 unsigned long long GPIOOut;
90 unsigned long long GPIOMask;
91 unsigned long long GPIOStatus;
92 unsigned long long GPIOClear;
93 unsigned long long RcvCtrl;
94 unsigned long long RcvBTHQP;
95 unsigned long long RcvHdrSize;
96 unsigned long long RcvHdrCnt;
97 unsigned long long RcvHdrEntSize;
98 unsigned long long RcvTIDBase;
99 unsigned long long RcvTIDCnt;
100 unsigned long long RcvEgrBase;
101 unsigned long long RcvEgrCnt;
102 unsigned long long RcvBufBase;
103 unsigned long long RcvBufSize;
104 unsigned long long RxIntMemBase;
105 unsigned long long RxIntMemSize;
106 unsigned long long RcvPartitionKey;
107 unsigned long long ReservedRcv[10];
108 unsigned long long SendCtrl;
109 unsigned long long SendPIOBufBase;
110 unsigned long long SendPIOSize;
111 unsigned long long SendPIOBufCnt;
112 unsigned long long SendPIOAvailAddr;
113 unsigned long long TxIntMemBase;
114 unsigned long long TxIntMemSize;
115 unsigned long long ReservedSend[9];
116 unsigned long long SendBufferError;
117 unsigned long long SendBufferErrorCONT1;
118 unsigned long long SendBufferErrorCONT2;
119 unsigned long long SendBufferErrorCONT3;
120 unsigned long long ReservedSBE[4];
121 unsigned long long RcvHdrAddr0;
122 unsigned long long RcvHdrAddr1;
123 unsigned long long RcvHdrAddr2;
124 unsigned long long RcvHdrAddr3;
125 unsigned long long RcvHdrAddr4;
126 unsigned long long RcvHdrAddr5;
127 unsigned long long RcvHdrAddr6;
128 unsigned long long RcvHdrAddr7;
129 unsigned long long RcvHdrAddr8;
130 unsigned long long ReservedRHA[7];
131 unsigned long long RcvHdrTailAddr0;
132 unsigned long long RcvHdrTailAddr1;
133 unsigned long long RcvHdrTailAddr2;
134 unsigned long long RcvHdrTailAddr3;
135 unsigned long long RcvHdrTailAddr4;
136 unsigned long long RcvHdrTailAddr5;
137 unsigned long long RcvHdrTailAddr6;
138 unsigned long long RcvHdrTailAddr7;
139 unsigned long long RcvHdrTailAddr8;
140 unsigned long long ReservedRHTA[7];
141 unsigned long long Sync; /* Software only */
142 unsigned long long Dump; /* Software only */
143 unsigned long long SimVer; /* Software only */
144 unsigned long long ReservedSW[5];
145 unsigned long long SerdesConfig0;
146 unsigned long long SerdesConfig1;
147 unsigned long long SerdesStatus;
148 unsigned long long XGXSConfig;
149 unsigned long long ReservedSW2[4];
150 };
151
152 struct _infinipath_do_not_use_counters {
153 __u64 LBIntCnt;
154 __u64 LBFlowStallCnt;
155 __u64 Reserved1;
156 __u64 TxUnsupVLErrCnt;
157 __u64 TxDataPktCnt;
158 __u64 TxFlowPktCnt;
159 __u64 TxDwordCnt;
160 __u64 TxLenErrCnt;
161 __u64 TxMaxMinLenErrCnt;
162 __u64 TxUnderrunCnt;
163 __u64 TxFlowStallCnt;
164 __u64 TxDroppedPktCnt;
165 __u64 RxDroppedPktCnt;
166 __u64 RxDataPktCnt;
167 __u64 RxFlowPktCnt;
168 __u64 RxDwordCnt;
169 __u64 RxLenErrCnt;
170 __u64 RxMaxMinLenErrCnt;
171 __u64 RxICRCErrCnt;
172 __u64 RxVCRCErrCnt;
173 __u64 RxFlowCtrlErrCnt;
174 __u64 RxBadFormatCnt;
175 __u64 RxLinkProblemCnt;
176 __u64 RxEBPCnt;
177 __u64 RxLPCRCErrCnt;
178 __u64 RxBufOvflCnt;
179 __u64 RxTIDFullErrCnt;
180 __u64 RxTIDValidErrCnt;
181 __u64 RxPKeyMismatchCnt;
182 __u64 RxP0HdrEgrOvflCnt;
183 __u64 RxP1HdrEgrOvflCnt;
184 __u64 RxP2HdrEgrOvflCnt;
185 __u64 RxP3HdrEgrOvflCnt;
186 __u64 RxP4HdrEgrOvflCnt;
187 __u64 RxP5HdrEgrOvflCnt;
188 __u64 RxP6HdrEgrOvflCnt;
189 __u64 RxP7HdrEgrOvflCnt;
190 __u64 RxP8HdrEgrOvflCnt;
191 __u64 Reserved6;
192 __u64 Reserved7;
193 __u64 IBStatusChangeCnt;
194 __u64 IBLinkErrRecoveryCnt;
195 __u64 IBLinkDownedCnt;
196 __u64 IBSymbolErrCnt;
197 };
198
199 #define IPATH_KREG_OFFSET(field) (offsetof( \
200 struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
201 #define IPATH_CREG_OFFSET(field) (offsetof( \
202 struct _infinipath_do_not_use_counters, field) / sizeof(u64))
203
204 static const struct ipath_kregs ipath_ht_kregs = {
205 .kr_control = IPATH_KREG_OFFSET(Control),
206 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
207 .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
208 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
209 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
210 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
211 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
212 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
213 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
214 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
215 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
216 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
217 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
218 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
219 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
220 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
221 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
222 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
223 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
224 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
225 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
226 .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
227 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
228 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
229 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
230 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
231 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
232 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
233 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
234 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
235 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
236 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
237 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
238 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
239 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
240 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
241 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
242 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
243 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
244 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
245 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
246 .kr_revision = IPATH_KREG_OFFSET(Revision),
247 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
248 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
249 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
250 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
251 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
252 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
253 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
254 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
255 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
256 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
257 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
258 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
259 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
260 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
261 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
262 /*
263 * These should not be used directly via ipath_write_kreg64(),
264 * use them with ipath_write_kreg64_port(),
265 */
266 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
267 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
268 };
269
270 static const struct ipath_cregs ipath_ht_cregs = {
271 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
272 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
273 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
274 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
275 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
276 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
277 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
278 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
279 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
280 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
281 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
282 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
283 /* calc from Reg_CounterRegBase + offset */
284 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
285 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
286 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
287 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
288 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
289 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
290 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
291 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
292 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
293 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
294 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
295 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
296 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
297 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
298 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
299 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
300 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
301 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
302 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
303 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
304 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
305 };
306
307 /* kr_intstatus, kr_intclear, kr_intmask bits */
308 #define INFINIPATH_I_RCVURG_MASK ((1U<<9)-1)
309 #define INFINIPATH_I_RCVURG_SHIFT 0
310 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<9)-1)
311 #define INFINIPATH_I_RCVAVAIL_SHIFT 12
312
313 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
314 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
315 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
316 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR 0x0000000000800000ULL
317 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR 0x0000000001000000ULL
318 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR 0x0000000002000000ULL
319 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR 0x0000000004000000ULL
320 #define INFINIPATH_HWE_HTCMISCERR4 0x0000000008000000ULL
321 #define INFINIPATH_HWE_HTCMISCERR5 0x0000000010000000ULL
322 #define INFINIPATH_HWE_HTCMISCERR6 0x0000000020000000ULL
323 #define INFINIPATH_HWE_HTCMISCERR7 0x0000000040000000ULL
324 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR 0x0000000080000000ULL
325 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
326 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR 0x0000000200000000ULL
327 #define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
328 #define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
329 #define INFINIPATH_HWE_HTBPLL_FBSLIP 0x0200000000000000ULL
330 #define INFINIPATH_HWE_HTBPLL_RFSLIP 0x0400000000000000ULL
331 #define INFINIPATH_HWE_HTAPLL_FBSLIP 0x0800000000000000ULL
332 #define INFINIPATH_HWE_HTAPLL_RFSLIP 0x1000000000000000ULL
333 #define INFINIPATH_HWE_SERDESPLLFAILED 0x2000000000000000ULL
334
335 #define IBA6110_IBCS_LINKTRAININGSTATE_MASK 0xf
336 #define IBA6110_IBCS_LINKSTATE_SHIFT 4
337
338 /* kr_extstatus bits */
339 #define INFINIPATH_EXTS_FREQSEL 0x2
340 #define INFINIPATH_EXTS_SERDESSEL 0x4
341 #define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
342 #define INFINIPATH_EXTS_MEMBIST_CORRECT 0x0000000000008000
343
344
345 /* TID entries (memory), HT-only */
346 #define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */
347 #define INFINIPATH_RT_VALID 0x8000000000000000ULL
348 #define INFINIPATH_RT_ADDR_SHIFT 0
349 #define INFINIPATH_RT_BUFSIZE_MASK 0x3FFFULL
350 #define INFINIPATH_RT_BUFSIZE_SHIFT 48
351
352 #define INFINIPATH_R_INTRAVAIL_SHIFT 16
353 #define INFINIPATH_R_TAILUPD_SHIFT 31
354
355 /* kr_xgxsconfig bits */
356 #define INFINIPATH_XGXS_RESET 0x7ULL
357
358 /*
359 * masks and bits that are different in different chips, or present only
360 * in one
361 */
362 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
363 INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
364 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
365 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
366
367 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
368 INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
369 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
370 INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
371 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
372 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
373 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
374 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
375
376 #define _IPATH_GPIO_SDA_NUM 1
377 #define _IPATH_GPIO_SCL_NUM 0
378
379 #define IPATH_GPIO_SDA \
380 (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
381 #define IPATH_GPIO_SCL \
382 (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
383
384 /* keep the code below somewhat more readable; not used elsewhere */
385 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \
386 infinipath_hwe_htclnkabyte1crcerr)
387 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr | \
388 infinipath_hwe_htclnkbbyte1crcerr)
389 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \
390 infinipath_hwe_htclnkbbyte0crcerr)
391 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr | \
392 infinipath_hwe_htclnkbbyte1crcerr)
393
hwerr_crcbits(struct ipath_devdata * dd,ipath_err_t hwerrs,char * msg,size_t msgl)394 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
395 char *msg, size_t msgl)
396 {
397 char bitsmsg[64];
398 ipath_err_t crcbits = hwerrs &
399 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
400 /* don't check if 8bit HT */
401 if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
402 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
403 /* don't check if 8bit HT */
404 if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
405 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
406 /*
407 * we'll want to ignore link errors on link that is
408 * not in use, if any. For now, complain about both
409 */
410 if (crcbits) {
411 u16 ctrl0, ctrl1;
412 snprintf(bitsmsg, sizeof bitsmsg,
413 "[HT%s lane %s CRC (%llx); powercycle to completely clear]",
414 !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
415 "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
416 ? "1 (B)" : "0+1 (A+B)"),
417 !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
418 : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
419 "0+1"), (unsigned long long) crcbits);
420 strlcat(msg, bitsmsg, msgl);
421
422 /*
423 * print extra info for debugging. slave/primary
424 * config word 4, 8 (link control 0, 1)
425 */
426
427 if (pci_read_config_word(dd->pcidev,
428 dd->ipath_ht_slave_off + 0x4,
429 &ctrl0))
430 dev_info(&dd->pcidev->dev, "Couldn't read "
431 "linkctrl0 of slave/primary "
432 "config block\n");
433 else if (!(ctrl0 & 1 << 6))
434 /* not if EOC bit set */
435 ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
436 ((ctrl0 >> 8) & 7) ? " CRC" : "",
437 ((ctrl0 >> 4) & 1) ? "linkfail" :
438 "");
439 if (pci_read_config_word(dd->pcidev,
440 dd->ipath_ht_slave_off + 0x8,
441 &ctrl1))
442 dev_info(&dd->pcidev->dev, "Couldn't read "
443 "linkctrl1 of slave/primary "
444 "config block\n");
445 else if (!(ctrl1 & 1 << 6))
446 /* not if EOC bit set */
447 ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
448 ((ctrl1 >> 8) & 7) ? " CRC" : "",
449 ((ctrl1 >> 4) & 1) ? "linkfail" :
450 "");
451
452 /* disable until driver reloaded */
453 dd->ipath_hwerrmask &= ~crcbits;
454 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
455 dd->ipath_hwerrmask);
456 ipath_dbg("HT crc errs: %s\n", msg);
457 } else
458 ipath_dbg("ignoring HT crc errors 0x%llx, "
459 "not in use\n", (unsigned long long)
460 (hwerrs & (_IPATH_HTLINK0_CRCBITS |
461 _IPATH_HTLINK1_CRCBITS)));
462 }
463
464 /* 6110 specific hardware errors... */
465 static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = {
466 INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"),
467 INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"),
468 INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"),
469 INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"),
470 INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"),
471 INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"),
472 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
473 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
474 };
475
476 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
477 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
478 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
479 #define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \
480 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)
481
ipath_ht_txe_recover(struct ipath_devdata * dd)482 static void ipath_ht_txe_recover(struct ipath_devdata *dd)
483 {
484 ++ipath_stats.sps_txeparity;
485 dev_info(&dd->pcidev->dev,
486 "Recovering from TXE PIO parity error\n");
487 }
488
489
490 /**
491 * ipath_ht_handle_hwerrors - display hardware errors.
492 * @dd: the infinipath device
493 * @msg: the output buffer
494 * @msgl: the size of the output buffer
495 *
496 * Use same msg buffer as regular errors to avoid excessive stack
497 * use. Most hardware errors are catastrophic, but for right now,
498 * we'll print them and continue. We reuse the same message buffer as
499 * ipath_handle_errors() to avoid excessive stack usage.
500 */
ipath_ht_handle_hwerrors(struct ipath_devdata * dd,char * msg,size_t msgl)501 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
502 size_t msgl)
503 {
504 ipath_err_t hwerrs;
505 u32 bits, ctrl;
506 int isfatal = 0;
507 char bitsmsg[64];
508 int log_idx;
509
510 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
511
512 if (!hwerrs) {
513 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
514 /*
515 * better than printing cofusing messages
516 * This seems to be related to clearing the crc error, or
517 * the pll error during init.
518 */
519 goto bail;
520 } else if (hwerrs == -1LL) {
521 ipath_dev_err(dd, "Read of hardware error status failed "
522 "(all bits set); ignoring\n");
523 goto bail;
524 }
525 ipath_stats.sps_hwerrs++;
526
527 /* Always clear the error status register, except MEMBISTFAIL,
528 * regardless of whether we continue or stop using the chip.
529 * We want that set so we know it failed, even across driver reload.
530 * We'll still ignore it in the hwerrmask. We do this partly for
531 * diagnostics, but also for support */
532 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
533 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
534
535 hwerrs &= dd->ipath_hwerrmask;
536
537 /* We log some errors to EEPROM, check if we have any of those. */
538 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
539 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
540 ipath_inc_eeprom_err(dd, log_idx, 1);
541
542 /*
543 * make sure we get this much out, unless told to be quiet,
544 * it's a parity error we may recover from,
545 * or it's occurred within the last 5 seconds
546 */
547 if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY |
548 RXE_EAGER_PARITY)) ||
549 (ipath_debug & __IPATH_VERBDBG))
550 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
551 "(cleared)\n", (unsigned long long) hwerrs);
552 dd->ipath_lasthwerror |= hwerrs;
553
554 if (hwerrs & ~dd->ipath_hwe_bitsextant)
555 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
556 "%llx set\n", (unsigned long long)
557 (hwerrs & ~dd->ipath_hwe_bitsextant));
558
559 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
560 if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
561 /*
562 * parity errors in send memory are recoverable,
563 * just cancel the send (if indicated in * sendbuffererror),
564 * count the occurrence, unfreeze (if no other handled
565 * hardware error bits are set), and continue. They can
566 * occur if a processor speculative read is done to the PIO
567 * buffer while we are sending a packet, for example.
568 */
569 if (hwerrs & TXE_PIO_PARITY) {
570 ipath_ht_txe_recover(dd);
571 hwerrs &= ~TXE_PIO_PARITY;
572 }
573
574 if (!hwerrs) {
575 ipath_dbg("Clearing freezemode on ignored or "
576 "recovered hardware error\n");
577 ipath_clear_freeze(dd);
578 }
579 }
580
581 *msg = '\0';
582
583 /*
584 * may someday want to decode into which bits are which
585 * functional area for parity errors, etc.
586 */
587 if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
588 << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
589 bits = (u32) ((hwerrs >>
590 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
591 INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
592 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
593 bits);
594 strlcat(msg, bitsmsg, msgl);
595 }
596
597 ipath_format_hwerrors(hwerrs,
598 ipath_6110_hwerror_msgs,
599 ARRAY_SIZE(ipath_6110_hwerror_msgs),
600 msg, msgl);
601
602 if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
603 hwerr_crcbits(dd, hwerrs, msg, msgl);
604
605 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
606 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
607 msgl);
608 /* ignore from now on, so disable until driver reloaded */
609 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
610 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
611 dd->ipath_hwerrmask);
612 }
613 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
614 INFINIPATH_HWE_COREPLL_RFSLIP | \
615 INFINIPATH_HWE_HTBPLL_FBSLIP | \
616 INFINIPATH_HWE_HTBPLL_RFSLIP | \
617 INFINIPATH_HWE_HTAPLL_FBSLIP | \
618 INFINIPATH_HWE_HTAPLL_RFSLIP)
619
620 if (hwerrs & _IPATH_PLL_FAIL) {
621 snprintf(bitsmsg, sizeof bitsmsg,
622 "[PLL failed (%llx), InfiniPath hardware unusable]",
623 (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
624 strlcat(msg, bitsmsg, msgl);
625 /* ignore from now on, so disable until driver reloaded */
626 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
627 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
628 dd->ipath_hwerrmask);
629 }
630
631 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
632 /*
633 * If it occurs, it is left masked since the eternal
634 * interface is unused
635 */
636 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
637 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
638 dd->ipath_hwerrmask);
639 }
640
641 if (hwerrs) {
642 /*
643 * if any set that we aren't ignoring; only
644 * make the complaint once, in case it's stuck
645 * or recurring, and we get here multiple
646 * times.
647 * force link down, so switch knows, and
648 * LEDs are turned off
649 */
650 if (dd->ipath_flags & IPATH_INITTED) {
651 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
652 ipath_setup_ht_setextled(dd,
653 INFINIPATH_IBCS_L_STATE_DOWN,
654 INFINIPATH_IBCS_LT_STATE_DISABLED);
655 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
656 "mode), no longer usable, SN %.16s\n",
657 dd->ipath_serial);
658 isfatal = 1;
659 }
660 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
661 /* mark as having had error */
662 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
663 /*
664 * mark as not usable, at a minimum until driver
665 * is reloaded, probably until reboot, since no
666 * other reset is possible.
667 */
668 dd->ipath_flags &= ~IPATH_INITTED;
669 } else {
670 *msg = 0; /* recovered from all of them */
671 }
672 if (*msg)
673 ipath_dev_err(dd, "%s hardware error\n", msg);
674 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
675 /*
676 * for status file; if no trailing brace is copied,
677 * we'll know it was truncated.
678 */
679 snprintf(dd->ipath_freezemsg,
680 dd->ipath_freezelen, "{%s}", msg);
681
682 bail:;
683 }
684
685 /**
686 * ipath_ht_boardname - fill in the board name
687 * @dd: the infinipath device
688 * @name: the output buffer
689 * @namelen: the size of the output buffer
690 *
691 * fill in the board name, based on the board revision register
692 */
ipath_ht_boardname(struct ipath_devdata * dd,char * name,size_t namelen)693 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
694 size_t namelen)
695 {
696 char *n = NULL;
697 u8 boardrev = dd->ipath_boardrev;
698 int ret = 0;
699
700 switch (boardrev) {
701 case 5:
702 /*
703 * original production board; two production levels, with
704 * different serial number ranges. See ipath_ht_early_init() for
705 * case where we enable IPATH_GPIO_INTR for later serial # range.
706 * Original 112* serial number is no longer supported.
707 */
708 n = "InfiniPath_QHT7040";
709 break;
710 case 7:
711 /* small form factor production board */
712 n = "InfiniPath_QHT7140";
713 break;
714 default: /* don't know, just print the number */
715 ipath_dev_err(dd, "Don't yet know about board "
716 "with ID %u\n", boardrev);
717 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u",
718 boardrev);
719 break;
720 }
721 if (n)
722 snprintf(name, namelen, "%s", n);
723
724 if (ret) {
725 ipath_dev_err(dd, "Unsupported InfiniPath board %s!\n", name);
726 goto bail;
727 }
728 if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 ||
729 dd->ipath_minrev > 4)) {
730 /*
731 * This version of the driver only supports Rev 3.2 - 3.4
732 */
733 ipath_dev_err(dd,
734 "Unsupported InfiniPath hardware revision %u.%u!\n",
735 dd->ipath_majrev, dd->ipath_minrev);
736 ret = 1;
737 goto bail;
738 }
739 /*
740 * pkt/word counters are 32 bit, and therefore wrap fast enough
741 * that we snapshot them from a timer, and maintain 64 bit shadow
742 * copies
743 */
744 dd->ipath_flags |= IPATH_32BITCOUNTERS;
745 dd->ipath_flags |= IPATH_GPIO_INTR;
746 if (dd->ipath_lbus_speed != 800)
747 ipath_dev_err(dd,
748 "Incorrectly configured for HT @ %uMHz\n",
749 dd->ipath_lbus_speed);
750
751 /*
752 * set here, not in ipath_init_*_funcs because we have to do
753 * it after we can read chip registers.
754 */
755 dd->ipath_ureg_align =
756 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
757
758 bail:
759 return ret;
760 }
761
ipath_check_htlink(struct ipath_devdata * dd)762 static void ipath_check_htlink(struct ipath_devdata *dd)
763 {
764 u8 linkerr, link_off, i;
765
766 for (i = 0; i < 2; i++) {
767 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
768 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
769 dev_info(&dd->pcidev->dev, "Couldn't read "
770 "linkerror%d of HT slave/primary block\n",
771 i);
772 else if (linkerr & 0xf0) {
773 ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
774 "clearing\n", linkerr >> 4, i);
775 /*
776 * writing the linkerr bits that are set should
777 * clear them
778 */
779 if (pci_write_config_byte(dd->pcidev, link_off,
780 linkerr))
781 ipath_dbg("Failed write to clear HT "
782 "linkerror%d\n", i);
783 if (pci_read_config_byte(dd->pcidev, link_off,
784 &linkerr))
785 dev_info(&dd->pcidev->dev,
786 "Couldn't reread linkerror%d of "
787 "HT slave/primary block\n", i);
788 else if (linkerr & 0xf0)
789 dev_info(&dd->pcidev->dev,
790 "HT linkerror%d bits 0x%x "
791 "couldn't be cleared\n",
792 i, linkerr >> 4);
793 }
794 }
795 }
796
ipath_setup_ht_reset(struct ipath_devdata * dd)797 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
798 {
799 ipath_dbg("No reset possible for this InfiniPath hardware\n");
800 return 0;
801 }
802
803 #define HT_INTR_DISC_CONFIG 0x80 /* HT interrupt and discovery cap */
804 #define HT_INTR_REG_INDEX 2 /* intconfig requires indirect accesses */
805
806 /*
807 * Bits 13-15 of command==0 is slave/primary block. Clear any HT CRC
808 * errors. We only bother to do this at load time, because it's OK if
809 * it happened before we were loaded (first time after boot/reset),
810 * but any time after that, it's fatal anyway. Also need to not check
811 * for upper byte errors if we are in 8 bit mode, so figure out
812 * our width. For now, at least, also complain if it's 8 bit.
813 */
slave_or_pri_blk(struct ipath_devdata * dd,struct pci_dev * pdev,int pos,u8 cap_type)814 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
815 int pos, u8 cap_type)
816 {
817 u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
818 u16 linkctrl = 0;
819 int i;
820
821 dd->ipath_ht_slave_off = pos;
822 /* command word, master_host bit */
823 /* master host || slave */
824 if ((cap_type >> 2) & 1)
825 link_a_b_off = 4;
826 else
827 link_a_b_off = 0;
828 ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
829 link_a_b_off ? 1 : 0,
830 link_a_b_off ? 'B' : 'A');
831
832 link_a_b_off += pos;
833
834 /*
835 * check both link control registers; clear both HT CRC sets if
836 * necessary.
837 */
838 for (i = 0; i < 2; i++) {
839 link_off = pos + i * 4 + 0x4;
840 if (pci_read_config_word(pdev, link_off, &linkctrl))
841 ipath_dev_err(dd, "Couldn't read HT link control%d "
842 "register\n", i);
843 else if (linkctrl & (0xf << 8)) {
844 ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
845 "bits %x\n", i, linkctrl & (0xf << 8));
846 /*
847 * now write them back to clear the error.
848 */
849 pci_write_config_word(pdev, link_off,
850 linkctrl & (0xf << 8));
851 }
852 }
853
854 /*
855 * As with HT CRC bits, same for protocol errors that might occur
856 * during boot.
857 */
858 for (i = 0; i < 2; i++) {
859 link_off = pos + i * 4 + 0xd;
860 if (pci_read_config_byte(pdev, link_off, &linkerr))
861 dev_info(&pdev->dev, "Couldn't read linkerror%d "
862 "of HT slave/primary block\n", i);
863 else if (linkerr & 0xf0) {
864 ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
865 "clearing\n", linkerr >> 4, i);
866 /*
867 * writing the linkerr bits that are set will clear
868 * them
869 */
870 if (pci_write_config_byte
871 (pdev, link_off, linkerr))
872 ipath_dbg("Failed write to clear HT "
873 "linkerror%d\n", i);
874 if (pci_read_config_byte(pdev, link_off, &linkerr))
875 dev_info(&pdev->dev, "Couldn't reread "
876 "linkerror%d of HT slave/primary "
877 "block\n", i);
878 else if (linkerr & 0xf0)
879 dev_info(&pdev->dev, "HT linkerror%d bits "
880 "0x%x couldn't be cleared\n",
881 i, linkerr >> 4);
882 }
883 }
884
885 /*
886 * this is just for our link to the host, not devices connected
887 * through tunnel.
888 */
889
890 if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
891 ipath_dev_err(dd, "Couldn't read HT link width "
892 "config register\n");
893 else {
894 u32 width;
895 switch (linkwidth & 7) {
896 case 5:
897 width = 4;
898 break;
899 case 4:
900 width = 2;
901 break;
902 case 3:
903 width = 32;
904 break;
905 case 1:
906 width = 16;
907 break;
908 case 0:
909 default: /* if wrong, assume 8 bit */
910 width = 8;
911 break;
912 }
913
914 dd->ipath_lbus_width = width;
915
916 if (linkwidth != 0x11) {
917 ipath_dev_err(dd, "Not configured for 16 bit HT "
918 "(%x)\n", linkwidth);
919 if (!(linkwidth & 0xf)) {
920 ipath_dbg("Will ignore HT lane1 errors\n");
921 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
922 }
923 }
924 }
925
926 /*
927 * this is just for our link to the host, not devices connected
928 * through tunnel.
929 */
930 if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
931 ipath_dev_err(dd, "Couldn't read HT link frequency "
932 "config register\n");
933 else {
934 u32 speed;
935 switch (linkwidth & 0xf) {
936 case 6:
937 speed = 1000;
938 break;
939 case 5:
940 speed = 800;
941 break;
942 case 4:
943 speed = 600;
944 break;
945 case 3:
946 speed = 500;
947 break;
948 case 2:
949 speed = 400;
950 break;
951 case 1:
952 speed = 300;
953 break;
954 default:
955 /*
956 * assume reserved and vendor-specific are 200...
957 */
958 case 0:
959 speed = 200;
960 break;
961 }
962 dd->ipath_lbus_speed = speed;
963 }
964
965 snprintf(dd->ipath_lbus_info, sizeof(dd->ipath_lbus_info),
966 "HyperTransport,%uMHz,x%u\n",
967 dd->ipath_lbus_speed,
968 dd->ipath_lbus_width);
969 }
970
ipath_ht_intconfig(struct ipath_devdata * dd)971 static int ipath_ht_intconfig(struct ipath_devdata *dd)
972 {
973 int ret;
974
975 if (dd->ipath_intconfig) {
976 ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
977 dd->ipath_intconfig); /* interrupt address */
978 ret = 0;
979 } else {
980 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
981 "interrupt address\n");
982 ret = -EINVAL;
983 }
984
985 return ret;
986 }
987
ipath_ht_irq_update(struct pci_dev * dev,int irq,struct ht_irq_msg * msg)988 static void ipath_ht_irq_update(struct pci_dev *dev, int irq,
989 struct ht_irq_msg *msg)
990 {
991 struct ipath_devdata *dd = pci_get_drvdata(dev);
992 u64 prev_intconfig = dd->ipath_intconfig;
993
994 dd->ipath_intconfig = msg->address_lo;
995 dd->ipath_intconfig |= ((u64) msg->address_hi) << 32;
996
997 /*
998 * If the previous value of dd->ipath_intconfig is zero, we're
999 * getting configured for the first time, and must not program the
1000 * intconfig register here (it will be programmed later, when the
1001 * hardware is ready). Otherwise, we should.
1002 */
1003 if (prev_intconfig)
1004 ipath_ht_intconfig(dd);
1005 }
1006
1007 /**
1008 * ipath_setup_ht_config - setup the interruptconfig register
1009 * @dd: the infinipath device
1010 * @pdev: the PCI device
1011 *
1012 * setup the interruptconfig register from the HT config info.
1013 * Also clear CRC errors in HT linkcontrol, if necessary.
1014 * This is done only for the real hardware. It is done before
1015 * chip address space is initted, so can't touch infinipath registers
1016 */
ipath_setup_ht_config(struct ipath_devdata * dd,struct pci_dev * pdev)1017 static int ipath_setup_ht_config(struct ipath_devdata *dd,
1018 struct pci_dev *pdev)
1019 {
1020 int pos, ret;
1021
1022 ret = __ht_create_irq(pdev, 0, ipath_ht_irq_update);
1023 if (ret < 0) {
1024 ipath_dev_err(dd, "Couldn't create interrupt handler: "
1025 "err %d\n", ret);
1026 goto bail;
1027 }
1028 dd->ipath_irq = ret;
1029 ret = 0;
1030
1031 /*
1032 * Handle clearing CRC errors in linkctrl register if necessary. We
1033 * do this early, before we ever enable errors or hardware errors,
1034 * mostly to avoid causing the chip to enter freeze mode.
1035 */
1036 pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
1037 if (!pos) {
1038 ipath_dev_err(dd, "Couldn't find HyperTransport "
1039 "capability; no interrupts\n");
1040 ret = -ENODEV;
1041 goto bail;
1042 }
1043 do {
1044 u8 cap_type;
1045
1046 /*
1047 * The HT capability type byte is 3 bytes after the
1048 * capability byte.
1049 */
1050 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
1051 dev_info(&pdev->dev, "Couldn't read config "
1052 "command @ %d\n", pos);
1053 continue;
1054 }
1055 if (!(cap_type & 0xE0))
1056 slave_or_pri_blk(dd, pdev, pos, cap_type);
1057 } while ((pos = pci_find_next_capability(pdev, pos,
1058 PCI_CAP_ID_HT)));
1059
1060 dd->ipath_flags |= IPATH_SWAP_PIOBUFS;
1061
1062 bail:
1063 return ret;
1064 }
1065
1066 /**
1067 * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
1068 * @dd: the infinipath device
1069 *
1070 * Called during driver unload.
1071 * This is currently a nop for the HT chip, not for all chips
1072 */
ipath_setup_ht_cleanup(struct ipath_devdata * dd)1073 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
1074 {
1075 }
1076
1077 /**
1078 * ipath_setup_ht_setextled - set the state of the two external LEDs
1079 * @dd: the infinipath device
1080 * @lst: the L state
1081 * @ltst: the LT state
1082 *
1083 * Set the state of the two external LEDs, to indicate physical and
1084 * logical state of IB link. For this chip (at least with recommended
1085 * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1086 * (logical state)
1087 *
1088 * Note: We try to match the Mellanox HCA LED behavior as best
1089 * we can. Green indicates physical link state is OK (something is
1090 * plugged in, and we can train).
1091 * Amber indicates the link is logically up (ACTIVE).
1092 * Mellanox further blinks the amber LED to indicate data packet
1093 * activity, but we have no hardware support for that, so it would
1094 * require waking up every 10-20 msecs and checking the counters
1095 * on the chip, and then turning the LED off if appropriate. That's
1096 * visible overhead, so not something we will do.
1097 *
1098 */
ipath_setup_ht_setextled(struct ipath_devdata * dd,u64 lst,u64 ltst)1099 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1100 u64 lst, u64 ltst)
1101 {
1102 u64 extctl;
1103 unsigned long flags = 0;
1104
1105 /* the diags use the LED to indicate diag info, so we leave
1106 * the external LED alone when the diags are running */
1107 if (ipath_diag_inuse)
1108 return;
1109
1110 /* Allow override of LED display for, e.g. Locating system in rack */
1111 if (dd->ipath_led_override) {
1112 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
1113 ? INFINIPATH_IBCS_LT_STATE_LINKUP
1114 : INFINIPATH_IBCS_LT_STATE_DISABLED;
1115 lst = (dd->ipath_led_override & IPATH_LED_LOG)
1116 ? INFINIPATH_IBCS_L_STATE_ACTIVE
1117 : INFINIPATH_IBCS_L_STATE_DOWN;
1118 }
1119
1120 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
1121 /*
1122 * start by setting both LED control bits to off, then turn
1123 * on the appropriate bit(s).
1124 */
1125 if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1126 /*
1127 * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1128 * is inverted, because it is normally used to indicate
1129 * a hardware fault at reset, if there were errors
1130 */
1131 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1132 | INFINIPATH_EXTC_LEDGBLERR_OFF;
1133 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1134 extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1135 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1136 extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1137 } else {
1138 extctl = dd->ipath_extctrl &
1139 ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1140 INFINIPATH_EXTC_LED2PRIPORT_ON);
1141 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1142 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1143 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1144 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1145 }
1146 dd->ipath_extctrl = extctl;
1147 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1148 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
1149 }
1150
ipath_init_ht_variables(struct ipath_devdata * dd)1151 static void ipath_init_ht_variables(struct ipath_devdata *dd)
1152 {
1153 /*
1154 * setup the register offsets, since they are different for each
1155 * chip
1156 */
1157 dd->ipath_kregs = &ipath_ht_kregs;
1158 dd->ipath_cregs = &ipath_ht_cregs;
1159
1160 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1161 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1162 dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1163 dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1164
1165 /*
1166 * Fill in data for field-values that change in newer chips.
1167 * We dynamically specify only the mask for LINKTRAININGSTATE
1168 * and only the shift for LINKSTATE, as they are the only ones
1169 * that change. Also precalculate the 3 link states of interest
1170 * and the combined mask.
1171 */
1172 dd->ibcs_ls_shift = IBA6110_IBCS_LINKSTATE_SHIFT;
1173 dd->ibcs_lts_mask = IBA6110_IBCS_LINKTRAININGSTATE_MASK;
1174 dd->ibcs_mask = (INFINIPATH_IBCS_LINKSTATE_MASK <<
1175 dd->ibcs_ls_shift) | dd->ibcs_lts_mask;
1176 dd->ib_init = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1177 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1178 (INFINIPATH_IBCS_L_STATE_INIT << dd->ibcs_ls_shift);
1179 dd->ib_arm = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1180 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1181 (INFINIPATH_IBCS_L_STATE_ARM << dd->ibcs_ls_shift);
1182 dd->ib_active = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1183 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1184 (INFINIPATH_IBCS_L_STATE_ACTIVE << dd->ibcs_ls_shift);
1185
1186 /*
1187 * Fill in data for ibcc field-values that change in newer chips.
1188 * We dynamically specify only the mask for LINKINITCMD
1189 * and only the shift for LINKCMD and MAXPKTLEN, as they are
1190 * the only ones that change.
1191 */
1192 dd->ibcc_lic_mask = INFINIPATH_IBCC_LINKINITCMD_MASK;
1193 dd->ibcc_lc_shift = INFINIPATH_IBCC_LINKCMD_SHIFT;
1194 dd->ibcc_mpl_shift = INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
1195
1196 /* Fill in shifts for RcvCtrl. */
1197 dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
1198 dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT;
1199 dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT;
1200 dd->ipath_r_portcfg_shift = 0; /* Not on IBA6110 */
1201
1202 dd->ipath_i_bitsextant =
1203 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1204 (INFINIPATH_I_RCVAVAIL_MASK <<
1205 INFINIPATH_I_RCVAVAIL_SHIFT) |
1206 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1207 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1208
1209 dd->ipath_e_bitsextant =
1210 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1211 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1212 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1213 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1214 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1215 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1216 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1217 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1218 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1219 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1220 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1221 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1222 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1223 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1224 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1225 INFINIPATH_E_HARDWARE;
1226
1227 dd->ipath_hwe_bitsextant =
1228 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1229 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1230 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1231 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1232 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1233 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1234 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1235 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1236 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1237 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1238 INFINIPATH_HWE_HTCMISCERR4 |
1239 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1240 INFINIPATH_HWE_HTCMISCERR7 |
1241 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1242 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1243 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1244 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1245 INFINIPATH_HWE_MEMBISTFAILED |
1246 INFINIPATH_HWE_COREPLL_FBSLIP |
1247 INFINIPATH_HWE_COREPLL_RFSLIP |
1248 INFINIPATH_HWE_HTBPLL_FBSLIP |
1249 INFINIPATH_HWE_HTBPLL_RFSLIP |
1250 INFINIPATH_HWE_HTAPLL_FBSLIP |
1251 INFINIPATH_HWE_HTAPLL_RFSLIP |
1252 INFINIPATH_HWE_SERDESPLLFAILED |
1253 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1254 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1255
1256 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1257 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1258 dd->ipath_i_rcvavail_shift = INFINIPATH_I_RCVAVAIL_SHIFT;
1259 dd->ipath_i_rcvurg_shift = INFINIPATH_I_RCVURG_SHIFT;
1260
1261 /*
1262 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1263 * 2 is Some Misc, 3 is reserved for future.
1264 */
1265 dd->ipath_eep_st_masks[0].hwerrs_to_log =
1266 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1267 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1268
1269 dd->ipath_eep_st_masks[1].hwerrs_to_log =
1270 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1271 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1272
1273 dd->ipath_eep_st_masks[2].errs_to_log = INFINIPATH_E_RESET;
1274
1275 dd->delay_mult = 2; /* SDR, 4X, can't change */
1276
1277 dd->ipath_link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
1278 dd->ipath_link_speed_supported = IPATH_IB_SDR;
1279 dd->ipath_link_width_enabled = IB_WIDTH_4X;
1280 dd->ipath_link_speed_enabled = dd->ipath_link_speed_supported;
1281 /* these can't change for this chip, so set once */
1282 dd->ipath_link_width_active = dd->ipath_link_width_enabled;
1283 dd->ipath_link_speed_active = dd->ipath_link_speed_enabled;
1284 }
1285
1286 /**
1287 * ipath_ht_init_hwerrors - enable hardware errors
1288 * @dd: the infinipath device
1289 *
1290 * now that we have finished initializing everything that might reasonably
1291 * cause a hardware error, and cleared those errors bits as they occur,
1292 * we can enable hardware errors in the mask (potentially enabling
1293 * freeze mode), and enable hardware errors as errors (along with
1294 * everything else) in errormask
1295 */
ipath_ht_init_hwerrors(struct ipath_devdata * dd)1296 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1297 {
1298 ipath_err_t val;
1299 u64 extsval;
1300
1301 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1302
1303 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1304 ipath_dev_err(dd, "MemBIST did not complete!\n");
1305 if (extsval & INFINIPATH_EXTS_MEMBIST_CORRECT)
1306 ipath_dbg("MemBIST corrected\n");
1307
1308 ipath_check_htlink(dd);
1309
1310 /* barring bugs, all hwerrors become interrupts, which can */
1311 val = -1LL;
1312 /* don't look at crc lane1 if 8 bit */
1313 if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1314 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1315 /* don't look at crc lane1 if 8 bit */
1316 if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1317 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1318
1319 /*
1320 * disable RXDSYNCMEMPARITY because external serdes is unused,
1321 * and therefore the logic will never be used or initialized,
1322 * and uninitialized state will normally result in this error
1323 * being asserted. Similarly for the external serdess pll
1324 * lock signal.
1325 */
1326 val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1327 INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1328
1329 /*
1330 * Disable MISCERR4 because of an inversion in the HT core
1331 * logic checking for errors that cause this bit to be set.
1332 * The errata can also cause the protocol error bit to be set
1333 * in the HT config space linkerror register(s).
1334 */
1335 val &= ~INFINIPATH_HWE_HTCMISCERR4;
1336
1337 /*
1338 * PLL ignored because unused MDIO interface has a logic problem
1339 */
1340 if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1341 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1342 dd->ipath_hwerrmask = val;
1343 }
1344
1345
1346
1347
1348 /**
1349 * ipath_ht_bringup_serdes - bring up the serdes
1350 * @dd: the infinipath device
1351 */
ipath_ht_bringup_serdes(struct ipath_devdata * dd)1352 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1353 {
1354 u64 val, config1;
1355 int ret = 0, change = 0;
1356
1357 ipath_dbg("Trying to bringup serdes\n");
1358
1359 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1360 INFINIPATH_HWE_SERDESPLLFAILED)
1361 {
1362 ipath_dbg("At start, serdes PLL failed bit set in "
1363 "hwerrstatus, clearing and continuing\n");
1364 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1365 INFINIPATH_HWE_SERDESPLLFAILED);
1366 }
1367
1368 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1369 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1370
1371 ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1372 "config1=%llx, sstatus=%llx xgxs %llx\n",
1373 (unsigned long long) val, (unsigned long long) config1,
1374 (unsigned long long)
1375 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1376 (unsigned long long)
1377 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1378
1379 /* force reset on */
1380 val |= INFINIPATH_SERDC0_RESET_PLL
1381 /* | INFINIPATH_SERDC0_RESET_MASK */
1382 ;
1383 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1384 udelay(15); /* need pll reset set at least for a bit */
1385
1386 if (val & INFINIPATH_SERDC0_RESET_PLL) {
1387 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1388 /* set lane resets, and tx idle, during pll reset */
1389 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1390 INFINIPATH_SERDC0_TXIDLE;
1391 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1392 "%llx)\n", (unsigned long long) val2);
1393 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1394 val2);
1395 /*
1396 * be sure chip saw it
1397 */
1398 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1399 /*
1400 * need pll reset clear at least 11 usec before lane
1401 * resets cleared; give it a few more
1402 */
1403 udelay(15);
1404 val = val2; /* for check below */
1405 }
1406
1407 if (val & (INFINIPATH_SERDC0_RESET_PLL |
1408 INFINIPATH_SERDC0_RESET_MASK |
1409 INFINIPATH_SERDC0_TXIDLE)) {
1410 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1411 INFINIPATH_SERDC0_RESET_MASK |
1412 INFINIPATH_SERDC0_TXIDLE);
1413 /* clear them */
1414 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1415 val);
1416 }
1417
1418 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1419 if (val & INFINIPATH_XGXS_RESET) {
1420 /* normally true after boot */
1421 val &= ~INFINIPATH_XGXS_RESET;
1422 change = 1;
1423 }
1424 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
1425 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
1426 /* need to compensate for Tx inversion in partner */
1427 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
1428 INFINIPATH_XGXS_RX_POL_SHIFT);
1429 val |= dd->ipath_rx_pol_inv <<
1430 INFINIPATH_XGXS_RX_POL_SHIFT;
1431 change = 1;
1432 }
1433 if (change)
1434 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1435
1436 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1437
1438 /* clear current and de-emphasis bits */
1439 config1 &= ~0x0ffffffff00ULL;
1440 /* set current to 20ma */
1441 config1 |= 0x00000000000ULL;
1442 /* set de-emphasis to -5.68dB */
1443 config1 |= 0x0cccc000000ULL;
1444 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1445
1446 ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1447 "config1=%llx, sstatus=%llx xgxs %llx\n",
1448 (unsigned long long) val, (unsigned long long) config1,
1449 (unsigned long long)
1450 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1451 (unsigned long long)
1452 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1453
1454 return ret; /* for now, say we always succeeded */
1455 }
1456
1457 /**
1458 * ipath_ht_quiet_serdes - set serdes to txidle
1459 * @dd: the infinipath device
1460 * driver is being unloaded
1461 */
ipath_ht_quiet_serdes(struct ipath_devdata * dd)1462 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1463 {
1464 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1465
1466 val |= INFINIPATH_SERDC0_TXIDLE;
1467 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1468 (unsigned long long) val);
1469 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1470 }
1471
1472 /**
1473 * ipath_pe_put_tid - write a TID in chip
1474 * @dd: the infinipath device
1475 * @tidptr: pointer to the expected TID (in chip) to update
1476 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1477 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1478 *
1479 * This exists as a separate routine to allow for special locking etc.
1480 * It's used for both the full cleanup on exit, as well as the normal
1481 * setup and teardown.
1482 */
ipath_ht_put_tid(struct ipath_devdata * dd,u64 __iomem * tidptr,u32 type,unsigned long pa)1483 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1484 u64 __iomem *tidptr, u32 type,
1485 unsigned long pa)
1486 {
1487 if (!dd->ipath_kregbase)
1488 return;
1489
1490 if (pa != dd->ipath_tidinvalid) {
1491 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1492 dev_info(&dd->pcidev->dev,
1493 "physaddr %lx has more than "
1494 "40 bits, using only 40!!!\n", pa);
1495 pa &= INFINIPATH_RT_ADDR_MASK;
1496 }
1497 if (type == RCVHQ_RCV_TYPE_EAGER)
1498 pa |= dd->ipath_tidtemplate;
1499 else {
1500 /* in words (fixed, full page). */
1501 u64 lenvalid = PAGE_SIZE >> 2;
1502 lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1503 pa |= lenvalid | INFINIPATH_RT_VALID;
1504 }
1505 }
1506
1507 writeq(pa, tidptr);
1508 }
1509
1510
1511 /**
1512 * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1513 * @dd: the infinipath device
1514 * @port: the port
1515 *
1516 * Used from ipath_close(), and at chip initialization.
1517 */
ipath_ht_clear_tids(struct ipath_devdata * dd,unsigned port)1518 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1519 {
1520 u64 __iomem *tidbase;
1521 int i;
1522
1523 if (!dd->ipath_kregbase)
1524 return;
1525
1526 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1527
1528 /*
1529 * need to invalidate all of the expected TID entries for this
1530 * port, so we don't have valid entries that might somehow get
1531 * used (early in next use of this port, or through some bug)
1532 */
1533 tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1534 dd->ipath_rcvtidbase +
1535 port * dd->ipath_rcvtidcnt *
1536 sizeof(*tidbase));
1537 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1538 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1539 dd->ipath_tidinvalid);
1540
1541 tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1542 dd->ipath_rcvegrbase +
1543 port * dd->ipath_rcvegrcnt *
1544 sizeof(*tidbase));
1545
1546 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1547 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1548 dd->ipath_tidinvalid);
1549 }
1550
1551 /**
1552 * ipath_ht_tidtemplate - setup constants for TID updates
1553 * @dd: the infinipath device
1554 *
1555 * We setup stuff that we use a lot, to avoid calculating each time
1556 */
ipath_ht_tidtemplate(struct ipath_devdata * dd)1557 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1558 {
1559 dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1560 dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1561 dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1562
1563 /*
1564 * work around chip errata bug 7358, by marking invalid tids
1565 * as having max length
1566 */
1567 dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1568 INFINIPATH_RT_BUFSIZE_SHIFT;
1569 }
1570
ipath_ht_early_init(struct ipath_devdata * dd)1571 static int ipath_ht_early_init(struct ipath_devdata *dd)
1572 {
1573 u32 __iomem *piobuf;
1574 u32 pioincr, val32;
1575 int i;
1576
1577 /*
1578 * one cache line; long IB headers will spill over into received
1579 * buffer
1580 */
1581 dd->ipath_rcvhdrentsize = 16;
1582 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1583
1584 /*
1585 * For HT, we allocate a somewhat overly large eager buffer,
1586 * such that we can guarantee that we can receive the largest
1587 * packet that we can send out. To truly support a 4KB MTU,
1588 * we need to bump this to a large value. To date, other than
1589 * testing, we have never encountered an HCA that can really
1590 * send 4KB MTU packets, so we do not handle that (we'll get
1591 * errors interrupts if we ever see one).
1592 */
1593 dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1594
1595 /*
1596 * the min() check here is currently a nop, but it may not
1597 * always be, depending on just how we do ipath_rcvegrbufsize
1598 */
1599 dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1600 dd->ipath_rcvegrbufsize);
1601 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1602 ipath_ht_tidtemplate(dd);
1603
1604 /*
1605 * zero all the TID entries at startup. We do this for sanity,
1606 * in case of a previous driver crash of some kind, and also
1607 * because the chip powers up with these memories in an unknown
1608 * state. Use portcnt, not cfgports, since this is for the
1609 * full chip, not for current (possibly different) configuration
1610 * value.
1611 * Chip Errata bug 6447
1612 */
1613 for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1614 ipath_ht_clear_tids(dd, val32);
1615
1616 /*
1617 * write the pbc of each buffer, to be sure it's initialized, then
1618 * cancel all the buffers, and also abort any packets that might
1619 * have been in flight for some reason (the latter is for driver
1620 * unload/reload, but isn't a bad idea at first init). PIO send
1621 * isn't enabled at this point, so there is no danger of sending
1622 * these out on the wire.
1623 * Chip Errata bug 6610
1624 */
1625 piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1626 dd->ipath_piobufbase);
1627 pioincr = dd->ipath_palign / sizeof(*piobuf);
1628 for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1629 /*
1630 * reasonable word count, just to init pbc
1631 */
1632 writel(16, piobuf);
1633 piobuf += pioincr;
1634 }
1635
1636 ipath_get_eeprom_info(dd);
1637 if (dd->ipath_boardrev == 5) {
1638 /*
1639 * Later production QHT7040 has same changes as QHT7140, so
1640 * can use GPIO interrupts. They have serial #'s starting
1641 * with 128, rather than 112.
1642 */
1643 if (dd->ipath_serial[0] == '1' &&
1644 dd->ipath_serial[1] == '2' &&
1645 dd->ipath_serial[2] == '8')
1646 dd->ipath_flags |= IPATH_GPIO_INTR;
1647 else {
1648 ipath_dev_err(dd, "Unsupported InfiniPath board "
1649 "(serial number %.16s)!\n",
1650 dd->ipath_serial);
1651 return 1;
1652 }
1653 }
1654
1655 if (dd->ipath_minrev >= 4) {
1656 /* Rev4+ reports extra errors via internal GPIO pins */
1657 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
1658 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
1659 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
1660 dd->ipath_gpio_mask);
1661 }
1662
1663 return 0;
1664 }
1665
1666
1667 /**
1668 * ipath_init_ht_get_base_info - set chip-specific flags for user code
1669 * @dd: the infinipath device
1670 * @kbase: ipath_base_info pointer
1671 *
1672 * We set the PCIE flag because the lower bandwidth on PCIe vs
1673 * HyperTransport can affect some user packet algorithms.
1674 */
ipath_ht_get_base_info(struct ipath_portdata * pd,void * kbase)1675 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1676 {
1677 struct ipath_base_info *kinfo = kbase;
1678
1679 kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1680 IPATH_RUNTIME_PIO_REGSWAPPED;
1681
1682 if (pd->port_dd->ipath_minrev < 4)
1683 kinfo->spi_runtime_flags |= IPATH_RUNTIME_RCVHDR_COPY;
1684
1685 return 0;
1686 }
1687
ipath_ht_free_irq(struct ipath_devdata * dd)1688 static void ipath_ht_free_irq(struct ipath_devdata *dd)
1689 {
1690 free_irq(dd->ipath_irq, dd);
1691 ht_destroy_irq(dd->ipath_irq);
1692 dd->ipath_irq = 0;
1693 dd->ipath_intconfig = 0;
1694 }
1695
1696 static struct ipath_message_header *
ipath_ht_get_msgheader(struct ipath_devdata * dd,__le32 * rhf_addr)1697 ipath_ht_get_msgheader(struct ipath_devdata *dd, __le32 *rhf_addr)
1698 {
1699 return (struct ipath_message_header *)
1700 &rhf_addr[sizeof(u64) / sizeof(u32)];
1701 }
1702
ipath_ht_config_ports(struct ipath_devdata * dd,ushort cfgports)1703 static void ipath_ht_config_ports(struct ipath_devdata *dd, ushort cfgports)
1704 {
1705 dd->ipath_portcnt =
1706 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
1707 dd->ipath_p0_rcvegrcnt =
1708 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
1709 }
1710
ipath_ht_read_counters(struct ipath_devdata * dd,struct infinipath_counters * cntrs)1711 static void ipath_ht_read_counters(struct ipath_devdata *dd,
1712 struct infinipath_counters *cntrs)
1713 {
1714 cntrs->LBIntCnt =
1715 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBIntCnt));
1716 cntrs->LBFlowStallCnt =
1717 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBFlowStallCnt));
1718 cntrs->TxSDmaDescCnt = 0;
1719 cntrs->TxUnsupVLErrCnt =
1720 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnsupVLErrCnt));
1721 cntrs->TxDataPktCnt =
1722 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDataPktCnt));
1723 cntrs->TxFlowPktCnt =
1724 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowPktCnt));
1725 cntrs->TxDwordCnt =
1726 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDwordCnt));
1727 cntrs->TxLenErrCnt =
1728 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxLenErrCnt));
1729 cntrs->TxMaxMinLenErrCnt =
1730 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxMaxMinLenErrCnt));
1731 cntrs->TxUnderrunCnt =
1732 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnderrunCnt));
1733 cntrs->TxFlowStallCnt =
1734 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowStallCnt));
1735 cntrs->TxDroppedPktCnt =
1736 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDroppedPktCnt));
1737 cntrs->RxDroppedPktCnt =
1738 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDroppedPktCnt));
1739 cntrs->RxDataPktCnt =
1740 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDataPktCnt));
1741 cntrs->RxFlowPktCnt =
1742 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowPktCnt));
1743 cntrs->RxDwordCnt =
1744 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDwordCnt));
1745 cntrs->RxLenErrCnt =
1746 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLenErrCnt));
1747 cntrs->RxMaxMinLenErrCnt =
1748 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxMaxMinLenErrCnt));
1749 cntrs->RxICRCErrCnt =
1750 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxICRCErrCnt));
1751 cntrs->RxVCRCErrCnt =
1752 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxVCRCErrCnt));
1753 cntrs->RxFlowCtrlErrCnt =
1754 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowCtrlErrCnt));
1755 cntrs->RxBadFormatCnt =
1756 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBadFormatCnt));
1757 cntrs->RxLinkProblemCnt =
1758 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLinkProblemCnt));
1759 cntrs->RxEBPCnt =
1760 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxEBPCnt));
1761 cntrs->RxLPCRCErrCnt =
1762 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLPCRCErrCnt));
1763 cntrs->RxBufOvflCnt =
1764 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBufOvflCnt));
1765 cntrs->RxTIDFullErrCnt =
1766 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDFullErrCnt));
1767 cntrs->RxTIDValidErrCnt =
1768 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDValidErrCnt));
1769 cntrs->RxPKeyMismatchCnt =
1770 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxPKeyMismatchCnt));
1771 cntrs->RxP0HdrEgrOvflCnt =
1772 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt));
1773 cntrs->RxP1HdrEgrOvflCnt =
1774 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP1HdrEgrOvflCnt));
1775 cntrs->RxP2HdrEgrOvflCnt =
1776 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP2HdrEgrOvflCnt));
1777 cntrs->RxP3HdrEgrOvflCnt =
1778 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP3HdrEgrOvflCnt));
1779 cntrs->RxP4HdrEgrOvflCnt =
1780 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP4HdrEgrOvflCnt));
1781 cntrs->RxP5HdrEgrOvflCnt =
1782 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP5HdrEgrOvflCnt));
1783 cntrs->RxP6HdrEgrOvflCnt =
1784 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP6HdrEgrOvflCnt));
1785 cntrs->RxP7HdrEgrOvflCnt =
1786 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP7HdrEgrOvflCnt));
1787 cntrs->RxP8HdrEgrOvflCnt =
1788 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP8HdrEgrOvflCnt));
1789 cntrs->RxP9HdrEgrOvflCnt = 0;
1790 cntrs->RxP10HdrEgrOvflCnt = 0;
1791 cntrs->RxP11HdrEgrOvflCnt = 0;
1792 cntrs->RxP12HdrEgrOvflCnt = 0;
1793 cntrs->RxP13HdrEgrOvflCnt = 0;
1794 cntrs->RxP14HdrEgrOvflCnt = 0;
1795 cntrs->RxP15HdrEgrOvflCnt = 0;
1796 cntrs->RxP16HdrEgrOvflCnt = 0;
1797 cntrs->IBStatusChangeCnt =
1798 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBStatusChangeCnt));
1799 cntrs->IBLinkErrRecoveryCnt =
1800 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt));
1801 cntrs->IBLinkDownedCnt =
1802 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkDownedCnt));
1803 cntrs->IBSymbolErrCnt =
1804 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBSymbolErrCnt));
1805 cntrs->RxVL15DroppedPktCnt = 0;
1806 cntrs->RxOtherLocalPhyErrCnt = 0;
1807 cntrs->PcieRetryBufDiagQwordCnt = 0;
1808 cntrs->ExcessBufferOvflCnt = dd->ipath_overrun_thresh_errs;
1809 cntrs->LocalLinkIntegrityErrCnt =
1810 (dd->ipath_flags & IPATH_GPIO_ERRINTRS) ?
1811 dd->ipath_lli_errs : dd->ipath_lli_errors;
1812 cntrs->RxVlErrCnt = 0;
1813 cntrs->RxDlidFltrCnt = 0;
1814 }
1815
1816
1817 /* no interrupt fallback for these chips */
ipath_ht_nointr_fallback(struct ipath_devdata * dd)1818 static int ipath_ht_nointr_fallback(struct ipath_devdata *dd)
1819 {
1820 return 0;
1821 }
1822
1823
1824 /*
1825 * reset the XGXS (between serdes and IBC). Slightly less intrusive
1826 * than resetting the IBC or external link state, and useful in some
1827 * cases to cause some retraining. To do this right, we reset IBC
1828 * as well.
1829 */
ipath_ht_xgxs_reset(struct ipath_devdata * dd)1830 static void ipath_ht_xgxs_reset(struct ipath_devdata *dd)
1831 {
1832 u64 val, prev_val;
1833
1834 prev_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1835 val = prev_val | INFINIPATH_XGXS_RESET;
1836 prev_val &= ~INFINIPATH_XGXS_RESET; /* be sure */
1837 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1838 dd->ipath_control & ~INFINIPATH_C_LINKENABLE);
1839 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1840 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1841 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, prev_val);
1842 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1843 dd->ipath_control);
1844 }
1845
1846
ipath_ht_get_ib_cfg(struct ipath_devdata * dd,int which)1847 static int ipath_ht_get_ib_cfg(struct ipath_devdata *dd, int which)
1848 {
1849 int ret;
1850
1851 switch (which) {
1852 case IPATH_IB_CFG_LWID:
1853 ret = dd->ipath_link_width_active;
1854 break;
1855 case IPATH_IB_CFG_SPD:
1856 ret = dd->ipath_link_speed_active;
1857 break;
1858 case IPATH_IB_CFG_LWID_ENB:
1859 ret = dd->ipath_link_width_enabled;
1860 break;
1861 case IPATH_IB_CFG_SPD_ENB:
1862 ret = dd->ipath_link_speed_enabled;
1863 break;
1864 default:
1865 ret = -ENOTSUPP;
1866 break;
1867 }
1868 return ret;
1869 }
1870
1871
1872 /* we assume range checking is already done, if needed */
ipath_ht_set_ib_cfg(struct ipath_devdata * dd,int which,u32 val)1873 static int ipath_ht_set_ib_cfg(struct ipath_devdata *dd, int which, u32 val)
1874 {
1875 int ret = 0;
1876
1877 if (which == IPATH_IB_CFG_LWID_ENB)
1878 dd->ipath_link_width_enabled = val;
1879 else if (which == IPATH_IB_CFG_SPD_ENB)
1880 dd->ipath_link_speed_enabled = val;
1881 else
1882 ret = -ENOTSUPP;
1883 return ret;
1884 }
1885
1886
ipath_ht_config_jint(struct ipath_devdata * dd,u16 a,u16 b)1887 static void ipath_ht_config_jint(struct ipath_devdata *dd, u16 a, u16 b)
1888 {
1889 }
1890
1891
ipath_ht_ib_updown(struct ipath_devdata * dd,int ibup,u64 ibcs)1892 static int ipath_ht_ib_updown(struct ipath_devdata *dd, int ibup, u64 ibcs)
1893 {
1894 ipath_setup_ht_setextled(dd, ipath_ib_linkstate(dd, ibcs),
1895 ipath_ib_linktrstate(dd, ibcs));
1896 return 0;
1897 }
1898
1899
1900 /**
1901 * ipath_init_iba6110_funcs - set up the chip-specific function pointers
1902 * @dd: the infinipath device
1903 *
1904 * This is global, and is called directly at init to set up the
1905 * chip-specific function pointers for later use.
1906 */
ipath_init_iba6110_funcs(struct ipath_devdata * dd)1907 void ipath_init_iba6110_funcs(struct ipath_devdata *dd)
1908 {
1909 dd->ipath_f_intrsetup = ipath_ht_intconfig;
1910 dd->ipath_f_bus = ipath_setup_ht_config;
1911 dd->ipath_f_reset = ipath_setup_ht_reset;
1912 dd->ipath_f_get_boardname = ipath_ht_boardname;
1913 dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1914 dd->ipath_f_early_init = ipath_ht_early_init;
1915 dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1916 dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1917 dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1918 dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1919 dd->ipath_f_put_tid = ipath_ht_put_tid;
1920 dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1921 dd->ipath_f_setextled = ipath_setup_ht_setextled;
1922 dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1923 dd->ipath_f_free_irq = ipath_ht_free_irq;
1924 dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1925 dd->ipath_f_intr_fallback = ipath_ht_nointr_fallback;
1926 dd->ipath_f_get_msgheader = ipath_ht_get_msgheader;
1927 dd->ipath_f_config_ports = ipath_ht_config_ports;
1928 dd->ipath_f_read_counters = ipath_ht_read_counters;
1929 dd->ipath_f_xgxs_reset = ipath_ht_xgxs_reset;
1930 dd->ipath_f_get_ib_cfg = ipath_ht_get_ib_cfg;
1931 dd->ipath_f_set_ib_cfg = ipath_ht_set_ib_cfg;
1932 dd->ipath_f_config_jint = ipath_ht_config_jint;
1933 dd->ipath_f_ib_updown = ipath_ht_ib_updown;
1934
1935 /*
1936 * initialize chip-specific variables
1937 */
1938 ipath_init_ht_variables(dd);
1939 }
1940