1 /* 2 * Copyright 2012 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 */ 14 15 /* Machine-generated file; do not edit. */ 16 17 #ifndef __ARCH_TRIO_PCIE_INTFC_H__ 18 #define __ARCH_TRIO_PCIE_INTFC_H__ 19 20 #include <arch/abi.h> 21 #include <arch/trio_pcie_intfc_def.h> 22 23 #ifndef __ASSEMBLER__ 24 25 /* 26 * Port Configuration. 27 * Configuration of the PCIe Port 28 */ 29 30 __extension__ 31 typedef union 32 { 33 struct 34 { 35 #ifndef __BIG_ENDIAN__ 36 /* Provides the state of the strapping pins for this port. */ 37 uint_reg_t strap_state : 3; 38 /* Reserved. */ 39 uint_reg_t __reserved_0 : 1; 40 /* 41 * When 1, the device type will be overridden using OVD_DEV_TYPE_VAL. 42 * When 0, the device type is determined based on the STRAP_STATE. 43 */ 44 uint_reg_t ovd_dev_type : 1; 45 /* Provides the device type when OVD_DEV_TYPE is 1. */ 46 uint_reg_t ovd_dev_type_val : 4; 47 /* Determines how link is trained. */ 48 uint_reg_t train_mode : 2; 49 /* Reserved. */ 50 uint_reg_t __reserved_1 : 1; 51 /* 52 * For PCIe, used to flip physical RX lanes that were not properly wired. 53 * This is not the same as lane reversal which is handled automatically 54 * during link training. When 0, RX Lane0 must be wired to the link 55 * partner (either to its Lane0 or it's LaneN). When RX_LANE_FLIP is 1, 56 * the highest numbered lane for this port becomes Lane0 and Lane0 does 57 * NOT have to be wired to the link partner. 58 */ 59 uint_reg_t rx_lane_flip : 1; 60 /* 61 * For PCIe, used to flip physical TX lanes that were not properly wired. 62 * This is not the same as lane reversal which is handled automatically 63 * during link training. When 0, TX Lane0 must be wired to the link 64 * partner (either to its Lane0 or it's LaneN). When TX_LANE_FLIP is 1, 65 * the highest numbered lane for this port becomes Lane0 and Lane0 does 66 * NOT have to be wired to the link partner. 67 */ 68 uint_reg_t tx_lane_flip : 1; 69 /* 70 * For StreamIO port, configures the width of the port when TRAIN_MODE is 71 * not STRAP. 72 */ 73 uint_reg_t stream_width : 2; 74 /* 75 * For StreamIO port, configures the rate of the port when TRAIN_MODE is 76 * not STRAP. 77 */ 78 uint_reg_t stream_rate : 2; 79 /* Reserved. */ 80 uint_reg_t __reserved_2 : 46; 81 #else /* __BIG_ENDIAN__ */ 82 uint_reg_t __reserved_2 : 46; 83 uint_reg_t stream_rate : 2; 84 uint_reg_t stream_width : 2; 85 uint_reg_t tx_lane_flip : 1; 86 uint_reg_t rx_lane_flip : 1; 87 uint_reg_t __reserved_1 : 1; 88 uint_reg_t train_mode : 2; 89 uint_reg_t ovd_dev_type_val : 4; 90 uint_reg_t ovd_dev_type : 1; 91 uint_reg_t __reserved_0 : 1; 92 uint_reg_t strap_state : 3; 93 #endif 94 }; 95 96 uint_reg_t word; 97 } TRIO_PCIE_INTFC_PORT_CONFIG_t; 98 99 /* 100 * Port Status. 101 * Status of the PCIe Port. This register applies to the StreamIO port when 102 * StreamIO is enabled. 103 */ 104 105 __extension__ 106 typedef union 107 { 108 struct 109 { 110 #ifndef __BIG_ENDIAN__ 111 /* 112 * Indicates the DL state of the port. When 1, the port is up and ready 113 * to receive traffic. 114 */ 115 uint_reg_t dl_up : 1; 116 /* 117 * Indicates the number of times the link has gone down. Clears on read. 118 */ 119 uint_reg_t dl_down_cnt : 7; 120 /* Indicates the SERDES PLL has spun up and is providing a valid clock. */ 121 uint_reg_t clock_ready : 1; 122 /* Reserved. */ 123 uint_reg_t __reserved_0 : 7; 124 /* Device revision ID. */ 125 uint_reg_t device_rev : 8; 126 /* Link state (PCIe). */ 127 uint_reg_t ltssm_state : 6; 128 /* Link power management state (PCIe). */ 129 uint_reg_t pm_state : 3; 130 /* Reserved. */ 131 uint_reg_t __reserved_1 : 31; 132 #else /* __BIG_ENDIAN__ */ 133 uint_reg_t __reserved_1 : 31; 134 uint_reg_t pm_state : 3; 135 uint_reg_t ltssm_state : 6; 136 uint_reg_t device_rev : 8; 137 uint_reg_t __reserved_0 : 7; 138 uint_reg_t clock_ready : 1; 139 uint_reg_t dl_down_cnt : 7; 140 uint_reg_t dl_up : 1; 141 #endif 142 }; 143 144 uint_reg_t word; 145 } TRIO_PCIE_INTFC_PORT_STATUS_t; 146 147 /* 148 * Transmit FIFO Control. 149 * Contains TX FIFO thresholds. These registers are for diagnostics purposes 150 * only. Changing these values causes undefined behavior. 151 */ 152 153 __extension__ 154 typedef union 155 { 156 struct 157 { 158 #ifndef __BIG_ENDIAN__ 159 /* 160 * Almost-Empty level for TX0 data. Typically set to at least 161 * roundup(38.0*M/N) where N=tclk frequency and M=MAC symbol rate in MHz 162 * for a x4 port (250MHz). 163 */ 164 uint_reg_t tx0_data_ae_lvl : 7; 165 /* Reserved. */ 166 uint_reg_t __reserved_0 : 1; 167 /* Almost-Empty level for TX1 data. */ 168 uint_reg_t tx1_data_ae_lvl : 7; 169 /* Reserved. */ 170 uint_reg_t __reserved_1 : 1; 171 /* Almost-Full level for TX0 data. */ 172 uint_reg_t tx0_data_af_lvl : 7; 173 /* Reserved. */ 174 uint_reg_t __reserved_2 : 1; 175 /* Almost-Full level for TX1 data. */ 176 uint_reg_t tx1_data_af_lvl : 7; 177 /* Reserved. */ 178 uint_reg_t __reserved_3 : 1; 179 /* Almost-Full level for TX0 info. */ 180 uint_reg_t tx0_info_af_lvl : 5; 181 /* Reserved. */ 182 uint_reg_t __reserved_4 : 3; 183 /* Almost-Full level for TX1 info. */ 184 uint_reg_t tx1_info_af_lvl : 5; 185 /* Reserved. */ 186 uint_reg_t __reserved_5 : 3; 187 /* 188 * This register provides performance adjustment for high bandwidth 189 * flows. The MAC will assert almost-full to TRIO if non-posted credits 190 * fall below this level. Note that setting this larger than the initial 191 * PORT_CREDIT.NPH value will cause READS to never be sent. If the 192 * initial credit value from the link partner is smaller than this value 193 * when the link comes up, the value will be reset to the initial credit 194 * value to prevent lockup. 195 */ 196 uint_reg_t min_np_credits : 8; 197 /* 198 * This register provides performance adjustment for high bandwidth 199 * flows. The MAC will assert almost-full to TRIO if posted credits fall 200 * below this level. Note that setting this larger than the initial 201 * PORT_CREDIT.PH value will cause WRITES to never be sent. If the 202 * initial credit value from the link partner is smaller than this value 203 * when the link comes up, the value will be reset to the initial credit 204 * value to prevent lockup. 205 */ 206 uint_reg_t min_p_credits : 8; 207 #else /* __BIG_ENDIAN__ */ 208 uint_reg_t min_p_credits : 8; 209 uint_reg_t min_np_credits : 8; 210 uint_reg_t __reserved_5 : 3; 211 uint_reg_t tx1_info_af_lvl : 5; 212 uint_reg_t __reserved_4 : 3; 213 uint_reg_t tx0_info_af_lvl : 5; 214 uint_reg_t __reserved_3 : 1; 215 uint_reg_t tx1_data_af_lvl : 7; 216 uint_reg_t __reserved_2 : 1; 217 uint_reg_t tx0_data_af_lvl : 7; 218 uint_reg_t __reserved_1 : 1; 219 uint_reg_t tx1_data_ae_lvl : 7; 220 uint_reg_t __reserved_0 : 1; 221 uint_reg_t tx0_data_ae_lvl : 7; 222 #endif 223 }; 224 225 uint_reg_t word; 226 } TRIO_PCIE_INTFC_TX_FIFO_CTL_t; 227 #endif /* !defined(__ASSEMBLER__) */ 228 229 #endif /* !defined(__ARCH_TRIO_PCIE_INTFC_H__) */ 230