1 /*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 /* HC should halt within 16 ms, but use 32 ms as some hosts take longer */
24 #define XHCI_MAX_HALT_USEC (32 * 1000)
25 /* HC not running - set to 1 when run/stop bit is cleared. */
26 #define XHCI_STS_HALT (1<<0)
27
28 /* HCCPARAMS offset from PCI base address */
29 #define XHCI_HCC_PARAMS_OFFSET 0x10
30 /* HCCPARAMS contains the first extended capability pointer */
31 #define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff)
32
33 /* Command and Status registers offset from the Operational Registers address */
34 #define XHCI_CMD_OFFSET 0x00
35 #define XHCI_STS_OFFSET 0x04
36
37 #define XHCI_MAX_EXT_CAPS 50
38
39 /* Capability Register */
40 /* bits 7:0 - how long is the Capabilities register */
41 #define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff)
42
43 /* Extended capability register fields */
44 #define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff)
45 #define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff)
46 #define XHCI_EXT_CAPS_VAL(p) ((p)>>16)
47 /* Extended capability IDs - ID 0 reserved */
48 #define XHCI_EXT_CAPS_LEGACY 1
49 #define XHCI_EXT_CAPS_PROTOCOL 2
50 #define XHCI_EXT_CAPS_PM 3
51 #define XHCI_EXT_CAPS_VIRT 4
52 #define XHCI_EXT_CAPS_ROUTE 5
53 /* IDs 6-9 reserved */
54 #define XHCI_EXT_CAPS_DEBUG 10
55 /* USB Legacy Support Capability - section 7.1.1 */
56 #define XHCI_HC_BIOS_OWNED (1 << 16)
57 #define XHCI_HC_OS_OWNED (1 << 24)
58
59 /* USB Legacy Support Capability - section 7.1.1 */
60 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
61 #define XHCI_LEGACY_SUPPORT_OFFSET (0x00)
62
63 /* USB Legacy Support Control and Status Register - section 7.1.2 */
64 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
65 #define XHCI_LEGACY_CONTROL_OFFSET (0x04)
66 /* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
67 #define XHCI_LEGACY_DISABLE_SMI ((0x7 << 1) + (0xff << 5) + (0x7 << 17))
68 #define XHCI_LEGACY_SMI_EVENTS (0x7 << 29)
69
70 /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
71 #define XHCI_L1C (1 << 16)
72
73 /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
74 #define XHCI_HLC (1 << 19)
75 #define XHCI_BLC (1 << 20)
76
77 /* command register values to disable interrupts and halt the HC */
78 /* start/stop HC execution - do not write unless HC is halted*/
79 #define XHCI_CMD_RUN (1 << 0)
80 /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
81 #define XHCI_CMD_EIE (1 << 2)
82 /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
83 #define XHCI_CMD_HSEIE (1 << 3)
84 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
85 #define XHCI_CMD_EWE (1 << 10)
86
87 #define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
88
89 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
90 #define XHCI_STS_CNR (1 << 11)
91
92 #include <linux/io.h>
93
94 /**
95 * Return the next extended capability pointer register.
96 *
97 * @base PCI register base address.
98 *
99 * @ext_offset Offset of the 32-bit register that contains the extended
100 * capabilites pointer. If searching for the first extended capability, pass
101 * in XHCI_HCC_PARAMS_OFFSET. If searching for the next extended capability,
102 * pass in the offset of the current extended capability register.
103 *
104 * Returns 0 if there is no next extended capability register or returns the register offset
105 * from the PCI registers base address.
106 */
xhci_find_next_cap_offset(void __iomem * base,int ext_offset)107 static inline int xhci_find_next_cap_offset(void __iomem *base, int ext_offset)
108 {
109 u32 next;
110
111 next = readl(base + ext_offset);
112
113 if (ext_offset == XHCI_HCC_PARAMS_OFFSET) {
114 /* Find the first extended capability */
115 next = XHCI_HCC_EXT_CAPS(next);
116 ext_offset = 0;
117 } else {
118 /* Find the next extended capability */
119 next = XHCI_EXT_CAPS_NEXT(next);
120 }
121
122 if (!next)
123 return 0;
124 /*
125 * Address calculation from offset of extended capabilities
126 * (or HCCPARAMS) register - see section 5.3.6 and section 7.
127 */
128 return ext_offset + (next << 2);
129 }
130
131 /**
132 * Find the offset of the extended capabilities with capability ID id.
133 *
134 * @base PCI MMIO registers base address.
135 * @ext_offset Offset from base of the first extended capability to look at,
136 * or the address of HCCPARAMS.
137 * @id Extended capability ID to search for.
138 *
139 * This uses an arbitrary limit of XHCI_MAX_EXT_CAPS extended capabilities
140 * to make sure that the list doesn't contain a loop.
141 */
xhci_find_ext_cap_by_id(void __iomem * base,int ext_offset,int id)142 static inline int xhci_find_ext_cap_by_id(void __iomem *base, int ext_offset, int id)
143 {
144 u32 val;
145 int limit = XHCI_MAX_EXT_CAPS;
146
147 while (ext_offset && limit > 0) {
148 val = readl(base + ext_offset);
149 if (XHCI_EXT_CAPS_ID(val) == id)
150 break;
151 ext_offset = xhci_find_next_cap_offset(base, ext_offset);
152 limit--;
153 }
154 if (limit > 0)
155 return ext_offset;
156 return 0;
157 }
158