1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
ath9k_parse_mpdudensity(u8 mpdudensity)22 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
23 {
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55 }
56
ath9k_has_pending_frames(struct ath_softc * sc,struct ath_txq * txq,bool sw_pending)57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
58 bool sw_pending)
59 {
60 bool pending = false;
61
62 spin_lock_bh(&txq->axq_lock);
63
64 if (txq->axq_depth) {
65 pending = true;
66 goto out;
67 }
68
69 if (!sw_pending)
70 goto out;
71
72 if (txq->mac80211_qnum >= 0) {
73 struct list_head *list;
74
75 list = &sc->cur_chan->acq[txq->mac80211_qnum];
76 if (!list_empty(list))
77 pending = true;
78 }
79 out:
80 spin_unlock_bh(&txq->axq_lock);
81 return pending;
82 }
83
ath9k_setpower(struct ath_softc * sc,enum ath9k_power_mode mode)84 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
85 {
86 unsigned long flags;
87 bool ret;
88
89 spin_lock_irqsave(&sc->sc_pm_lock, flags);
90 ret = ath9k_hw_setpower(sc->sc_ah, mode);
91 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
92
93 return ret;
94 }
95
ath_ps_full_sleep(unsigned long data)96 void ath_ps_full_sleep(unsigned long data)
97 {
98 struct ath_softc *sc = (struct ath_softc *) data;
99 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
100 bool reset;
101
102 spin_lock(&common->cc_lock);
103 ath_hw_cycle_counters_update(common);
104 spin_unlock(&common->cc_lock);
105
106 ath9k_hw_setrxabort(sc->sc_ah, 1);
107 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
108
109 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
110 }
111
ath9k_ps_wakeup(struct ath_softc * sc)112 void ath9k_ps_wakeup(struct ath_softc *sc)
113 {
114 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
115 unsigned long flags;
116 enum ath9k_power_mode power_mode;
117
118 spin_lock_irqsave(&sc->sc_pm_lock, flags);
119 if (++sc->ps_usecount != 1)
120 goto unlock;
121
122 del_timer_sync(&sc->sleep_timer);
123 power_mode = sc->sc_ah->power_mode;
124 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
125
126 /*
127 * While the hardware is asleep, the cycle counters contain no
128 * useful data. Better clear them now so that they don't mess up
129 * survey data results.
130 */
131 if (power_mode != ATH9K_PM_AWAKE) {
132 spin_lock(&common->cc_lock);
133 ath_hw_cycle_counters_update(common);
134 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
135 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
136 spin_unlock(&common->cc_lock);
137 }
138
139 unlock:
140 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
141 }
142
ath9k_ps_restore(struct ath_softc * sc)143 void ath9k_ps_restore(struct ath_softc *sc)
144 {
145 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
146 enum ath9k_power_mode mode;
147 unsigned long flags;
148
149 spin_lock_irqsave(&sc->sc_pm_lock, flags);
150 if (--sc->ps_usecount != 0)
151 goto unlock;
152
153 if (sc->ps_idle) {
154 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
155 goto unlock;
156 }
157
158 if (sc->ps_enabled &&
159 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
160 PS_WAIT_FOR_CAB |
161 PS_WAIT_FOR_PSPOLL_DATA |
162 PS_WAIT_FOR_TX_ACK |
163 PS_WAIT_FOR_ANI))) {
164 mode = ATH9K_PM_NETWORK_SLEEP;
165 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
166 ath9k_btcoex_stop_gen_timer(sc);
167 } else {
168 goto unlock;
169 }
170
171 spin_lock(&common->cc_lock);
172 ath_hw_cycle_counters_update(common);
173 spin_unlock(&common->cc_lock);
174
175 ath9k_hw_setpower(sc->sc_ah, mode);
176
177 unlock:
178 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
179 }
180
__ath_cancel_work(struct ath_softc * sc)181 static void __ath_cancel_work(struct ath_softc *sc)
182 {
183 cancel_work_sync(&sc->paprd_work);
184 cancel_delayed_work_sync(&sc->tx_complete_work);
185 cancel_delayed_work_sync(&sc->hw_pll_work);
186
187 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
188 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
189 cancel_work_sync(&sc->mci_work);
190 #endif
191 }
192
ath_cancel_work(struct ath_softc * sc)193 void ath_cancel_work(struct ath_softc *sc)
194 {
195 __ath_cancel_work(sc);
196 cancel_work_sync(&sc->hw_reset_work);
197 }
198
ath_restart_work(struct ath_softc * sc)199 void ath_restart_work(struct ath_softc *sc)
200 {
201 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
202
203 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
204 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
205 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
206
207 ath_start_ani(sc);
208 }
209
ath_prepare_reset(struct ath_softc * sc)210 static bool ath_prepare_reset(struct ath_softc *sc)
211 {
212 struct ath_hw *ah = sc->sc_ah;
213 bool ret = true;
214
215 ieee80211_stop_queues(sc->hw);
216 ath_stop_ani(sc);
217 ath9k_hw_disable_interrupts(ah);
218
219 if (AR_SREV_9300_20_OR_LATER(ah)) {
220 ret &= ath_stoprecv(sc);
221 ret &= ath_drain_all_txq(sc);
222 } else {
223 ret &= ath_drain_all_txq(sc);
224 ret &= ath_stoprecv(sc);
225 }
226
227 return ret;
228 }
229
ath_complete_reset(struct ath_softc * sc,bool start)230 static bool ath_complete_reset(struct ath_softc *sc, bool start)
231 {
232 struct ath_hw *ah = sc->sc_ah;
233 struct ath_common *common = ath9k_hw_common(ah);
234 unsigned long flags;
235
236 ath9k_calculate_summary_state(sc, sc->cur_chan);
237 ath_startrecv(sc);
238 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
239 sc->cur_chan->txpower,
240 &sc->cur_chan->cur_txpower);
241 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
242
243 if (!sc->cur_chan->offchannel && start) {
244 /* restore per chanctx TSF timer */
245 if (sc->cur_chan->tsf_val) {
246 u32 offset;
247
248 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
249 NULL);
250 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
251 }
252
253
254 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
255 goto work;
256
257 if (ah->opmode == NL80211_IFTYPE_STATION &&
258 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
259 spin_lock_irqsave(&sc->sc_pm_lock, flags);
260 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
261 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
262 } else {
263 ath9k_set_beacon(sc);
264 }
265 work:
266 ath_restart_work(sc);
267 ath_txq_schedule_all(sc);
268 }
269
270 sc->gtt_cnt = 0;
271
272 ath9k_hw_set_interrupts(ah);
273 ath9k_hw_enable_interrupts(ah);
274 ieee80211_wake_queues(sc->hw);
275 ath9k_p2p_ps_timer(sc);
276
277 return true;
278 }
279
ath_reset_internal(struct ath_softc * sc,struct ath9k_channel * hchan)280 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
281 {
282 struct ath_hw *ah = sc->sc_ah;
283 struct ath_common *common = ath9k_hw_common(ah);
284 struct ath9k_hw_cal_data *caldata = NULL;
285 bool fastcc = true;
286 int r;
287
288 __ath_cancel_work(sc);
289
290 disable_irq(sc->irq);
291 tasklet_disable(&sc->intr_tq);
292 tasklet_disable(&sc->bcon_tasklet);
293 spin_lock_bh(&sc->sc_pcu_lock);
294
295 if (!sc->cur_chan->offchannel) {
296 fastcc = false;
297 caldata = &sc->cur_chan->caldata;
298 }
299
300 if (!hchan) {
301 fastcc = false;
302 hchan = ah->curchan;
303 }
304
305 if (!hchan) {
306 fastcc = false;
307 hchan = ath9k_cmn_get_channel(sc->hw, ah, &sc->cur_chan->chandef);
308 }
309
310 if (!ath_prepare_reset(sc))
311 fastcc = false;
312
313 if (ath9k_is_chanctx_enabled())
314 fastcc = false;
315
316 spin_lock_bh(&sc->chan_lock);
317 sc->cur_chandef = sc->cur_chan->chandef;
318 spin_unlock_bh(&sc->chan_lock);
319
320 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
321 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
322
323 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
324 if (r) {
325 ath_err(common,
326 "Unable to reset channel, reset status %d\n", r);
327
328 ath9k_hw_enable_interrupts(ah);
329 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
330
331 goto out;
332 }
333
334 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
335 sc->cur_chan->offchannel)
336 ath9k_mci_set_txpower(sc, true, false);
337
338 if (!ath_complete_reset(sc, true))
339 r = -EIO;
340
341 out:
342 enable_irq(sc->irq);
343 spin_unlock_bh(&sc->sc_pcu_lock);
344 tasklet_enable(&sc->bcon_tasklet);
345 tasklet_enable(&sc->intr_tq);
346
347 return r;
348 }
349
ath_node_attach(struct ath_softc * sc,struct ieee80211_sta * sta,struct ieee80211_vif * vif)350 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
351 struct ieee80211_vif *vif)
352 {
353 struct ath_node *an;
354 an = (struct ath_node *)sta->drv_priv;
355
356 an->sc = sc;
357 an->sta = sta;
358 an->vif = vif;
359 memset(&an->key_idx, 0, sizeof(an->key_idx));
360
361 ath_tx_node_init(sc, an);
362
363 ath_dynack_node_init(sc->sc_ah, an);
364 }
365
ath_node_detach(struct ath_softc * sc,struct ieee80211_sta * sta)366 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
367 {
368 struct ath_node *an = (struct ath_node *)sta->drv_priv;
369 ath_tx_node_cleanup(sc, an);
370
371 ath_dynack_node_deinit(sc->sc_ah, an);
372 }
373
ath9k_tasklet(unsigned long data)374 void ath9k_tasklet(unsigned long data)
375 {
376 struct ath_softc *sc = (struct ath_softc *)data;
377 struct ath_hw *ah = sc->sc_ah;
378 struct ath_common *common = ath9k_hw_common(ah);
379 enum ath_reset_type type;
380 unsigned long flags;
381 u32 status;
382 u32 rxmask;
383
384 spin_lock_irqsave(&sc->intr_lock, flags);
385 status = sc->intrstatus;
386 sc->intrstatus = 0;
387 spin_unlock_irqrestore(&sc->intr_lock, flags);
388
389 ath9k_ps_wakeup(sc);
390 spin_lock(&sc->sc_pcu_lock);
391
392 if (status & ATH9K_INT_FATAL) {
393 type = RESET_TYPE_FATAL_INT;
394 ath9k_queue_reset(sc, type);
395 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
396 goto out;
397 }
398
399 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
400 (status & ATH9K_INT_BB_WATCHDOG)) {
401 spin_lock(&common->cc_lock);
402 ath_hw_cycle_counters_update(common);
403 ar9003_hw_bb_watchdog_dbg_info(ah);
404 spin_unlock(&common->cc_lock);
405
406 if (ar9003_hw_bb_watchdog_check(ah)) {
407 type = RESET_TYPE_BB_WATCHDOG;
408 ath9k_queue_reset(sc, type);
409
410 ath_dbg(common, RESET,
411 "BB_WATCHDOG: Skipping interrupts\n");
412 goto out;
413 }
414 }
415
416 if (status & ATH9K_INT_GTT) {
417 sc->gtt_cnt++;
418
419 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
420 type = RESET_TYPE_TX_GTT;
421 ath9k_queue_reset(sc, type);
422 ath_dbg(common, RESET,
423 "GTT: Skipping interrupts\n");
424 goto out;
425 }
426 }
427
428 spin_lock_irqsave(&sc->sc_pm_lock, flags);
429 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
430 /*
431 * TSF sync does not look correct; remain awake to sync with
432 * the next Beacon.
433 */
434 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
435 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
436 }
437 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
438
439 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
440 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
441 ATH9K_INT_RXORN);
442 else
443 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
444
445 if (status & rxmask) {
446 /* Check for high priority Rx first */
447 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
448 (status & ATH9K_INT_RXHP))
449 ath_rx_tasklet(sc, 0, true);
450
451 ath_rx_tasklet(sc, 0, false);
452 }
453
454 if (status & ATH9K_INT_TX) {
455 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
456 /*
457 * For EDMA chips, TX completion is enabled for the
458 * beacon queue, so if a beacon has been transmitted
459 * successfully after a GTT interrupt, the GTT counter
460 * gets reset to zero here.
461 */
462 sc->gtt_cnt = 0;
463
464 ath_tx_edma_tasklet(sc);
465 } else {
466 ath_tx_tasklet(sc);
467 }
468
469 wake_up(&sc->tx_wait);
470 }
471
472 if (status & ATH9K_INT_GENTIMER)
473 ath_gen_timer_isr(sc->sc_ah);
474
475 ath9k_btcoex_handle_interrupt(sc, status);
476
477 /* re-enable hardware interrupt */
478 ath9k_hw_resume_interrupts(ah);
479 out:
480 spin_unlock(&sc->sc_pcu_lock);
481 ath9k_ps_restore(sc);
482 }
483
ath_isr(int irq,void * dev)484 irqreturn_t ath_isr(int irq, void *dev)
485 {
486 #define SCHED_INTR ( \
487 ATH9K_INT_FATAL | \
488 ATH9K_INT_BB_WATCHDOG | \
489 ATH9K_INT_RXORN | \
490 ATH9K_INT_RXEOL | \
491 ATH9K_INT_RX | \
492 ATH9K_INT_RXLP | \
493 ATH9K_INT_RXHP | \
494 ATH9K_INT_TX | \
495 ATH9K_INT_BMISS | \
496 ATH9K_INT_CST | \
497 ATH9K_INT_GTT | \
498 ATH9K_INT_TSFOOR | \
499 ATH9K_INT_GENTIMER | \
500 ATH9K_INT_MCI)
501
502 struct ath_softc *sc = dev;
503 struct ath_hw *ah = sc->sc_ah;
504 struct ath_common *common = ath9k_hw_common(ah);
505 enum ath9k_int status;
506 u32 sync_cause = 0;
507 bool sched = false;
508
509 /*
510 * The hardware is not ready/present, don't
511 * touch anything. Note this can happen early
512 * on if the IRQ is shared.
513 */
514 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
515 return IRQ_NONE;
516
517 /* shared irq, not for us */
518 if (!ath9k_hw_intrpend(ah))
519 return IRQ_NONE;
520
521 /*
522 * Figure out the reason(s) for the interrupt. Note
523 * that the hal returns a pseudo-ISR that may include
524 * bits we haven't explicitly enabled so we mask the
525 * value to insure we only process bits we requested.
526 */
527 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
528 ath9k_debug_sync_cause(sc, sync_cause);
529 status &= ah->imask; /* discard unasked-for bits */
530
531 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
532 ath9k_hw_kill_interrupts(sc->sc_ah);
533 return IRQ_HANDLED;
534 }
535
536 /*
537 * If there are no status bits set, then this interrupt was not
538 * for me (should have been caught above).
539 */
540 if (!status)
541 return IRQ_NONE;
542
543 /* Cache the status */
544 spin_lock(&sc->intr_lock);
545 sc->intrstatus |= status;
546 spin_unlock(&sc->intr_lock);
547
548 if (status & SCHED_INTR)
549 sched = true;
550
551 /*
552 * If a FATAL interrupt is received, we have to reset the chip
553 * immediately.
554 */
555 if (status & ATH9K_INT_FATAL)
556 goto chip_reset;
557
558 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
559 (status & ATH9K_INT_BB_WATCHDOG))
560 goto chip_reset;
561
562 if (status & ATH9K_INT_SWBA)
563 tasklet_schedule(&sc->bcon_tasklet);
564
565 if (status & ATH9K_INT_TXURN)
566 ath9k_hw_updatetxtriglevel(ah, true);
567
568 if (status & ATH9K_INT_RXEOL) {
569 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
570 ath9k_hw_set_interrupts(ah);
571 }
572
573 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
574 if (status & ATH9K_INT_TIM_TIMER) {
575 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
576 goto chip_reset;
577 /* Clear RxAbort bit so that we can
578 * receive frames */
579 ath9k_setpower(sc, ATH9K_PM_AWAKE);
580 spin_lock(&sc->sc_pm_lock);
581 ath9k_hw_setrxabort(sc->sc_ah, 0);
582 sc->ps_flags |= PS_WAIT_FOR_BEACON;
583 spin_unlock(&sc->sc_pm_lock);
584 }
585
586 chip_reset:
587
588 ath_debug_stat_interrupt(sc, status);
589
590 if (sched) {
591 /* turn off every interrupt */
592 ath9k_hw_kill_interrupts(ah);
593 tasklet_schedule(&sc->intr_tq);
594 }
595
596 return IRQ_HANDLED;
597
598 #undef SCHED_INTR
599 }
600
601 /*
602 * This function is called when a HW reset cannot be deferred
603 * and has to be immediate.
604 */
ath_reset(struct ath_softc * sc,struct ath9k_channel * hchan)605 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
606 {
607 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
608 int r;
609
610 ath9k_hw_kill_interrupts(sc->sc_ah);
611 set_bit(ATH_OP_HW_RESET, &common->op_flags);
612
613 ath9k_ps_wakeup(sc);
614 r = ath_reset_internal(sc, hchan);
615 ath9k_ps_restore(sc);
616
617 return r;
618 }
619
620 /*
621 * When a HW reset can be deferred, it is added to the
622 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
623 * queueing.
624 */
ath9k_queue_reset(struct ath_softc * sc,enum ath_reset_type type)625 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
626 {
627 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
628 #ifdef CONFIG_ATH9K_DEBUGFS
629 RESET_STAT_INC(sc, type);
630 #endif
631 ath9k_hw_kill_interrupts(sc->sc_ah);
632 set_bit(ATH_OP_HW_RESET, &common->op_flags);
633 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
634 }
635
ath_reset_work(struct work_struct * work)636 void ath_reset_work(struct work_struct *work)
637 {
638 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
639
640 ath9k_ps_wakeup(sc);
641 ath_reset_internal(sc, NULL);
642 ath9k_ps_restore(sc);
643 }
644
645 /**********************/
646 /* mac80211 callbacks */
647 /**********************/
648
ath9k_start(struct ieee80211_hw * hw)649 static int ath9k_start(struct ieee80211_hw *hw)
650 {
651 struct ath_softc *sc = hw->priv;
652 struct ath_hw *ah = sc->sc_ah;
653 struct ath_common *common = ath9k_hw_common(ah);
654 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
655 struct ath_chanctx *ctx = sc->cur_chan;
656 struct ath9k_channel *init_channel;
657 int r;
658
659 ath_dbg(common, CONFIG,
660 "Starting driver with initial channel: %d MHz\n",
661 curchan->center_freq);
662
663 ath9k_ps_wakeup(sc);
664 mutex_lock(&sc->mutex);
665
666 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
667 sc->cur_chandef = hw->conf.chandef;
668
669 /* Reset SERDES registers */
670 ath9k_hw_configpcipowersave(ah, false);
671
672 /*
673 * The basic interface to setting the hardware in a good
674 * state is ``reset''. On return the hardware is known to
675 * be powered up and with interrupts disabled. This must
676 * be followed by initialization of the appropriate bits
677 * and then setup of the interrupt mask.
678 */
679 spin_lock_bh(&sc->sc_pcu_lock);
680
681 atomic_set(&ah->intr_ref_cnt, -1);
682
683 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
684 if (r) {
685 ath_err(common,
686 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
687 r, curchan->center_freq);
688 ah->reset_power_on = false;
689 }
690
691 /* Setup our intr mask. */
692 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
693 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
694 ATH9K_INT_GLOBAL;
695
696 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
697 ah->imask |= ATH9K_INT_RXHP |
698 ATH9K_INT_RXLP;
699 else
700 ah->imask |= ATH9K_INT_RX;
701
702 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
703 ah->imask |= ATH9K_INT_BB_WATCHDOG;
704
705 /*
706 * Enable GTT interrupts only for AR9003/AR9004 chips
707 * for now.
708 */
709 if (AR_SREV_9300_20_OR_LATER(ah))
710 ah->imask |= ATH9K_INT_GTT;
711
712 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
713 ah->imask |= ATH9K_INT_CST;
714
715 ath_mci_enable(sc);
716
717 clear_bit(ATH_OP_INVALID, &common->op_flags);
718 sc->sc_ah->is_monitoring = false;
719
720 if (!ath_complete_reset(sc, false))
721 ah->reset_power_on = false;
722
723 if (ah->led_pin >= 0) {
724 ath9k_hw_cfg_output(ah, ah->led_pin,
725 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
726 ath9k_hw_set_gpio(ah, ah->led_pin,
727 (ah->config.led_active_high) ? 1 : 0);
728 }
729
730 /*
731 * Reset key cache to sane defaults (all entries cleared) instead of
732 * semi-random values after suspend/resume.
733 */
734 ath9k_cmn_init_crypto(sc->sc_ah);
735
736 ath9k_hw_reset_tsf(ah);
737
738 spin_unlock_bh(&sc->sc_pcu_lock);
739
740 mutex_unlock(&sc->mutex);
741
742 ath9k_ps_restore(sc);
743
744 return 0;
745 }
746
ath9k_tx(struct ieee80211_hw * hw,struct ieee80211_tx_control * control,struct sk_buff * skb)747 static void ath9k_tx(struct ieee80211_hw *hw,
748 struct ieee80211_tx_control *control,
749 struct sk_buff *skb)
750 {
751 struct ath_softc *sc = hw->priv;
752 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
753 struct ath_tx_control txctl;
754 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
755 unsigned long flags;
756
757 if (sc->ps_enabled) {
758 /*
759 * mac80211 does not set PM field for normal data frames, so we
760 * need to update that based on the current PS mode.
761 */
762 if (ieee80211_is_data(hdr->frame_control) &&
763 !ieee80211_is_nullfunc(hdr->frame_control) &&
764 !ieee80211_has_pm(hdr->frame_control)) {
765 ath_dbg(common, PS,
766 "Add PM=1 for a TX frame while in PS mode\n");
767 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
768 }
769 }
770
771 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
772 /*
773 * We are using PS-Poll and mac80211 can request TX while in
774 * power save mode. Need to wake up hardware for the TX to be
775 * completed and if needed, also for RX of buffered frames.
776 */
777 ath9k_ps_wakeup(sc);
778 spin_lock_irqsave(&sc->sc_pm_lock, flags);
779 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
780 ath9k_hw_setrxabort(sc->sc_ah, 0);
781 if (ieee80211_is_pspoll(hdr->frame_control)) {
782 ath_dbg(common, PS,
783 "Sending PS-Poll to pick a buffered frame\n");
784 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
785 } else {
786 ath_dbg(common, PS, "Wake up to complete TX\n");
787 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
788 }
789 /*
790 * The actual restore operation will happen only after
791 * the ps_flags bit is cleared. We are just dropping
792 * the ps_usecount here.
793 */
794 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
795 ath9k_ps_restore(sc);
796 }
797
798 /*
799 * Cannot tx while the hardware is in full sleep, it first needs a full
800 * chip reset to recover from that
801 */
802 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
803 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
804 goto exit;
805 }
806
807 memset(&txctl, 0, sizeof(struct ath_tx_control));
808 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
809 txctl.sta = control->sta;
810
811 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
812
813 if (ath_tx_start(hw, skb, &txctl) != 0) {
814 ath_dbg(common, XMIT, "TX failed\n");
815 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
816 goto exit;
817 }
818
819 return;
820 exit:
821 ieee80211_free_txskb(hw, skb);
822 }
823
ath9k_txq_list_has_key(struct list_head * txq_list,u32 keyix)824 static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix)
825 {
826 struct ath_buf *bf;
827 struct ieee80211_tx_info *txinfo;
828 struct ath_frame_info *fi;
829
830 list_for_each_entry(bf, txq_list, list) {
831 if (bf->bf_state.stale || !bf->bf_mpdu)
832 continue;
833
834 txinfo = IEEE80211_SKB_CB(bf->bf_mpdu);
835 fi = (struct ath_frame_info *)&txinfo->rate_driver_data[0];
836 if (fi->keyix == keyix)
837 return true;
838 }
839
840 return false;
841 }
842
ath9k_txq_has_key(struct ath_softc * sc,u32 keyix)843 static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix)
844 {
845 struct ath_hw *ah = sc->sc_ah;
846 int i;
847 struct ath_txq *txq;
848 bool key_in_use = false;
849
850 for (i = 0; !key_in_use && i < ATH9K_NUM_TX_QUEUES; i++) {
851 if (!ATH_TXQ_SETUP(sc, i))
852 continue;
853 txq = &sc->tx.txq[i];
854 if (!txq->axq_depth)
855 continue;
856 if (!ath9k_hw_numtxpending(ah, txq->axq_qnum))
857 continue;
858
859 ath_txq_lock(sc, txq);
860 key_in_use = ath9k_txq_list_has_key(&txq->axq_q, keyix);
861 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
862 int idx = txq->txq_tailidx;
863
864 while (!key_in_use &&
865 !list_empty(&txq->txq_fifo[idx])) {
866 key_in_use = ath9k_txq_list_has_key(
867 &txq->txq_fifo[idx], keyix);
868 INCR(idx, ATH_TXFIFO_DEPTH);
869 }
870 }
871 ath_txq_unlock(sc, txq);
872 }
873
874 return key_in_use;
875 }
876
ath9k_pending_key_del(struct ath_softc * sc,u8 keyix)877 static void ath9k_pending_key_del(struct ath_softc *sc, u8 keyix)
878 {
879 struct ath_hw *ah = sc->sc_ah;
880 struct ath_common *common = ath9k_hw_common(ah);
881
882 if (!test_bit(keyix, ah->pending_del_keymap) ||
883 ath9k_txq_has_key(sc, keyix))
884 return;
885
886 /* No more TXQ frames point to this key cache entry, so delete it. */
887 clear_bit(keyix, ah->pending_del_keymap);
888 ath_key_delete(common, keyix);
889 }
890
ath9k_stop(struct ieee80211_hw * hw)891 static void ath9k_stop(struct ieee80211_hw *hw)
892 {
893 struct ath_softc *sc = hw->priv;
894 struct ath_hw *ah = sc->sc_ah;
895 struct ath_common *common = ath9k_hw_common(ah);
896 bool prev_idle;
897 int i;
898
899 ath9k_deinit_channel_context(sc);
900
901 mutex_lock(&sc->mutex);
902
903 ath_cancel_work(sc);
904
905 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
906 ath_dbg(common, ANY, "Device not present\n");
907 mutex_unlock(&sc->mutex);
908 return;
909 }
910
911 /* Ensure HW is awake when we try to shut it down. */
912 ath9k_ps_wakeup(sc);
913
914 spin_lock_bh(&sc->sc_pcu_lock);
915
916 /* prevent tasklets to enable interrupts once we disable them */
917 ah->imask &= ~ATH9K_INT_GLOBAL;
918
919 /* make sure h/w will not generate any interrupt
920 * before setting the invalid flag. */
921 ath9k_hw_disable_interrupts(ah);
922
923 spin_unlock_bh(&sc->sc_pcu_lock);
924
925 /* we can now sync irq and kill any running tasklets, since we already
926 * disabled interrupts and not holding a spin lock */
927 synchronize_irq(sc->irq);
928 tasklet_kill(&sc->intr_tq);
929 tasklet_kill(&sc->bcon_tasklet);
930
931 prev_idle = sc->ps_idle;
932 sc->ps_idle = true;
933
934 spin_lock_bh(&sc->sc_pcu_lock);
935
936 if (ah->led_pin >= 0) {
937 ath9k_hw_set_gpio(ah, ah->led_pin,
938 (ah->config.led_active_high) ? 0 : 1);
939 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
940 }
941
942 ath_prepare_reset(sc);
943
944 if (sc->rx.frag) {
945 dev_kfree_skb_any(sc->rx.frag);
946 sc->rx.frag = NULL;
947 }
948
949 if (!ah->curchan)
950 ah->curchan = ath9k_cmn_get_channel(hw, ah,
951 &sc->cur_chan->chandef);
952
953 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
954
955 set_bit(ATH_OP_INVALID, &common->op_flags);
956
957 ath9k_hw_phy_disable(ah);
958
959 ath9k_hw_configpcipowersave(ah, true);
960
961 spin_unlock_bh(&sc->sc_pcu_lock);
962
963 for (i = 0; i < ATH_KEYMAX; i++)
964 ath9k_pending_key_del(sc, i);
965
966 /* Clear key cache entries explicitly to get rid of any potentially
967 * remaining keys.
968 */
969 ath9k_cmn_init_crypto(sc->sc_ah);
970
971 ath9k_ps_restore(sc);
972
973 sc->ps_idle = prev_idle;
974
975 mutex_unlock(&sc->mutex);
976
977 ath_dbg(common, CONFIG, "Driver halt\n");
978 }
979
ath9k_uses_beacons(int type)980 static bool ath9k_uses_beacons(int type)
981 {
982 switch (type) {
983 case NL80211_IFTYPE_AP:
984 case NL80211_IFTYPE_ADHOC:
985 case NL80211_IFTYPE_MESH_POINT:
986 return true;
987 default:
988 return false;
989 }
990 }
991
ath9k_vif_iter(struct ath9k_vif_iter_data * iter_data,u8 * mac,struct ieee80211_vif * vif)992 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
993 u8 *mac, struct ieee80211_vif *vif)
994 {
995 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
996 int i;
997
998 if (iter_data->has_hw_macaddr) {
999 for (i = 0; i < ETH_ALEN; i++)
1000 iter_data->mask[i] &=
1001 ~(iter_data->hw_macaddr[i] ^ mac[i]);
1002 } else {
1003 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
1004 iter_data->has_hw_macaddr = true;
1005 }
1006
1007 if (!vif->bss_conf.use_short_slot)
1008 iter_data->slottime = ATH9K_SLOT_TIME_20;
1009
1010 switch (vif->type) {
1011 case NL80211_IFTYPE_AP:
1012 iter_data->naps++;
1013 break;
1014 case NL80211_IFTYPE_STATION:
1015 iter_data->nstations++;
1016 if (avp->assoc && !iter_data->primary_sta)
1017 iter_data->primary_sta = vif;
1018 break;
1019 case NL80211_IFTYPE_OCB:
1020 iter_data->nocbs++;
1021 break;
1022 case NL80211_IFTYPE_ADHOC:
1023 iter_data->nadhocs++;
1024 if (vif->bss_conf.enable_beacon)
1025 iter_data->beacons = true;
1026 break;
1027 case NL80211_IFTYPE_MESH_POINT:
1028 iter_data->nmeshes++;
1029 if (vif->bss_conf.enable_beacon)
1030 iter_data->beacons = true;
1031 break;
1032 case NL80211_IFTYPE_WDS:
1033 iter_data->nwds++;
1034 break;
1035 default:
1036 break;
1037 }
1038 }
1039
ath9k_update_bssid_mask(struct ath_softc * sc,struct ath_chanctx * ctx,struct ath9k_vif_iter_data * iter_data)1040 static void ath9k_update_bssid_mask(struct ath_softc *sc,
1041 struct ath_chanctx *ctx,
1042 struct ath9k_vif_iter_data *iter_data)
1043 {
1044 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1045 struct ath_vif *avp;
1046 int i;
1047
1048 if (!ath9k_is_chanctx_enabled())
1049 return;
1050
1051 list_for_each_entry(avp, &ctx->vifs, list) {
1052 if (ctx->nvifs_assigned != 1)
1053 continue;
1054
1055 if (!avp->vif->p2p || !iter_data->has_hw_macaddr)
1056 continue;
1057
1058 ether_addr_copy(common->curbssid, avp->bssid);
1059
1060 /* perm_addr will be used as the p2p device address. */
1061 for (i = 0; i < ETH_ALEN; i++)
1062 iter_data->mask[i] &=
1063 ~(iter_data->hw_macaddr[i] ^
1064 sc->hw->wiphy->perm_addr[i]);
1065 }
1066 }
1067
1068 /* Called with sc->mutex held. */
ath9k_calculate_iter_data(struct ath_softc * sc,struct ath_chanctx * ctx,struct ath9k_vif_iter_data * iter_data)1069 void ath9k_calculate_iter_data(struct ath_softc *sc,
1070 struct ath_chanctx *ctx,
1071 struct ath9k_vif_iter_data *iter_data)
1072 {
1073 struct ath_vif *avp;
1074
1075 /*
1076 * The hardware will use primary station addr together with the
1077 * BSSID mask when matching addresses.
1078 */
1079 memset(iter_data, 0, sizeof(*iter_data));
1080 eth_broadcast_addr(iter_data->mask);
1081 iter_data->slottime = ATH9K_SLOT_TIME_9;
1082
1083 list_for_each_entry(avp, &ctx->vifs, list)
1084 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1085
1086 ath9k_update_bssid_mask(sc, ctx, iter_data);
1087 }
1088
ath9k_set_assoc_state(struct ath_softc * sc,struct ieee80211_vif * vif,bool changed)1089 static void ath9k_set_assoc_state(struct ath_softc *sc,
1090 struct ieee80211_vif *vif, bool changed)
1091 {
1092 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1093 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1094 unsigned long flags;
1095
1096 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1097
1098 ether_addr_copy(common->curbssid, avp->bssid);
1099 common->curaid = avp->aid;
1100 ath9k_hw_write_associd(sc->sc_ah);
1101
1102 if (changed) {
1103 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1104 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1105
1106 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1107 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1108 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1109 }
1110
1111 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1112 ath9k_mci_update_wlan_channels(sc, false);
1113
1114 ath_dbg(common, CONFIG,
1115 "Primary Station interface: %pM, BSSID: %pM\n",
1116 vif->addr, common->curbssid);
1117 }
1118
1119 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
ath9k_set_offchannel_state(struct ath_softc * sc)1120 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1121 {
1122 struct ath_hw *ah = sc->sc_ah;
1123 struct ath_common *common = ath9k_hw_common(ah);
1124 struct ieee80211_vif *vif = NULL;
1125
1126 ath9k_ps_wakeup(sc);
1127
1128 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1129 vif = sc->offchannel.scan_vif;
1130 else
1131 vif = sc->offchannel.roc_vif;
1132
1133 if (WARN_ON(!vif))
1134 goto exit;
1135
1136 eth_zero_addr(common->curbssid);
1137 eth_broadcast_addr(common->bssidmask);
1138 memcpy(common->macaddr, vif->addr, ETH_ALEN);
1139 common->curaid = 0;
1140 ah->opmode = vif->type;
1141 ah->imask &= ~ATH9K_INT_SWBA;
1142 ah->imask &= ~ATH9K_INT_TSFOOR;
1143 ah->slottime = ATH9K_SLOT_TIME_9;
1144
1145 ath_hw_setbssidmask(common);
1146 ath9k_hw_setopmode(ah);
1147 ath9k_hw_write_associd(sc->sc_ah);
1148 ath9k_hw_set_interrupts(ah);
1149 ath9k_hw_init_global_settings(ah);
1150
1151 exit:
1152 ath9k_ps_restore(sc);
1153 }
1154 #endif
1155
1156 /* Called with sc->mutex held. */
ath9k_calculate_summary_state(struct ath_softc * sc,struct ath_chanctx * ctx)1157 void ath9k_calculate_summary_state(struct ath_softc *sc,
1158 struct ath_chanctx *ctx)
1159 {
1160 struct ath_hw *ah = sc->sc_ah;
1161 struct ath_common *common = ath9k_hw_common(ah);
1162 struct ath9k_vif_iter_data iter_data;
1163 struct ath_beacon_config *cur_conf;
1164
1165 ath_chanctx_check_active(sc, ctx);
1166
1167 if (ctx != sc->cur_chan)
1168 return;
1169
1170 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1171 if (ctx == &sc->offchannel.chan)
1172 return ath9k_set_offchannel_state(sc);
1173 #endif
1174
1175 ath9k_ps_wakeup(sc);
1176 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1177
1178 if (iter_data.has_hw_macaddr)
1179 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1180
1181 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1182 ath_hw_setbssidmask(common);
1183
1184 if (iter_data.naps > 0) {
1185 cur_conf = &ctx->beacon;
1186 ath9k_hw_set_tsfadjust(ah, true);
1187 ah->opmode = NL80211_IFTYPE_AP;
1188 if (cur_conf->enable_beacon)
1189 iter_data.beacons = true;
1190 } else {
1191 ath9k_hw_set_tsfadjust(ah, false);
1192
1193 if (iter_data.nmeshes)
1194 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1195 else if (iter_data.nocbs)
1196 ah->opmode = NL80211_IFTYPE_OCB;
1197 else if (iter_data.nwds)
1198 ah->opmode = NL80211_IFTYPE_AP;
1199 else if (iter_data.nadhocs)
1200 ah->opmode = NL80211_IFTYPE_ADHOC;
1201 else
1202 ah->opmode = NL80211_IFTYPE_STATION;
1203 }
1204
1205 ath9k_hw_setopmode(ah);
1206
1207 ctx->switch_after_beacon = false;
1208 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1209 ah->imask |= ATH9K_INT_TSFOOR;
1210 else {
1211 ah->imask &= ~ATH9K_INT_TSFOOR;
1212 if (iter_data.naps == 1 && iter_data.beacons)
1213 ctx->switch_after_beacon = true;
1214 }
1215
1216 ah->imask &= ~ATH9K_INT_SWBA;
1217 if (ah->opmode == NL80211_IFTYPE_STATION) {
1218 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1219
1220 if (iter_data.primary_sta) {
1221 iter_data.beacons = true;
1222 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1223 changed);
1224 ctx->primary_sta = iter_data.primary_sta;
1225 } else {
1226 ctx->primary_sta = NULL;
1227 eth_zero_addr(common->curbssid);
1228 common->curaid = 0;
1229 ath9k_hw_write_associd(sc->sc_ah);
1230 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1231 ath9k_mci_update_wlan_channels(sc, true);
1232 }
1233 } else if (iter_data.beacons) {
1234 ah->imask |= ATH9K_INT_SWBA;
1235 }
1236 ath9k_hw_set_interrupts(ah);
1237
1238 if (iter_data.beacons)
1239 set_bit(ATH_OP_BEACONS, &common->op_flags);
1240 else
1241 clear_bit(ATH_OP_BEACONS, &common->op_flags);
1242
1243 if (ah->slottime != iter_data.slottime) {
1244 ah->slottime = iter_data.slottime;
1245 ath9k_hw_init_global_settings(ah);
1246 }
1247
1248 if (iter_data.primary_sta)
1249 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1250 else
1251 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1252
1253 ath_dbg(common, CONFIG,
1254 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1255 common->macaddr, common->curbssid, common->bssidmask);
1256
1257 ath9k_ps_restore(sc);
1258 }
1259
ath9k_tpc_vif_iter(void * data,u8 * mac,struct ieee80211_vif * vif)1260 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1261 {
1262 int *power = (int *)data;
1263
1264 if (*power < vif->bss_conf.txpower)
1265 *power = vif->bss_conf.txpower;
1266 }
1267
1268 /* Called with sc->mutex held. */
ath9k_set_txpower(struct ath_softc * sc,struct ieee80211_vif * vif)1269 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1270 {
1271 int power;
1272 struct ath_hw *ah = sc->sc_ah;
1273 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1274
1275 ath9k_ps_wakeup(sc);
1276 if (ah->tpc_enabled) {
1277 power = (vif) ? vif->bss_conf.txpower : -1;
1278 ieee80211_iterate_active_interfaces_atomic(
1279 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1280 ath9k_tpc_vif_iter, &power);
1281 if (power == -1)
1282 power = sc->hw->conf.power_level;
1283 } else {
1284 power = sc->hw->conf.power_level;
1285 }
1286 sc->cur_chan->txpower = 2 * power;
1287 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1288 sc->cur_chan->cur_txpower = reg->max_power_level;
1289 ath9k_ps_restore(sc);
1290 }
1291
ath9k_assign_hw_queues(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1292 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1293 struct ieee80211_vif *vif)
1294 {
1295 int i;
1296
1297 if (!ath9k_is_chanctx_enabled())
1298 return;
1299
1300 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1301 vif->hw_queue[i] = i;
1302
1303 if (vif->type == NL80211_IFTYPE_AP ||
1304 vif->type == NL80211_IFTYPE_MESH_POINT)
1305 vif->cab_queue = hw->queues - 2;
1306 else
1307 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1308 }
1309
ath9k_add_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1310 static int ath9k_add_interface(struct ieee80211_hw *hw,
1311 struct ieee80211_vif *vif)
1312 {
1313 struct ath_softc *sc = hw->priv;
1314 struct ath_hw *ah = sc->sc_ah;
1315 struct ath_common *common = ath9k_hw_common(ah);
1316 struct ath_vif *avp = (void *)vif->drv_priv;
1317 struct ath_node *an = &avp->mcast_node;
1318
1319 mutex_lock(&sc->mutex);
1320
1321 if (config_enabled(CONFIG_ATH9K_TX99)) {
1322 if (sc->cur_chan->nvifs >= 1) {
1323 mutex_unlock(&sc->mutex);
1324 return -EOPNOTSUPP;
1325 }
1326 sc->tx99_vif = vif;
1327 }
1328
1329 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1330 sc->cur_chan->nvifs++;
1331
1332 if (ath9k_uses_beacons(vif->type))
1333 ath9k_beacon_assign_slot(sc, vif);
1334
1335 avp->vif = vif;
1336 if (!ath9k_is_chanctx_enabled()) {
1337 avp->chanctx = sc->cur_chan;
1338 list_add_tail(&avp->list, &avp->chanctx->vifs);
1339 }
1340
1341 ath9k_calculate_summary_state(sc, avp->chanctx);
1342
1343 ath9k_assign_hw_queues(hw, vif);
1344
1345 ath9k_set_txpower(sc, vif);
1346
1347 an->sc = sc;
1348 an->sta = NULL;
1349 an->vif = vif;
1350 an->no_ps_filter = true;
1351 ath_tx_node_init(sc, an);
1352
1353 mutex_unlock(&sc->mutex);
1354 return 0;
1355 }
1356
ath9k_change_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif,enum nl80211_iftype new_type,bool p2p)1357 static int ath9k_change_interface(struct ieee80211_hw *hw,
1358 struct ieee80211_vif *vif,
1359 enum nl80211_iftype new_type,
1360 bool p2p)
1361 {
1362 struct ath_softc *sc = hw->priv;
1363 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1364 struct ath_vif *avp = (void *)vif->drv_priv;
1365
1366 mutex_lock(&sc->mutex);
1367
1368 if (config_enabled(CONFIG_ATH9K_TX99)) {
1369 mutex_unlock(&sc->mutex);
1370 return -EOPNOTSUPP;
1371 }
1372
1373 ath_dbg(common, CONFIG, "Change Interface\n");
1374
1375 if (ath9k_uses_beacons(vif->type))
1376 ath9k_beacon_remove_slot(sc, vif);
1377
1378 vif->type = new_type;
1379 vif->p2p = p2p;
1380
1381 if (ath9k_uses_beacons(vif->type))
1382 ath9k_beacon_assign_slot(sc, vif);
1383
1384 ath9k_assign_hw_queues(hw, vif);
1385 ath9k_calculate_summary_state(sc, avp->chanctx);
1386
1387 ath9k_set_txpower(sc, vif);
1388
1389 mutex_unlock(&sc->mutex);
1390 return 0;
1391 }
1392
ath9k_remove_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1393 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1394 struct ieee80211_vif *vif)
1395 {
1396 struct ath_softc *sc = hw->priv;
1397 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1398 struct ath_vif *avp = (void *)vif->drv_priv;
1399
1400 ath_dbg(common, CONFIG, "Detach Interface\n");
1401
1402 mutex_lock(&sc->mutex);
1403
1404 ath9k_p2p_remove_vif(sc, vif);
1405
1406 sc->cur_chan->nvifs--;
1407 sc->tx99_vif = NULL;
1408 if (!ath9k_is_chanctx_enabled())
1409 list_del(&avp->list);
1410
1411 if (ath9k_uses_beacons(vif->type))
1412 ath9k_beacon_remove_slot(sc, vif);
1413
1414 ath_tx_node_cleanup(sc, &avp->mcast_node);
1415
1416 ath9k_calculate_summary_state(sc, avp->chanctx);
1417
1418 ath9k_set_txpower(sc, NULL);
1419
1420 mutex_unlock(&sc->mutex);
1421 }
1422
ath9k_enable_ps(struct ath_softc * sc)1423 static void ath9k_enable_ps(struct ath_softc *sc)
1424 {
1425 struct ath_hw *ah = sc->sc_ah;
1426 struct ath_common *common = ath9k_hw_common(ah);
1427
1428 if (config_enabled(CONFIG_ATH9K_TX99))
1429 return;
1430
1431 sc->ps_enabled = true;
1432 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1433 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1434 ah->imask |= ATH9K_INT_TIM_TIMER;
1435 ath9k_hw_set_interrupts(ah);
1436 }
1437 ath9k_hw_setrxabort(ah, 1);
1438 }
1439 ath_dbg(common, PS, "PowerSave enabled\n");
1440 }
1441
ath9k_disable_ps(struct ath_softc * sc)1442 static void ath9k_disable_ps(struct ath_softc *sc)
1443 {
1444 struct ath_hw *ah = sc->sc_ah;
1445 struct ath_common *common = ath9k_hw_common(ah);
1446
1447 if (config_enabled(CONFIG_ATH9K_TX99))
1448 return;
1449
1450 sc->ps_enabled = false;
1451 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1452 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1453 ath9k_hw_setrxabort(ah, 0);
1454 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1455 PS_WAIT_FOR_CAB |
1456 PS_WAIT_FOR_PSPOLL_DATA |
1457 PS_WAIT_FOR_TX_ACK);
1458 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1459 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1460 ath9k_hw_set_interrupts(ah);
1461 }
1462 }
1463 ath_dbg(common, PS, "PowerSave disabled\n");
1464 }
1465
ath9k_config(struct ieee80211_hw * hw,u32 changed)1466 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1467 {
1468 struct ath_softc *sc = hw->priv;
1469 struct ath_hw *ah = sc->sc_ah;
1470 struct ath_common *common = ath9k_hw_common(ah);
1471 struct ieee80211_conf *conf = &hw->conf;
1472 struct ath_chanctx *ctx = sc->cur_chan;
1473
1474 ath9k_ps_wakeup(sc);
1475 mutex_lock(&sc->mutex);
1476
1477 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1478 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1479 if (sc->ps_idle) {
1480 ath_cancel_work(sc);
1481 ath9k_stop_btcoex(sc);
1482 } else {
1483 ath9k_start_btcoex(sc);
1484 /*
1485 * The chip needs a reset to properly wake up from
1486 * full sleep
1487 */
1488 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1489 }
1490 }
1491
1492 /*
1493 * We just prepare to enable PS. We have to wait until our AP has
1494 * ACK'd our null data frame to disable RX otherwise we'll ignore
1495 * those ACKs and end up retransmitting the same null data frames.
1496 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1497 */
1498 if (changed & IEEE80211_CONF_CHANGE_PS) {
1499 unsigned long flags;
1500 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1501 if (conf->flags & IEEE80211_CONF_PS)
1502 ath9k_enable_ps(sc);
1503 else
1504 ath9k_disable_ps(sc);
1505 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1506 }
1507
1508 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1509 if (conf->flags & IEEE80211_CONF_MONITOR) {
1510 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1511 sc->sc_ah->is_monitoring = true;
1512 } else {
1513 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1514 sc->sc_ah->is_monitoring = false;
1515 }
1516 }
1517
1518 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1519 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1520 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1521 }
1522
1523 if (changed & IEEE80211_CONF_CHANGE_POWER)
1524 ath9k_set_txpower(sc, NULL);
1525
1526 mutex_unlock(&sc->mutex);
1527 ath9k_ps_restore(sc);
1528
1529 return 0;
1530 }
1531
1532 #define SUPPORTED_FILTERS \
1533 (FIF_ALLMULTI | \
1534 FIF_CONTROL | \
1535 FIF_PSPOLL | \
1536 FIF_OTHER_BSS | \
1537 FIF_BCN_PRBRESP_PROMISC | \
1538 FIF_PROBE_REQ | \
1539 FIF_FCSFAIL)
1540
1541 /* FIXME: sc->sc_full_reset ? */
ath9k_configure_filter(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags,u64 multicast)1542 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1543 unsigned int changed_flags,
1544 unsigned int *total_flags,
1545 u64 multicast)
1546 {
1547 struct ath_softc *sc = hw->priv;
1548 struct ath_chanctx *ctx;
1549 u32 rfilt;
1550
1551 changed_flags &= SUPPORTED_FILTERS;
1552 *total_flags &= SUPPORTED_FILTERS;
1553
1554 spin_lock_bh(&sc->chan_lock);
1555 ath_for_each_chanctx(sc, ctx)
1556 ctx->rxfilter = *total_flags;
1557 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1558 sc->offchannel.chan.rxfilter = *total_flags;
1559 #endif
1560 spin_unlock_bh(&sc->chan_lock);
1561
1562 ath9k_ps_wakeup(sc);
1563 rfilt = ath_calcrxfilter(sc);
1564 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1565 ath9k_ps_restore(sc);
1566
1567 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1568 rfilt);
1569 }
1570
ath9k_sta_add(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1571 static int ath9k_sta_add(struct ieee80211_hw *hw,
1572 struct ieee80211_vif *vif,
1573 struct ieee80211_sta *sta)
1574 {
1575 struct ath_softc *sc = hw->priv;
1576 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1577 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1578 struct ieee80211_key_conf ps_key = { };
1579 int key;
1580
1581 ath_node_attach(sc, sta, vif);
1582
1583 if (vif->type != NL80211_IFTYPE_AP &&
1584 vif->type != NL80211_IFTYPE_AP_VLAN)
1585 return 0;
1586
1587 key = ath_key_config(common, vif, sta, &ps_key);
1588 if (key > 0) {
1589 an->ps_key = key;
1590 an->key_idx[0] = key;
1591 }
1592
1593 return 0;
1594 }
1595
ath9k_del_ps_key(struct ath_softc * sc,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1596 static void ath9k_del_ps_key(struct ath_softc *sc,
1597 struct ieee80211_vif *vif,
1598 struct ieee80211_sta *sta)
1599 {
1600 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1601 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1602
1603 if (!an->ps_key)
1604 return;
1605
1606 ath_key_delete(common, an->ps_key);
1607 an->ps_key = 0;
1608 an->key_idx[0] = 0;
1609 }
1610
ath9k_sta_remove(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1611 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1612 struct ieee80211_vif *vif,
1613 struct ieee80211_sta *sta)
1614 {
1615 struct ath_softc *sc = hw->priv;
1616
1617 ath9k_del_ps_key(sc, vif, sta);
1618 ath_node_detach(sc, sta);
1619
1620 return 0;
1621 }
1622
ath9k_sta_state(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,enum ieee80211_sta_state old_state,enum ieee80211_sta_state new_state)1623 static int ath9k_sta_state(struct ieee80211_hw *hw,
1624 struct ieee80211_vif *vif,
1625 struct ieee80211_sta *sta,
1626 enum ieee80211_sta_state old_state,
1627 enum ieee80211_sta_state new_state)
1628 {
1629 struct ath_softc *sc = hw->priv;
1630 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1631 int ret = 0;
1632
1633 if (old_state == IEEE80211_STA_NOTEXIST &&
1634 new_state == IEEE80211_STA_NONE) {
1635 ret = ath9k_sta_add(hw, vif, sta);
1636 ath_dbg(common, CONFIG,
1637 "Add station: %pM\n", sta->addr);
1638 } else if (old_state == IEEE80211_STA_NONE &&
1639 new_state == IEEE80211_STA_NOTEXIST) {
1640 ret = ath9k_sta_remove(hw, vif, sta);
1641 ath_dbg(common, CONFIG,
1642 "Remove station: %pM\n", sta->addr);
1643 }
1644
1645 if (ath9k_is_chanctx_enabled()) {
1646 if (vif->type == NL80211_IFTYPE_STATION) {
1647 if (old_state == IEEE80211_STA_ASSOC &&
1648 new_state == IEEE80211_STA_AUTHORIZED)
1649 ath_chanctx_event(sc, vif,
1650 ATH_CHANCTX_EVENT_AUTHORIZED);
1651 }
1652 }
1653
1654 return ret;
1655 }
1656
ath9k_sta_set_tx_filter(struct ath_hw * ah,struct ath_node * an,bool set)1657 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1658 struct ath_node *an,
1659 bool set)
1660 {
1661 int i;
1662
1663 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1664 if (!an->key_idx[i])
1665 continue;
1666 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1667 }
1668 }
1669
ath9k_sta_notify(struct ieee80211_hw * hw,struct ieee80211_vif * vif,enum sta_notify_cmd cmd,struct ieee80211_sta * sta)1670 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1671 struct ieee80211_vif *vif,
1672 enum sta_notify_cmd cmd,
1673 struct ieee80211_sta *sta)
1674 {
1675 struct ath_softc *sc = hw->priv;
1676 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1677
1678 switch (cmd) {
1679 case STA_NOTIFY_SLEEP:
1680 an->sleeping = true;
1681 ath_tx_aggr_sleep(sta, sc, an);
1682 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1683 break;
1684 case STA_NOTIFY_AWAKE:
1685 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1686 an->sleeping = false;
1687 ath_tx_aggr_wakeup(sc, an);
1688 break;
1689 }
1690 }
1691
ath9k_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 queue,const struct ieee80211_tx_queue_params * params)1692 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1693 struct ieee80211_vif *vif, u16 queue,
1694 const struct ieee80211_tx_queue_params *params)
1695 {
1696 struct ath_softc *sc = hw->priv;
1697 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1698 struct ath_txq *txq;
1699 struct ath9k_tx_queue_info qi;
1700 int ret = 0;
1701
1702 if (queue >= IEEE80211_NUM_ACS)
1703 return 0;
1704
1705 txq = sc->tx.txq_map[queue];
1706
1707 ath9k_ps_wakeup(sc);
1708 mutex_lock(&sc->mutex);
1709
1710 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1711
1712 qi.tqi_aifs = params->aifs;
1713 qi.tqi_cwmin = params->cw_min;
1714 qi.tqi_cwmax = params->cw_max;
1715 qi.tqi_burstTime = params->txop * 32;
1716
1717 ath_dbg(common, CONFIG,
1718 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1719 queue, txq->axq_qnum, params->aifs, params->cw_min,
1720 params->cw_max, params->txop);
1721
1722 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1723 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1724 if (ret)
1725 ath_err(common, "TXQ Update failed\n");
1726
1727 mutex_unlock(&sc->mutex);
1728 ath9k_ps_restore(sc);
1729
1730 return ret;
1731 }
1732
ath9k_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key)1733 static int ath9k_set_key(struct ieee80211_hw *hw,
1734 enum set_key_cmd cmd,
1735 struct ieee80211_vif *vif,
1736 struct ieee80211_sta *sta,
1737 struct ieee80211_key_conf *key)
1738 {
1739 struct ath_softc *sc = hw->priv;
1740 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1741 struct ath_node *an = NULL;
1742 int ret = 0, i;
1743
1744 if (ath9k_modparam_nohwcrypt)
1745 return -ENOSPC;
1746
1747 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1748 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1749 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1750 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1751 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1752 /*
1753 * For now, disable hw crypto for the RSN IBSS group keys. This
1754 * could be optimized in the future to use a modified key cache
1755 * design to support per-STA RX GTK, but until that gets
1756 * implemented, use of software crypto for group addressed
1757 * frames is a acceptable to allow RSN IBSS to be used.
1758 */
1759 return -EOPNOTSUPP;
1760 }
1761
1762 mutex_lock(&sc->mutex);
1763 ath9k_ps_wakeup(sc);
1764 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1765 if (sta)
1766 an = (struct ath_node *)sta->drv_priv;
1767
1768 /* Delete pending key cache entries if no more frames are pointing to
1769 * them in TXQs.
1770 */
1771 for (i = 0; i < ATH_KEYMAX; i++)
1772 ath9k_pending_key_del(sc, i);
1773
1774 switch (cmd) {
1775 case SET_KEY:
1776 if (sta)
1777 ath9k_del_ps_key(sc, vif, sta);
1778
1779 key->hw_key_idx = 0;
1780 ret = ath_key_config(common, vif, sta, key);
1781 if (ret >= 0) {
1782 key->hw_key_idx = ret;
1783 /* push IV and Michael MIC generation to stack */
1784 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1785 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1786 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1787 if (sc->sc_ah->sw_mgmt_crypto_tx &&
1788 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1789 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1790 ret = 0;
1791 }
1792 if (an && key->hw_key_idx) {
1793 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1794 if (an->key_idx[i])
1795 continue;
1796 an->key_idx[i] = key->hw_key_idx;
1797 break;
1798 }
1799 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1800 }
1801 break;
1802 case DISABLE_KEY:
1803 if (ath9k_txq_has_key(sc, key->hw_key_idx)) {
1804 /* Delay key cache entry deletion until there are no
1805 * remaining TXQ frames pointing to this entry.
1806 */
1807 set_bit(key->hw_key_idx, sc->sc_ah->pending_del_keymap);
1808 ath_hw_keysetmac(common, key->hw_key_idx, NULL);
1809 } else {
1810 ath_key_delete(common, key->hw_key_idx);
1811 }
1812 if (an) {
1813 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1814 if (an->key_idx[i] != key->hw_key_idx)
1815 continue;
1816 an->key_idx[i] = 0;
1817 break;
1818 }
1819 }
1820 key->hw_key_idx = 0;
1821 break;
1822 default:
1823 ret = -EINVAL;
1824 }
1825
1826 ath9k_ps_restore(sc);
1827 mutex_unlock(&sc->mutex);
1828
1829 return ret;
1830 }
1831
ath9k_bss_info_changed(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf,u32 changed)1832 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1833 struct ieee80211_vif *vif,
1834 struct ieee80211_bss_conf *bss_conf,
1835 u32 changed)
1836 {
1837 #define CHECK_ANI \
1838 (BSS_CHANGED_ASSOC | \
1839 BSS_CHANGED_IBSS | \
1840 BSS_CHANGED_BEACON_ENABLED)
1841
1842 struct ath_softc *sc = hw->priv;
1843 struct ath_hw *ah = sc->sc_ah;
1844 struct ath_common *common = ath9k_hw_common(ah);
1845 struct ath_vif *avp = (void *)vif->drv_priv;
1846 int slottime;
1847
1848 ath9k_ps_wakeup(sc);
1849 mutex_lock(&sc->mutex);
1850
1851 if (changed & BSS_CHANGED_ASSOC) {
1852 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1853 bss_conf->bssid, bss_conf->assoc);
1854
1855 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1856 avp->aid = bss_conf->aid;
1857 avp->assoc = bss_conf->assoc;
1858
1859 ath9k_calculate_summary_state(sc, avp->chanctx);
1860 }
1861
1862 if ((changed & BSS_CHANGED_IBSS) ||
1863 (changed & BSS_CHANGED_OCB)) {
1864 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1865 common->curaid = bss_conf->aid;
1866 ath9k_hw_write_associd(sc->sc_ah);
1867 }
1868
1869 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1870 (changed & BSS_CHANGED_BEACON_INT) ||
1871 (changed & BSS_CHANGED_BEACON_INFO)) {
1872 ath9k_beacon_config(sc, vif, changed);
1873 if (changed & BSS_CHANGED_BEACON_ENABLED)
1874 ath9k_calculate_summary_state(sc, avp->chanctx);
1875 }
1876
1877 if ((avp->chanctx == sc->cur_chan) &&
1878 (changed & BSS_CHANGED_ERP_SLOT)) {
1879 if (bss_conf->use_short_slot)
1880 slottime = 9;
1881 else
1882 slottime = 20;
1883 if (vif->type == NL80211_IFTYPE_AP) {
1884 /*
1885 * Defer update, so that connected stations can adjust
1886 * their settings at the same time.
1887 * See beacon.c for more details
1888 */
1889 sc->beacon.slottime = slottime;
1890 sc->beacon.updateslot = UPDATE;
1891 } else {
1892 ah->slottime = slottime;
1893 ath9k_hw_init_global_settings(ah);
1894 }
1895 }
1896
1897 if (changed & BSS_CHANGED_P2P_PS)
1898 ath9k_p2p_bss_info_changed(sc, vif);
1899
1900 if (changed & CHECK_ANI)
1901 ath_check_ani(sc);
1902
1903 if (changed & BSS_CHANGED_TXPOWER) {
1904 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1905 vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1906 ath9k_set_txpower(sc, vif);
1907 }
1908
1909 mutex_unlock(&sc->mutex);
1910 ath9k_ps_restore(sc);
1911
1912 #undef CHECK_ANI
1913 }
1914
ath9k_get_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1915 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1916 {
1917 struct ath_softc *sc = hw->priv;
1918 u64 tsf;
1919
1920 mutex_lock(&sc->mutex);
1921 ath9k_ps_wakeup(sc);
1922 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1923 ath9k_ps_restore(sc);
1924 mutex_unlock(&sc->mutex);
1925
1926 return tsf;
1927 }
1928
ath9k_set_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u64 tsf)1929 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1930 struct ieee80211_vif *vif,
1931 u64 tsf)
1932 {
1933 struct ath_softc *sc = hw->priv;
1934
1935 mutex_lock(&sc->mutex);
1936 ath9k_ps_wakeup(sc);
1937 ath9k_hw_settsf64(sc->sc_ah, tsf);
1938 ath9k_ps_restore(sc);
1939 mutex_unlock(&sc->mutex);
1940 }
1941
ath9k_reset_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1942 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1943 {
1944 struct ath_softc *sc = hw->priv;
1945
1946 mutex_lock(&sc->mutex);
1947
1948 ath9k_ps_wakeup(sc);
1949 ath9k_hw_reset_tsf(sc->sc_ah);
1950 ath9k_ps_restore(sc);
1951
1952 mutex_unlock(&sc->mutex);
1953 }
1954
ath9k_ampdu_action(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_ampdu_params * params)1955 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1956 struct ieee80211_vif *vif,
1957 struct ieee80211_ampdu_params *params)
1958 {
1959 struct ath_softc *sc = hw->priv;
1960 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1961 bool flush = false;
1962 int ret = 0;
1963 struct ieee80211_sta *sta = params->sta;
1964 enum ieee80211_ampdu_mlme_action action = params->action;
1965 u16 tid = params->tid;
1966 u16 *ssn = ¶ms->ssn;
1967
1968 mutex_lock(&sc->mutex);
1969
1970 switch (action) {
1971 case IEEE80211_AMPDU_RX_START:
1972 break;
1973 case IEEE80211_AMPDU_RX_STOP:
1974 break;
1975 case IEEE80211_AMPDU_TX_START:
1976 if (ath9k_is_chanctx_enabled()) {
1977 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
1978 ret = -EBUSY;
1979 break;
1980 }
1981 }
1982 ath9k_ps_wakeup(sc);
1983 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1984 if (!ret)
1985 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1986 ath9k_ps_restore(sc);
1987 break;
1988 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1989 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1990 flush = true;
1991 case IEEE80211_AMPDU_TX_STOP_CONT:
1992 ath9k_ps_wakeup(sc);
1993 ath_tx_aggr_stop(sc, sta, tid);
1994 if (!flush)
1995 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1996 ath9k_ps_restore(sc);
1997 break;
1998 case IEEE80211_AMPDU_TX_OPERATIONAL:
1999 ath9k_ps_wakeup(sc);
2000 ath_tx_aggr_resume(sc, sta, tid);
2001 ath9k_ps_restore(sc);
2002 break;
2003 default:
2004 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
2005 }
2006
2007 mutex_unlock(&sc->mutex);
2008
2009 return ret;
2010 }
2011
ath9k_get_survey(struct ieee80211_hw * hw,int idx,struct survey_info * survey)2012 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2013 struct survey_info *survey)
2014 {
2015 struct ath_softc *sc = hw->priv;
2016 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2017 struct ieee80211_supported_band *sband;
2018 struct ieee80211_channel *chan;
2019 int pos;
2020
2021 if (config_enabled(CONFIG_ATH9K_TX99))
2022 return -EOPNOTSUPP;
2023
2024 spin_lock_bh(&common->cc_lock);
2025 if (idx == 0)
2026 ath_update_survey_stats(sc);
2027
2028 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2029 if (sband && idx >= sband->n_channels) {
2030 idx -= sband->n_channels;
2031 sband = NULL;
2032 }
2033
2034 if (!sband)
2035 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
2036
2037 if (!sband || idx >= sband->n_channels) {
2038 spin_unlock_bh(&common->cc_lock);
2039 return -ENOENT;
2040 }
2041
2042 chan = &sband->channels[idx];
2043 pos = chan->hw_value;
2044 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2045 survey->channel = chan;
2046 spin_unlock_bh(&common->cc_lock);
2047
2048 return 0;
2049 }
2050
ath9k_enable_dynack(struct ath_softc * sc)2051 static void ath9k_enable_dynack(struct ath_softc *sc)
2052 {
2053 #ifdef CONFIG_ATH9K_DYNACK
2054 u32 rfilt;
2055 struct ath_hw *ah = sc->sc_ah;
2056
2057 ath_dynack_reset(ah);
2058
2059 ah->dynack.enabled = true;
2060 rfilt = ath_calcrxfilter(sc);
2061 ath9k_hw_setrxfilter(ah, rfilt);
2062 #endif
2063 }
2064
ath9k_set_coverage_class(struct ieee80211_hw * hw,s16 coverage_class)2065 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
2066 s16 coverage_class)
2067 {
2068 struct ath_softc *sc = hw->priv;
2069 struct ath_hw *ah = sc->sc_ah;
2070
2071 if (config_enabled(CONFIG_ATH9K_TX99))
2072 return;
2073
2074 mutex_lock(&sc->mutex);
2075
2076 if (coverage_class >= 0) {
2077 ah->coverage_class = coverage_class;
2078 if (ah->dynack.enabled) {
2079 u32 rfilt;
2080
2081 ah->dynack.enabled = false;
2082 rfilt = ath_calcrxfilter(sc);
2083 ath9k_hw_setrxfilter(ah, rfilt);
2084 }
2085 ath9k_ps_wakeup(sc);
2086 ath9k_hw_init_global_settings(ah);
2087 ath9k_ps_restore(sc);
2088 } else if (!ah->dynack.enabled) {
2089 ath9k_enable_dynack(sc);
2090 }
2091
2092 mutex_unlock(&sc->mutex);
2093 }
2094
ath9k_has_tx_pending(struct ath_softc * sc,bool sw_pending)2095 static bool ath9k_has_tx_pending(struct ath_softc *sc,
2096 bool sw_pending)
2097 {
2098 int i, npend = 0;
2099
2100 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2101 if (!ATH_TXQ_SETUP(sc, i))
2102 continue;
2103
2104 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2105 sw_pending);
2106 if (npend)
2107 break;
2108 }
2109
2110 return !!npend;
2111 }
2112
ath9k_flush(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u32 queues,bool drop)2113 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2114 u32 queues, bool drop)
2115 {
2116 struct ath_softc *sc = hw->priv;
2117 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2118
2119 if (ath9k_is_chanctx_enabled()) {
2120 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2121 goto flush;
2122
2123 /*
2124 * If MCC is active, extend the flush timeout
2125 * and wait for the HW/SW queues to become
2126 * empty. This needs to be done outside the
2127 * sc->mutex lock to allow the channel scheduler
2128 * to switch channel contexts.
2129 *
2130 * The vif queues have been stopped in mac80211,
2131 * so there won't be any incoming frames.
2132 */
2133 __ath9k_flush(hw, queues, drop, true, true);
2134 return;
2135 }
2136 flush:
2137 mutex_lock(&sc->mutex);
2138 __ath9k_flush(hw, queues, drop, true, false);
2139 mutex_unlock(&sc->mutex);
2140 }
2141
__ath9k_flush(struct ieee80211_hw * hw,u32 queues,bool drop,bool sw_pending,bool timeout_override)2142 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
2143 bool sw_pending, bool timeout_override)
2144 {
2145 struct ath_softc *sc = hw->priv;
2146 struct ath_hw *ah = sc->sc_ah;
2147 struct ath_common *common = ath9k_hw_common(ah);
2148 int timeout;
2149 bool drain_txq;
2150
2151 cancel_delayed_work_sync(&sc->tx_complete_work);
2152
2153 if (ah->ah_flags & AH_UNPLUGGED) {
2154 ath_dbg(common, ANY, "Device has been unplugged!\n");
2155 return;
2156 }
2157
2158 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2159 ath_dbg(common, ANY, "Device not present\n");
2160 return;
2161 }
2162
2163 spin_lock_bh(&sc->chan_lock);
2164 if (timeout_override)
2165 timeout = HZ / 5;
2166 else
2167 timeout = sc->cur_chan->flush_timeout;
2168 spin_unlock_bh(&sc->chan_lock);
2169
2170 ath_dbg(common, CHAN_CTX,
2171 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2172
2173 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2174 timeout) > 0)
2175 drop = false;
2176
2177 if (drop) {
2178 ath9k_ps_wakeup(sc);
2179 spin_lock_bh(&sc->sc_pcu_lock);
2180 drain_txq = ath_drain_all_txq(sc);
2181 spin_unlock_bh(&sc->sc_pcu_lock);
2182
2183 if (!drain_txq)
2184 ath_reset(sc, NULL);
2185
2186 ath9k_ps_restore(sc);
2187 }
2188
2189 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2190 }
2191
ath9k_tx_frames_pending(struct ieee80211_hw * hw)2192 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2193 {
2194 struct ath_softc *sc = hw->priv;
2195
2196 return ath9k_has_tx_pending(sc, true);
2197 }
2198
ath9k_tx_last_beacon(struct ieee80211_hw * hw)2199 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2200 {
2201 struct ath_softc *sc = hw->priv;
2202 struct ath_hw *ah = sc->sc_ah;
2203 struct ieee80211_vif *vif;
2204 struct ath_vif *avp;
2205 struct ath_buf *bf;
2206 struct ath_tx_status ts;
2207 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2208 int status;
2209
2210 vif = sc->beacon.bslot[0];
2211 if (!vif)
2212 return 0;
2213
2214 if (!vif->bss_conf.enable_beacon)
2215 return 0;
2216
2217 avp = (void *)vif->drv_priv;
2218
2219 if (!sc->beacon.tx_processed && !edma) {
2220 tasklet_disable(&sc->bcon_tasklet);
2221
2222 bf = avp->av_bcbuf;
2223 if (!bf || !bf->bf_mpdu)
2224 goto skip;
2225
2226 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2227 if (status == -EINPROGRESS)
2228 goto skip;
2229
2230 sc->beacon.tx_processed = true;
2231 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2232
2233 skip:
2234 tasklet_enable(&sc->bcon_tasklet);
2235 }
2236
2237 return sc->beacon.tx_last;
2238 }
2239
ath9k_get_stats(struct ieee80211_hw * hw,struct ieee80211_low_level_stats * stats)2240 static int ath9k_get_stats(struct ieee80211_hw *hw,
2241 struct ieee80211_low_level_stats *stats)
2242 {
2243 struct ath_softc *sc = hw->priv;
2244 struct ath_hw *ah = sc->sc_ah;
2245 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2246
2247 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2248 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2249 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2250 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2251 return 0;
2252 }
2253
fill_chainmask(u32 cap,u32 new)2254 static u32 fill_chainmask(u32 cap, u32 new)
2255 {
2256 u32 filled = 0;
2257 int i;
2258
2259 for (i = 0; cap && new; i++, cap >>= 1) {
2260 if (!(cap & BIT(0)))
2261 continue;
2262
2263 if (new & BIT(0))
2264 filled |= BIT(i);
2265
2266 new >>= 1;
2267 }
2268
2269 return filled;
2270 }
2271
validate_antenna_mask(struct ath_hw * ah,u32 val)2272 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2273 {
2274 if (AR_SREV_9300_20_OR_LATER(ah))
2275 return true;
2276
2277 switch (val & 0x7) {
2278 case 0x1:
2279 case 0x3:
2280 case 0x7:
2281 return true;
2282 case 0x2:
2283 return (ah->caps.rx_chainmask == 1);
2284 default:
2285 return false;
2286 }
2287 }
2288
ath9k_set_antenna(struct ieee80211_hw * hw,u32 tx_ant,u32 rx_ant)2289 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2290 {
2291 struct ath_softc *sc = hw->priv;
2292 struct ath_hw *ah = sc->sc_ah;
2293
2294 if (ah->caps.rx_chainmask != 1)
2295 rx_ant |= tx_ant;
2296
2297 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2298 return -EINVAL;
2299
2300 sc->ant_rx = rx_ant;
2301 sc->ant_tx = tx_ant;
2302
2303 if (ah->caps.rx_chainmask == 1)
2304 return 0;
2305
2306 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2307 if (AR_SREV_9100(ah))
2308 ah->rxchainmask = 0x7;
2309 else
2310 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2311
2312 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2313 ath9k_cmn_reload_chainmask(ah);
2314
2315 return 0;
2316 }
2317
ath9k_get_antenna(struct ieee80211_hw * hw,u32 * tx_ant,u32 * rx_ant)2318 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2319 {
2320 struct ath_softc *sc = hw->priv;
2321
2322 *tx_ant = sc->ant_tx;
2323 *rx_ant = sc->ant_rx;
2324 return 0;
2325 }
2326
ath9k_sw_scan_start(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * mac_addr)2327 static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2328 struct ieee80211_vif *vif,
2329 const u8 *mac_addr)
2330 {
2331 struct ath_softc *sc = hw->priv;
2332 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2333 set_bit(ATH_OP_SCANNING, &common->op_flags);
2334 }
2335
ath9k_sw_scan_complete(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2336 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2337 struct ieee80211_vif *vif)
2338 {
2339 struct ath_softc *sc = hw->priv;
2340 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2341 clear_bit(ATH_OP_SCANNING, &common->op_flags);
2342 }
2343
2344 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2345
ath9k_cancel_pending_offchannel(struct ath_softc * sc)2346 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2347 {
2348 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2349
2350 if (sc->offchannel.roc_vif) {
2351 ath_dbg(common, CHAN_CTX,
2352 "%s: Aborting RoC\n", __func__);
2353
2354 del_timer_sync(&sc->offchannel.timer);
2355 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2356 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
2357 }
2358
2359 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2360 ath_dbg(common, CHAN_CTX,
2361 "%s: Aborting HW scan\n", __func__);
2362
2363 del_timer_sync(&sc->offchannel.timer);
2364 ath_scan_complete(sc, true);
2365 }
2366 }
2367
ath9k_hw_scan(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_scan_request * hw_req)2368 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2369 struct ieee80211_scan_request *hw_req)
2370 {
2371 struct cfg80211_scan_request *req = &hw_req->req;
2372 struct ath_softc *sc = hw->priv;
2373 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2374 int ret = 0;
2375
2376 mutex_lock(&sc->mutex);
2377
2378 if (WARN_ON(sc->offchannel.scan_req)) {
2379 ret = -EBUSY;
2380 goto out;
2381 }
2382
2383 ath9k_ps_wakeup(sc);
2384 set_bit(ATH_OP_SCANNING, &common->op_flags);
2385 sc->offchannel.scan_vif = vif;
2386 sc->offchannel.scan_req = req;
2387 sc->offchannel.scan_idx = 0;
2388
2389 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2390 vif->addr);
2391
2392 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2393 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2394 ath_offchannel_next(sc);
2395 }
2396
2397 out:
2398 mutex_unlock(&sc->mutex);
2399
2400 return ret;
2401 }
2402
ath9k_cancel_hw_scan(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2403 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2404 struct ieee80211_vif *vif)
2405 {
2406 struct ath_softc *sc = hw->priv;
2407 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2408
2409 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2410
2411 mutex_lock(&sc->mutex);
2412 del_timer_sync(&sc->offchannel.timer);
2413 ath_scan_complete(sc, true);
2414 mutex_unlock(&sc->mutex);
2415 }
2416
ath9k_remain_on_channel(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_channel * chan,int duration,enum ieee80211_roc_type type)2417 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2418 struct ieee80211_vif *vif,
2419 struct ieee80211_channel *chan, int duration,
2420 enum ieee80211_roc_type type)
2421 {
2422 struct ath_softc *sc = hw->priv;
2423 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2424 int ret = 0;
2425
2426 mutex_lock(&sc->mutex);
2427
2428 if (WARN_ON(sc->offchannel.roc_vif)) {
2429 ret = -EBUSY;
2430 goto out;
2431 }
2432
2433 ath9k_ps_wakeup(sc);
2434 sc->offchannel.roc_vif = vif;
2435 sc->offchannel.roc_chan = chan;
2436 sc->offchannel.roc_duration = duration;
2437
2438 ath_dbg(common, CHAN_CTX,
2439 "RoC request on vif: %pM, type: %d duration: %d\n",
2440 vif->addr, type, duration);
2441
2442 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2443 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2444 ath_offchannel_next(sc);
2445 }
2446
2447 out:
2448 mutex_unlock(&sc->mutex);
2449
2450 return ret;
2451 }
2452
ath9k_cancel_remain_on_channel(struct ieee80211_hw * hw)2453 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2454 {
2455 struct ath_softc *sc = hw->priv;
2456 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2457
2458 mutex_lock(&sc->mutex);
2459
2460 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2461 del_timer_sync(&sc->offchannel.timer);
2462
2463 if (sc->offchannel.roc_vif) {
2464 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2465 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
2466 }
2467
2468 mutex_unlock(&sc->mutex);
2469
2470 return 0;
2471 }
2472
ath9k_add_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf)2473 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2474 struct ieee80211_chanctx_conf *conf)
2475 {
2476 struct ath_softc *sc = hw->priv;
2477 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2478 struct ath_chanctx *ctx, **ptr;
2479 int pos;
2480
2481 mutex_lock(&sc->mutex);
2482
2483 ath_for_each_chanctx(sc, ctx) {
2484 if (ctx->assigned)
2485 continue;
2486
2487 ptr = (void *) conf->drv_priv;
2488 *ptr = ctx;
2489 ctx->assigned = true;
2490 pos = ctx - &sc->chanctx[0];
2491 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2492
2493 ath_dbg(common, CHAN_CTX,
2494 "Add channel context: %d MHz\n",
2495 conf->def.chan->center_freq);
2496
2497 ath_chanctx_set_channel(sc, ctx, &conf->def);
2498
2499 mutex_unlock(&sc->mutex);
2500 return 0;
2501 }
2502
2503 mutex_unlock(&sc->mutex);
2504 return -ENOSPC;
2505 }
2506
2507
ath9k_remove_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf)2508 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2509 struct ieee80211_chanctx_conf *conf)
2510 {
2511 struct ath_softc *sc = hw->priv;
2512 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2513 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2514
2515 mutex_lock(&sc->mutex);
2516
2517 ath_dbg(common, CHAN_CTX,
2518 "Remove channel context: %d MHz\n",
2519 conf->def.chan->center_freq);
2520
2521 ctx->assigned = false;
2522 ctx->hw_queue_base = 0;
2523 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2524
2525 mutex_unlock(&sc->mutex);
2526 }
2527
ath9k_change_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf,u32 changed)2528 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2529 struct ieee80211_chanctx_conf *conf,
2530 u32 changed)
2531 {
2532 struct ath_softc *sc = hw->priv;
2533 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2534 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2535
2536 mutex_lock(&sc->mutex);
2537 ath_dbg(common, CHAN_CTX,
2538 "Change channel context: %d MHz\n",
2539 conf->def.chan->center_freq);
2540 ath_chanctx_set_channel(sc, ctx, &conf->def);
2541 mutex_unlock(&sc->mutex);
2542 }
2543
ath9k_assign_vif_chanctx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_chanctx_conf * conf)2544 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2545 struct ieee80211_vif *vif,
2546 struct ieee80211_chanctx_conf *conf)
2547 {
2548 struct ath_softc *sc = hw->priv;
2549 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2550 struct ath_vif *avp = (void *)vif->drv_priv;
2551 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2552 int i;
2553
2554 ath9k_cancel_pending_offchannel(sc);
2555
2556 mutex_lock(&sc->mutex);
2557
2558 ath_dbg(common, CHAN_CTX,
2559 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2560 vif->addr, vif->type, vif->p2p,
2561 conf->def.chan->center_freq);
2562
2563 avp->chanctx = ctx;
2564 ctx->nvifs_assigned++;
2565 list_add_tail(&avp->list, &ctx->vifs);
2566 ath9k_calculate_summary_state(sc, ctx);
2567 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2568 vif->hw_queue[i] = ctx->hw_queue_base + i;
2569
2570 mutex_unlock(&sc->mutex);
2571
2572 return 0;
2573 }
2574
ath9k_unassign_vif_chanctx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_chanctx_conf * conf)2575 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2576 struct ieee80211_vif *vif,
2577 struct ieee80211_chanctx_conf *conf)
2578 {
2579 struct ath_softc *sc = hw->priv;
2580 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2581 struct ath_vif *avp = (void *)vif->drv_priv;
2582 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2583 int ac;
2584
2585 ath9k_cancel_pending_offchannel(sc);
2586
2587 mutex_lock(&sc->mutex);
2588
2589 ath_dbg(common, CHAN_CTX,
2590 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2591 vif->addr, vif->type, vif->p2p,
2592 conf->def.chan->center_freq);
2593
2594 avp->chanctx = NULL;
2595 ctx->nvifs_assigned--;
2596 list_del(&avp->list);
2597 ath9k_calculate_summary_state(sc, ctx);
2598 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2599 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2600
2601 mutex_unlock(&sc->mutex);
2602 }
2603
ath9k_mgd_prepare_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2604 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2605 struct ieee80211_vif *vif)
2606 {
2607 struct ath_softc *sc = hw->priv;
2608 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2609 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2610 struct ath_beacon_config *cur_conf;
2611 struct ath_chanctx *go_ctx;
2612 unsigned long timeout;
2613 bool changed = false;
2614 u32 beacon_int;
2615
2616 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2617 return;
2618
2619 if (!avp->chanctx)
2620 return;
2621
2622 mutex_lock(&sc->mutex);
2623
2624 spin_lock_bh(&sc->chan_lock);
2625 if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2626 changed = true;
2627 spin_unlock_bh(&sc->chan_lock);
2628
2629 if (!changed)
2630 goto out;
2631
2632 ath9k_cancel_pending_offchannel(sc);
2633
2634 go_ctx = ath_is_go_chanctx_present(sc);
2635
2636 if (go_ctx) {
2637 /*
2638 * Wait till the GO interface gets a chance
2639 * to send out an NoA.
2640 */
2641 spin_lock_bh(&sc->chan_lock);
2642 sc->sched.mgd_prepare_tx = true;
2643 cur_conf = &go_ctx->beacon;
2644 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2645 spin_unlock_bh(&sc->chan_lock);
2646
2647 timeout = usecs_to_jiffies(beacon_int * 2);
2648 init_completion(&sc->go_beacon);
2649
2650 mutex_unlock(&sc->mutex);
2651
2652 if (wait_for_completion_timeout(&sc->go_beacon,
2653 timeout) == 0) {
2654 ath_dbg(common, CHAN_CTX,
2655 "Failed to send new NoA\n");
2656
2657 spin_lock_bh(&sc->chan_lock);
2658 sc->sched.mgd_prepare_tx = false;
2659 spin_unlock_bh(&sc->chan_lock);
2660 }
2661
2662 mutex_lock(&sc->mutex);
2663 }
2664
2665 ath_dbg(common, CHAN_CTX,
2666 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2667 __func__, vif->addr);
2668
2669 spin_lock_bh(&sc->chan_lock);
2670 sc->next_chan = avp->chanctx;
2671 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2672 spin_unlock_bh(&sc->chan_lock);
2673
2674 ath_chanctx_set_next(sc, true);
2675 out:
2676 mutex_unlock(&sc->mutex);
2677 }
2678
ath9k_fill_chanctx_ops(void)2679 void ath9k_fill_chanctx_ops(void)
2680 {
2681 if (!ath9k_is_chanctx_enabled())
2682 return;
2683
2684 ath9k_ops.hw_scan = ath9k_hw_scan;
2685 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2686 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
2687 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2688 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2689 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2690 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2691 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2692 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
2693 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
2694 }
2695
2696 #endif
2697
ath9k_get_txpower(struct ieee80211_hw * hw,struct ieee80211_vif * vif,int * dbm)2698 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2699 int *dbm)
2700 {
2701 struct ath_softc *sc = hw->priv;
2702 struct ath_vif *avp = (void *)vif->drv_priv;
2703
2704 mutex_lock(&sc->mutex);
2705 if (avp->chanctx)
2706 *dbm = avp->chanctx->cur_txpower;
2707 else
2708 *dbm = sc->cur_chan->cur_txpower;
2709 mutex_unlock(&sc->mutex);
2710
2711 *dbm /= 2;
2712
2713 return 0;
2714 }
2715
2716 struct ieee80211_ops ath9k_ops = {
2717 .tx = ath9k_tx,
2718 .start = ath9k_start,
2719 .stop = ath9k_stop,
2720 .add_interface = ath9k_add_interface,
2721 .change_interface = ath9k_change_interface,
2722 .remove_interface = ath9k_remove_interface,
2723 .config = ath9k_config,
2724 .configure_filter = ath9k_configure_filter,
2725 .sta_state = ath9k_sta_state,
2726 .sta_notify = ath9k_sta_notify,
2727 .conf_tx = ath9k_conf_tx,
2728 .bss_info_changed = ath9k_bss_info_changed,
2729 .set_key = ath9k_set_key,
2730 .get_tsf = ath9k_get_tsf,
2731 .set_tsf = ath9k_set_tsf,
2732 .reset_tsf = ath9k_reset_tsf,
2733 .ampdu_action = ath9k_ampdu_action,
2734 .get_survey = ath9k_get_survey,
2735 .rfkill_poll = ath9k_rfkill_poll_state,
2736 .set_coverage_class = ath9k_set_coverage_class,
2737 .flush = ath9k_flush,
2738 .tx_frames_pending = ath9k_tx_frames_pending,
2739 .tx_last_beacon = ath9k_tx_last_beacon,
2740 .release_buffered_frames = ath9k_release_buffered_frames,
2741 .get_stats = ath9k_get_stats,
2742 .set_antenna = ath9k_set_antenna,
2743 .get_antenna = ath9k_get_antenna,
2744
2745 #ifdef CONFIG_ATH9K_WOW
2746 .suspend = ath9k_suspend,
2747 .resume = ath9k_resume,
2748 .set_wakeup = ath9k_set_wakeup,
2749 #endif
2750
2751 #ifdef CONFIG_ATH9K_DEBUGFS
2752 .get_et_sset_count = ath9k_get_et_sset_count,
2753 .get_et_stats = ath9k_get_et_stats,
2754 .get_et_strings = ath9k_get_et_strings,
2755 #endif
2756
2757 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2758 .sta_add_debugfs = ath9k_sta_add_debugfs,
2759 #endif
2760 .sw_scan_start = ath9k_sw_scan_start,
2761 .sw_scan_complete = ath9k_sw_scan_complete,
2762 .get_txpower = ath9k_get_txpower,
2763 };
2764