1 #ifndef _S390_TLBFLUSH_H
2 #define _S390_TLBFLUSH_H
3
4 #include <linux/mm.h>
5 #include <linux/sched.h>
6 #include <asm/processor.h>
7 #include <asm/pgalloc.h>
8
9 /*
10 * Flush all TLB entries on the local CPU.
11 */
__tlb_flush_local(void)12 static inline void __tlb_flush_local(void)
13 {
14 asm volatile("ptlb" : : : "memory");
15 }
16
17 /*
18 * Flush TLB entries for a specific ASCE on all CPUs
19 */
__tlb_flush_idte(unsigned long asce)20 static inline void __tlb_flush_idte(unsigned long asce)
21 {
22 /* Global TLB flush for the mm */
23 asm volatile(
24 " .insn rrf,0xb98e0000,0,%0,%1,0"
25 : : "a" (2048), "a" (asce) : "cc");
26 }
27
28 /*
29 * Flush TLB entries for a specific ASCE on the local CPU
30 */
__tlb_flush_idte_local(unsigned long asce)31 static inline void __tlb_flush_idte_local(unsigned long asce)
32 {
33 /* Local TLB flush for the mm */
34 asm volatile(
35 " .insn rrf,0xb98e0000,0,%0,%1,1"
36 : : "a" (2048), "a" (asce) : "cc");
37 }
38
39 #ifdef CONFIG_SMP
40 void smp_ptlb_all(void);
41
42 /*
43 * Flush all TLB entries on all CPUs.
44 */
__tlb_flush_global(void)45 static inline void __tlb_flush_global(void)
46 {
47 register unsigned long reg2 asm("2");
48 register unsigned long reg3 asm("3");
49 register unsigned long reg4 asm("4");
50 long dummy;
51
52 dummy = 0;
53 reg2 = reg3 = 0;
54 reg4 = ((unsigned long) &dummy) + 1;
55 asm volatile(
56 " csp %0,%2"
57 : : "d" (reg2), "d" (reg3), "d" (reg4), "m" (dummy) : "cc" );
58 }
59
60 /*
61 * Flush TLB entries for a specific mm on all CPUs (in case gmap is used
62 * this implicates multiple ASCEs!).
63 */
__tlb_flush_full(struct mm_struct * mm)64 static inline void __tlb_flush_full(struct mm_struct *mm)
65 {
66 preempt_disable();
67 atomic_add(0x10000, &mm->context.attach_count);
68 if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) {
69 /* Local TLB flush */
70 __tlb_flush_local();
71 } else {
72 /* Global TLB flush */
73 __tlb_flush_global();
74 /* Reset TLB flush mask */
75 if (MACHINE_HAS_TLB_LC)
76 cpumask_copy(mm_cpumask(mm),
77 &mm->context.cpu_attach_mask);
78 }
79 atomic_sub(0x10000, &mm->context.attach_count);
80 preempt_enable();
81 }
82
83 /*
84 * Flush TLB entries for a specific ASCE on all CPUs. Should never be used
85 * when more than one asce (e.g. gmap) ran on this mm.
86 */
__tlb_flush_asce(struct mm_struct * mm,unsigned long asce)87 static inline void __tlb_flush_asce(struct mm_struct *mm, unsigned long asce)
88 {
89 int active, count;
90
91 preempt_disable();
92 active = (mm == current->active_mm) ? 1 : 0;
93 count = atomic_add_return(0x10000, &mm->context.attach_count);
94 if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active &&
95 cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) {
96 __tlb_flush_idte_local(asce);
97 } else {
98 if (MACHINE_HAS_IDTE)
99 __tlb_flush_idte(asce);
100 else
101 __tlb_flush_global();
102 /* Reset TLB flush mask */
103 if (MACHINE_HAS_TLB_LC)
104 cpumask_copy(mm_cpumask(mm),
105 &mm->context.cpu_attach_mask);
106 }
107 atomic_sub(0x10000, &mm->context.attach_count);
108 preempt_enable();
109 }
110
__tlb_flush_kernel(void)111 static inline void __tlb_flush_kernel(void)
112 {
113 if (MACHINE_HAS_IDTE)
114 __tlb_flush_idte(init_mm.context.asce);
115 else
116 __tlb_flush_global();
117 }
118 #else
119 #define __tlb_flush_global() __tlb_flush_local()
120 #define __tlb_flush_full(mm) __tlb_flush_local()
121
122 /*
123 * Flush TLB entries for a specific ASCE on all CPUs.
124 */
__tlb_flush_asce(struct mm_struct * mm,unsigned long asce)125 static inline void __tlb_flush_asce(struct mm_struct *mm, unsigned long asce)
126 {
127 if (MACHINE_HAS_TLB_LC)
128 __tlb_flush_idte_local(asce);
129 else
130 __tlb_flush_local();
131 }
132
__tlb_flush_kernel(void)133 static inline void __tlb_flush_kernel(void)
134 {
135 if (MACHINE_HAS_TLB_LC)
136 __tlb_flush_idte_local(init_mm.context.asce);
137 else
138 __tlb_flush_local();
139 }
140 #endif
141
__tlb_flush_mm(struct mm_struct * mm)142 static inline void __tlb_flush_mm(struct mm_struct * mm)
143 {
144 /*
145 * If the machine has IDTE we prefer to do a per mm flush
146 * on all cpus instead of doing a local flush if the mm
147 * only ran on the local cpu.
148 */
149 if (MACHINE_HAS_IDTE && list_empty(&mm->context.gmap_list))
150 __tlb_flush_asce(mm, mm->context.asce);
151 else
152 __tlb_flush_full(mm);
153 }
154
__tlb_flush_mm_lazy(struct mm_struct * mm)155 static inline void __tlb_flush_mm_lazy(struct mm_struct * mm)
156 {
157 if (mm->context.flush_mm) {
158 __tlb_flush_mm(mm);
159 mm->context.flush_mm = 0;
160 }
161 }
162
163 /*
164 * TLB flushing:
165 * flush_tlb() - flushes the current mm struct TLBs
166 * flush_tlb_all() - flushes all processes TLBs
167 * flush_tlb_mm(mm) - flushes the specified mm context TLB's
168 * flush_tlb_page(vma, vmaddr) - flushes one page
169 * flush_tlb_range(vma, start, end) - flushes a range of pages
170 * flush_tlb_kernel_range(start, end) - flushes a range of kernel pages
171 */
172
173 /*
174 * flush_tlb_mm goes together with ptep_set_wrprotect for the
175 * copy_page_range operation and flush_tlb_range is related to
176 * ptep_get_and_clear for change_protection. ptep_set_wrprotect and
177 * ptep_get_and_clear do not flush the TLBs directly if the mm has
178 * only one user. At the end of the update the flush_tlb_mm and
179 * flush_tlb_range functions need to do the flush.
180 */
181 #define flush_tlb() do { } while (0)
182 #define flush_tlb_all() do { } while (0)
183 #define flush_tlb_page(vma, addr) do { } while (0)
184
flush_tlb_mm(struct mm_struct * mm)185 static inline void flush_tlb_mm(struct mm_struct *mm)
186 {
187 __tlb_flush_mm_lazy(mm);
188 }
189
flush_tlb_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)190 static inline void flush_tlb_range(struct vm_area_struct *vma,
191 unsigned long start, unsigned long end)
192 {
193 __tlb_flush_mm_lazy(vma->vm_mm);
194 }
195
flush_tlb_kernel_range(unsigned long start,unsigned long end)196 static inline void flush_tlb_kernel_range(unsigned long start,
197 unsigned long end)
198 {
199 __tlb_flush_kernel();
200 }
201
202 #endif /* _S390_TLBFLUSH_H */
203