1 /*
2 * Copyright 2004-2009 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7 #ifndef _CPLB_H
8 #define _CPLB_H
9
10 #include <mach/anomaly.h>
11
12 #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
13 #define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
14 #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
15 #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
16
17 #if ANOMALY_05000158
18 #define ANOMALY_05000158_WORKAROUND 0x200
19 #else
20 #define ANOMALY_05000158_WORKAROUND 0x0
21 #endif
22
23 #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
24
25 #ifdef CONFIG_BFIN_EXTMEM_WRITEBACK
26 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
27 #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
28 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
29 #else
30 #define SDRAM_DGENERIC (CPLB_COMMON)
31 #endif
32
33 #define SDRAM_DNON_CHBL (CPLB_COMMON)
34 #define SDRAM_EBIU (CPLB_COMMON)
35 #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
36
37 #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
38
39 #ifdef CONFIG_SMP
40 #define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB)
41 #define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
42 #define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB)
43
44 #else
45 #define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
46 # if defined(CONFIG_BFIN_L2_ICACHEABLE)
47 # define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
48 # else
49 # define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
50 # endif
51
52 # if defined(CONFIG_BFIN_L2_WRITEBACK)
53 # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)
54 # elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
55 # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
56 # else
57 # define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
58 # endif
59 #endif /* CONFIG_SMP */
60
61 #define SIZE_1K 0x00000400 /* 1K */
62 #define SIZE_4K 0x00001000 /* 4K */
63 #define SIZE_1M 0x00100000 /* 1M */
64 #define SIZE_4M 0x00400000 /* 4M */
65 #define SIZE_16K 0x00004000 /* 16K */
66 #define SIZE_64K 0x00010000 /* 64K */
67 #define SIZE_16M 0x01000000 /* 16M */
68 #define SIZE_64M 0x04000000 /* 64M */
69
70 #define MAX_CPLBS 16
71
72 #define CPLB_ENABLE_ICACHE_P 0
73 #define CPLB_ENABLE_DCACHE_P 1
74 #define CPLB_ENABLE_DCACHE2_P 2
75 #define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
76 #define CPLB_ENABLE_ICPLBS_P 4
77 #define CPLB_ENABLE_DCPLBS_P 5
78
79 #define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
80 #define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
81 #define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
82 #define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
83 #define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
84 #define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
85 #define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
86 CPLB_ENABLE_ICPLBS | \
87 CPLB_ENABLE_DCPLBS
88
89 #define CPLB_RELOADED 0x0000
90 #define CPLB_NO_UNLOCKED 0x0001
91 #define CPLB_NO_ADDR_MATCH 0x0002
92 #define CPLB_PROT_VIOL 0x0003
93 #define CPLB_UNKNOWN_ERR 0x0004
94
95 #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
96 #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
97
98 #define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
99 #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
100 #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
101 #define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
102 #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
103 #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
104
105 #define FAULT_RW (1 << 16)
106 #define FAULT_USERSUPV (1 << 17)
107 #define FAULT_CPLBBITS 0x0000ffff
108
109 #ifndef __ASSEMBLY__
110
_disable_cplb(u32 mmr,u32 mask)111 static inline void _disable_cplb(u32 mmr, u32 mask)
112 {
113 u32 ctrl = bfin_read32(mmr) & ~mask;
114 /* CSYNC to ensure load store ordering */
115 __builtin_bfin_csync();
116 bfin_write32(mmr, ctrl);
117 __builtin_bfin_ssync();
118 }
disable_cplb(u32 mmr,u32 mask)119 static inline void disable_cplb(u32 mmr, u32 mask)
120 {
121 u32 ctrl = bfin_read32(mmr) & ~mask;
122 CSYNC();
123 bfin_write32(mmr, ctrl);
124 SSYNC();
125 }
126 #define _disable_dcplb() _disable_cplb(DMEM_CONTROL, ENDCPLB)
127 #define disable_dcplb() disable_cplb(DMEM_CONTROL, ENDCPLB)
128 #define _disable_icplb() _disable_cplb(IMEM_CONTROL, ENICPLB)
129 #define disable_icplb() disable_cplb(IMEM_CONTROL, ENICPLB)
130
_enable_cplb(u32 mmr,u32 mask)131 static inline void _enable_cplb(u32 mmr, u32 mask)
132 {
133 u32 ctrl = bfin_read32(mmr) | mask;
134 /* CSYNC to ensure load store ordering */
135 __builtin_bfin_csync();
136 bfin_write32(mmr, ctrl);
137 __builtin_bfin_ssync();
138 }
enable_cplb(u32 mmr,u32 mask)139 static inline void enable_cplb(u32 mmr, u32 mask)
140 {
141 u32 ctrl = bfin_read32(mmr) | mask;
142 CSYNC();
143 bfin_write32(mmr, ctrl);
144 SSYNC();
145 }
146 #define _enable_dcplb() _enable_cplb(DMEM_CONTROL, ENDCPLB)
147 #define enable_dcplb() enable_cplb(DMEM_CONTROL, ENDCPLB)
148 #define _enable_icplb() _enable_cplb(IMEM_CONTROL, ENICPLB)
149 #define enable_icplb() enable_cplb(IMEM_CONTROL, ENICPLB)
150
151 #endif /* __ASSEMBLY__ */
152
153 #endif /* _CPLB_H */
154