| /drivers/clk/tegra/ |
| D | clk-tegra-periph.c | 130 #define MUX(_name, _parents, _offset, \ argument
137 #define MUX_FLAGS(_name, _parents, _offset,\ argument
144 #define MUX8(_name, _parents, _offset, \ argument
151 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
157 #define INT(_name, _parents, _offset, \ argument
164 #define INT_FLAGS(_name, _parents, _offset,\ argument
171 #define INT8(_name, _parents, _offset,\ argument
178 #define UART(_name, _parents, _offset,\ argument
185 #define I2C(_name, _parents, _offset,\ argument
191 #define XUSB(_name, _parents, _offset, \ argument
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| D | clk-tegra30.c | 181 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
187 #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \ argument
193 #define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \ argument
200 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
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| D | clk-tegra20.c | 144 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
151 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \ argument
158 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
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| D | clk-tegra114.c | 152 #define MUX8(_name, _parents, _offset, \ argument
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| /drivers/clk/mediatek/ |
| D | clk-mtk.h | 86 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \ argument
100 #define MUX(_id, _name, _parents, _reg, _shift, _width) { \ argument
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