| /drivers/clk/mediatek/ |
| D | clk-mt8173.c | 607 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
646 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
655 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
722 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
753 #define GATE_MM0(_id, _name, _parent, _shift) { \ argument
762 #define GATE_MM1(_id, _name, _parent, _shift) { \ argument
840 #define GATE_VDEC0(_id, _name, _parent, _shift) { \ argument
849 #define GATE_VDEC1(_id, _name, _parent, _shift) { \ argument
863 #define GATE_VENC(_id, _name, _parent, _shift) { \ argument
879 #define GATE_VENCLT(_id, _name, _parent, _shift) { \ argument
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| D | clk-mt8135.c | 411 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
448 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
457 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
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| D | clk-mtk.h | 86 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \ argument
100 #define MUX(_id, _name, _parents, _reg, _shift, _width) { \ argument
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| /drivers/net/ethernet/mellanox/mlxsw/ |
| D | item.h | 250 #define MLXSW_ITEM16(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
266 #define MLXSW_ITEM16_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
291 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
307 #define MLXSW_ITEM32_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
332 #define MLXSW_ITEM64(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
348 #define MLXSW_ITEM64_INDEXED(_type, _cname, _iname, _offset, _shift, \ argument
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| /drivers/bcma/ |
| D | sprom.c | 185 #define SPEX(_field, _offset, _mask, _shift) \ argument
188 #define SPEX32(_field, _offset, _mask, _shift) \ argument
192 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
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| /drivers/ssb/ |
| D | pci.c | 172 #define SPEX16(_outvar, _offset, _mask, _shift) \ argument
174 #define SPEX32(_outvar, _offset, _mask, _shift) \ argument
177 #define SPEX(_outvar, _offset, _mask, _shift) \ argument
180 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
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| /drivers/clk/st/ |
| D | clkgen.h | 37 #define CLKGEN_FIELD(_offset, _mask, _shift) { \ argument
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| /drivers/clk/pistachio/ |
| D | clk.h | 22 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
42 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
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| /drivers/clk/bcm/ |
| D | clk-kona.h | 299 #define DIVIDER(_offset, _shift, _width) \ argument
309 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
350 #define SELECTOR(_offset, _shift, _width) \ argument
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| /drivers/iio/adc/ |
| D | ad7476.c | 136 #define _AD7476_CHAN(bits, _shift, _info_mask_sep) \ argument
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| /drivers/iio/dac/ |
| D | ad5686.c | 270 #define AD5868_CHANNEL(chan, bits, _shift) { \ argument
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| D | ad5791.c | 295 #define AD5791_CHAN(bits, _shift) { \ argument
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| D | ad5446.c | 142 #define _AD5446_CHANNEL(bits, storage, _shift, ext) { \ argument
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| D | ad5064.c | 298 #define AD5064_CHANNEL(chan, addr, bits, _shift) { \ argument
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| /drivers/regulator/ |
| D | max8998.c | 198 int *_reg, int *_shift, int *_mask) in max8998_get_voltage_register()
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| D | tps6524x-regulator.c | 372 #define __MK_FIELD(_reg, _mask, _shift) \ argument
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| D | max8997.c | 302 int *_reg, int *_shift, int *_mask) in max8997_get_voltage_register()
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| /drivers/pinctrl/ |
| D | pinctrl-pistachio.c | 503 #define FUNCTION_SCENARIO(_name, _reg, _shift, _mask) \ argument
666 #define MFIO_MUX_PIN_GROUP(_pin, _f0, _f1, _f2, _reg, _shift, _mask) \ argument
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| D | pinctrl-tegra-xusb.c | 833 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ argument
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