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1 /*
2  * Copyright (C) 2013 Red Hat
3  * Author: Rob Clark <robdclark@gmail.com>
4  *
5  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License version 2 as published by
9  * the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "adreno_gpu.h"
21 #include "msm_gem.h"
22 #include "msm_mmu.h"
23 
24 #define RB_SIZE    SZ_32K
25 #define RB_BLKSIZE 16
26 
adreno_get_param(struct msm_gpu * gpu,uint32_t param,uint64_t * value)27 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
28 {
29 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
30 
31 	switch (param) {
32 	case MSM_PARAM_GPU_ID:
33 		*value = adreno_gpu->info->revn;
34 		return 0;
35 	case MSM_PARAM_GMEM_SIZE:
36 		*value = adreno_gpu->gmem;
37 		return 0;
38 	case MSM_PARAM_CHIP_ID:
39 		*value = adreno_gpu->rev.patchid |
40 				(adreno_gpu->rev.minor << 8) |
41 				(adreno_gpu->rev.major << 16) |
42 				(adreno_gpu->rev.core << 24);
43 		return 0;
44 	default:
45 		DBG("%s: invalid param: %u", gpu->name, param);
46 		return -EINVAL;
47 	}
48 }
49 
50 #define rbmemptr(adreno_gpu, member)  \
51 	((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member))
52 
adreno_hw_init(struct msm_gpu * gpu)53 int adreno_hw_init(struct msm_gpu *gpu)
54 {
55 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
56 	int ret;
57 
58 	DBG("%s", gpu->name);
59 
60 	ret = msm_gem_get_iova(gpu->rb->bo, gpu->id, &gpu->rb_iova);
61 	if (ret) {
62 		gpu->rb_iova = 0;
63 		dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret);
64 		return ret;
65 	}
66 
67 	/* Setup REG_CP_RB_CNTL: */
68 	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
69 			/* size is log2(quad-words): */
70 			AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
71 			AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)));
72 
73 	/* Setup ringbuffer address: */
74 	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova);
75 	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
76 			rbmemptr(adreno_gpu, rptr));
77 
78 	/* Setup scratch/timestamp: */
79 	adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_ADDR,
80 			rbmemptr(adreno_gpu, fence));
81 
82 	adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_UMSK, 0x1);
83 
84 	return 0;
85 }
86 
get_wptr(struct msm_ringbuffer * ring)87 static uint32_t get_wptr(struct msm_ringbuffer *ring)
88 {
89 	return ring->cur - ring->start;
90 }
91 
adreno_last_fence(struct msm_gpu * gpu)92 uint32_t adreno_last_fence(struct msm_gpu *gpu)
93 {
94 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
95 	return adreno_gpu->memptrs->fence;
96 }
97 
adreno_recover(struct msm_gpu * gpu)98 void adreno_recover(struct msm_gpu *gpu)
99 {
100 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
101 	struct drm_device *dev = gpu->dev;
102 	int ret;
103 
104 	gpu->funcs->pm_suspend(gpu);
105 
106 	/* reset ringbuffer: */
107 	gpu->rb->cur = gpu->rb->start;
108 
109 	/* reset completed fence seqno, just discard anything pending: */
110 	adreno_gpu->memptrs->fence = gpu->submitted_fence;
111 	adreno_gpu->memptrs->rptr  = 0;
112 	adreno_gpu->memptrs->wptr  = 0;
113 
114 	gpu->funcs->pm_resume(gpu);
115 	ret = gpu->funcs->hw_init(gpu);
116 	if (ret) {
117 		dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
118 		/* hmm, oh well? */
119 	}
120 }
121 
adreno_submit(struct msm_gpu * gpu,struct msm_gem_submit * submit,struct msm_file_private * ctx)122 int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
123 		struct msm_file_private *ctx)
124 {
125 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
126 	struct msm_drm_private *priv = gpu->dev->dev_private;
127 	struct msm_ringbuffer *ring = gpu->rb;
128 	unsigned i, ibs = 0;
129 
130 	for (i = 0; i < submit->nr_cmds; i++) {
131 		switch (submit->cmd[i].type) {
132 		case MSM_SUBMIT_CMD_IB_TARGET_BUF:
133 			/* ignore IB-targets */
134 			break;
135 		case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
136 			/* ignore if there has not been a ctx switch: */
137 			if (priv->lastctx == ctx)
138 				break;
139 		case MSM_SUBMIT_CMD_BUF:
140 			OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2);
141 			OUT_RING(ring, submit->cmd[i].iova);
142 			OUT_RING(ring, submit->cmd[i].size);
143 			ibs++;
144 			break;
145 		}
146 	}
147 
148 	/* on a320, at least, we seem to need to pad things out to an
149 	 * even number of qwords to avoid issue w/ CP hanging on wrap-
150 	 * around:
151 	 */
152 	if (ibs % 2)
153 		OUT_PKT2(ring);
154 
155 	OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
156 	OUT_RING(ring, submit->fence);
157 
158 	if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {
159 		/* Flush HLSQ lazy updates to make sure there is nothing
160 		 * pending for indirect loads after the timestamp has
161 		 * passed:
162 		 */
163 		OUT_PKT3(ring, CP_EVENT_WRITE, 1);
164 		OUT_RING(ring, HLSQ_FLUSH);
165 
166 		OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
167 		OUT_RING(ring, 0x00000000);
168 	}
169 
170 	OUT_PKT3(ring, CP_EVENT_WRITE, 3);
171 	OUT_RING(ring, CACHE_FLUSH_TS);
172 	OUT_RING(ring, rbmemptr(adreno_gpu, fence));
173 	OUT_RING(ring, submit->fence);
174 
175 	/* we could maybe be clever and only CP_COND_EXEC the interrupt: */
176 	OUT_PKT3(ring, CP_INTERRUPT, 1);
177 	OUT_RING(ring, 0x80000000);
178 
179 	/* Workaround for missing irq issue on 8x16/a306.  Unsure if the
180 	 * root cause is a platform issue or some a306 quirk, but this
181 	 * keeps things humming along:
182 	 */
183 	if (adreno_is_a306(adreno_gpu)) {
184 		OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
185 		OUT_RING(ring, 0x00000000);
186 		OUT_PKT3(ring, CP_INTERRUPT, 1);
187 		OUT_RING(ring, 0x80000000);
188 	}
189 
190 #if 0
191 	if (adreno_is_a3xx(adreno_gpu)) {
192 		/* Dummy set-constant to trigger context rollover */
193 		OUT_PKT3(ring, CP_SET_CONSTANT, 2);
194 		OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
195 		OUT_RING(ring, 0x00000000);
196 	}
197 #endif
198 
199 	gpu->funcs->flush(gpu);
200 
201 	return 0;
202 }
203 
adreno_flush(struct msm_gpu * gpu)204 void adreno_flush(struct msm_gpu *gpu)
205 {
206 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
207 	uint32_t wptr;
208 
209 	/*
210 	 * Mask wptr value that we calculate to fit in the HW range. This is
211 	 * to account for the possibility that the last command fit exactly into
212 	 * the ringbuffer and rb->next hasn't wrapped to zero yet
213 	 */
214 	wptr = get_wptr(gpu->rb) & ((gpu->rb->size / 4) - 1);
215 
216 	/* ensure writes to ringbuffer have hit system memory: */
217 	mb();
218 
219 	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
220 }
221 
adreno_idle(struct msm_gpu * gpu)222 void adreno_idle(struct msm_gpu *gpu)
223 {
224 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
225 	uint32_t wptr = get_wptr(gpu->rb);
226 
227 	/* wait for CP to drain ringbuffer: */
228 	if (spin_until(adreno_gpu->memptrs->rptr == wptr))
229 		DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);
230 
231 	/* TODO maybe we need to reset GPU here to recover from hang? */
232 }
233 
234 #ifdef CONFIG_DEBUG_FS
adreno_show(struct msm_gpu * gpu,struct seq_file * m)235 void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
236 {
237 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
238 	int i;
239 
240 	seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
241 			adreno_gpu->info->revn, adreno_gpu->rev.core,
242 			adreno_gpu->rev.major, adreno_gpu->rev.minor,
243 			adreno_gpu->rev.patchid);
244 
245 	seq_printf(m, "fence:    %d/%d\n", adreno_gpu->memptrs->fence,
246 			gpu->submitted_fence);
247 	seq_printf(m, "rptr:     %d\n", adreno_gpu->memptrs->rptr);
248 	seq_printf(m, "wptr:     %d\n", adreno_gpu->memptrs->wptr);
249 	seq_printf(m, "rb wptr:  %d\n", get_wptr(gpu->rb));
250 
251 	gpu->funcs->pm_resume(gpu);
252 
253 	/* dump these out in a form that can be parsed by demsm: */
254 	seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
255 	for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
256 		uint32_t start = adreno_gpu->registers[i];
257 		uint32_t end   = adreno_gpu->registers[i+1];
258 		uint32_t addr;
259 
260 		for (addr = start; addr <= end; addr++) {
261 			uint32_t val = gpu_read(gpu, addr);
262 			seq_printf(m, "IO:R %08x %08x\n", addr<<2, val);
263 		}
264 	}
265 
266 	gpu->funcs->pm_suspend(gpu);
267 }
268 #endif
269 
270 /* Dump common gpu status and scratch registers on any hang, to make
271  * the hangcheck logs more useful.  The scratch registers seem always
272  * safe to read when GPU has hung (unlike some other regs, depending
273  * on how the GPU hung), and they are useful to match up to cmdstream
274  * dumps when debugging hangs:
275  */
adreno_dump_info(struct msm_gpu * gpu)276 void adreno_dump_info(struct msm_gpu *gpu)
277 {
278 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
279 	int i;
280 
281 	printk("revision: %d (%d.%d.%d.%d)\n",
282 			adreno_gpu->info->revn, adreno_gpu->rev.core,
283 			adreno_gpu->rev.major, adreno_gpu->rev.minor,
284 			adreno_gpu->rev.patchid);
285 
286 	printk("fence:    %d/%d\n", adreno_gpu->memptrs->fence,
287 			gpu->submitted_fence);
288 	printk("rptr:     %d\n", adreno_gpu->memptrs->rptr);
289 	printk("wptr:     %d\n", adreno_gpu->memptrs->wptr);
290 	printk("rb wptr:  %d\n", get_wptr(gpu->rb));
291 
292 	for (i = 0; i < 8; i++) {
293 		printk("CP_SCRATCH_REG%d: %u\n", i,
294 			gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));
295 	}
296 }
297 
298 /* would be nice to not have to duplicate the _show() stuff with printk(): */
adreno_dump(struct msm_gpu * gpu)299 void adreno_dump(struct msm_gpu *gpu)
300 {
301 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
302 	int i;
303 
304 	/* dump these out in a form that can be parsed by demsm: */
305 	printk("IO:region %s 00000000 00020000\n", gpu->name);
306 	for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
307 		uint32_t start = adreno_gpu->registers[i];
308 		uint32_t end   = adreno_gpu->registers[i+1];
309 		uint32_t addr;
310 
311 		for (addr = start; addr <= end; addr++) {
312 			uint32_t val = gpu_read(gpu, addr);
313 			printk("IO:R %08x %08x\n", addr<<2, val);
314 		}
315 	}
316 }
317 
ring_freewords(struct msm_gpu * gpu)318 static uint32_t ring_freewords(struct msm_gpu *gpu)
319 {
320 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
321 	uint32_t size = gpu->rb->size / 4;
322 	uint32_t wptr = get_wptr(gpu->rb);
323 	uint32_t rptr = adreno_gpu->memptrs->rptr;
324 	return (rptr + (size - 1) - wptr) % size;
325 }
326 
adreno_wait_ring(struct msm_gpu * gpu,uint32_t ndwords)327 void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords)
328 {
329 	if (spin_until(ring_freewords(gpu) >= ndwords))
330 		DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name);
331 }
332 
333 static const char *iommu_ports[] = {
334 		"gfx3d_user", "gfx3d_priv",
335 		"gfx3d1_user", "gfx3d1_priv",
336 };
337 
adreno_gpu_init(struct drm_device * drm,struct platform_device * pdev,struct adreno_gpu * adreno_gpu,const struct adreno_gpu_funcs * funcs)338 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
339 		struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs)
340 {
341 	struct adreno_platform_config *config = pdev->dev.platform_data;
342 	struct msm_gpu *gpu = &adreno_gpu->base;
343 	struct msm_mmu *mmu;
344 	int ret;
345 
346 	adreno_gpu->funcs = funcs;
347 	adreno_gpu->info = adreno_info(config->rev);
348 	adreno_gpu->gmem = adreno_gpu->info->gmem;
349 	adreno_gpu->revn = adreno_gpu->info->revn;
350 	adreno_gpu->rev = config->rev;
351 
352 	gpu->fast_rate = config->fast_rate;
353 	gpu->slow_rate = config->slow_rate;
354 	gpu->bus_freq  = config->bus_freq;
355 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
356 	gpu->bus_scale_table = config->bus_scale_table;
357 #endif
358 
359 	DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
360 			gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
361 
362 	ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
363 			adreno_gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq",
364 			RB_SIZE);
365 	if (ret)
366 		return ret;
367 
368 	ret = request_firmware(&adreno_gpu->pm4, adreno_gpu->info->pm4fw, drm->dev);
369 	if (ret) {
370 		dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n",
371 				adreno_gpu->info->pm4fw, ret);
372 		return ret;
373 	}
374 
375 	ret = request_firmware(&adreno_gpu->pfp, adreno_gpu->info->pfpfw, drm->dev);
376 	if (ret) {
377 		dev_err(drm->dev, "failed to load %s PFP firmware: %d\n",
378 				adreno_gpu->info->pfpfw, ret);
379 		return ret;
380 	}
381 
382 	mmu = gpu->mmu;
383 	if (mmu) {
384 		ret = mmu->funcs->attach(mmu, iommu_ports,
385 				ARRAY_SIZE(iommu_ports));
386 		if (ret)
387 			return ret;
388 	}
389 
390 	mutex_lock(&drm->struct_mutex);
391 	adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs),
392 			MSM_BO_UNCACHED);
393 	mutex_unlock(&drm->struct_mutex);
394 	if (IS_ERR(adreno_gpu->memptrs_bo)) {
395 		ret = PTR_ERR(adreno_gpu->memptrs_bo);
396 		adreno_gpu->memptrs_bo = NULL;
397 		dev_err(drm->dev, "could not allocate memptrs: %d\n", ret);
398 		return ret;
399 	}
400 
401 	adreno_gpu->memptrs = msm_gem_vaddr(adreno_gpu->memptrs_bo);
402 	if (!adreno_gpu->memptrs) {
403 		dev_err(drm->dev, "could not vmap memptrs\n");
404 		return -ENOMEM;
405 	}
406 
407 	ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->id,
408 			&adreno_gpu->memptrs_iova);
409 	if (ret) {
410 		dev_err(drm->dev, "could not map memptrs: %d\n", ret);
411 		return ret;
412 	}
413 
414 	return 0;
415 }
416 
adreno_gpu_cleanup(struct adreno_gpu * gpu)417 void adreno_gpu_cleanup(struct adreno_gpu *gpu)
418 {
419 	if (gpu->memptrs_bo) {
420 		if (gpu->memptrs_iova)
421 			msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id);
422 		drm_gem_object_unreference_unlocked(gpu->memptrs_bo);
423 	}
424 	release_firmware(gpu->pm4);
425 	release_firmware(gpu->pfp);
426 	msm_gpu_cleanup(&gpu->base);
427 }
428