1 /*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "ahci.h"
47 #include "libata.h"
48
49 static int ahci_skip_host_reset;
50 int ahci_ignore_sss;
51 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
52
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
58
59 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
60 unsigned hints);
61 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
63 size_t size);
64 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
65 ssize_t size);
66
67
68
69 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
71 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
72 static int ahci_port_start(struct ata_port *ap);
73 static void ahci_port_stop(struct ata_port *ap);
74 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc);
75 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
76 static void ahci_freeze(struct ata_port *ap);
77 static void ahci_thaw(struct ata_port *ap);
78 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
79 static void ahci_enable_fbs(struct ata_port *ap);
80 static void ahci_disable_fbs(struct ata_port *ap);
81 static void ahci_pmp_attach(struct ata_port *ap);
82 static void ahci_pmp_detach(struct ata_port *ap);
83 static int ahci_softreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static void ahci_postreset(struct ata_link *link, unsigned int *class);
90 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
91 static void ahci_dev_config(struct ata_device *dev);
92 #ifdef CONFIG_PM
93 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
94 #endif
95 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
96 static ssize_t ahci_activity_store(struct ata_device *dev,
97 enum sw_activity val);
98 static void ahci_init_sw_activity(struct ata_link *link);
99
100 static ssize_t ahci_show_host_caps(struct device *dev,
101 struct device_attribute *attr, char *buf);
102 static ssize_t ahci_show_host_cap2(struct device *dev,
103 struct device_attribute *attr, char *buf);
104 static ssize_t ahci_show_host_version(struct device *dev,
105 struct device_attribute *attr, char *buf);
106 static ssize_t ahci_show_port_cmd(struct device *dev,
107 struct device_attribute *attr, char *buf);
108 static ssize_t ahci_read_em_buffer(struct device *dev,
109 struct device_attribute *attr, char *buf);
110 static ssize_t ahci_store_em_buffer(struct device *dev,
111 struct device_attribute *attr,
112 const char *buf, size_t size);
113 static ssize_t ahci_show_em_supported(struct device *dev,
114 struct device_attribute *attr, char *buf);
115
116 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
117 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
118 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
119 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
120 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
121 ahci_read_em_buffer, ahci_store_em_buffer);
122 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
123
124 struct device_attribute *ahci_shost_attrs[] = {
125 &dev_attr_link_power_management_policy,
126 &dev_attr_em_message_type,
127 &dev_attr_em_message,
128 &dev_attr_ahci_host_caps,
129 &dev_attr_ahci_host_cap2,
130 &dev_attr_ahci_host_version,
131 &dev_attr_ahci_port_cmd,
132 &dev_attr_em_buffer,
133 &dev_attr_em_message_supported,
134 NULL
135 };
136 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
137
138 struct device_attribute *ahci_sdev_attrs[] = {
139 &dev_attr_sw_activity,
140 &dev_attr_unload_heads,
141 NULL
142 };
143 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
144
145 struct ata_port_operations ahci_ops = {
146 .inherits = &sata_pmp_port_ops,
147
148 .qc_defer = ahci_pmp_qc_defer,
149 .qc_prep = ahci_qc_prep,
150 .qc_issue = ahci_qc_issue,
151 .qc_fill_rtf = ahci_qc_fill_rtf,
152
153 .freeze = ahci_freeze,
154 .thaw = ahci_thaw,
155 .softreset = ahci_softreset,
156 .hardreset = ahci_hardreset,
157 .postreset = ahci_postreset,
158 .pmp_softreset = ahci_softreset,
159 .error_handler = ahci_error_handler,
160 .post_internal_cmd = ahci_post_internal_cmd,
161 .dev_config = ahci_dev_config,
162
163 .scr_read = ahci_scr_read,
164 .scr_write = ahci_scr_write,
165 .pmp_attach = ahci_pmp_attach,
166 .pmp_detach = ahci_pmp_detach,
167
168 .set_lpm = ahci_set_lpm,
169 .em_show = ahci_led_show,
170 .em_store = ahci_led_store,
171 .sw_activity_show = ahci_activity_show,
172 .sw_activity_store = ahci_activity_store,
173 .transmit_led_message = ahci_transmit_led_message,
174 #ifdef CONFIG_PM
175 .port_suspend = ahci_port_suspend,
176 .port_resume = ahci_port_resume,
177 #endif
178 .port_start = ahci_port_start,
179 .port_stop = ahci_port_stop,
180 };
181 EXPORT_SYMBOL_GPL(ahci_ops);
182
183 struct ata_port_operations ahci_pmp_retry_srst_ops = {
184 .inherits = &ahci_ops,
185 .softreset = ahci_pmp_retry_softreset,
186 };
187 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
188
189 static bool ahci_em_messages __read_mostly = true;
190 module_param(ahci_em_messages, bool, 0444);
191 /* add other LED protocol types when they become supported */
192 MODULE_PARM_DESC(ahci_em_messages,
193 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
194
195 /* device sleep idle timeout in ms */
196 static int devslp_idle_timeout __read_mostly = 1000;
197 module_param(devslp_idle_timeout, int, 0644);
198 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
199
ahci_enable_ahci(void __iomem * mmio)200 static void ahci_enable_ahci(void __iomem *mmio)
201 {
202 int i;
203 u32 tmp;
204
205 /* turn on AHCI_EN */
206 tmp = readl(mmio + HOST_CTL);
207 if (tmp & HOST_AHCI_EN)
208 return;
209
210 /* Some controllers need AHCI_EN to be written multiple times.
211 * Try a few times before giving up.
212 */
213 for (i = 0; i < 5; i++) {
214 tmp |= HOST_AHCI_EN;
215 writel(tmp, mmio + HOST_CTL);
216 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
217 if (tmp & HOST_AHCI_EN)
218 return;
219 msleep(10);
220 }
221
222 WARN_ON(1);
223 }
224
ahci_show_host_caps(struct device * dev,struct device_attribute * attr,char * buf)225 static ssize_t ahci_show_host_caps(struct device *dev,
226 struct device_attribute *attr, char *buf)
227 {
228 struct Scsi_Host *shost = class_to_shost(dev);
229 struct ata_port *ap = ata_shost_to_port(shost);
230 struct ahci_host_priv *hpriv = ap->host->private_data;
231
232 return sprintf(buf, "%x\n", hpriv->cap);
233 }
234
ahci_show_host_cap2(struct device * dev,struct device_attribute * attr,char * buf)235 static ssize_t ahci_show_host_cap2(struct device *dev,
236 struct device_attribute *attr, char *buf)
237 {
238 struct Scsi_Host *shost = class_to_shost(dev);
239 struct ata_port *ap = ata_shost_to_port(shost);
240 struct ahci_host_priv *hpriv = ap->host->private_data;
241
242 return sprintf(buf, "%x\n", hpriv->cap2);
243 }
244
ahci_show_host_version(struct device * dev,struct device_attribute * attr,char * buf)245 static ssize_t ahci_show_host_version(struct device *dev,
246 struct device_attribute *attr, char *buf)
247 {
248 struct Scsi_Host *shost = class_to_shost(dev);
249 struct ata_port *ap = ata_shost_to_port(shost);
250 struct ahci_host_priv *hpriv = ap->host->private_data;
251 void __iomem *mmio = hpriv->mmio;
252
253 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
254 }
255
ahci_show_port_cmd(struct device * dev,struct device_attribute * attr,char * buf)256 static ssize_t ahci_show_port_cmd(struct device *dev,
257 struct device_attribute *attr, char *buf)
258 {
259 struct Scsi_Host *shost = class_to_shost(dev);
260 struct ata_port *ap = ata_shost_to_port(shost);
261 void __iomem *port_mmio = ahci_port_base(ap);
262
263 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
264 }
265
ahci_read_em_buffer(struct device * dev,struct device_attribute * attr,char * buf)266 static ssize_t ahci_read_em_buffer(struct device *dev,
267 struct device_attribute *attr, char *buf)
268 {
269 struct Scsi_Host *shost = class_to_shost(dev);
270 struct ata_port *ap = ata_shost_to_port(shost);
271 struct ahci_host_priv *hpriv = ap->host->private_data;
272 void __iomem *mmio = hpriv->mmio;
273 void __iomem *em_mmio = mmio + hpriv->em_loc;
274 u32 em_ctl, msg;
275 unsigned long flags;
276 size_t count;
277 int i;
278
279 spin_lock_irqsave(ap->lock, flags);
280
281 em_ctl = readl(mmio + HOST_EM_CTL);
282 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
283 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
284 spin_unlock_irqrestore(ap->lock, flags);
285 return -EINVAL;
286 }
287
288 if (!(em_ctl & EM_CTL_MR)) {
289 spin_unlock_irqrestore(ap->lock, flags);
290 return -EAGAIN;
291 }
292
293 if (!(em_ctl & EM_CTL_SMB))
294 em_mmio += hpriv->em_buf_sz;
295
296 count = hpriv->em_buf_sz;
297
298 /* the count should not be larger than PAGE_SIZE */
299 if (count > PAGE_SIZE) {
300 if (printk_ratelimit())
301 ata_port_warn(ap,
302 "EM read buffer size too large: "
303 "buffer size %u, page size %lu\n",
304 hpriv->em_buf_sz, PAGE_SIZE);
305 count = PAGE_SIZE;
306 }
307
308 for (i = 0; i < count; i += 4) {
309 msg = readl(em_mmio + i);
310 buf[i] = msg & 0xff;
311 buf[i + 1] = (msg >> 8) & 0xff;
312 buf[i + 2] = (msg >> 16) & 0xff;
313 buf[i + 3] = (msg >> 24) & 0xff;
314 }
315
316 spin_unlock_irqrestore(ap->lock, flags);
317
318 return i;
319 }
320
ahci_store_em_buffer(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)321 static ssize_t ahci_store_em_buffer(struct device *dev,
322 struct device_attribute *attr,
323 const char *buf, size_t size)
324 {
325 struct Scsi_Host *shost = class_to_shost(dev);
326 struct ata_port *ap = ata_shost_to_port(shost);
327 struct ahci_host_priv *hpriv = ap->host->private_data;
328 void __iomem *mmio = hpriv->mmio;
329 void __iomem *em_mmio = mmio + hpriv->em_loc;
330 const unsigned char *msg_buf = buf;
331 u32 em_ctl, msg;
332 unsigned long flags;
333 int i;
334
335 /* check size validity */
336 if (!(ap->flags & ATA_FLAG_EM) ||
337 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
338 size % 4 || size > hpriv->em_buf_sz)
339 return -EINVAL;
340
341 spin_lock_irqsave(ap->lock, flags);
342
343 em_ctl = readl(mmio + HOST_EM_CTL);
344 if (em_ctl & EM_CTL_TM) {
345 spin_unlock_irqrestore(ap->lock, flags);
346 return -EBUSY;
347 }
348
349 for (i = 0; i < size; i += 4) {
350 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
351 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
352 writel(msg, em_mmio + i);
353 }
354
355 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
356
357 spin_unlock_irqrestore(ap->lock, flags);
358
359 return size;
360 }
361
ahci_show_em_supported(struct device * dev,struct device_attribute * attr,char * buf)362 static ssize_t ahci_show_em_supported(struct device *dev,
363 struct device_attribute *attr, char *buf)
364 {
365 struct Scsi_Host *shost = class_to_shost(dev);
366 struct ata_port *ap = ata_shost_to_port(shost);
367 struct ahci_host_priv *hpriv = ap->host->private_data;
368 void __iomem *mmio = hpriv->mmio;
369 u32 em_ctl;
370
371 em_ctl = readl(mmio + HOST_EM_CTL);
372
373 return sprintf(buf, "%s%s%s%s\n",
374 em_ctl & EM_CTL_LED ? "led " : "",
375 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
376 em_ctl & EM_CTL_SES ? "ses-2 " : "",
377 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
378 }
379
380 /**
381 * ahci_save_initial_config - Save and fixup initial config values
382 * @dev: target AHCI device
383 * @hpriv: host private area to store config values
384 *
385 * Some registers containing configuration info might be setup by
386 * BIOS and might be cleared on reset. This function saves the
387 * initial values of those registers into @hpriv such that they
388 * can be restored after controller reset.
389 *
390 * If inconsistent, config values are fixed up by this function.
391 *
392 * If it is not set already this function sets hpriv->start_engine to
393 * ahci_start_engine.
394 *
395 * LOCKING:
396 * None.
397 */
ahci_save_initial_config(struct device * dev,struct ahci_host_priv * hpriv)398 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
399 {
400 void __iomem *mmio = hpriv->mmio;
401 u32 cap, cap2, vers, port_map;
402 int i;
403
404 /* make sure AHCI mode is enabled before accessing CAP */
405 ahci_enable_ahci(mmio);
406
407 /* Values prefixed with saved_ are written back to host after
408 * reset. Values without are used for driver operation.
409 */
410 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
411 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
412
413 /* CAP2 register is only defined for AHCI 1.2 and later */
414 vers = readl(mmio + HOST_VERSION);
415 if ((vers >> 16) > 1 ||
416 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
417 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
418 else
419 hpriv->saved_cap2 = cap2 = 0;
420
421 /* some chips have errata preventing 64bit use */
422 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
423 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
424 cap &= ~HOST_CAP_64;
425 }
426
427 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
428 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
429 cap &= ~HOST_CAP_NCQ;
430 }
431
432 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
433 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
434 cap |= HOST_CAP_NCQ;
435 }
436
437 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
438 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
439 cap &= ~HOST_CAP_PMP;
440 }
441
442 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
443 dev_info(dev,
444 "controller can't do SNTF, turning off CAP_SNTF\n");
445 cap &= ~HOST_CAP_SNTF;
446 }
447
448 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
449 dev_info(dev,
450 "controller can't do DEVSLP, turning off\n");
451 cap2 &= ~HOST_CAP2_SDS;
452 cap2 &= ~HOST_CAP2_SADM;
453 }
454
455 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
456 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
457 cap |= HOST_CAP_FBS;
458 }
459
460 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
461 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
462 cap &= ~HOST_CAP_FBS;
463 }
464
465 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
466 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
467 port_map, hpriv->force_port_map);
468 port_map = hpriv->force_port_map;
469 hpriv->saved_port_map = port_map;
470 }
471
472 if (hpriv->mask_port_map) {
473 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
474 port_map,
475 port_map & hpriv->mask_port_map);
476 port_map &= hpriv->mask_port_map;
477 }
478
479 /* cross check port_map and cap.n_ports */
480 if (port_map) {
481 int map_ports = 0;
482
483 for (i = 0; i < AHCI_MAX_PORTS; i++)
484 if (port_map & (1 << i))
485 map_ports++;
486
487 /* If PI has more ports than n_ports, whine, clear
488 * port_map and let it be generated from n_ports.
489 */
490 if (map_ports > ahci_nr_ports(cap)) {
491 dev_warn(dev,
492 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
493 port_map, ahci_nr_ports(cap));
494 port_map = 0;
495 }
496 }
497
498 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
499 if (!port_map && vers < 0x10300) {
500 port_map = (1 << ahci_nr_ports(cap)) - 1;
501 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
502
503 /* write the fixed up value to the PI register */
504 hpriv->saved_port_map = port_map;
505 }
506
507 /* record values to use during operation */
508 hpriv->cap = cap;
509 hpriv->cap2 = cap2;
510 hpriv->port_map = port_map;
511
512 if (!hpriv->start_engine)
513 hpriv->start_engine = ahci_start_engine;
514 }
515 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
516
517 /**
518 * ahci_restore_initial_config - Restore initial config
519 * @host: target ATA host
520 *
521 * Restore initial config stored by ahci_save_initial_config().
522 *
523 * LOCKING:
524 * None.
525 */
ahci_restore_initial_config(struct ata_host * host)526 static void ahci_restore_initial_config(struct ata_host *host)
527 {
528 struct ahci_host_priv *hpriv = host->private_data;
529 void __iomem *mmio = hpriv->mmio;
530
531 writel(hpriv->saved_cap, mmio + HOST_CAP);
532 if (hpriv->saved_cap2)
533 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
534 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
535 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
536 }
537
ahci_scr_offset(struct ata_port * ap,unsigned int sc_reg)538 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
539 {
540 static const int offset[] = {
541 [SCR_STATUS] = PORT_SCR_STAT,
542 [SCR_CONTROL] = PORT_SCR_CTL,
543 [SCR_ERROR] = PORT_SCR_ERR,
544 [SCR_ACTIVE] = PORT_SCR_ACT,
545 [SCR_NOTIFICATION] = PORT_SCR_NTF,
546 };
547 struct ahci_host_priv *hpriv = ap->host->private_data;
548
549 if (sc_reg < ARRAY_SIZE(offset) &&
550 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
551 return offset[sc_reg];
552 return 0;
553 }
554
ahci_scr_read(struct ata_link * link,unsigned int sc_reg,u32 * val)555 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
556 {
557 void __iomem *port_mmio = ahci_port_base(link->ap);
558 int offset = ahci_scr_offset(link->ap, sc_reg);
559
560 if (offset) {
561 *val = readl(port_mmio + offset);
562 return 0;
563 }
564 return -EINVAL;
565 }
566
ahci_scr_write(struct ata_link * link,unsigned int sc_reg,u32 val)567 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
568 {
569 void __iomem *port_mmio = ahci_port_base(link->ap);
570 int offset = ahci_scr_offset(link->ap, sc_reg);
571
572 if (offset) {
573 writel(val, port_mmio + offset);
574 return 0;
575 }
576 return -EINVAL;
577 }
578
ahci_start_engine(struct ata_port * ap)579 void ahci_start_engine(struct ata_port *ap)
580 {
581 void __iomem *port_mmio = ahci_port_base(ap);
582 u32 tmp;
583
584 /* start DMA */
585 tmp = readl(port_mmio + PORT_CMD);
586 tmp |= PORT_CMD_START;
587 writel(tmp, port_mmio + PORT_CMD);
588 readl(port_mmio + PORT_CMD); /* flush */
589 }
590 EXPORT_SYMBOL_GPL(ahci_start_engine);
591
ahci_stop_engine(struct ata_port * ap)592 int ahci_stop_engine(struct ata_port *ap)
593 {
594 void __iomem *port_mmio = ahci_port_base(ap);
595 u32 tmp;
596
597 tmp = readl(port_mmio + PORT_CMD);
598
599 /* check if the HBA is idle */
600 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
601 return 0;
602
603 /* setting HBA to idle */
604 tmp &= ~PORT_CMD_START;
605 writel(tmp, port_mmio + PORT_CMD);
606
607 /* wait for engine to stop. This could be as long as 500 msec */
608 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
609 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
610 if (tmp & PORT_CMD_LIST_ON)
611 return -EIO;
612
613 return 0;
614 }
615 EXPORT_SYMBOL_GPL(ahci_stop_engine);
616
ahci_start_fis_rx(struct ata_port * ap)617 void ahci_start_fis_rx(struct ata_port *ap)
618 {
619 void __iomem *port_mmio = ahci_port_base(ap);
620 struct ahci_host_priv *hpriv = ap->host->private_data;
621 struct ahci_port_priv *pp = ap->private_data;
622 u32 tmp;
623
624 /* set FIS registers */
625 if (hpriv->cap & HOST_CAP_64)
626 writel((pp->cmd_slot_dma >> 16) >> 16,
627 port_mmio + PORT_LST_ADDR_HI);
628 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
629
630 if (hpriv->cap & HOST_CAP_64)
631 writel((pp->rx_fis_dma >> 16) >> 16,
632 port_mmio + PORT_FIS_ADDR_HI);
633 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
634
635 /* enable FIS reception */
636 tmp = readl(port_mmio + PORT_CMD);
637 tmp |= PORT_CMD_FIS_RX;
638 writel(tmp, port_mmio + PORT_CMD);
639
640 /* flush */
641 readl(port_mmio + PORT_CMD);
642 }
643 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
644
ahci_stop_fis_rx(struct ata_port * ap)645 static int ahci_stop_fis_rx(struct ata_port *ap)
646 {
647 void __iomem *port_mmio = ahci_port_base(ap);
648 u32 tmp;
649
650 /* disable FIS reception */
651 tmp = readl(port_mmio + PORT_CMD);
652 tmp &= ~PORT_CMD_FIS_RX;
653 writel(tmp, port_mmio + PORT_CMD);
654
655 /* wait for completion, spec says 500ms, give it 1000 */
656 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
657 PORT_CMD_FIS_ON, 10, 1000);
658 if (tmp & PORT_CMD_FIS_ON)
659 return -EBUSY;
660
661 return 0;
662 }
663
ahci_power_up(struct ata_port * ap)664 static void ahci_power_up(struct ata_port *ap)
665 {
666 struct ahci_host_priv *hpriv = ap->host->private_data;
667 void __iomem *port_mmio = ahci_port_base(ap);
668 u32 cmd;
669
670 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
671
672 /* spin up device */
673 if (hpriv->cap & HOST_CAP_SSS) {
674 cmd |= PORT_CMD_SPIN_UP;
675 writel(cmd, port_mmio + PORT_CMD);
676 }
677
678 /* wake up link */
679 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
680 }
681
ahci_set_lpm(struct ata_link * link,enum ata_lpm_policy policy,unsigned int hints)682 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
683 unsigned int hints)
684 {
685 struct ata_port *ap = link->ap;
686 struct ahci_host_priv *hpriv = ap->host->private_data;
687 struct ahci_port_priv *pp = ap->private_data;
688 void __iomem *port_mmio = ahci_port_base(ap);
689
690 if (policy != ATA_LPM_MAX_POWER) {
691 /*
692 * Disable interrupts on Phy Ready. This keeps us from
693 * getting woken up due to spurious phy ready
694 * interrupts.
695 */
696 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
697 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
698
699 sata_link_scr_lpm(link, policy, false);
700 }
701
702 if (hpriv->cap & HOST_CAP_ALPM) {
703 u32 cmd = readl(port_mmio + PORT_CMD);
704
705 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
706 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
707 cmd |= PORT_CMD_ICC_ACTIVE;
708
709 writel(cmd, port_mmio + PORT_CMD);
710 readl(port_mmio + PORT_CMD);
711
712 /* wait 10ms to be sure we've come out of LPM state */
713 ata_msleep(ap, 10);
714 } else {
715 cmd |= PORT_CMD_ALPE;
716 if (policy == ATA_LPM_MIN_POWER)
717 cmd |= PORT_CMD_ASP;
718
719 /* write out new cmd value */
720 writel(cmd, port_mmio + PORT_CMD);
721 }
722 }
723
724 /* set aggressive device sleep */
725 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
726 (hpriv->cap2 & HOST_CAP2_SADM) &&
727 (link->device->flags & ATA_DFLAG_DEVSLP)) {
728 if (policy == ATA_LPM_MIN_POWER)
729 ahci_set_aggressive_devslp(ap, true);
730 else
731 ahci_set_aggressive_devslp(ap, false);
732 }
733
734 if (policy == ATA_LPM_MAX_POWER) {
735 sata_link_scr_lpm(link, policy, false);
736
737 /* turn PHYRDY IRQ back on */
738 pp->intr_mask |= PORT_IRQ_PHYRDY;
739 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
740 }
741
742 return 0;
743 }
744
745 #ifdef CONFIG_PM
ahci_power_down(struct ata_port * ap)746 static void ahci_power_down(struct ata_port *ap)
747 {
748 struct ahci_host_priv *hpriv = ap->host->private_data;
749 void __iomem *port_mmio = ahci_port_base(ap);
750 u32 cmd, scontrol;
751
752 if (!(hpriv->cap & HOST_CAP_SSS))
753 return;
754
755 /* put device into listen mode, first set PxSCTL.DET to 0 */
756 scontrol = readl(port_mmio + PORT_SCR_CTL);
757 scontrol &= ~0xf;
758 writel(scontrol, port_mmio + PORT_SCR_CTL);
759
760 /* then set PxCMD.SUD to 0 */
761 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
762 cmd &= ~PORT_CMD_SPIN_UP;
763 writel(cmd, port_mmio + PORT_CMD);
764 }
765 #endif
766
ahci_start_port(struct ata_port * ap)767 static void ahci_start_port(struct ata_port *ap)
768 {
769 struct ahci_host_priv *hpriv = ap->host->private_data;
770 struct ahci_port_priv *pp = ap->private_data;
771 struct ata_link *link;
772 struct ahci_em_priv *emp;
773 ssize_t rc;
774 int i;
775
776 /* enable FIS reception */
777 ahci_start_fis_rx(ap);
778
779 /* enable DMA */
780 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
781 hpriv->start_engine(ap);
782
783 /* turn on LEDs */
784 if (ap->flags & ATA_FLAG_EM) {
785 ata_for_each_link(link, ap, EDGE) {
786 emp = &pp->em_priv[link->pmp];
787
788 /* EM Transmit bit maybe busy during init */
789 for (i = 0; i < EM_MAX_RETRY; i++) {
790 rc = ap->ops->transmit_led_message(ap,
791 emp->led_state,
792 4);
793 /*
794 * If busy, give a breather but do not
795 * release EH ownership by using msleep()
796 * instead of ata_msleep(). EM Transmit
797 * bit is busy for the whole host and
798 * releasing ownership will cause other
799 * ports to fail the same way.
800 */
801 if (rc == -EBUSY)
802 msleep(1);
803 else
804 break;
805 }
806 }
807 }
808
809 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
810 ata_for_each_link(link, ap, EDGE)
811 ahci_init_sw_activity(link);
812
813 }
814
ahci_deinit_port(struct ata_port * ap,const char ** emsg)815 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
816 {
817 int rc;
818
819 /* disable DMA */
820 rc = ahci_stop_engine(ap);
821 if (rc) {
822 *emsg = "failed to stop engine";
823 return rc;
824 }
825
826 /* disable FIS reception */
827 rc = ahci_stop_fis_rx(ap);
828 if (rc) {
829 *emsg = "failed stop FIS RX";
830 return rc;
831 }
832
833 return 0;
834 }
835
ahci_reset_controller(struct ata_host * host)836 int ahci_reset_controller(struct ata_host *host)
837 {
838 struct ahci_host_priv *hpriv = host->private_data;
839 void __iomem *mmio = hpriv->mmio;
840 u32 tmp;
841
842 /* we must be in AHCI mode, before using anything
843 * AHCI-specific, such as HOST_RESET.
844 */
845 ahci_enable_ahci(mmio);
846
847 /* global controller reset */
848 if (!ahci_skip_host_reset) {
849 tmp = readl(mmio + HOST_CTL);
850 if ((tmp & HOST_RESET) == 0) {
851 writel(tmp | HOST_RESET, mmio + HOST_CTL);
852 readl(mmio + HOST_CTL); /* flush */
853 }
854
855 /*
856 * to perform host reset, OS should set HOST_RESET
857 * and poll until this bit is read to be "0".
858 * reset must complete within 1 second, or
859 * the hardware should be considered fried.
860 */
861 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
862 HOST_RESET, 10, 1000);
863
864 if (tmp & HOST_RESET) {
865 dev_err(host->dev, "controller reset failed (0x%x)\n",
866 tmp);
867 return -EIO;
868 }
869
870 /* turn on AHCI mode */
871 ahci_enable_ahci(mmio);
872
873 /* Some registers might be cleared on reset. Restore
874 * initial values.
875 */
876 ahci_restore_initial_config(host);
877 } else
878 dev_info(host->dev, "skipping global host reset\n");
879
880 return 0;
881 }
882 EXPORT_SYMBOL_GPL(ahci_reset_controller);
883
ahci_sw_activity(struct ata_link * link)884 static void ahci_sw_activity(struct ata_link *link)
885 {
886 struct ata_port *ap = link->ap;
887 struct ahci_port_priv *pp = ap->private_data;
888 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
889
890 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
891 return;
892
893 emp->activity++;
894 if (!timer_pending(&emp->timer))
895 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
896 }
897
ahci_sw_activity_blink(unsigned long arg)898 static void ahci_sw_activity_blink(unsigned long arg)
899 {
900 struct ata_link *link = (struct ata_link *)arg;
901 struct ata_port *ap = link->ap;
902 struct ahci_port_priv *pp = ap->private_data;
903 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
904 unsigned long led_message = emp->led_state;
905 u32 activity_led_state;
906 unsigned long flags;
907
908 led_message &= EM_MSG_LED_VALUE;
909 led_message |= ap->port_no | (link->pmp << 8);
910
911 /* check to see if we've had activity. If so,
912 * toggle state of LED and reset timer. If not,
913 * turn LED to desired idle state.
914 */
915 spin_lock_irqsave(ap->lock, flags);
916 if (emp->saved_activity != emp->activity) {
917 emp->saved_activity = emp->activity;
918 /* get the current LED state */
919 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
920
921 if (activity_led_state)
922 activity_led_state = 0;
923 else
924 activity_led_state = 1;
925
926 /* clear old state */
927 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
928
929 /* toggle state */
930 led_message |= (activity_led_state << 16);
931 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
932 } else {
933 /* switch to idle */
934 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
935 if (emp->blink_policy == BLINK_OFF)
936 led_message |= (1 << 16);
937 }
938 spin_unlock_irqrestore(ap->lock, flags);
939 ap->ops->transmit_led_message(ap, led_message, 4);
940 }
941
ahci_init_sw_activity(struct ata_link * link)942 static void ahci_init_sw_activity(struct ata_link *link)
943 {
944 struct ata_port *ap = link->ap;
945 struct ahci_port_priv *pp = ap->private_data;
946 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
947
948 /* init activity stats, setup timer */
949 emp->saved_activity = emp->activity = 0;
950 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
951
952 /* check our blink policy and set flag for link if it's enabled */
953 if (emp->blink_policy)
954 link->flags |= ATA_LFLAG_SW_ACTIVITY;
955 }
956
ahci_reset_em(struct ata_host * host)957 int ahci_reset_em(struct ata_host *host)
958 {
959 struct ahci_host_priv *hpriv = host->private_data;
960 void __iomem *mmio = hpriv->mmio;
961 u32 em_ctl;
962
963 em_ctl = readl(mmio + HOST_EM_CTL);
964 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
965 return -EINVAL;
966
967 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
968 return 0;
969 }
970 EXPORT_SYMBOL_GPL(ahci_reset_em);
971
ahci_transmit_led_message(struct ata_port * ap,u32 state,ssize_t size)972 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
973 ssize_t size)
974 {
975 struct ahci_host_priv *hpriv = ap->host->private_data;
976 struct ahci_port_priv *pp = ap->private_data;
977 void __iomem *mmio = hpriv->mmio;
978 u32 em_ctl;
979 u32 message[] = {0, 0};
980 unsigned long flags;
981 int pmp;
982 struct ahci_em_priv *emp;
983
984 /* get the slot number from the message */
985 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
986 if (pmp < EM_MAX_SLOTS)
987 emp = &pp->em_priv[pmp];
988 else
989 return -EINVAL;
990
991 spin_lock_irqsave(ap->lock, flags);
992
993 /*
994 * if we are still busy transmitting a previous message,
995 * do not allow
996 */
997 em_ctl = readl(mmio + HOST_EM_CTL);
998 if (em_ctl & EM_CTL_TM) {
999 spin_unlock_irqrestore(ap->lock, flags);
1000 return -EBUSY;
1001 }
1002
1003 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1004 /*
1005 * create message header - this is all zero except for
1006 * the message size, which is 4 bytes.
1007 */
1008 message[0] |= (4 << 8);
1009
1010 /* ignore 0:4 of byte zero, fill in port info yourself */
1011 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1012
1013 /* write message to EM_LOC */
1014 writel(message[0], mmio + hpriv->em_loc);
1015 writel(message[1], mmio + hpriv->em_loc+4);
1016
1017 /*
1018 * tell hardware to transmit the message
1019 */
1020 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1021 }
1022
1023 /* save off new led state for port/slot */
1024 emp->led_state = state;
1025
1026 spin_unlock_irqrestore(ap->lock, flags);
1027 return size;
1028 }
1029
ahci_led_show(struct ata_port * ap,char * buf)1030 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1031 {
1032 struct ahci_port_priv *pp = ap->private_data;
1033 struct ata_link *link;
1034 struct ahci_em_priv *emp;
1035 int rc = 0;
1036
1037 ata_for_each_link(link, ap, EDGE) {
1038 emp = &pp->em_priv[link->pmp];
1039 rc += sprintf(buf, "%lx\n", emp->led_state);
1040 }
1041 return rc;
1042 }
1043
ahci_led_store(struct ata_port * ap,const char * buf,size_t size)1044 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1045 size_t size)
1046 {
1047 unsigned int state;
1048 int pmp;
1049 struct ahci_port_priv *pp = ap->private_data;
1050 struct ahci_em_priv *emp;
1051
1052 if (kstrtouint(buf, 0, &state) < 0)
1053 return -EINVAL;
1054
1055 /* get the slot number from the message */
1056 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1057 if (pmp < EM_MAX_SLOTS)
1058 emp = &pp->em_priv[pmp];
1059 else
1060 return -EINVAL;
1061
1062 /* mask off the activity bits if we are in sw_activity
1063 * mode, user should turn off sw_activity before setting
1064 * activity led through em_message
1065 */
1066 if (emp->blink_policy)
1067 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1068
1069 return ap->ops->transmit_led_message(ap, state, size);
1070 }
1071
ahci_activity_store(struct ata_device * dev,enum sw_activity val)1072 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1073 {
1074 struct ata_link *link = dev->link;
1075 struct ata_port *ap = link->ap;
1076 struct ahci_port_priv *pp = ap->private_data;
1077 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1078 u32 port_led_state = emp->led_state;
1079
1080 /* save the desired Activity LED behavior */
1081 if (val == OFF) {
1082 /* clear LFLAG */
1083 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1084
1085 /* set the LED to OFF */
1086 port_led_state &= EM_MSG_LED_VALUE_OFF;
1087 port_led_state |= (ap->port_no | (link->pmp << 8));
1088 ap->ops->transmit_led_message(ap, port_led_state, 4);
1089 } else {
1090 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1091 if (val == BLINK_OFF) {
1092 /* set LED to ON for idle */
1093 port_led_state &= EM_MSG_LED_VALUE_OFF;
1094 port_led_state |= (ap->port_no | (link->pmp << 8));
1095 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1096 ap->ops->transmit_led_message(ap, port_led_state, 4);
1097 }
1098 }
1099 emp->blink_policy = val;
1100 return 0;
1101 }
1102
ahci_activity_show(struct ata_device * dev,char * buf)1103 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1104 {
1105 struct ata_link *link = dev->link;
1106 struct ata_port *ap = link->ap;
1107 struct ahci_port_priv *pp = ap->private_data;
1108 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1109
1110 /* display the saved value of activity behavior for this
1111 * disk.
1112 */
1113 return sprintf(buf, "%d\n", emp->blink_policy);
1114 }
1115
ahci_port_init(struct device * dev,struct ata_port * ap,int port_no,void __iomem * mmio,void __iomem * port_mmio)1116 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1117 int port_no, void __iomem *mmio,
1118 void __iomem *port_mmio)
1119 {
1120 struct ahci_host_priv *hpriv = ap->host->private_data;
1121 const char *emsg = NULL;
1122 int rc;
1123 u32 tmp;
1124
1125 /* make sure port is not active */
1126 rc = ahci_deinit_port(ap, &emsg);
1127 if (rc)
1128 dev_warn(dev, "%s (%d)\n", emsg, rc);
1129
1130 /* clear SError */
1131 tmp = readl(port_mmio + PORT_SCR_ERR);
1132 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1133 writel(tmp, port_mmio + PORT_SCR_ERR);
1134
1135 /* clear port IRQ */
1136 tmp = readl(port_mmio + PORT_IRQ_STAT);
1137 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1138 if (tmp)
1139 writel(tmp, port_mmio + PORT_IRQ_STAT);
1140
1141 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1142
1143 /* mark esata ports */
1144 tmp = readl(port_mmio + PORT_CMD);
1145 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1146 ap->pflags |= ATA_PFLAG_EXTERNAL;
1147 }
1148
ahci_init_controller(struct ata_host * host)1149 void ahci_init_controller(struct ata_host *host)
1150 {
1151 struct ahci_host_priv *hpriv = host->private_data;
1152 void __iomem *mmio = hpriv->mmio;
1153 int i;
1154 void __iomem *port_mmio;
1155 u32 tmp;
1156
1157 for (i = 0; i < host->n_ports; i++) {
1158 struct ata_port *ap = host->ports[i];
1159
1160 port_mmio = ahci_port_base(ap);
1161 if (ata_port_is_dummy(ap))
1162 continue;
1163
1164 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1165 }
1166
1167 tmp = readl(mmio + HOST_CTL);
1168 VPRINTK("HOST_CTL 0x%x\n", tmp);
1169 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1170 tmp = readl(mmio + HOST_CTL);
1171 VPRINTK("HOST_CTL 0x%x\n", tmp);
1172 }
1173 EXPORT_SYMBOL_GPL(ahci_init_controller);
1174
ahci_dev_config(struct ata_device * dev)1175 static void ahci_dev_config(struct ata_device *dev)
1176 {
1177 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1178
1179 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1180 dev->max_sectors = 255;
1181 ata_dev_info(dev,
1182 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1183 }
1184 }
1185
ahci_dev_classify(struct ata_port * ap)1186 unsigned int ahci_dev_classify(struct ata_port *ap)
1187 {
1188 void __iomem *port_mmio = ahci_port_base(ap);
1189 struct ata_taskfile tf;
1190 u32 tmp;
1191
1192 tmp = readl(port_mmio + PORT_SIG);
1193 tf.lbah = (tmp >> 24) & 0xff;
1194 tf.lbam = (tmp >> 16) & 0xff;
1195 tf.lbal = (tmp >> 8) & 0xff;
1196 tf.nsect = (tmp) & 0xff;
1197
1198 return ata_dev_classify(&tf);
1199 }
1200 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1201
ahci_fill_cmd_slot(struct ahci_port_priv * pp,unsigned int tag,u32 opts)1202 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1203 u32 opts)
1204 {
1205 dma_addr_t cmd_tbl_dma;
1206
1207 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1208
1209 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1210 pp->cmd_slot[tag].status = 0;
1211 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1212 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1213 }
1214 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1215
ahci_kick_engine(struct ata_port * ap)1216 int ahci_kick_engine(struct ata_port *ap)
1217 {
1218 void __iomem *port_mmio = ahci_port_base(ap);
1219 struct ahci_host_priv *hpriv = ap->host->private_data;
1220 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1221 u32 tmp;
1222 int busy, rc;
1223
1224 /* stop engine */
1225 rc = ahci_stop_engine(ap);
1226 if (rc)
1227 goto out_restart;
1228
1229 /* need to do CLO?
1230 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1231 */
1232 busy = status & (ATA_BUSY | ATA_DRQ);
1233 if (!busy && !sata_pmp_attached(ap)) {
1234 rc = 0;
1235 goto out_restart;
1236 }
1237
1238 if (!(hpriv->cap & HOST_CAP_CLO)) {
1239 rc = -EOPNOTSUPP;
1240 goto out_restart;
1241 }
1242
1243 /* perform CLO */
1244 tmp = readl(port_mmio + PORT_CMD);
1245 tmp |= PORT_CMD_CLO;
1246 writel(tmp, port_mmio + PORT_CMD);
1247
1248 rc = 0;
1249 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1250 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1251 if (tmp & PORT_CMD_CLO)
1252 rc = -EIO;
1253
1254 /* restart engine */
1255 out_restart:
1256 hpriv->start_engine(ap);
1257 return rc;
1258 }
1259 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1260
ahci_exec_polled_cmd(struct ata_port * ap,int pmp,struct ata_taskfile * tf,int is_cmd,u16 flags,unsigned long timeout_msec)1261 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1262 struct ata_taskfile *tf, int is_cmd, u16 flags,
1263 unsigned long timeout_msec)
1264 {
1265 const u32 cmd_fis_len = 5; /* five dwords */
1266 struct ahci_port_priv *pp = ap->private_data;
1267 void __iomem *port_mmio = ahci_port_base(ap);
1268 u8 *fis = pp->cmd_tbl;
1269 u32 tmp;
1270
1271 /* prep the command */
1272 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1273 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1274
1275 /* set port value for softreset of Port Multiplier */
1276 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1277 tmp = readl(port_mmio + PORT_FBS);
1278 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1279 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1280 writel(tmp, port_mmio + PORT_FBS);
1281 pp->fbs_last_dev = pmp;
1282 }
1283
1284 /* issue & wait */
1285 writel(1, port_mmio + PORT_CMD_ISSUE);
1286
1287 if (timeout_msec) {
1288 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1289 0x1, 0x1, 1, timeout_msec);
1290 if (tmp & 0x1) {
1291 ahci_kick_engine(ap);
1292 return -EBUSY;
1293 }
1294 } else
1295 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1296
1297 return 0;
1298 }
1299
ahci_do_softreset(struct ata_link * link,unsigned int * class,int pmp,unsigned long deadline,int (* check_ready)(struct ata_link * link))1300 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1301 int pmp, unsigned long deadline,
1302 int (*check_ready)(struct ata_link *link))
1303 {
1304 struct ata_port *ap = link->ap;
1305 struct ahci_host_priv *hpriv = ap->host->private_data;
1306 struct ahci_port_priv *pp = ap->private_data;
1307 const char *reason = NULL;
1308 unsigned long now, msecs;
1309 struct ata_taskfile tf;
1310 bool fbs_disabled = false;
1311 int rc;
1312
1313 DPRINTK("ENTER\n");
1314
1315 /* prepare for SRST (AHCI-1.1 10.4.1) */
1316 rc = ahci_kick_engine(ap);
1317 if (rc && rc != -EOPNOTSUPP)
1318 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1319
1320 /*
1321 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1322 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1323 * that is attached to port multiplier.
1324 */
1325 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1326 ahci_disable_fbs(ap);
1327 fbs_disabled = true;
1328 }
1329
1330 ata_tf_init(link->device, &tf);
1331
1332 /* issue the first D2H Register FIS */
1333 msecs = 0;
1334 now = jiffies;
1335 if (time_after(deadline, now))
1336 msecs = jiffies_to_msecs(deadline - now);
1337
1338 tf.ctl |= ATA_SRST;
1339 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1340 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1341 rc = -EIO;
1342 reason = "1st FIS failed";
1343 goto fail;
1344 }
1345
1346 /* spec says at least 5us, but be generous and sleep for 1ms */
1347 ata_msleep(ap, 1);
1348
1349 /* issue the second D2H Register FIS */
1350 tf.ctl &= ~ATA_SRST;
1351 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1352
1353 /* wait for link to become ready */
1354 rc = ata_wait_after_reset(link, deadline, check_ready);
1355 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1356 /*
1357 * Workaround for cases where link online status can't
1358 * be trusted. Treat device readiness timeout as link
1359 * offline.
1360 */
1361 ata_link_info(link, "device not ready, treating as offline\n");
1362 *class = ATA_DEV_NONE;
1363 } else if (rc) {
1364 /* link occupied, -ENODEV too is an error */
1365 reason = "device not ready";
1366 goto fail;
1367 } else
1368 *class = ahci_dev_classify(ap);
1369
1370 /* re-enable FBS if disabled before */
1371 if (fbs_disabled)
1372 ahci_enable_fbs(ap);
1373
1374 DPRINTK("EXIT, class=%u\n", *class);
1375 return 0;
1376
1377 fail:
1378 ata_link_err(link, "softreset failed (%s)\n", reason);
1379 return rc;
1380 }
1381
ahci_check_ready(struct ata_link * link)1382 int ahci_check_ready(struct ata_link *link)
1383 {
1384 void __iomem *port_mmio = ahci_port_base(link->ap);
1385 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1386
1387 return ata_check_ready(status);
1388 }
1389 EXPORT_SYMBOL_GPL(ahci_check_ready);
1390
ahci_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1391 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1392 unsigned long deadline)
1393 {
1394 int pmp = sata_srst_pmp(link);
1395
1396 DPRINTK("ENTER\n");
1397
1398 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1399 }
1400 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1401
ahci_bad_pmp_check_ready(struct ata_link * link)1402 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1403 {
1404 void __iomem *port_mmio = ahci_port_base(link->ap);
1405 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1406 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1407
1408 /*
1409 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1410 * which can save timeout delay.
1411 */
1412 if (irq_status & PORT_IRQ_BAD_PMP)
1413 return -EIO;
1414
1415 return ata_check_ready(status);
1416 }
1417
ahci_pmp_retry_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1418 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1419 unsigned long deadline)
1420 {
1421 struct ata_port *ap = link->ap;
1422 void __iomem *port_mmio = ahci_port_base(ap);
1423 int pmp = sata_srst_pmp(link);
1424 int rc;
1425 u32 irq_sts;
1426
1427 DPRINTK("ENTER\n");
1428
1429 rc = ahci_do_softreset(link, class, pmp, deadline,
1430 ahci_bad_pmp_check_ready);
1431
1432 /*
1433 * Soft reset fails with IPMS set when PMP is enabled but
1434 * SATA HDD/ODD is connected to SATA port, do soft reset
1435 * again to port 0.
1436 */
1437 if (rc == -EIO) {
1438 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1439 if (irq_sts & PORT_IRQ_BAD_PMP) {
1440 ata_link_warn(link,
1441 "applying PMP SRST workaround "
1442 "and retrying\n");
1443 rc = ahci_do_softreset(link, class, 0, deadline,
1444 ahci_check_ready);
1445 }
1446 }
1447
1448 return rc;
1449 }
1450
ahci_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1451 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1452 unsigned long deadline)
1453 {
1454 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1455 struct ata_port *ap = link->ap;
1456 struct ahci_port_priv *pp = ap->private_data;
1457 struct ahci_host_priv *hpriv = ap->host->private_data;
1458 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1459 struct ata_taskfile tf;
1460 bool online;
1461 int rc;
1462
1463 DPRINTK("ENTER\n");
1464
1465 ahci_stop_engine(ap);
1466
1467 /* clear D2H reception area to properly wait for D2H FIS */
1468 ata_tf_init(link->device, &tf);
1469 tf.command = ATA_BUSY;
1470 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1471
1472 rc = sata_link_hardreset(link, timing, deadline, &online,
1473 ahci_check_ready);
1474
1475 hpriv->start_engine(ap);
1476
1477 if (online)
1478 *class = ahci_dev_classify(ap);
1479
1480 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1481 return rc;
1482 }
1483
ahci_postreset(struct ata_link * link,unsigned int * class)1484 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1485 {
1486 struct ata_port *ap = link->ap;
1487 void __iomem *port_mmio = ahci_port_base(ap);
1488 u32 new_tmp, tmp;
1489
1490 ata_std_postreset(link, class);
1491
1492 /* Make sure port's ATAPI bit is set appropriately */
1493 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1494 if (*class == ATA_DEV_ATAPI)
1495 new_tmp |= PORT_CMD_ATAPI;
1496 else
1497 new_tmp &= ~PORT_CMD_ATAPI;
1498 if (new_tmp != tmp) {
1499 writel(new_tmp, port_mmio + PORT_CMD);
1500 readl(port_mmio + PORT_CMD); /* flush */
1501 }
1502 }
1503
ahci_fill_sg(struct ata_queued_cmd * qc,void * cmd_tbl)1504 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1505 {
1506 struct scatterlist *sg;
1507 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1508 unsigned int si;
1509
1510 VPRINTK("ENTER\n");
1511
1512 /*
1513 * Next, the S/G list.
1514 */
1515 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1516 dma_addr_t addr = sg_dma_address(sg);
1517 u32 sg_len = sg_dma_len(sg);
1518
1519 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1520 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1521 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1522 }
1523
1524 return si;
1525 }
1526
ahci_pmp_qc_defer(struct ata_queued_cmd * qc)1527 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1528 {
1529 struct ata_port *ap = qc->ap;
1530 struct ahci_port_priv *pp = ap->private_data;
1531
1532 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1533 return ata_std_qc_defer(qc);
1534 else
1535 return sata_pmp_qc_defer_cmd_switch(qc);
1536 }
1537
ahci_qc_prep(struct ata_queued_cmd * qc)1538 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc)
1539 {
1540 struct ata_port *ap = qc->ap;
1541 struct ahci_port_priv *pp = ap->private_data;
1542 int is_atapi = ata_is_atapi(qc->tf.protocol);
1543 void *cmd_tbl;
1544 u32 opts;
1545 const u32 cmd_fis_len = 5; /* five dwords */
1546 unsigned int n_elem;
1547
1548 /*
1549 * Fill in command table information. First, the header,
1550 * a SATA Register - Host to Device command FIS.
1551 */
1552 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1553
1554 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1555 if (is_atapi) {
1556 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1557 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1558 }
1559
1560 n_elem = 0;
1561 if (qc->flags & ATA_QCFLAG_DMAMAP)
1562 n_elem = ahci_fill_sg(qc, cmd_tbl);
1563
1564 /*
1565 * Fill in command slot information.
1566 */
1567 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1568 if (qc->tf.flags & ATA_TFLAG_WRITE)
1569 opts |= AHCI_CMD_WRITE;
1570 if (is_atapi)
1571 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1572
1573 ahci_fill_cmd_slot(pp, qc->tag, opts);
1574
1575 return AC_ERR_OK;
1576 }
1577
ahci_fbs_dec_intr(struct ata_port * ap)1578 static void ahci_fbs_dec_intr(struct ata_port *ap)
1579 {
1580 struct ahci_port_priv *pp = ap->private_data;
1581 void __iomem *port_mmio = ahci_port_base(ap);
1582 u32 fbs = readl(port_mmio + PORT_FBS);
1583 int retries = 3;
1584
1585 DPRINTK("ENTER\n");
1586 BUG_ON(!pp->fbs_enabled);
1587
1588 /* time to wait for DEC is not specified by AHCI spec,
1589 * add a retry loop for safety.
1590 */
1591 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1592 fbs = readl(port_mmio + PORT_FBS);
1593 while ((fbs & PORT_FBS_DEC) && retries--) {
1594 udelay(1);
1595 fbs = readl(port_mmio + PORT_FBS);
1596 }
1597
1598 if (fbs & PORT_FBS_DEC)
1599 dev_err(ap->host->dev, "failed to clear device error\n");
1600 }
1601
ahci_error_intr(struct ata_port * ap,u32 irq_stat)1602 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1603 {
1604 struct ahci_host_priv *hpriv = ap->host->private_data;
1605 struct ahci_port_priv *pp = ap->private_data;
1606 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1607 struct ata_link *link = NULL;
1608 struct ata_queued_cmd *active_qc;
1609 struct ata_eh_info *active_ehi;
1610 bool fbs_need_dec = false;
1611 u32 serror;
1612
1613 /* determine active link with error */
1614 if (pp->fbs_enabled) {
1615 void __iomem *port_mmio = ahci_port_base(ap);
1616 u32 fbs = readl(port_mmio + PORT_FBS);
1617 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1618
1619 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1620 link = &ap->pmp_link[pmp];
1621 fbs_need_dec = true;
1622 }
1623
1624 } else
1625 ata_for_each_link(link, ap, EDGE)
1626 if (ata_link_active(link))
1627 break;
1628
1629 if (!link)
1630 link = &ap->link;
1631
1632 active_qc = ata_qc_from_tag(ap, link->active_tag);
1633 active_ehi = &link->eh_info;
1634
1635 /* record irq stat */
1636 ata_ehi_clear_desc(host_ehi);
1637 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1638
1639 /* AHCI needs SError cleared; otherwise, it might lock up */
1640 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1641 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1642 host_ehi->serror |= serror;
1643
1644 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1645 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1646 irq_stat &= ~PORT_IRQ_IF_ERR;
1647
1648 if (irq_stat & PORT_IRQ_TF_ERR) {
1649 /* If qc is active, charge it; otherwise, the active
1650 * link. There's no active qc on NCQ errors. It will
1651 * be determined by EH by reading log page 10h.
1652 */
1653 if (active_qc)
1654 active_qc->err_mask |= AC_ERR_DEV;
1655 else
1656 active_ehi->err_mask |= AC_ERR_DEV;
1657
1658 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1659 host_ehi->serror &= ~SERR_INTERNAL;
1660 }
1661
1662 if (irq_stat & PORT_IRQ_UNK_FIS) {
1663 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1664
1665 active_ehi->err_mask |= AC_ERR_HSM;
1666 active_ehi->action |= ATA_EH_RESET;
1667 ata_ehi_push_desc(active_ehi,
1668 "unknown FIS %08x %08x %08x %08x" ,
1669 unk[0], unk[1], unk[2], unk[3]);
1670 }
1671
1672 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1673 active_ehi->err_mask |= AC_ERR_HSM;
1674 active_ehi->action |= ATA_EH_RESET;
1675 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1676 }
1677
1678 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1679 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1680 host_ehi->action |= ATA_EH_RESET;
1681 ata_ehi_push_desc(host_ehi, "host bus error");
1682 }
1683
1684 if (irq_stat & PORT_IRQ_IF_ERR) {
1685 if (fbs_need_dec)
1686 active_ehi->err_mask |= AC_ERR_DEV;
1687 else {
1688 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1689 host_ehi->action |= ATA_EH_RESET;
1690 }
1691
1692 ata_ehi_push_desc(host_ehi, "interface fatal error");
1693 }
1694
1695 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1696 ata_ehi_hotplugged(host_ehi);
1697 ata_ehi_push_desc(host_ehi, "%s",
1698 irq_stat & PORT_IRQ_CONNECT ?
1699 "connection status changed" : "PHY RDY changed");
1700 }
1701
1702 /* okay, let's hand over to EH */
1703
1704 if (irq_stat & PORT_IRQ_FREEZE)
1705 ata_port_freeze(ap);
1706 else if (fbs_need_dec) {
1707 ata_link_abort(link);
1708 ahci_fbs_dec_intr(ap);
1709 } else
1710 ata_port_abort(ap);
1711 }
1712
ahci_handle_port_interrupt(struct ata_port * ap,void __iomem * port_mmio,u32 status)1713 static void ahci_handle_port_interrupt(struct ata_port *ap,
1714 void __iomem *port_mmio, u32 status)
1715 {
1716 struct ata_eh_info *ehi = &ap->link.eh_info;
1717 struct ahci_port_priv *pp = ap->private_data;
1718 struct ahci_host_priv *hpriv = ap->host->private_data;
1719 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1720 u32 qc_active = 0;
1721 int rc;
1722
1723 /* ignore BAD_PMP while resetting */
1724 if (unlikely(resetting))
1725 status &= ~PORT_IRQ_BAD_PMP;
1726
1727 if (sata_lpm_ignore_phy_events(&ap->link)) {
1728 status &= ~PORT_IRQ_PHYRDY;
1729 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1730 }
1731
1732 if (unlikely(status & PORT_IRQ_ERROR)) {
1733 ahci_error_intr(ap, status);
1734 return;
1735 }
1736
1737 if (status & PORT_IRQ_SDB_FIS) {
1738 /* If SNotification is available, leave notification
1739 * handling to sata_async_notification(). If not,
1740 * emulate it by snooping SDB FIS RX area.
1741 *
1742 * Snooping FIS RX area is probably cheaper than
1743 * poking SNotification but some constrollers which
1744 * implement SNotification, ICH9 for example, don't
1745 * store AN SDB FIS into receive area.
1746 */
1747 if (hpriv->cap & HOST_CAP_SNTF)
1748 sata_async_notification(ap);
1749 else {
1750 /* If the 'N' bit in word 0 of the FIS is set,
1751 * we just received asynchronous notification.
1752 * Tell libata about it.
1753 *
1754 * Lack of SNotification should not appear in
1755 * ahci 1.2, so the workaround is unnecessary
1756 * when FBS is enabled.
1757 */
1758 if (pp->fbs_enabled)
1759 WARN_ON_ONCE(1);
1760 else {
1761 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1762 u32 f0 = le32_to_cpu(f[0]);
1763 if (f0 & (1 << 15))
1764 sata_async_notification(ap);
1765 }
1766 }
1767 }
1768
1769 /* pp->active_link is not reliable once FBS is enabled, both
1770 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1771 * NCQ and non-NCQ commands may be in flight at the same time.
1772 */
1773 if (pp->fbs_enabled) {
1774 if (ap->qc_active) {
1775 qc_active = readl(port_mmio + PORT_SCR_ACT);
1776 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1777 }
1778 } else {
1779 /* pp->active_link is valid iff any command is in flight */
1780 if (ap->qc_active && pp->active_link->sactive)
1781 qc_active = readl(port_mmio + PORT_SCR_ACT);
1782 else
1783 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1784 }
1785
1786
1787 rc = ata_qc_complete_multiple(ap, qc_active);
1788
1789 /* while resetting, invalid completions are expected */
1790 if (unlikely(rc < 0 && !resetting)) {
1791 ehi->err_mask |= AC_ERR_HSM;
1792 ehi->action |= ATA_EH_RESET;
1793 ata_port_freeze(ap);
1794 }
1795 }
1796
ahci_port_intr(struct ata_port * ap)1797 static void ahci_port_intr(struct ata_port *ap)
1798 {
1799 void __iomem *port_mmio = ahci_port_base(ap);
1800 u32 status;
1801
1802 status = readl(port_mmio + PORT_IRQ_STAT);
1803 writel(status, port_mmio + PORT_IRQ_STAT);
1804
1805 ahci_handle_port_interrupt(ap, port_mmio, status);
1806 }
1807
ahci_port_thread_fn(int irq,void * dev_instance)1808 static irqreturn_t ahci_port_thread_fn(int irq, void *dev_instance)
1809 {
1810 struct ata_port *ap = dev_instance;
1811 struct ahci_port_priv *pp = ap->private_data;
1812 void __iomem *port_mmio = ahci_port_base(ap);
1813 u32 status;
1814
1815 status = atomic_xchg(&pp->intr_status, 0);
1816 if (!status)
1817 return IRQ_NONE;
1818
1819 spin_lock_bh(ap->lock);
1820 ahci_handle_port_interrupt(ap, port_mmio, status);
1821 spin_unlock_bh(ap->lock);
1822
1823 return IRQ_HANDLED;
1824 }
1825
ahci_multi_irqs_intr(int irq,void * dev_instance)1826 static irqreturn_t ahci_multi_irqs_intr(int irq, void *dev_instance)
1827 {
1828 struct ata_port *ap = dev_instance;
1829 void __iomem *port_mmio = ahci_port_base(ap);
1830 struct ahci_port_priv *pp = ap->private_data;
1831 u32 status;
1832
1833 VPRINTK("ENTER\n");
1834
1835 status = readl(port_mmio + PORT_IRQ_STAT);
1836 writel(status, port_mmio + PORT_IRQ_STAT);
1837
1838 atomic_or(status, &pp->intr_status);
1839
1840 VPRINTK("EXIT\n");
1841
1842 return IRQ_WAKE_THREAD;
1843 }
1844
ahci_handle_port_intr(struct ata_host * host,u32 irq_masked)1845 static u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1846 {
1847 unsigned int i, handled = 0;
1848
1849 for (i = 0; i < host->n_ports; i++) {
1850 struct ata_port *ap;
1851
1852 if (!(irq_masked & (1 << i)))
1853 continue;
1854
1855 ap = host->ports[i];
1856 if (ap) {
1857 ahci_port_intr(ap);
1858 VPRINTK("port %u\n", i);
1859 } else {
1860 VPRINTK("port %u (no irq)\n", i);
1861 if (ata_ratelimit())
1862 dev_warn(host->dev,
1863 "interrupt on disabled port %u\n", i);
1864 }
1865
1866 handled = 1;
1867 }
1868
1869 return handled;
1870 }
1871
ahci_single_edge_irq_intr(int irq,void * dev_instance)1872 static irqreturn_t ahci_single_edge_irq_intr(int irq, void *dev_instance)
1873 {
1874 struct ata_host *host = dev_instance;
1875 struct ahci_host_priv *hpriv;
1876 unsigned int rc = 0;
1877 void __iomem *mmio;
1878 u32 irq_stat, irq_masked;
1879
1880 VPRINTK("ENTER\n");
1881
1882 hpriv = host->private_data;
1883 mmio = hpriv->mmio;
1884
1885 /* sigh. 0xffffffff is a valid return from h/w */
1886 irq_stat = readl(mmio + HOST_IRQ_STAT);
1887 if (!irq_stat)
1888 return IRQ_NONE;
1889
1890 irq_masked = irq_stat & hpriv->port_map;
1891
1892 spin_lock(&host->lock);
1893
1894 /*
1895 * HOST_IRQ_STAT behaves as edge triggered latch meaning that
1896 * it should be cleared before all the port events are cleared.
1897 */
1898 writel(irq_stat, mmio + HOST_IRQ_STAT);
1899
1900 rc = ahci_handle_port_intr(host, irq_masked);
1901
1902 spin_unlock(&host->lock);
1903
1904 VPRINTK("EXIT\n");
1905
1906 return IRQ_RETVAL(rc);
1907 }
1908
ahci_single_level_irq_intr(int irq,void * dev_instance)1909 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1910 {
1911 struct ata_host *host = dev_instance;
1912 struct ahci_host_priv *hpriv;
1913 unsigned int rc = 0;
1914 void __iomem *mmio;
1915 u32 irq_stat, irq_masked;
1916
1917 VPRINTK("ENTER\n");
1918
1919 hpriv = host->private_data;
1920 mmio = hpriv->mmio;
1921
1922 /* sigh. 0xffffffff is a valid return from h/w */
1923 irq_stat = readl(mmio + HOST_IRQ_STAT);
1924 if (!irq_stat)
1925 return IRQ_NONE;
1926
1927 irq_masked = irq_stat & hpriv->port_map;
1928
1929 spin_lock(&host->lock);
1930
1931 rc = ahci_handle_port_intr(host, irq_masked);
1932
1933 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1934 * it should be cleared after all the port events are cleared;
1935 * otherwise, it will raise a spurious interrupt after each
1936 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1937 * information.
1938 *
1939 * Also, use the unmasked value to clear interrupt as spurious
1940 * pending event on a dummy port might cause screaming IRQ.
1941 */
1942 writel(irq_stat, mmio + HOST_IRQ_STAT);
1943
1944 spin_unlock(&host->lock);
1945
1946 VPRINTK("EXIT\n");
1947
1948 return IRQ_RETVAL(rc);
1949 }
1950
ahci_qc_issue(struct ata_queued_cmd * qc)1951 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1952 {
1953 struct ata_port *ap = qc->ap;
1954 void __iomem *port_mmio = ahci_port_base(ap);
1955 struct ahci_port_priv *pp = ap->private_data;
1956
1957 /* Keep track of the currently active link. It will be used
1958 * in completion path to determine whether NCQ phase is in
1959 * progress.
1960 */
1961 pp->active_link = qc->dev->link;
1962
1963 if (qc->tf.protocol == ATA_PROT_NCQ)
1964 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1965
1966 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1967 u32 fbs = readl(port_mmio + PORT_FBS);
1968 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1969 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1970 writel(fbs, port_mmio + PORT_FBS);
1971 pp->fbs_last_dev = qc->dev->link->pmp;
1972 }
1973
1974 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1975
1976 ahci_sw_activity(qc->dev->link);
1977
1978 return 0;
1979 }
1980 EXPORT_SYMBOL_GPL(ahci_qc_issue);
1981
ahci_qc_fill_rtf(struct ata_queued_cmd * qc)1982 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1983 {
1984 struct ahci_port_priv *pp = qc->ap->private_data;
1985 u8 *rx_fis = pp->rx_fis;
1986
1987 if (pp->fbs_enabled)
1988 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1989
1990 /*
1991 * After a successful execution of an ATA PIO data-in command,
1992 * the device doesn't send D2H Reg FIS to update the TF and
1993 * the host should take TF and E_Status from the preceding PIO
1994 * Setup FIS.
1995 */
1996 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1997 !(qc->flags & ATA_QCFLAG_FAILED)) {
1998 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1999 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2000 } else
2001 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2002
2003 return true;
2004 }
2005
ahci_freeze(struct ata_port * ap)2006 static void ahci_freeze(struct ata_port *ap)
2007 {
2008 void __iomem *port_mmio = ahci_port_base(ap);
2009
2010 /* turn IRQ off */
2011 writel(0, port_mmio + PORT_IRQ_MASK);
2012 }
2013
ahci_thaw(struct ata_port * ap)2014 static void ahci_thaw(struct ata_port *ap)
2015 {
2016 struct ahci_host_priv *hpriv = ap->host->private_data;
2017 void __iomem *mmio = hpriv->mmio;
2018 void __iomem *port_mmio = ahci_port_base(ap);
2019 u32 tmp;
2020 struct ahci_port_priv *pp = ap->private_data;
2021
2022 /* clear IRQ */
2023 tmp = readl(port_mmio + PORT_IRQ_STAT);
2024 writel(tmp, port_mmio + PORT_IRQ_STAT);
2025 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2026
2027 /* turn IRQ back on */
2028 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2029 }
2030
ahci_error_handler(struct ata_port * ap)2031 void ahci_error_handler(struct ata_port *ap)
2032 {
2033 struct ahci_host_priv *hpriv = ap->host->private_data;
2034
2035 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2036 /* restart engine */
2037 ahci_stop_engine(ap);
2038 hpriv->start_engine(ap);
2039 }
2040
2041 sata_pmp_error_handler(ap);
2042
2043 if (!ata_dev_enabled(ap->link.device))
2044 ahci_stop_engine(ap);
2045 }
2046 EXPORT_SYMBOL_GPL(ahci_error_handler);
2047
ahci_post_internal_cmd(struct ata_queued_cmd * qc)2048 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2049 {
2050 struct ata_port *ap = qc->ap;
2051
2052 /* make DMA engine forget about the failed command */
2053 if (qc->flags & ATA_QCFLAG_FAILED)
2054 ahci_kick_engine(ap);
2055 }
2056
ahci_set_aggressive_devslp(struct ata_port * ap,bool sleep)2057 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2058 {
2059 struct ahci_host_priv *hpriv = ap->host->private_data;
2060 void __iomem *port_mmio = ahci_port_base(ap);
2061 struct ata_device *dev = ap->link.device;
2062 u32 devslp, dm, dito, mdat, deto;
2063 int rc;
2064 unsigned int err_mask;
2065
2066 devslp = readl(port_mmio + PORT_DEVSLP);
2067 if (!(devslp & PORT_DEVSLP_DSP)) {
2068 dev_info(ap->host->dev, "port does not support device sleep\n");
2069 return;
2070 }
2071
2072 /* disable device sleep */
2073 if (!sleep) {
2074 if (devslp & PORT_DEVSLP_ADSE) {
2075 writel(devslp & ~PORT_DEVSLP_ADSE,
2076 port_mmio + PORT_DEVSLP);
2077 err_mask = ata_dev_set_feature(dev,
2078 SETFEATURES_SATA_DISABLE,
2079 SATA_DEVSLP);
2080 if (err_mask && err_mask != AC_ERR_DEV)
2081 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2082 }
2083 return;
2084 }
2085
2086 /* device sleep was already enabled */
2087 if (devslp & PORT_DEVSLP_ADSE)
2088 return;
2089
2090 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2091 rc = ahci_stop_engine(ap);
2092 if (rc)
2093 return;
2094
2095 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2096 dito = devslp_idle_timeout / (dm + 1);
2097 if (dito > 0x3ff)
2098 dito = 0x3ff;
2099
2100 /* Use the nominal value 10 ms if the read MDAT is zero,
2101 * the nominal value of DETO is 20 ms.
2102 */
2103 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2104 ATA_LOG_DEVSLP_VALID_MASK) {
2105 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2106 ATA_LOG_DEVSLP_MDAT_MASK;
2107 if (!mdat)
2108 mdat = 10;
2109 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2110 if (!deto)
2111 deto = 20;
2112 } else {
2113 mdat = 10;
2114 deto = 20;
2115 }
2116
2117 /* Make dito, mdat, deto bits to 0s */
2118 devslp &= ~GENMASK_ULL(24, 2);
2119 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2120 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2121 (deto << PORT_DEVSLP_DETO_OFFSET) |
2122 PORT_DEVSLP_ADSE);
2123 writel(devslp, port_mmio + PORT_DEVSLP);
2124
2125 hpriv->start_engine(ap);
2126
2127 /* enable device sleep feature for the drive */
2128 err_mask = ata_dev_set_feature(dev,
2129 SETFEATURES_SATA_ENABLE,
2130 SATA_DEVSLP);
2131 if (err_mask && err_mask != AC_ERR_DEV)
2132 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2133 }
2134
ahci_enable_fbs(struct ata_port * ap)2135 static void ahci_enable_fbs(struct ata_port *ap)
2136 {
2137 struct ahci_host_priv *hpriv = ap->host->private_data;
2138 struct ahci_port_priv *pp = ap->private_data;
2139 void __iomem *port_mmio = ahci_port_base(ap);
2140 u32 fbs;
2141 int rc;
2142
2143 if (!pp->fbs_supported)
2144 return;
2145
2146 fbs = readl(port_mmio + PORT_FBS);
2147 if (fbs & PORT_FBS_EN) {
2148 pp->fbs_enabled = true;
2149 pp->fbs_last_dev = -1; /* initialization */
2150 return;
2151 }
2152
2153 rc = ahci_stop_engine(ap);
2154 if (rc)
2155 return;
2156
2157 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2158 fbs = readl(port_mmio + PORT_FBS);
2159 if (fbs & PORT_FBS_EN) {
2160 dev_info(ap->host->dev, "FBS is enabled\n");
2161 pp->fbs_enabled = true;
2162 pp->fbs_last_dev = -1; /* initialization */
2163 } else
2164 dev_err(ap->host->dev, "Failed to enable FBS\n");
2165
2166 hpriv->start_engine(ap);
2167 }
2168
ahci_disable_fbs(struct ata_port * ap)2169 static void ahci_disable_fbs(struct ata_port *ap)
2170 {
2171 struct ahci_host_priv *hpriv = ap->host->private_data;
2172 struct ahci_port_priv *pp = ap->private_data;
2173 void __iomem *port_mmio = ahci_port_base(ap);
2174 u32 fbs;
2175 int rc;
2176
2177 if (!pp->fbs_supported)
2178 return;
2179
2180 fbs = readl(port_mmio + PORT_FBS);
2181 if ((fbs & PORT_FBS_EN) == 0) {
2182 pp->fbs_enabled = false;
2183 return;
2184 }
2185
2186 rc = ahci_stop_engine(ap);
2187 if (rc)
2188 return;
2189
2190 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2191 fbs = readl(port_mmio + PORT_FBS);
2192 if (fbs & PORT_FBS_EN)
2193 dev_err(ap->host->dev, "Failed to disable FBS\n");
2194 else {
2195 dev_info(ap->host->dev, "FBS is disabled\n");
2196 pp->fbs_enabled = false;
2197 }
2198
2199 hpriv->start_engine(ap);
2200 }
2201
ahci_pmp_attach(struct ata_port * ap)2202 static void ahci_pmp_attach(struct ata_port *ap)
2203 {
2204 void __iomem *port_mmio = ahci_port_base(ap);
2205 struct ahci_port_priv *pp = ap->private_data;
2206 u32 cmd;
2207
2208 cmd = readl(port_mmio + PORT_CMD);
2209 cmd |= PORT_CMD_PMP;
2210 writel(cmd, port_mmio + PORT_CMD);
2211
2212 ahci_enable_fbs(ap);
2213
2214 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2215
2216 /*
2217 * We must not change the port interrupt mask register if the
2218 * port is marked frozen, the value in pp->intr_mask will be
2219 * restored later when the port is thawed.
2220 *
2221 * Note that during initialization, the port is marked as
2222 * frozen since the irq handler is not yet registered.
2223 */
2224 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2225 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2226 }
2227
ahci_pmp_detach(struct ata_port * ap)2228 static void ahci_pmp_detach(struct ata_port *ap)
2229 {
2230 void __iomem *port_mmio = ahci_port_base(ap);
2231 struct ahci_port_priv *pp = ap->private_data;
2232 u32 cmd;
2233
2234 ahci_disable_fbs(ap);
2235
2236 cmd = readl(port_mmio + PORT_CMD);
2237 cmd &= ~PORT_CMD_PMP;
2238 writel(cmd, port_mmio + PORT_CMD);
2239
2240 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2241
2242 /* see comment above in ahci_pmp_attach() */
2243 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2244 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2245 }
2246
ahci_port_resume(struct ata_port * ap)2247 int ahci_port_resume(struct ata_port *ap)
2248 {
2249 ahci_power_up(ap);
2250 ahci_start_port(ap);
2251
2252 if (sata_pmp_attached(ap))
2253 ahci_pmp_attach(ap);
2254 else
2255 ahci_pmp_detach(ap);
2256
2257 return 0;
2258 }
2259 EXPORT_SYMBOL_GPL(ahci_port_resume);
2260
2261 #ifdef CONFIG_PM
ahci_port_suspend(struct ata_port * ap,pm_message_t mesg)2262 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2263 {
2264 const char *emsg = NULL;
2265 int rc;
2266
2267 rc = ahci_deinit_port(ap, &emsg);
2268 if (rc == 0)
2269 ahci_power_down(ap);
2270 else {
2271 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2272 ata_port_freeze(ap);
2273 }
2274
2275 return rc;
2276 }
2277 #endif
2278
ahci_port_start(struct ata_port * ap)2279 static int ahci_port_start(struct ata_port *ap)
2280 {
2281 struct ahci_host_priv *hpriv = ap->host->private_data;
2282 struct device *dev = ap->host->dev;
2283 struct ahci_port_priv *pp;
2284 void *mem;
2285 dma_addr_t mem_dma;
2286 size_t dma_sz, rx_fis_sz;
2287
2288 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2289 if (!pp)
2290 return -ENOMEM;
2291
2292 if (ap->host->n_ports > 1) {
2293 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2294 if (!pp->irq_desc) {
2295 devm_kfree(dev, pp);
2296 return -ENOMEM;
2297 }
2298 snprintf(pp->irq_desc, 8,
2299 "%s%d", dev_driver_string(dev), ap->port_no);
2300 }
2301
2302 /* check FBS capability */
2303 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2304 void __iomem *port_mmio = ahci_port_base(ap);
2305 u32 cmd = readl(port_mmio + PORT_CMD);
2306 if (cmd & PORT_CMD_FBSCP)
2307 pp->fbs_supported = true;
2308 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2309 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2310 ap->port_no);
2311 pp->fbs_supported = true;
2312 } else
2313 dev_warn(dev, "port %d is not capable of FBS\n",
2314 ap->port_no);
2315 }
2316
2317 if (pp->fbs_supported) {
2318 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2319 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2320 } else {
2321 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2322 rx_fis_sz = AHCI_RX_FIS_SZ;
2323 }
2324
2325 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2326 if (!mem)
2327 return -ENOMEM;
2328 memset(mem, 0, dma_sz);
2329
2330 /*
2331 * First item in chunk of DMA memory: 32-slot command table,
2332 * 32 bytes each in size
2333 */
2334 pp->cmd_slot = mem;
2335 pp->cmd_slot_dma = mem_dma;
2336
2337 mem += AHCI_CMD_SLOT_SZ;
2338 mem_dma += AHCI_CMD_SLOT_SZ;
2339
2340 /*
2341 * Second item: Received-FIS area
2342 */
2343 pp->rx_fis = mem;
2344 pp->rx_fis_dma = mem_dma;
2345
2346 mem += rx_fis_sz;
2347 mem_dma += rx_fis_sz;
2348
2349 /*
2350 * Third item: data area for storing a single command
2351 * and its scatter-gather table
2352 */
2353 pp->cmd_tbl = mem;
2354 pp->cmd_tbl_dma = mem_dma;
2355
2356 /*
2357 * Save off initial list of interrupts to be enabled.
2358 * This could be changed later
2359 */
2360 pp->intr_mask = DEF_PORT_IRQ;
2361
2362 /*
2363 * Switch to per-port locking in case each port has its own MSI vector.
2364 */
2365 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2366 spin_lock_init(&pp->lock);
2367 ap->lock = &pp->lock;
2368 }
2369
2370 ap->private_data = pp;
2371
2372 /* engage engines, captain */
2373 return ahci_port_resume(ap);
2374 }
2375
ahci_port_stop(struct ata_port * ap)2376 static void ahci_port_stop(struct ata_port *ap)
2377 {
2378 const char *emsg = NULL;
2379 int rc;
2380
2381 /* de-initialize port */
2382 rc = ahci_deinit_port(ap, &emsg);
2383 if (rc)
2384 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2385 }
2386
ahci_print_info(struct ata_host * host,const char * scc_s)2387 void ahci_print_info(struct ata_host *host, const char *scc_s)
2388 {
2389 struct ahci_host_priv *hpriv = host->private_data;
2390 void __iomem *mmio = hpriv->mmio;
2391 u32 vers, cap, cap2, impl, speed;
2392 const char *speed_s;
2393
2394 vers = readl(mmio + HOST_VERSION);
2395 cap = hpriv->cap;
2396 cap2 = hpriv->cap2;
2397 impl = hpriv->port_map;
2398
2399 speed = (cap >> 20) & 0xf;
2400 if (speed == 1)
2401 speed_s = "1.5";
2402 else if (speed == 2)
2403 speed_s = "3";
2404 else if (speed == 3)
2405 speed_s = "6";
2406 else
2407 speed_s = "?";
2408
2409 dev_info(host->dev,
2410 "AHCI %02x%02x.%02x%02x "
2411 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2412 ,
2413
2414 (vers >> 24) & 0xff,
2415 (vers >> 16) & 0xff,
2416 (vers >> 8) & 0xff,
2417 vers & 0xff,
2418
2419 ((cap >> 8) & 0x1f) + 1,
2420 (cap & 0x1f) + 1,
2421 speed_s,
2422 impl,
2423 scc_s);
2424
2425 dev_info(host->dev,
2426 "flags: "
2427 "%s%s%s%s%s%s%s"
2428 "%s%s%s%s%s%s%s"
2429 "%s%s%s%s%s%s%s"
2430 "%s%s\n"
2431 ,
2432
2433 cap & HOST_CAP_64 ? "64bit " : "",
2434 cap & HOST_CAP_NCQ ? "ncq " : "",
2435 cap & HOST_CAP_SNTF ? "sntf " : "",
2436 cap & HOST_CAP_MPS ? "ilck " : "",
2437 cap & HOST_CAP_SSS ? "stag " : "",
2438 cap & HOST_CAP_ALPM ? "pm " : "",
2439 cap & HOST_CAP_LED ? "led " : "",
2440 cap & HOST_CAP_CLO ? "clo " : "",
2441 cap & HOST_CAP_ONLY ? "only " : "",
2442 cap & HOST_CAP_PMP ? "pmp " : "",
2443 cap & HOST_CAP_FBS ? "fbs " : "",
2444 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2445 cap & HOST_CAP_SSC ? "slum " : "",
2446 cap & HOST_CAP_PART ? "part " : "",
2447 cap & HOST_CAP_CCC ? "ccc " : "",
2448 cap & HOST_CAP_EMS ? "ems " : "",
2449 cap & HOST_CAP_SXS ? "sxs " : "",
2450 cap2 & HOST_CAP2_DESO ? "deso " : "",
2451 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2452 cap2 & HOST_CAP2_SDS ? "sds " : "",
2453 cap2 & HOST_CAP2_APST ? "apst " : "",
2454 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2455 cap2 & HOST_CAP2_BOH ? "boh " : ""
2456 );
2457 }
2458 EXPORT_SYMBOL_GPL(ahci_print_info);
2459
ahci_set_em_messages(struct ahci_host_priv * hpriv,struct ata_port_info * pi)2460 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2461 struct ata_port_info *pi)
2462 {
2463 u8 messages;
2464 void __iomem *mmio = hpriv->mmio;
2465 u32 em_loc = readl(mmio + HOST_EM_LOC);
2466 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2467
2468 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2469 return;
2470
2471 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2472
2473 if (messages) {
2474 /* store em_loc */
2475 hpriv->em_loc = ((em_loc >> 16) * 4);
2476 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2477 hpriv->em_msg_type = messages;
2478 pi->flags |= ATA_FLAG_EM;
2479 if (!(em_ctl & EM_CTL_ALHD))
2480 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2481 }
2482 }
2483 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2484
ahci_host_activate_multi_irqs(struct ata_host * host,int irq,struct scsi_host_template * sht)2485 static int ahci_host_activate_multi_irqs(struct ata_host *host, int irq,
2486 struct scsi_host_template *sht)
2487 {
2488 int i, rc;
2489
2490 rc = ata_host_start(host);
2491 if (rc)
2492 return rc;
2493 /*
2494 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2495 * allocated. That is one MSI per port, starting from @irq.
2496 */
2497 for (i = 0; i < host->n_ports; i++) {
2498 struct ahci_port_priv *pp = host->ports[i]->private_data;
2499
2500 /* Do not receive interrupts sent by dummy ports */
2501 if (!pp) {
2502 disable_irq(irq + i);
2503 continue;
2504 }
2505
2506 rc = devm_request_threaded_irq(host->dev, irq + i,
2507 ahci_multi_irqs_intr,
2508 ahci_port_thread_fn, 0,
2509 pp->irq_desc, host->ports[i]);
2510 if (rc)
2511 return rc;
2512 ata_port_desc(host->ports[i], "irq %d", irq + i);
2513 }
2514 return ata_host_register(host, sht);
2515 }
2516
2517 /**
2518 * ahci_host_activate - start AHCI host, request IRQs and register it
2519 * @host: target ATA host
2520 * @sht: scsi_host_template to use when registering the host
2521 *
2522 * LOCKING:
2523 * Inherited from calling layer (may sleep).
2524 *
2525 * RETURNS:
2526 * 0 on success, -errno otherwise.
2527 */
ahci_host_activate(struct ata_host * host,struct scsi_host_template * sht)2528 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2529 {
2530 struct ahci_host_priv *hpriv = host->private_data;
2531 int irq = hpriv->irq;
2532 int rc;
2533
2534 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
2535 rc = ahci_host_activate_multi_irqs(host, irq, sht);
2536 else if (hpriv->flags & AHCI_HFLAG_EDGE_IRQ)
2537 rc = ata_host_activate(host, irq, ahci_single_edge_irq_intr,
2538 IRQF_SHARED, sht);
2539 else
2540 rc = ata_host_activate(host, irq, ahci_single_level_irq_intr,
2541 IRQF_SHARED, sht);
2542 return rc;
2543 }
2544 EXPORT_SYMBOL_GPL(ahci_host_activate);
2545
2546 MODULE_AUTHOR("Jeff Garzik");
2547 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2548 MODULE_LICENSE("GPL");
2549