1 /*
2 * AMD CPU Microcode Update Driver for Linux
3 *
4 * This driver allows to upgrade microcode on F10h AMD
5 * CPUs and later.
6 *
7 * Copyright (C) 2008-2011 Advanced Micro Devices Inc.
8 *
9 * Author: Peter Oruba <peter.oruba@amd.com>
10 *
11 * Based on work by:
12 * Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
13 *
14 * early loader:
15 * Copyright (C) 2013 Advanced Micro Devices, Inc.
16 *
17 * Author: Jacob Shin <jacob.shin@amd.com>
18 * Fixes: Borislav Petkov <bp@suse.de>
19 *
20 * Licensed under the terms of the GNU General Public
21 * License version 2. See file COPYING for details.
22 */
23 #define pr_fmt(fmt) "microcode: " fmt
24
25 #include <linux/earlycpio.h>
26 #include <linux/firmware.h>
27 #include <linux/uaccess.h>
28 #include <linux/vmalloc.h>
29 #include <linux/initrd.h>
30 #include <linux/kernel.h>
31 #include <linux/pci.h>
32
33 #include <asm/microcode_amd.h>
34 #include <asm/microcode.h>
35 #include <asm/processor.h>
36 #include <asm/setup.h>
37 #include <asm/cpu.h>
38 #include <asm/msr.h>
39
40 static struct equiv_cpu_entry *equiv_cpu_table;
41
42 struct ucode_patch {
43 struct list_head plist;
44 void *data;
45 u32 patch_id;
46 u16 equiv_cpu;
47 };
48
49 static LIST_HEAD(pcache);
50
51 /*
52 * This points to the current valid container of microcode patches which we will
53 * save from the initrd before jettisoning its contents.
54 */
55 static u8 *container;
56 static size_t container_size;
57
58 static u32 ucode_new_rev;
59 u8 amd_ucode_patch[PATCH_MAX_SIZE];
60 static u16 this_equiv_id;
61
62 static struct cpio_data ucode_cpio;
63
64 /*
65 * Microcode patch container file is prepended to the initrd in cpio format.
66 * See Documentation/x86/early-microcode.txt
67 */
68 static __initdata char ucode_path[] = "kernel/x86/microcode/AuthenticAMD.bin";
69
find_ucode_in_initrd(void)70 static struct cpio_data __init find_ucode_in_initrd(void)
71 {
72 long offset = 0;
73 char *path;
74 void *start;
75 size_t size;
76
77 #ifdef CONFIG_X86_32
78 struct boot_params *p;
79
80 /*
81 * On 32-bit, early load occurs before paging is turned on so we need
82 * to use physical addresses.
83 */
84 p = (struct boot_params *)__pa_nodebug(&boot_params);
85 path = (char *)__pa_nodebug(ucode_path);
86 start = (void *)p->hdr.ramdisk_image;
87 size = p->hdr.ramdisk_size;
88 #else
89 path = ucode_path;
90 start = (void *)(boot_params.hdr.ramdisk_image + PAGE_OFFSET);
91 size = boot_params.hdr.ramdisk_size;
92 #endif
93
94 return find_cpio_data(path, start, size, &offset);
95 }
96
compute_container_size(u8 * data,u32 total_size)97 static size_t compute_container_size(u8 *data, u32 total_size)
98 {
99 size_t size = 0;
100 u32 *header = (u32 *)data;
101
102 if (header[0] != UCODE_MAGIC ||
103 header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
104 header[2] == 0) /* size */
105 return size;
106
107 size = header[2] + CONTAINER_HDR_SZ;
108 total_size -= size;
109 data += size;
110
111 while (total_size) {
112 u16 patch_size;
113
114 header = (u32 *)data;
115
116 if (header[0] != UCODE_UCODE_TYPE)
117 break;
118
119 /*
120 * Sanity-check patch size.
121 */
122 patch_size = header[1];
123 if (patch_size > PATCH_MAX_SIZE)
124 break;
125
126 size += patch_size + SECTION_HDR_SIZE;
127 data += patch_size + SECTION_HDR_SIZE;
128 total_size -= patch_size + SECTION_HDR_SIZE;
129 }
130
131 return size;
132 }
133
134 static enum ucode_state
135 load_microcode_amd(bool save, u8 family, const u8 *data, size_t size);
136
137 /*
138 * Early load occurs before we can vmalloc(). So we look for the microcode
139 * patch container file in initrd, traverse equivalent cpu table, look for a
140 * matching microcode patch, and update, all in initrd memory in place.
141 * When vmalloc() is available for use later -- on 64-bit during first AP load,
142 * and on 32-bit during save_microcode_in_initrd_amd() -- we can call
143 * load_microcode_amd() to save equivalent cpu table and microcode patches in
144 * kernel heap memory.
145 */
apply_ucode_in_initrd(void * ucode,size_t size,bool save_patch)146 static void apply_ucode_in_initrd(void *ucode, size_t size, bool save_patch)
147 {
148 struct equiv_cpu_entry *eq;
149 size_t *cont_sz;
150 u32 *header;
151 u8 *data, **cont;
152 u8 (*patch)[PATCH_MAX_SIZE];
153 u16 eq_id = 0;
154 int offset, left;
155 u32 rev, eax, ebx, ecx, edx;
156 u32 *new_rev;
157
158 #ifdef CONFIG_X86_32
159 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
160 cont_sz = (size_t *)__pa_nodebug(&container_size);
161 cont = (u8 **)__pa_nodebug(&container);
162 patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch);
163 #else
164 new_rev = &ucode_new_rev;
165 cont_sz = &container_size;
166 cont = &container;
167 patch = &amd_ucode_patch;
168 #endif
169
170 data = ucode;
171 left = size;
172 header = (u32 *)data;
173
174 /* find equiv cpu table */
175 if (header[0] != UCODE_MAGIC ||
176 header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
177 header[2] == 0) /* size */
178 return;
179
180 eax = 0x00000001;
181 ecx = 0;
182 native_cpuid(&eax, &ebx, &ecx, &edx);
183
184 while (left > 0) {
185 eq = (struct equiv_cpu_entry *)(data + CONTAINER_HDR_SZ);
186
187 *cont = data;
188
189 /* Advance past the container header */
190 offset = header[2] + CONTAINER_HDR_SZ;
191 data += offset;
192 left -= offset;
193
194 eq_id = find_equiv_id(eq, eax);
195 if (eq_id) {
196 this_equiv_id = eq_id;
197 *cont_sz = compute_container_size(*cont, left + offset);
198
199 /*
200 * truncate how much we need to iterate over in the
201 * ucode update loop below
202 */
203 left = *cont_sz - offset;
204 break;
205 }
206
207 /*
208 * support multiple container files appended together. if this
209 * one does not have a matching equivalent cpu entry, we fast
210 * forward to the next container file.
211 */
212 while (left > 0) {
213 header = (u32 *)data;
214 if (header[0] == UCODE_MAGIC &&
215 header[1] == UCODE_EQUIV_CPU_TABLE_TYPE)
216 break;
217
218 offset = header[1] + SECTION_HDR_SIZE;
219 data += offset;
220 left -= offset;
221 }
222
223 /* mark where the next microcode container file starts */
224 offset = data - (u8 *)ucode;
225 ucode = data;
226 }
227
228 if (!eq_id) {
229 *cont = NULL;
230 *cont_sz = 0;
231 return;
232 }
233
234 if (check_current_patch_level(&rev, true))
235 return;
236
237 while (left > 0) {
238 struct microcode_amd *mc;
239
240 header = (u32 *)data;
241 if (header[0] != UCODE_UCODE_TYPE || /* type */
242 header[1] == 0) /* size */
243 break;
244
245 mc = (struct microcode_amd *)(data + SECTION_HDR_SIZE);
246
247 if (eq_id == mc->hdr.processor_rev_id && rev < mc->hdr.patch_id) {
248
249 if (!__apply_microcode_amd(mc)) {
250 rev = mc->hdr.patch_id;
251 *new_rev = rev;
252
253 if (save_patch)
254 memcpy(patch, mc,
255 min_t(u32, header[1], PATCH_MAX_SIZE));
256 }
257 }
258
259 offset = header[1] + SECTION_HDR_SIZE;
260 data += offset;
261 left -= offset;
262 }
263 }
264
load_builtin_amd_microcode(struct cpio_data * cp,unsigned int family)265 static bool __init load_builtin_amd_microcode(struct cpio_data *cp,
266 unsigned int family)
267 {
268 #ifdef CONFIG_X86_64
269 char fw_name[36] = "amd-ucode/microcode_amd.bin";
270
271 if (family >= 0x15)
272 snprintf(fw_name, sizeof(fw_name),
273 "amd-ucode/microcode_amd_fam%.2xh.bin", family);
274
275 return get_builtin_firmware(cp, fw_name);
276 #else
277 return false;
278 #endif
279 }
280
load_ucode_amd_bsp(unsigned int family)281 void __init load_ucode_amd_bsp(unsigned int family)
282 {
283 struct cpio_data cp;
284 void **data;
285 size_t *size;
286
287 #ifdef CONFIG_X86_32
288 data = (void **)__pa_nodebug(&ucode_cpio.data);
289 size = (size_t *)__pa_nodebug(&ucode_cpio.size);
290 #else
291 data = &ucode_cpio.data;
292 size = &ucode_cpio.size;
293 #endif
294
295 cp = find_ucode_in_initrd();
296 if (!cp.data) {
297 if (!load_builtin_amd_microcode(&cp, family))
298 return;
299 }
300
301 *data = cp.data;
302 *size = cp.size;
303
304 apply_ucode_in_initrd(cp.data, cp.size, true);
305 }
306
307 #ifdef CONFIG_X86_32
308 /*
309 * On 32-bit, since AP's early load occurs before paging is turned on, we
310 * cannot traverse cpu_equiv_table and pcache in kernel heap memory. So during
311 * cold boot, AP will apply_ucode_in_initrd() just like the BSP. During
312 * save_microcode_in_initrd_amd() BSP's patch is copied to amd_ucode_patch,
313 * which is used upon resume from suspend.
314 */
load_ucode_amd_ap(void)315 void load_ucode_amd_ap(void)
316 {
317 struct microcode_amd *mc;
318 size_t *usize;
319 void **ucode;
320
321 mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch);
322 if (mc->hdr.patch_id && mc->hdr.processor_rev_id) {
323 __apply_microcode_amd(mc);
324 return;
325 }
326
327 ucode = (void *)__pa_nodebug(&container);
328 usize = (size_t *)__pa_nodebug(&container_size);
329
330 if (!*ucode || !*usize)
331 return;
332
333 apply_ucode_in_initrd(*ucode, *usize, false);
334 }
335
collect_cpu_sig_on_bsp(void * arg)336 static void __init collect_cpu_sig_on_bsp(void *arg)
337 {
338 unsigned int cpu = smp_processor_id();
339 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
340
341 uci->cpu_sig.sig = cpuid_eax(0x00000001);
342 }
343
get_bsp_sig(void)344 static void __init get_bsp_sig(void)
345 {
346 unsigned int bsp = boot_cpu_data.cpu_index;
347 struct ucode_cpu_info *uci = ucode_cpu_info + bsp;
348
349 if (!uci->cpu_sig.sig)
350 smp_call_function_single(bsp, collect_cpu_sig_on_bsp, NULL, 1);
351 }
352 #else
load_ucode_amd_ap(void)353 void load_ucode_amd_ap(void)
354 {
355 unsigned int cpu = smp_processor_id();
356 struct equiv_cpu_entry *eq;
357 struct microcode_amd *mc;
358 u32 rev, eax;
359 u16 eq_id;
360
361 /* Exit if called on the BSP. */
362 if (!cpu)
363 return;
364
365 if (!container)
366 return;
367
368 /*
369 * 64-bit runs with paging enabled, thus early==false.
370 */
371 if (check_current_patch_level(&rev, false))
372 return;
373
374 eax = cpuid_eax(0x00000001);
375 eq = (struct equiv_cpu_entry *)(container + CONTAINER_HDR_SZ);
376
377 eq_id = find_equiv_id(eq, eax);
378 if (!eq_id)
379 return;
380
381 if (eq_id == this_equiv_id) {
382 mc = (struct microcode_amd *)amd_ucode_patch;
383
384 if (mc && rev < mc->hdr.patch_id) {
385 if (!__apply_microcode_amd(mc))
386 ucode_new_rev = mc->hdr.patch_id;
387 }
388
389 } else {
390 if (!ucode_cpio.data)
391 return;
392
393 /*
394 * AP has a different equivalence ID than BSP, looks like
395 * mixed-steppings silicon so go through the ucode blob anew.
396 */
397 apply_ucode_in_initrd(ucode_cpio.data, ucode_cpio.size, false);
398 }
399 }
400 #endif
401
save_microcode_in_initrd_amd(void)402 int __init save_microcode_in_initrd_amd(void)
403 {
404 unsigned long cont;
405 int retval = 0;
406 enum ucode_state ret;
407 u8 *cont_va;
408 u32 eax;
409
410 if (!container)
411 return -EINVAL;
412
413 #ifdef CONFIG_X86_32
414 get_bsp_sig();
415 cont = (unsigned long)container;
416 cont_va = __va(container);
417 #else
418 /*
419 * We need the physical address of the container for both bitness since
420 * boot_params.hdr.ramdisk_image is a physical address.
421 */
422 cont = __pa(container);
423 cont_va = container;
424 #endif
425
426 /*
427 * Take into account the fact that the ramdisk might get relocated and
428 * therefore we need to recompute the container's position in virtual
429 * memory space.
430 */
431 if (relocated_ramdisk)
432 container = (u8 *)(__va(relocated_ramdisk) +
433 (cont - boot_params.hdr.ramdisk_image));
434 else
435 container = cont_va;
436
437 if (ucode_new_rev)
438 pr_info("microcode: updated early to new patch_level=0x%08x\n",
439 ucode_new_rev);
440
441 eax = cpuid_eax(0x00000001);
442 eax = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
443
444 ret = load_microcode_amd(true, eax, container, container_size);
445 if (ret != UCODE_OK)
446 retval = -EINVAL;
447
448 /*
449 * This will be freed any msec now, stash patches for the current
450 * family and switch to patch cache for cpu hotplug, etc later.
451 */
452 container = NULL;
453 container_size = 0;
454
455 return retval;
456 }
457
reload_ucode_amd(void)458 void reload_ucode_amd(void)
459 {
460 struct microcode_amd *mc;
461 u32 rev;
462
463 /*
464 * early==false because this is a syscore ->resume path and by
465 * that time paging is long enabled.
466 */
467 if (check_current_patch_level(&rev, false))
468 return;
469
470 mc = (struct microcode_amd *)amd_ucode_patch;
471
472 if (mc && rev < mc->hdr.patch_id) {
473 if (!__apply_microcode_amd(mc)) {
474 ucode_new_rev = mc->hdr.patch_id;
475 pr_info("microcode: reload patch_level=0x%08x\n",
476 ucode_new_rev);
477 }
478 }
479 }
__find_equiv_id(unsigned int cpu)480 static u16 __find_equiv_id(unsigned int cpu)
481 {
482 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
483 return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig);
484 }
485
find_cpu_family_by_equiv_cpu(u16 equiv_cpu)486 static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
487 {
488 int i = 0;
489
490 BUG_ON(!equiv_cpu_table);
491
492 while (equiv_cpu_table[i].equiv_cpu != 0) {
493 if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
494 return equiv_cpu_table[i].installed_cpu;
495 i++;
496 }
497 return 0;
498 }
499
500 /*
501 * a small, trivial cache of per-family ucode patches
502 */
cache_find_patch(u16 equiv_cpu)503 static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
504 {
505 struct ucode_patch *p;
506
507 list_for_each_entry(p, &pcache, plist)
508 if (p->equiv_cpu == equiv_cpu)
509 return p;
510 return NULL;
511 }
512
update_cache(struct ucode_patch * new_patch)513 static void update_cache(struct ucode_patch *new_patch)
514 {
515 struct ucode_patch *p;
516
517 list_for_each_entry(p, &pcache, plist) {
518 if (p->equiv_cpu == new_patch->equiv_cpu) {
519 if (p->patch_id >= new_patch->patch_id)
520 /* we already have the latest patch */
521 return;
522
523 list_replace(&p->plist, &new_patch->plist);
524 kfree(p->data);
525 kfree(p);
526 return;
527 }
528 }
529 /* no patch found, add it */
530 list_add_tail(&new_patch->plist, &pcache);
531 }
532
free_cache(void)533 static void free_cache(void)
534 {
535 struct ucode_patch *p, *tmp;
536
537 list_for_each_entry_safe(p, tmp, &pcache, plist) {
538 __list_del(p->plist.prev, p->plist.next);
539 kfree(p->data);
540 kfree(p);
541 }
542 }
543
find_patch(unsigned int cpu)544 static struct ucode_patch *find_patch(unsigned int cpu)
545 {
546 u16 equiv_id;
547
548 equiv_id = __find_equiv_id(cpu);
549 if (!equiv_id)
550 return NULL;
551
552 return cache_find_patch(equiv_id);
553 }
554
collect_cpu_info_amd(int cpu,struct cpu_signature * csig)555 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
556 {
557 struct cpuinfo_x86 *c = &cpu_data(cpu);
558 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
559 struct ucode_patch *p;
560
561 csig->sig = cpuid_eax(0x00000001);
562 csig->rev = c->microcode;
563
564 /*
565 * a patch could have been loaded early, set uci->mc so that
566 * mc_bp_resume() can call apply_microcode()
567 */
568 p = find_patch(cpu);
569 if (p && (p->patch_id == csig->rev))
570 uci->mc = p->data;
571
572 pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
573
574 return 0;
575 }
576
verify_patch_size(u8 family,u32 patch_size,unsigned int size)577 static unsigned int verify_patch_size(u8 family, u32 patch_size,
578 unsigned int size)
579 {
580 u32 max_size;
581
582 #define F1XH_MPB_MAX_SIZE 2048
583 #define F14H_MPB_MAX_SIZE 1824
584 #define F15H_MPB_MAX_SIZE 4096
585 #define F16H_MPB_MAX_SIZE 3458
586 #define F17H_MPB_MAX_SIZE 3200
587
588 switch (family) {
589 case 0x14:
590 max_size = F14H_MPB_MAX_SIZE;
591 break;
592 case 0x15:
593 max_size = F15H_MPB_MAX_SIZE;
594 break;
595 case 0x16:
596 max_size = F16H_MPB_MAX_SIZE;
597 break;
598 case 0x17:
599 max_size = F17H_MPB_MAX_SIZE;
600 break;
601 default:
602 max_size = F1XH_MPB_MAX_SIZE;
603 break;
604 }
605
606 if (patch_size > min_t(u32, size, max_size)) {
607 pr_err("patch size mismatch\n");
608 return 0;
609 }
610
611 return patch_size;
612 }
613
614 /*
615 * Those patch levels cannot be updated to newer ones and thus should be final.
616 */
617 static u32 final_levels[] = {
618 0x01000098,
619 0x0100009f,
620 0x010000af,
621 0, /* T-101 terminator */
622 };
623
624 /*
625 * Check the current patch level on this CPU.
626 *
627 * @rev: Use it to return the patch level. It is set to 0 in the case of
628 * error.
629 *
630 * Returns:
631 * - true: if update should stop
632 * - false: otherwise
633 */
check_current_patch_level(u32 * rev,bool early)634 bool check_current_patch_level(u32 *rev, bool early)
635 {
636 u32 lvl, dummy, i;
637 bool ret = false;
638 u32 *levels;
639
640 native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy);
641
642 if (IS_ENABLED(CONFIG_X86_32) && early)
643 levels = (u32 *)__pa_nodebug(&final_levels);
644 else
645 levels = final_levels;
646
647 for (i = 0; levels[i]; i++) {
648 if (lvl == levels[i]) {
649 lvl = 0;
650 ret = true;
651 break;
652 }
653 }
654
655 if (rev)
656 *rev = lvl;
657
658 return ret;
659 }
660
__apply_microcode_amd(struct microcode_amd * mc_amd)661 int __apply_microcode_amd(struct microcode_amd *mc_amd)
662 {
663 u32 rev, dummy;
664
665 native_wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
666
667 /* verify patch application was successful */
668 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
669 if (rev != mc_amd->hdr.patch_id)
670 return -1;
671
672 return 0;
673 }
674
apply_microcode_amd(int cpu)675 int apply_microcode_amd(int cpu)
676 {
677 struct cpuinfo_x86 *c = &cpu_data(cpu);
678 struct microcode_amd *mc_amd;
679 struct ucode_cpu_info *uci;
680 struct ucode_patch *p;
681 u32 rev;
682
683 BUG_ON(raw_smp_processor_id() != cpu);
684
685 uci = ucode_cpu_info + cpu;
686
687 p = find_patch(cpu);
688 if (!p)
689 return 0;
690
691 mc_amd = p->data;
692 uci->mc = p->data;
693
694 if (check_current_patch_level(&rev, false))
695 return -1;
696
697 /* need to apply patch? */
698 if (rev >= mc_amd->hdr.patch_id)
699 goto out;
700
701 if (__apply_microcode_amd(mc_amd)) {
702 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
703 cpu, mc_amd->hdr.patch_id);
704 return -1;
705 }
706
707 rev = mc_amd->hdr.patch_id;
708
709 pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
710
711 out:
712 uci->cpu_sig.rev = rev;
713 c->microcode = rev;
714
715 /* Update boot_cpu_data's revision too, if we're on the BSP: */
716 if (c->cpu_index == boot_cpu_data.cpu_index)
717 boot_cpu_data.microcode = rev;
718
719 return 0;
720 }
721
install_equiv_cpu_table(const u8 * buf)722 static int install_equiv_cpu_table(const u8 *buf)
723 {
724 unsigned int *ibuf = (unsigned int *)buf;
725 unsigned int type = ibuf[1];
726 unsigned int size = ibuf[2];
727
728 if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
729 pr_err("empty section/"
730 "invalid type field in container file section header\n");
731 return -EINVAL;
732 }
733
734 equiv_cpu_table = vmalloc(size);
735 if (!equiv_cpu_table) {
736 pr_err("failed to allocate equivalent CPU table\n");
737 return -ENOMEM;
738 }
739
740 memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
741
742 /* add header length */
743 return size + CONTAINER_HDR_SZ;
744 }
745
free_equiv_cpu_table(void)746 static void free_equiv_cpu_table(void)
747 {
748 vfree(equiv_cpu_table);
749 equiv_cpu_table = NULL;
750 }
751
cleanup(void)752 static void cleanup(void)
753 {
754 free_equiv_cpu_table();
755 free_cache();
756 }
757
758 /*
759 * We return the current size even if some of the checks failed so that
760 * we can skip over the next patch. If we return a negative value, we
761 * signal a grave error like a memory allocation has failed and the
762 * driver cannot continue functioning normally. In such cases, we tear
763 * down everything we've used up so far and exit.
764 */
verify_and_add_patch(u8 family,u8 * fw,unsigned int leftover)765 static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover)
766 {
767 struct microcode_header_amd *mc_hdr;
768 struct ucode_patch *patch;
769 unsigned int patch_size, crnt_size, ret;
770 u32 proc_fam;
771 u16 proc_id;
772
773 patch_size = *(u32 *)(fw + 4);
774 crnt_size = patch_size + SECTION_HDR_SIZE;
775 mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
776 proc_id = mc_hdr->processor_rev_id;
777
778 proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
779 if (!proc_fam) {
780 pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
781 return crnt_size;
782 }
783
784 /* check if patch is for the current family */
785 proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
786 if (proc_fam != family)
787 return crnt_size;
788
789 if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
790 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
791 mc_hdr->patch_id);
792 return crnt_size;
793 }
794
795 ret = verify_patch_size(family, patch_size, leftover);
796 if (!ret) {
797 pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
798 return crnt_size;
799 }
800
801 patch = kzalloc(sizeof(*patch), GFP_KERNEL);
802 if (!patch) {
803 pr_err("Patch allocation failure.\n");
804 return -EINVAL;
805 }
806
807 patch->data = kzalloc(patch_size, GFP_KERNEL);
808 if (!patch->data) {
809 pr_err("Patch data allocation failure.\n");
810 kfree(patch);
811 return -EINVAL;
812 }
813
814 /* All looks ok, copy patch... */
815 memcpy(patch->data, fw + SECTION_HDR_SIZE, patch_size);
816 INIT_LIST_HEAD(&patch->plist);
817 patch->patch_id = mc_hdr->patch_id;
818 patch->equiv_cpu = proc_id;
819
820 pr_debug("%s: Added patch_id: 0x%08x, proc_id: 0x%04x\n",
821 __func__, patch->patch_id, proc_id);
822
823 /* ... and add to cache. */
824 update_cache(patch);
825
826 return crnt_size;
827 }
828
__load_microcode_amd(u8 family,const u8 * data,size_t size)829 static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
830 size_t size)
831 {
832 enum ucode_state ret = UCODE_ERROR;
833 unsigned int leftover;
834 u8 *fw = (u8 *)data;
835 int crnt_size = 0;
836 int offset;
837
838 offset = install_equiv_cpu_table(data);
839 if (offset < 0) {
840 pr_err("failed to create equivalent cpu table\n");
841 return ret;
842 }
843 fw += offset;
844 leftover = size - offset;
845
846 if (*(u32 *)fw != UCODE_UCODE_TYPE) {
847 pr_err("invalid type field in container file section header\n");
848 free_equiv_cpu_table();
849 return ret;
850 }
851
852 while (leftover) {
853 crnt_size = verify_and_add_patch(family, fw, leftover);
854 if (crnt_size < 0)
855 return ret;
856
857 fw += crnt_size;
858 leftover -= crnt_size;
859 }
860
861 return UCODE_OK;
862 }
863
864 static enum ucode_state
load_microcode_amd(bool save,u8 family,const u8 * data,size_t size)865 load_microcode_amd(bool save, u8 family, const u8 *data, size_t size)
866 {
867 enum ucode_state ret;
868
869 /* free old equiv table */
870 free_equiv_cpu_table();
871
872 ret = __load_microcode_amd(family, data, size);
873
874 if (ret != UCODE_OK)
875 cleanup();
876
877 #ifdef CONFIG_X86_32
878 /* save BSP's matching patch for early load */
879 if (save) {
880 struct ucode_patch *p = find_patch(0);
881 if (p) {
882 memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
883 memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data),
884 PATCH_MAX_SIZE));
885 }
886 }
887 #endif
888 return ret;
889 }
890
891 /*
892 * AMD microcode firmware naming convention, up to family 15h they are in
893 * the legacy file:
894 *
895 * amd-ucode/microcode_amd.bin
896 *
897 * This legacy file is always smaller than 2K in size.
898 *
899 * Beginning with family 15h, they are in family-specific firmware files:
900 *
901 * amd-ucode/microcode_amd_fam15h.bin
902 * amd-ucode/microcode_amd_fam16h.bin
903 * ...
904 *
905 * These might be larger than 2K.
906 */
request_microcode_amd(int cpu,struct device * device,bool refresh_fw)907 static enum ucode_state request_microcode_amd(int cpu, struct device *device,
908 bool refresh_fw)
909 {
910 char fw_name[36] = "amd-ucode/microcode_amd.bin";
911 struct cpuinfo_x86 *c = &cpu_data(cpu);
912 bool bsp = c->cpu_index == boot_cpu_data.cpu_index;
913 enum ucode_state ret = UCODE_NFOUND;
914 const struct firmware *fw;
915
916 /* reload ucode container only on the boot cpu */
917 if (!refresh_fw || !bsp)
918 return UCODE_OK;
919
920 if (c->x86 >= 0x15)
921 snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
922
923 if (request_firmware_direct(&fw, (const char *)fw_name, device)) {
924 pr_debug("failed to load file %s\n", fw_name);
925 goto out;
926 }
927
928 ret = UCODE_ERROR;
929 if (*(u32 *)fw->data != UCODE_MAGIC) {
930 pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
931 goto fw_release;
932 }
933
934 ret = load_microcode_amd(bsp, c->x86, fw->data, fw->size);
935
936 fw_release:
937 release_firmware(fw);
938
939 out:
940 return ret;
941 }
942
943 static enum ucode_state
request_microcode_user(int cpu,const void __user * buf,size_t size)944 request_microcode_user(int cpu, const void __user *buf, size_t size)
945 {
946 return UCODE_ERROR;
947 }
948
microcode_fini_cpu_amd(int cpu)949 static void microcode_fini_cpu_amd(int cpu)
950 {
951 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
952
953 uci->mc = NULL;
954 }
955
956 static struct microcode_ops microcode_amd_ops = {
957 .request_microcode_user = request_microcode_user,
958 .request_microcode_fw = request_microcode_amd,
959 .collect_cpu_info = collect_cpu_info_amd,
960 .apply_microcode = apply_microcode_amd,
961 .microcode_fini_cpu = microcode_fini_cpu_amd,
962 };
963
init_amd_microcode(void)964 struct microcode_ops * __init init_amd_microcode(void)
965 {
966 struct cpuinfo_x86 *c = &boot_cpu_data;
967
968 if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
969 pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
970 return NULL;
971 }
972
973 return µcode_amd_ops;
974 }
975
exit_amd_microcode(void)976 void __exit exit_amd_microcode(void)
977 {
978 cleanup();
979 }
980