1 /*
2 * Copyright © 2007 David Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * David Airlie
25 */
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 #include <linux/fb.h>
29
30 #include <drm/drmP.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/amdgpu_drm.h>
34 #include "amdgpu.h"
35 #include "cikd.h"
36
37 #include <drm/drm_fb_helper.h>
38
39 #include <linux/vga_switcheroo.h>
40
41 /* object hierarchy -
42 this contains a helper + a amdgpu fb
43 the helper contains a pointer to amdgpu framebuffer baseclass.
44 */
45 struct amdgpu_fbdev {
46 struct drm_fb_helper helper;
47 struct amdgpu_framebuffer rfb;
48 struct list_head fbdev_list;
49 struct amdgpu_device *adev;
50 };
51
52 static struct fb_ops amdgpufb_ops = {
53 .owner = THIS_MODULE,
54 .fb_check_var = drm_fb_helper_check_var,
55 .fb_set_par = drm_fb_helper_set_par,
56 .fb_fillrect = drm_fb_helper_cfb_fillrect,
57 .fb_copyarea = drm_fb_helper_cfb_copyarea,
58 .fb_imageblit = drm_fb_helper_cfb_imageblit,
59 .fb_pan_display = drm_fb_helper_pan_display,
60 .fb_blank = drm_fb_helper_blank,
61 .fb_setcmap = drm_fb_helper_setcmap,
62 .fb_debug_enter = drm_fb_helper_debug_enter,
63 .fb_debug_leave = drm_fb_helper_debug_leave,
64 };
65
66
amdgpu_align_pitch(struct amdgpu_device * adev,int width,int bpp,bool tiled)67 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled)
68 {
69 int aligned = width;
70 int pitch_mask = 0;
71
72 switch (bpp / 8) {
73 case 1:
74 pitch_mask = 255;
75 break;
76 case 2:
77 pitch_mask = 127;
78 break;
79 case 3:
80 case 4:
81 pitch_mask = 63;
82 break;
83 }
84
85 aligned += pitch_mask;
86 aligned &= ~pitch_mask;
87 return aligned;
88 }
89
amdgpufb_destroy_pinned_object(struct drm_gem_object * gobj)90 static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
91 {
92 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(gobj);
93 int ret;
94
95 ret = amdgpu_bo_reserve(rbo, false);
96 if (likely(ret == 0)) {
97 amdgpu_bo_kunmap(rbo);
98 amdgpu_bo_unpin(rbo);
99 amdgpu_bo_unreserve(rbo);
100 }
101 drm_gem_object_unreference_unlocked(gobj);
102 }
103
amdgpufb_create_pinned_object(struct amdgpu_fbdev * rfbdev,struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object ** gobj_p)104 static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
105 struct drm_mode_fb_cmd2 *mode_cmd,
106 struct drm_gem_object **gobj_p)
107 {
108 struct amdgpu_device *adev = rfbdev->adev;
109 struct drm_gem_object *gobj = NULL;
110 struct amdgpu_bo *rbo = NULL;
111 bool fb_tiled = false; /* useful for testing */
112 u32 tiling_flags = 0;
113 int ret;
114 int aligned_size, size;
115 int height = mode_cmd->height;
116 u32 bpp, depth;
117
118 drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);
119
120 /* need to align pitch with crtc limits */
121 mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, bpp,
122 fb_tiled) * ((bpp + 1) / 8);
123
124 height = ALIGN(mode_cmd->height, 8);
125 size = mode_cmd->pitches[0] * height;
126 aligned_size = ALIGN(size, PAGE_SIZE);
127 ret = amdgpu_gem_object_create(adev, aligned_size, 0,
128 AMDGPU_GEM_DOMAIN_VRAM,
129 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
130 true, &gobj);
131 if (ret) {
132 printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
133 aligned_size);
134 return -ENOMEM;
135 }
136 rbo = gem_to_amdgpu_bo(gobj);
137
138 if (fb_tiled)
139 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
140
141 ret = amdgpu_bo_reserve(rbo, false);
142 if (unlikely(ret != 0))
143 goto out_unref;
144
145 if (tiling_flags) {
146 ret = amdgpu_bo_set_tiling_flags(rbo,
147 tiling_flags);
148 if (ret)
149 dev_err(adev->dev, "FB failed to set tiling flags\n");
150 }
151
152
153 ret = amdgpu_bo_pin_restricted(rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, NULL);
154 if (ret) {
155 amdgpu_bo_unreserve(rbo);
156 goto out_unref;
157 }
158 ret = amdgpu_bo_kmap(rbo, NULL);
159 amdgpu_bo_unreserve(rbo);
160 if (ret) {
161 goto out_unref;
162 }
163
164 *gobj_p = gobj;
165 return 0;
166 out_unref:
167 amdgpufb_destroy_pinned_object(gobj);
168 *gobj_p = NULL;
169 return ret;
170 }
171
amdgpufb_create(struct drm_fb_helper * helper,struct drm_fb_helper_surface_size * sizes)172 static int amdgpufb_create(struct drm_fb_helper *helper,
173 struct drm_fb_helper_surface_size *sizes)
174 {
175 struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
176 struct amdgpu_device *adev = rfbdev->adev;
177 struct fb_info *info;
178 struct drm_framebuffer *fb = NULL;
179 struct drm_mode_fb_cmd2 mode_cmd;
180 struct drm_gem_object *gobj = NULL;
181 struct amdgpu_bo *rbo = NULL;
182 int ret;
183 unsigned long tmp;
184
185 mode_cmd.width = sizes->surface_width;
186 mode_cmd.height = sizes->surface_height;
187
188 if (sizes->surface_bpp == 24)
189 sizes->surface_bpp = 32;
190
191 mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
192 sizes->surface_depth);
193
194 ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
195 if (ret) {
196 DRM_ERROR("failed to create fbcon object %d\n", ret);
197 return ret;
198 }
199
200 rbo = gem_to_amdgpu_bo(gobj);
201
202 /* okay we have an object now allocate the framebuffer */
203 info = drm_fb_helper_alloc_fbi(helper);
204 if (IS_ERR(info)) {
205 ret = PTR_ERR(info);
206 goto out_unref;
207 }
208
209 info->par = rfbdev;
210 info->skip_vt_switch = true;
211
212 ret = amdgpu_framebuffer_init(adev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
213 if (ret) {
214 DRM_ERROR("failed to initialize framebuffer %d\n", ret);
215 goto out_destroy_fbi;
216 }
217
218 fb = &rfbdev->rfb.base;
219
220 /* setup helper */
221 rfbdev->helper.fb = fb;
222
223 memset_io(rbo->kptr, 0x0, amdgpu_bo_size(rbo));
224
225 strcpy(info->fix.id, "amdgpudrmfb");
226
227 drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
228
229 info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
230 info->fbops = &amdgpufb_ops;
231
232 tmp = amdgpu_bo_gpu_offset(rbo) - adev->mc.vram_start;
233 info->fix.smem_start = adev->mc.aper_base + tmp;
234 info->fix.smem_len = amdgpu_bo_size(rbo);
235 info->screen_base = rbo->kptr;
236 info->screen_size = amdgpu_bo_size(rbo);
237
238 drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
239
240 /* setup aperture base/size for vesafb takeover */
241 info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
242 info->apertures->ranges[0].size = adev->mc.aper_size;
243
244 /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
245
246 if (info->screen_base == NULL) {
247 ret = -ENOSPC;
248 goto out_destroy_fbi;
249 }
250
251 DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
252 DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->mc.aper_base);
253 DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(rbo));
254 DRM_INFO("fb depth is %d\n", fb->depth);
255 DRM_INFO(" pitch is %d\n", fb->pitches[0]);
256
257 vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
258 return 0;
259
260 out_destroy_fbi:
261 drm_fb_helper_release_fbi(helper);
262 out_unref:
263 if (rbo) {
264
265 }
266 if (fb && ret) {
267 drm_gem_object_unreference(gobj);
268 drm_framebuffer_unregister_private(fb);
269 drm_framebuffer_cleanup(fb);
270 kfree(fb);
271 }
272 return ret;
273 }
274
amdgpu_fb_output_poll_changed(struct amdgpu_device * adev)275 void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev)
276 {
277 if (adev->mode_info.rfbdev)
278 drm_fb_helper_hotplug_event(&adev->mode_info.rfbdev->helper);
279 }
280
amdgpu_fbdev_destroy(struct drm_device * dev,struct amdgpu_fbdev * rfbdev)281 static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
282 {
283 struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
284
285 drm_fb_helper_unregister_fbi(&rfbdev->helper);
286 drm_fb_helper_release_fbi(&rfbdev->helper);
287
288 if (rfb->obj) {
289 amdgpufb_destroy_pinned_object(rfb->obj);
290 rfb->obj = NULL;
291 }
292 drm_fb_helper_fini(&rfbdev->helper);
293 drm_framebuffer_unregister_private(&rfb->base);
294 drm_framebuffer_cleanup(&rfb->base);
295
296 return 0;
297 }
298
299 /** Sets the color ramps on behalf of fbcon */
amdgpu_crtc_fb_gamma_set(struct drm_crtc * crtc,u16 red,u16 green,u16 blue,int regno)300 static void amdgpu_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
301 u16 blue, int regno)
302 {
303 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
304
305 amdgpu_crtc->lut_r[regno] = red >> 6;
306 amdgpu_crtc->lut_g[regno] = green >> 6;
307 amdgpu_crtc->lut_b[regno] = blue >> 6;
308 }
309
310 /** Gets the color ramps on behalf of fbcon */
amdgpu_crtc_fb_gamma_get(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,int regno)311 static void amdgpu_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
312 u16 *blue, int regno)
313 {
314 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
315
316 *red = amdgpu_crtc->lut_r[regno] << 6;
317 *green = amdgpu_crtc->lut_g[regno] << 6;
318 *blue = amdgpu_crtc->lut_b[regno] << 6;
319 }
320
321 static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
322 .gamma_set = amdgpu_crtc_fb_gamma_set,
323 .gamma_get = amdgpu_crtc_fb_gamma_get,
324 .fb_probe = amdgpufb_create,
325 };
326
amdgpu_fbdev_init(struct amdgpu_device * adev)327 int amdgpu_fbdev_init(struct amdgpu_device *adev)
328 {
329 struct amdgpu_fbdev *rfbdev;
330 int bpp_sel = 32;
331 int ret;
332
333 /* don't init fbdev on hw without DCE */
334 if (!adev->mode_info.mode_config_initialized)
335 return 0;
336
337 /* select 8 bpp console on low vram cards */
338 if (adev->mc.real_vram_size <= (32*1024*1024))
339 bpp_sel = 8;
340
341 rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
342 if (!rfbdev)
343 return -ENOMEM;
344
345 rfbdev->adev = adev;
346 adev->mode_info.rfbdev = rfbdev;
347
348 drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
349 &amdgpu_fb_helper_funcs);
350
351 ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
352 adev->mode_info.num_crtc,
353 AMDGPUFB_CONN_LIMIT);
354 if (ret) {
355 kfree(rfbdev);
356 return ret;
357 }
358
359 drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
360
361 /* disable all the possible outputs/crtcs before entering KMS mode */
362 drm_helper_disable_unused_functions(adev->ddev);
363
364 drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
365 return 0;
366 }
367
amdgpu_fbdev_fini(struct amdgpu_device * adev)368 void amdgpu_fbdev_fini(struct amdgpu_device *adev)
369 {
370 if (!adev->mode_info.rfbdev)
371 return;
372
373 amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
374 kfree(adev->mode_info.rfbdev);
375 adev->mode_info.rfbdev = NULL;
376 }
377
amdgpu_fbdev_set_suspend(struct amdgpu_device * adev,int state)378 void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
379 {
380 if (adev->mode_info.rfbdev)
381 drm_fb_helper_set_suspend(&adev->mode_info.rfbdev->helper,
382 state);
383 }
384
amdgpu_fbdev_total_size(struct amdgpu_device * adev)385 int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
386 {
387 struct amdgpu_bo *robj;
388 int size = 0;
389
390 if (!adev->mode_info.rfbdev)
391 return 0;
392
393 robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj);
394 size += amdgpu_bo_size(robj);
395 return size;
396 }
397
amdgpu_fbdev_robj_is_fb(struct amdgpu_device * adev,struct amdgpu_bo * robj)398 bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
399 {
400 if (!adev->mode_info.rfbdev)
401 return false;
402 if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj))
403 return true;
404 return false;
405 }
406
amdgpu_fbdev_restore_mode(struct amdgpu_device * adev)407 void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev)
408 {
409 struct amdgpu_fbdev *afbdev = adev->mode_info.rfbdev;
410 struct drm_fb_helper *fb_helper;
411 int ret;
412
413 if (!afbdev)
414 return;
415
416 fb_helper = &afbdev->helper;
417
418 ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
419 if (ret)
420 DRM_DEBUG("failed to restore crtc mode\n");
421 }
422