1 /*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32 #include <ttm/ttm_bo_api.h>
33 #include <ttm/ttm_bo_driver.h>
34 #include <ttm/ttm_placement.h>
35 #include <ttm/ttm_module.h>
36 #include <ttm/ttm_page_alloc.h>
37 #include <drm/drmP.h>
38 #include <drm/amdgpu_drm.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/swiotlb.h>
42 #include <linux/swap.h>
43 #include <linux/pagemap.h>
44 #include <linux/debugfs.h>
45 #include "amdgpu.h"
46 #include "bif/bif_4_1_d.h"
47
48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
49
50 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
51 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
52
amdgpu_get_adev(struct ttm_bo_device * bdev)53 static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
54 {
55 struct amdgpu_mman *mman;
56 struct amdgpu_device *adev;
57
58 mman = container_of(bdev, struct amdgpu_mman, bdev);
59 adev = container_of(mman, struct amdgpu_device, mman);
60 return adev;
61 }
62
63
64 /*
65 * Global memory.
66 */
amdgpu_ttm_mem_global_init(struct drm_global_reference * ref)67 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
68 {
69 return ttm_mem_global_init(ref->object);
70 }
71
amdgpu_ttm_mem_global_release(struct drm_global_reference * ref)72 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
73 {
74 ttm_mem_global_release(ref->object);
75 }
76
amdgpu_ttm_global_init(struct amdgpu_device * adev)77 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
78 {
79 struct drm_global_reference *global_ref;
80 int r;
81
82 adev->mman.mem_global_referenced = false;
83 global_ref = &adev->mman.mem_global_ref;
84 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
85 global_ref->size = sizeof(struct ttm_mem_global);
86 global_ref->init = &amdgpu_ttm_mem_global_init;
87 global_ref->release = &amdgpu_ttm_mem_global_release;
88 r = drm_global_item_ref(global_ref);
89 if (r != 0) {
90 DRM_ERROR("Failed setting up TTM memory accounting "
91 "subsystem.\n");
92 return r;
93 }
94
95 adev->mman.bo_global_ref.mem_glob =
96 adev->mman.mem_global_ref.object;
97 global_ref = &adev->mman.bo_global_ref.ref;
98 global_ref->global_type = DRM_GLOBAL_TTM_BO;
99 global_ref->size = sizeof(struct ttm_bo_global);
100 global_ref->init = &ttm_bo_global_init;
101 global_ref->release = &ttm_bo_global_release;
102 r = drm_global_item_ref(global_ref);
103 if (r != 0) {
104 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
105 drm_global_item_unref(&adev->mman.mem_global_ref);
106 return r;
107 }
108
109 adev->mman.mem_global_referenced = true;
110 return 0;
111 }
112
amdgpu_ttm_global_fini(struct amdgpu_device * adev)113 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
114 {
115 if (adev->mman.mem_global_referenced) {
116 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
117 drm_global_item_unref(&adev->mman.mem_global_ref);
118 adev->mman.mem_global_referenced = false;
119 }
120 }
121
amdgpu_invalidate_caches(struct ttm_bo_device * bdev,uint32_t flags)122 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
123 {
124 return 0;
125 }
126
amdgpu_init_mem_type(struct ttm_bo_device * bdev,uint32_t type,struct ttm_mem_type_manager * man)127 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
128 struct ttm_mem_type_manager *man)
129 {
130 struct amdgpu_device *adev;
131
132 adev = amdgpu_get_adev(bdev);
133
134 switch (type) {
135 case TTM_PL_SYSTEM:
136 /* System memory */
137 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
138 man->available_caching = TTM_PL_MASK_CACHING;
139 man->default_caching = TTM_PL_FLAG_CACHED;
140 break;
141 case TTM_PL_TT:
142 man->func = &ttm_bo_manager_func;
143 man->gpu_offset = adev->mc.gtt_start;
144 man->available_caching = TTM_PL_MASK_CACHING;
145 man->default_caching = TTM_PL_FLAG_CACHED;
146 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
147 break;
148 case TTM_PL_VRAM:
149 /* "On-card" video ram */
150 man->func = &ttm_bo_manager_func;
151 man->gpu_offset = adev->mc.vram_start;
152 man->flags = TTM_MEMTYPE_FLAG_FIXED |
153 TTM_MEMTYPE_FLAG_MAPPABLE;
154 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
155 man->default_caching = TTM_PL_FLAG_WC;
156 break;
157 case AMDGPU_PL_GDS:
158 case AMDGPU_PL_GWS:
159 case AMDGPU_PL_OA:
160 /* On-chip GDS memory*/
161 man->func = &ttm_bo_manager_func;
162 man->gpu_offset = 0;
163 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
164 man->available_caching = TTM_PL_FLAG_UNCACHED;
165 man->default_caching = TTM_PL_FLAG_UNCACHED;
166 break;
167 default:
168 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
169 return -EINVAL;
170 }
171 return 0;
172 }
173
amdgpu_evict_flags(struct ttm_buffer_object * bo,struct ttm_placement * placement)174 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
175 struct ttm_placement *placement)
176 {
177 struct amdgpu_bo *rbo;
178 static struct ttm_place placements = {
179 .fpfn = 0,
180 .lpfn = 0,
181 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
182 };
183
184 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
185 placement->placement = &placements;
186 placement->busy_placement = &placements;
187 placement->num_placement = 1;
188 placement->num_busy_placement = 1;
189 return;
190 }
191 rbo = container_of(bo, struct amdgpu_bo, tbo);
192 switch (bo->mem.mem_type) {
193 case TTM_PL_VRAM:
194 if (rbo->adev->mman.buffer_funcs_ring->ready == false)
195 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
196 else
197 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT);
198 break;
199 case TTM_PL_TT:
200 default:
201 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
202 }
203 *placement = rbo->placement;
204 }
205
amdgpu_verify_access(struct ttm_buffer_object * bo,struct file * filp)206 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
207 {
208 struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
209
210 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
211 }
212
amdgpu_move_null(struct ttm_buffer_object * bo,struct ttm_mem_reg * new_mem)213 static void amdgpu_move_null(struct ttm_buffer_object *bo,
214 struct ttm_mem_reg *new_mem)
215 {
216 struct ttm_mem_reg *old_mem = &bo->mem;
217
218 BUG_ON(old_mem->mm_node != NULL);
219 *old_mem = *new_mem;
220 new_mem->mm_node = NULL;
221 }
222
amdgpu_move_blit(struct ttm_buffer_object * bo,bool evict,bool no_wait_gpu,struct ttm_mem_reg * new_mem,struct ttm_mem_reg * old_mem)223 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
224 bool evict, bool no_wait_gpu,
225 struct ttm_mem_reg *new_mem,
226 struct ttm_mem_reg *old_mem)
227 {
228 struct amdgpu_device *adev;
229 struct amdgpu_ring *ring;
230 uint64_t old_start, new_start;
231 struct fence *fence;
232 int r;
233
234 adev = amdgpu_get_adev(bo->bdev);
235 ring = adev->mman.buffer_funcs_ring;
236 old_start = (u64)old_mem->start << PAGE_SHIFT;
237 new_start = (u64)new_mem->start << PAGE_SHIFT;
238
239 switch (old_mem->mem_type) {
240 case TTM_PL_VRAM:
241 old_start += adev->mc.vram_start;
242 break;
243 case TTM_PL_TT:
244 old_start += adev->mc.gtt_start;
245 break;
246 default:
247 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
248 return -EINVAL;
249 }
250 switch (new_mem->mem_type) {
251 case TTM_PL_VRAM:
252 new_start += adev->mc.vram_start;
253 break;
254 case TTM_PL_TT:
255 new_start += adev->mc.gtt_start;
256 break;
257 default:
258 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
259 return -EINVAL;
260 }
261 if (!ring->ready) {
262 DRM_ERROR("Trying to move memory with ring turned off.\n");
263 return -EINVAL;
264 }
265
266 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
267
268 r = amdgpu_copy_buffer(ring, old_start, new_start,
269 new_mem->num_pages * PAGE_SIZE, /* bytes */
270 bo->resv, &fence);
271 /* FIXME: handle copy error */
272 r = ttm_bo_move_accel_cleanup(bo, fence,
273 evict, no_wait_gpu, new_mem);
274 fence_put(fence);
275 return r;
276 }
277
amdgpu_move_vram_ram(struct ttm_buffer_object * bo,bool evict,bool interruptible,bool no_wait_gpu,struct ttm_mem_reg * new_mem)278 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
279 bool evict, bool interruptible,
280 bool no_wait_gpu,
281 struct ttm_mem_reg *new_mem)
282 {
283 struct amdgpu_device *adev;
284 struct ttm_mem_reg *old_mem = &bo->mem;
285 struct ttm_mem_reg tmp_mem;
286 struct ttm_place placements;
287 struct ttm_placement placement;
288 int r;
289
290 adev = amdgpu_get_adev(bo->bdev);
291 tmp_mem = *new_mem;
292 tmp_mem.mm_node = NULL;
293 placement.num_placement = 1;
294 placement.placement = &placements;
295 placement.num_busy_placement = 1;
296 placement.busy_placement = &placements;
297 placements.fpfn = 0;
298 placements.lpfn = 0;
299 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
300 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
301 interruptible, no_wait_gpu);
302 if (unlikely(r)) {
303 return r;
304 }
305
306 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
307 if (unlikely(r)) {
308 goto out_cleanup;
309 }
310
311 r = ttm_tt_bind(bo->ttm, &tmp_mem);
312 if (unlikely(r)) {
313 goto out_cleanup;
314 }
315 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
316 if (unlikely(r)) {
317 goto out_cleanup;
318 }
319 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
320 out_cleanup:
321 ttm_bo_mem_put(bo, &tmp_mem);
322 return r;
323 }
324
amdgpu_move_ram_vram(struct ttm_buffer_object * bo,bool evict,bool interruptible,bool no_wait_gpu,struct ttm_mem_reg * new_mem)325 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
326 bool evict, bool interruptible,
327 bool no_wait_gpu,
328 struct ttm_mem_reg *new_mem)
329 {
330 struct amdgpu_device *adev;
331 struct ttm_mem_reg *old_mem = &bo->mem;
332 struct ttm_mem_reg tmp_mem;
333 struct ttm_placement placement;
334 struct ttm_place placements;
335 int r;
336
337 adev = amdgpu_get_adev(bo->bdev);
338 tmp_mem = *new_mem;
339 tmp_mem.mm_node = NULL;
340 placement.num_placement = 1;
341 placement.placement = &placements;
342 placement.num_busy_placement = 1;
343 placement.busy_placement = &placements;
344 placements.fpfn = 0;
345 placements.lpfn = 0;
346 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
347 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
348 interruptible, no_wait_gpu);
349 if (unlikely(r)) {
350 return r;
351 }
352 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
353 if (unlikely(r)) {
354 goto out_cleanup;
355 }
356 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
357 if (unlikely(r)) {
358 goto out_cleanup;
359 }
360 out_cleanup:
361 ttm_bo_mem_put(bo, &tmp_mem);
362 return r;
363 }
364
amdgpu_bo_move(struct ttm_buffer_object * bo,bool evict,bool interruptible,bool no_wait_gpu,struct ttm_mem_reg * new_mem)365 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
366 bool evict, bool interruptible,
367 bool no_wait_gpu,
368 struct ttm_mem_reg *new_mem)
369 {
370 struct amdgpu_device *adev;
371 struct ttm_mem_reg *old_mem = &bo->mem;
372 int r;
373
374 adev = amdgpu_get_adev(bo->bdev);
375 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
376 amdgpu_move_null(bo, new_mem);
377 return 0;
378 }
379 if ((old_mem->mem_type == TTM_PL_TT &&
380 new_mem->mem_type == TTM_PL_SYSTEM) ||
381 (old_mem->mem_type == TTM_PL_SYSTEM &&
382 new_mem->mem_type == TTM_PL_TT)) {
383 /* bind is enough */
384 amdgpu_move_null(bo, new_mem);
385 return 0;
386 }
387 if (adev->mman.buffer_funcs == NULL ||
388 adev->mman.buffer_funcs_ring == NULL ||
389 !adev->mman.buffer_funcs_ring->ready) {
390 /* use memcpy */
391 goto memcpy;
392 }
393
394 if (old_mem->mem_type == TTM_PL_VRAM &&
395 new_mem->mem_type == TTM_PL_SYSTEM) {
396 r = amdgpu_move_vram_ram(bo, evict, interruptible,
397 no_wait_gpu, new_mem);
398 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
399 new_mem->mem_type == TTM_PL_VRAM) {
400 r = amdgpu_move_ram_vram(bo, evict, interruptible,
401 no_wait_gpu, new_mem);
402 } else {
403 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
404 }
405
406 if (r) {
407 memcpy:
408 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
409 if (r) {
410 return r;
411 }
412 }
413
414 /* update statistics */
415 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
416 return 0;
417 }
418
amdgpu_ttm_io_mem_reserve(struct ttm_bo_device * bdev,struct ttm_mem_reg * mem)419 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
420 {
421 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
422 struct amdgpu_device *adev = amdgpu_get_adev(bdev);
423
424 mem->bus.addr = NULL;
425 mem->bus.offset = 0;
426 mem->bus.size = mem->num_pages << PAGE_SHIFT;
427 mem->bus.base = 0;
428 mem->bus.is_iomem = false;
429 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
430 return -EINVAL;
431 switch (mem->mem_type) {
432 case TTM_PL_SYSTEM:
433 /* system memory */
434 return 0;
435 case TTM_PL_TT:
436 break;
437 case TTM_PL_VRAM:
438 mem->bus.offset = mem->start << PAGE_SHIFT;
439 /* check if it's visible */
440 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
441 return -EINVAL;
442 mem->bus.base = adev->mc.aper_base;
443 mem->bus.is_iomem = true;
444 #ifdef __alpha__
445 /*
446 * Alpha: use bus.addr to hold the ioremap() return,
447 * so we can modify bus.base below.
448 */
449 if (mem->placement & TTM_PL_FLAG_WC)
450 mem->bus.addr =
451 ioremap_wc(mem->bus.base + mem->bus.offset,
452 mem->bus.size);
453 else
454 mem->bus.addr =
455 ioremap_nocache(mem->bus.base + mem->bus.offset,
456 mem->bus.size);
457
458 /*
459 * Alpha: Use just the bus offset plus
460 * the hose/domain memory base for bus.base.
461 * It then can be used to build PTEs for VRAM
462 * access, as done in ttm_bo_vm_fault().
463 */
464 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
465 adev->ddev->hose->dense_mem_base;
466 #endif
467 break;
468 default:
469 return -EINVAL;
470 }
471 return 0;
472 }
473
amdgpu_ttm_io_mem_free(struct ttm_bo_device * bdev,struct ttm_mem_reg * mem)474 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
475 {
476 }
477
478 /*
479 * TTM backend functions.
480 */
481 struct amdgpu_ttm_tt {
482 struct ttm_dma_tt ttm;
483 struct amdgpu_device *adev;
484 u64 offset;
485 uint64_t userptr;
486 struct mm_struct *usermm;
487 uint32_t userflags;
488 };
489
490 /* prepare the sg table with the user pages */
amdgpu_ttm_tt_pin_userptr(struct ttm_tt * ttm)491 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
492 {
493 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
494 struct amdgpu_ttm_tt *gtt = (void *)ttm;
495 unsigned pinned = 0, nents;
496 int r;
497
498 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
499 unsigned int flags = 0;
500 enum dma_data_direction direction = write ?
501 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
502
503 if (write)
504 flags |= FOLL_WRITE;
505
506 if (current->mm != gtt->usermm)
507 return -EPERM;
508
509 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
510 /* check that we only pin down anonymous memory
511 to prevent problems with writeback */
512 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
513 struct vm_area_struct *vma;
514
515 vma = find_vma(gtt->usermm, gtt->userptr);
516 if (!vma || vma->vm_file || vma->vm_end < end)
517 return -EPERM;
518 }
519
520 do {
521 unsigned num_pages = ttm->num_pages - pinned;
522 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
523 struct page **pages = ttm->pages + pinned;
524
525 r = get_user_pages(current, current->mm, userptr, num_pages,
526 flags, pages, NULL);
527 if (r < 0)
528 goto release_pages;
529
530 pinned += r;
531
532 } while (pinned < ttm->num_pages);
533
534 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
535 ttm->num_pages << PAGE_SHIFT,
536 GFP_KERNEL);
537 if (r)
538 goto release_sg;
539
540 r = -ENOMEM;
541 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
542 if (nents != ttm->sg->nents)
543 goto release_sg;
544
545 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
546 gtt->ttm.dma_address, ttm->num_pages);
547
548 return 0;
549
550 release_sg:
551 kfree(ttm->sg);
552
553 release_pages:
554 release_pages(ttm->pages, pinned, 0);
555 return r;
556 }
557
amdgpu_ttm_tt_unpin_userptr(struct ttm_tt * ttm)558 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
559 {
560 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
561 struct amdgpu_ttm_tt *gtt = (void *)ttm;
562 struct sg_page_iter sg_iter;
563
564 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
565 enum dma_data_direction direction = write ?
566 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
567
568 /* double check that we don't free the table twice */
569 if (!ttm->sg || !ttm->sg->sgl)
570 return;
571
572 /* free the sg table and pages again */
573 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
574
575 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
576 struct page *page = sg_page_iter_page(&sg_iter);
577 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
578 set_page_dirty(page);
579
580 mark_page_accessed(page);
581 page_cache_release(page);
582 }
583
584 sg_free_table(ttm->sg);
585 }
586
amdgpu_ttm_backend_bind(struct ttm_tt * ttm,struct ttm_mem_reg * bo_mem)587 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
588 struct ttm_mem_reg *bo_mem)
589 {
590 struct amdgpu_ttm_tt *gtt = (void*)ttm;
591 uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
592 int r;
593
594 if (gtt->userptr) {
595 r = amdgpu_ttm_tt_pin_userptr(ttm);
596 if (r) {
597 DRM_ERROR("failed to pin userptr\n");
598 return r;
599 }
600 }
601 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
602 if (!ttm->num_pages) {
603 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
604 ttm->num_pages, bo_mem, ttm);
605 }
606
607 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
608 bo_mem->mem_type == AMDGPU_PL_GWS ||
609 bo_mem->mem_type == AMDGPU_PL_OA)
610 return -EINVAL;
611
612 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
613 ttm->pages, gtt->ttm.dma_address, flags);
614
615 if (r) {
616 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
617 ttm->num_pages, (unsigned)gtt->offset);
618 return r;
619 }
620 return 0;
621 }
622
amdgpu_ttm_backend_unbind(struct ttm_tt * ttm)623 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
624 {
625 struct amdgpu_ttm_tt *gtt = (void *)ttm;
626
627 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
628 if (gtt->adev->gart.ready)
629 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
630
631 if (gtt->userptr)
632 amdgpu_ttm_tt_unpin_userptr(ttm);
633
634 return 0;
635 }
636
amdgpu_ttm_backend_destroy(struct ttm_tt * ttm)637 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
638 {
639 struct amdgpu_ttm_tt *gtt = (void *)ttm;
640
641 ttm_dma_tt_fini(>t->ttm);
642 kfree(gtt);
643 }
644
645 static struct ttm_backend_func amdgpu_backend_func = {
646 .bind = &amdgpu_ttm_backend_bind,
647 .unbind = &amdgpu_ttm_backend_unbind,
648 .destroy = &amdgpu_ttm_backend_destroy,
649 };
650
amdgpu_ttm_tt_create(struct ttm_bo_device * bdev,unsigned long size,uint32_t page_flags,struct page * dummy_read_page)651 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
652 unsigned long size, uint32_t page_flags,
653 struct page *dummy_read_page)
654 {
655 struct amdgpu_device *adev;
656 struct amdgpu_ttm_tt *gtt;
657
658 adev = amdgpu_get_adev(bdev);
659
660 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
661 if (gtt == NULL) {
662 return NULL;
663 }
664 gtt->ttm.ttm.func = &amdgpu_backend_func;
665 gtt->adev = adev;
666 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) {
667 kfree(gtt);
668 return NULL;
669 }
670 return >t->ttm.ttm;
671 }
672
amdgpu_ttm_tt_populate(struct ttm_tt * ttm)673 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
674 {
675 struct amdgpu_device *adev;
676 struct amdgpu_ttm_tt *gtt = (void *)ttm;
677 unsigned i;
678 int r;
679 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
680
681 if (ttm->state != tt_unpopulated)
682 return 0;
683
684 if (gtt && gtt->userptr) {
685 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
686 if (!ttm->sg)
687 return -ENOMEM;
688
689 ttm->page_flags |= TTM_PAGE_FLAG_SG;
690 ttm->state = tt_unbound;
691 return 0;
692 }
693
694 if (slave && ttm->sg) {
695 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
696 gtt->ttm.dma_address, ttm->num_pages);
697 ttm->state = tt_unbound;
698 return 0;
699 }
700
701 adev = amdgpu_get_adev(ttm->bdev);
702
703 #ifdef CONFIG_SWIOTLB
704 if (swiotlb_nr_tbl()) {
705 return ttm_dma_populate(>t->ttm, adev->dev);
706 }
707 #endif
708
709 r = ttm_pool_populate(ttm);
710 if (r) {
711 return r;
712 }
713
714 for (i = 0; i < ttm->num_pages; i++) {
715 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
716 0, PAGE_SIZE,
717 PCI_DMA_BIDIRECTIONAL);
718 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
719 while (i--) {
720 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
721 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
722 gtt->ttm.dma_address[i] = 0;
723 }
724 ttm_pool_unpopulate(ttm);
725 return -EFAULT;
726 }
727 }
728 return 0;
729 }
730
amdgpu_ttm_tt_unpopulate(struct ttm_tt * ttm)731 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
732 {
733 struct amdgpu_device *adev;
734 struct amdgpu_ttm_tt *gtt = (void *)ttm;
735 unsigned i;
736 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
737
738 if (gtt && gtt->userptr) {
739 kfree(ttm->sg);
740 ttm->sg = NULL;
741 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
742 return;
743 }
744
745 if (slave)
746 return;
747
748 adev = amdgpu_get_adev(ttm->bdev);
749
750 #ifdef CONFIG_SWIOTLB
751 if (swiotlb_nr_tbl()) {
752 ttm_dma_unpopulate(>t->ttm, adev->dev);
753 return;
754 }
755 #endif
756
757 for (i = 0; i < ttm->num_pages; i++) {
758 if (gtt->ttm.dma_address[i]) {
759 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
760 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
761 }
762 }
763
764 ttm_pool_unpopulate(ttm);
765 }
766
amdgpu_ttm_tt_set_userptr(struct ttm_tt * ttm,uint64_t addr,uint32_t flags)767 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
768 uint32_t flags)
769 {
770 struct amdgpu_ttm_tt *gtt = (void *)ttm;
771
772 if (gtt == NULL)
773 return -EINVAL;
774
775 gtt->userptr = addr;
776 gtt->usermm = current->mm;
777 gtt->userflags = flags;
778 return 0;
779 }
780
amdgpu_ttm_tt_has_userptr(struct ttm_tt * ttm)781 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm)
782 {
783 struct amdgpu_ttm_tt *gtt = (void *)ttm;
784
785 if (gtt == NULL)
786 return false;
787
788 return !!gtt->userptr;
789 }
790
amdgpu_ttm_tt_affect_userptr(struct ttm_tt * ttm,unsigned long start,unsigned long end)791 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
792 unsigned long end)
793 {
794 struct amdgpu_ttm_tt *gtt = (void *)ttm;
795 unsigned long size;
796
797 if (gtt == NULL)
798 return false;
799
800 if (gtt->ttm.ttm.state != tt_bound || !gtt->userptr)
801 return false;
802
803 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
804 if (gtt->userptr > end || gtt->userptr + size <= start)
805 return false;
806
807 return true;
808 }
809
amdgpu_ttm_tt_is_readonly(struct ttm_tt * ttm)810 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
811 {
812 struct amdgpu_ttm_tt *gtt = (void *)ttm;
813
814 if (gtt == NULL)
815 return false;
816
817 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
818 }
819
amdgpu_ttm_tt_pte_flags(struct amdgpu_device * adev,struct ttm_tt * ttm,struct ttm_mem_reg * mem)820 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
821 struct ttm_mem_reg *mem)
822 {
823 uint32_t flags = 0;
824
825 if (mem && mem->mem_type != TTM_PL_SYSTEM)
826 flags |= AMDGPU_PTE_VALID;
827
828 if (mem && mem->mem_type == TTM_PL_TT) {
829 flags |= AMDGPU_PTE_SYSTEM;
830
831 if (ttm->caching_state == tt_cached)
832 flags |= AMDGPU_PTE_SNOOPED;
833 }
834
835 if (adev->asic_type >= CHIP_TONGA)
836 flags |= AMDGPU_PTE_EXECUTABLE;
837
838 flags |= AMDGPU_PTE_READABLE;
839
840 if (!amdgpu_ttm_tt_is_readonly(ttm))
841 flags |= AMDGPU_PTE_WRITEABLE;
842
843 return flags;
844 }
845
846 static struct ttm_bo_driver amdgpu_bo_driver = {
847 .ttm_tt_create = &amdgpu_ttm_tt_create,
848 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
849 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
850 .invalidate_caches = &amdgpu_invalidate_caches,
851 .init_mem_type = &amdgpu_init_mem_type,
852 .evict_flags = &amdgpu_evict_flags,
853 .move = &amdgpu_bo_move,
854 .verify_access = &amdgpu_verify_access,
855 .move_notify = &amdgpu_bo_move_notify,
856 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
857 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
858 .io_mem_free = &amdgpu_ttm_io_mem_free,
859 };
860
amdgpu_ttm_init(struct amdgpu_device * adev)861 int amdgpu_ttm_init(struct amdgpu_device *adev)
862 {
863 int r;
864
865 r = amdgpu_ttm_global_init(adev);
866 if (r) {
867 return r;
868 }
869 /* No others user of address space so set it to 0 */
870 r = ttm_bo_device_init(&adev->mman.bdev,
871 adev->mman.bo_global_ref.ref.object,
872 &amdgpu_bo_driver,
873 adev->ddev->anon_inode->i_mapping,
874 DRM_FILE_PAGE_OFFSET,
875 adev->need_dma32);
876 if (r) {
877 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
878 return r;
879 }
880 adev->mman.initialized = true;
881 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
882 adev->mc.real_vram_size >> PAGE_SHIFT);
883 if (r) {
884 DRM_ERROR("Failed initializing VRAM heap.\n");
885 return r;
886 }
887 /* Change the size here instead of the init above so only lpfn is affected */
888 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
889
890 r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
891 AMDGPU_GEM_DOMAIN_VRAM,
892 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
893 NULL, NULL, &adev->stollen_vga_memory);
894 if (r) {
895 return r;
896 }
897 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
898 if (r)
899 return r;
900 r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
901 amdgpu_bo_unreserve(adev->stollen_vga_memory);
902 if (r) {
903 amdgpu_bo_unref(&adev->stollen_vga_memory);
904 return r;
905 }
906 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
907 (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
908 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
909 adev->mc.gtt_size >> PAGE_SHIFT);
910 if (r) {
911 DRM_ERROR("Failed initializing GTT heap.\n");
912 return r;
913 }
914 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
915 (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
916
917 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
918 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
919 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
920 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
921 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
922 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
923 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
924 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
925 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
926 /* GDS Memory */
927 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
928 adev->gds.mem.total_size >> PAGE_SHIFT);
929 if (r) {
930 DRM_ERROR("Failed initializing GDS heap.\n");
931 return r;
932 }
933
934 /* GWS */
935 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
936 adev->gds.gws.total_size >> PAGE_SHIFT);
937 if (r) {
938 DRM_ERROR("Failed initializing gws heap.\n");
939 return r;
940 }
941
942 /* OA */
943 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
944 adev->gds.oa.total_size >> PAGE_SHIFT);
945 if (r) {
946 DRM_ERROR("Failed initializing oa heap.\n");
947 return r;
948 }
949
950 r = amdgpu_ttm_debugfs_init(adev);
951 if (r) {
952 DRM_ERROR("Failed to init debugfs\n");
953 return r;
954 }
955 return 0;
956 }
957
amdgpu_ttm_fini(struct amdgpu_device * adev)958 void amdgpu_ttm_fini(struct amdgpu_device *adev)
959 {
960 int r;
961
962 if (!adev->mman.initialized)
963 return;
964 amdgpu_ttm_debugfs_fini(adev);
965 if (adev->stollen_vga_memory) {
966 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
967 if (r == 0) {
968 amdgpu_bo_unpin(adev->stollen_vga_memory);
969 amdgpu_bo_unreserve(adev->stollen_vga_memory);
970 }
971 amdgpu_bo_unref(&adev->stollen_vga_memory);
972 }
973 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
974 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
975 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
976 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
977 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
978 ttm_bo_device_release(&adev->mman.bdev);
979 amdgpu_gart_fini(adev);
980 amdgpu_ttm_global_fini(adev);
981 adev->mman.initialized = false;
982 DRM_INFO("amdgpu: ttm finalized\n");
983 }
984
985 /* this should only be called at bootup or when userspace
986 * isn't running */
amdgpu_ttm_set_active_vram_size(struct amdgpu_device * adev,u64 size)987 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
988 {
989 struct ttm_mem_type_manager *man;
990
991 if (!adev->mman.initialized)
992 return;
993
994 man = &adev->mman.bdev.man[TTM_PL_VRAM];
995 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
996 man->size = size >> PAGE_SHIFT;
997 }
998
amdgpu_mmap(struct file * filp,struct vm_area_struct * vma)999 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1000 {
1001 struct drm_file *file_priv;
1002 struct amdgpu_device *adev;
1003
1004 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1005 return -EINVAL;
1006
1007 file_priv = filp->private_data;
1008 adev = file_priv->minor->dev->dev_private;
1009 if (adev == NULL)
1010 return -EINVAL;
1011
1012 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1013 }
1014
amdgpu_copy_buffer(struct amdgpu_ring * ring,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,struct reservation_object * resv,struct fence ** fence)1015 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1016 uint64_t src_offset,
1017 uint64_t dst_offset,
1018 uint32_t byte_count,
1019 struct reservation_object *resv,
1020 struct fence **fence)
1021 {
1022 struct amdgpu_device *adev = ring->adev;
1023 uint32_t max_bytes;
1024 unsigned num_loops, num_dw;
1025 struct amdgpu_ib *ib;
1026 unsigned i;
1027 int r;
1028
1029 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1030 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1031 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1032
1033 /* for IB padding */
1034 while (num_dw & 0x7)
1035 num_dw++;
1036
1037 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
1038 if (!ib)
1039 return -ENOMEM;
1040
1041 r = amdgpu_ib_get(ring, NULL, num_dw * 4, ib);
1042 if (r) {
1043 kfree(ib);
1044 return r;
1045 }
1046
1047 ib->length_dw = 0;
1048
1049 if (resv) {
1050 r = amdgpu_sync_resv(adev, &ib->sync, resv,
1051 AMDGPU_FENCE_OWNER_UNDEFINED);
1052 if (r) {
1053 DRM_ERROR("sync failed (%d).\n", r);
1054 goto error_free;
1055 }
1056 }
1057
1058 for (i = 0; i < num_loops; i++) {
1059 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1060
1061 amdgpu_emit_copy_buffer(adev, ib, src_offset, dst_offset,
1062 cur_size_in_bytes);
1063
1064 src_offset += cur_size_in_bytes;
1065 dst_offset += cur_size_in_bytes;
1066 byte_count -= cur_size_in_bytes;
1067 }
1068
1069 amdgpu_vm_pad_ib(adev, ib);
1070 WARN_ON(ib->length_dw > num_dw);
1071 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
1072 &amdgpu_vm_free_job,
1073 AMDGPU_FENCE_OWNER_UNDEFINED,
1074 fence);
1075 if (r)
1076 goto error_free;
1077
1078 if (!amdgpu_enable_scheduler) {
1079 amdgpu_ib_free(adev, ib);
1080 kfree(ib);
1081 }
1082 return 0;
1083 error_free:
1084 amdgpu_ib_free(adev, ib);
1085 kfree(ib);
1086 return r;
1087 }
1088
1089 #if defined(CONFIG_DEBUG_FS)
1090
amdgpu_mm_dump_table(struct seq_file * m,void * data)1091 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1092 {
1093 struct drm_info_node *node = (struct drm_info_node *)m->private;
1094 unsigned ttm_pl = *(int *)node->info_ent->data;
1095 struct drm_device *dev = node->minor->dev;
1096 struct amdgpu_device *adev = dev->dev_private;
1097 struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1098 int ret;
1099 struct ttm_bo_global *glob = adev->mman.bdev.glob;
1100
1101 spin_lock(&glob->lru_lock);
1102 ret = drm_mm_dump_table(m, mm);
1103 spin_unlock(&glob->lru_lock);
1104 if (ttm_pl == TTM_PL_VRAM)
1105 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1106 adev->mman.bdev.man[ttm_pl].size,
1107 (u64)atomic64_read(&adev->vram_usage) >> 20,
1108 (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1109 return ret;
1110 }
1111
1112 static int ttm_pl_vram = TTM_PL_VRAM;
1113 static int ttm_pl_tt = TTM_PL_TT;
1114
1115 static struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1116 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1117 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1118 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1119 #ifdef CONFIG_SWIOTLB
1120 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1121 #endif
1122 };
1123
amdgpu_ttm_vram_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1124 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1125 size_t size, loff_t *pos)
1126 {
1127 struct amdgpu_device *adev = f->f_inode->i_private;
1128 ssize_t result = 0;
1129 int r;
1130
1131 if (size & 0x3 || *pos & 0x3)
1132 return -EINVAL;
1133
1134 if (*pos >= adev->mc.mc_vram_size)
1135 return -ENXIO;
1136
1137 while (size) {
1138 unsigned long flags;
1139 uint32_t value;
1140
1141 if (*pos >= adev->mc.mc_vram_size)
1142 return result;
1143
1144 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1145 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1146 WREG32(mmMM_INDEX_HI, *pos >> 31);
1147 value = RREG32(mmMM_DATA);
1148 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1149
1150 r = put_user(value, (uint32_t *)buf);
1151 if (r)
1152 return r;
1153
1154 result += 4;
1155 buf += 4;
1156 *pos += 4;
1157 size -= 4;
1158 }
1159
1160 return result;
1161 }
1162
1163 static const struct file_operations amdgpu_ttm_vram_fops = {
1164 .owner = THIS_MODULE,
1165 .read = amdgpu_ttm_vram_read,
1166 .llseek = default_llseek
1167 };
1168
amdgpu_ttm_gtt_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1169 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1170 size_t size, loff_t *pos)
1171 {
1172 struct amdgpu_device *adev = f->f_inode->i_private;
1173 ssize_t result = 0;
1174 int r;
1175
1176 while (size) {
1177 loff_t p = *pos / PAGE_SIZE;
1178 unsigned off = *pos & ~PAGE_MASK;
1179 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1180 struct page *page;
1181 void *ptr;
1182
1183 if (p >= adev->gart.num_cpu_pages)
1184 return result;
1185
1186 page = adev->gart.pages[p];
1187 if (page) {
1188 ptr = kmap(page);
1189 ptr += off;
1190
1191 r = copy_to_user(buf, ptr, cur_size);
1192 kunmap(adev->gart.pages[p]);
1193 } else
1194 r = clear_user(buf, cur_size);
1195
1196 if (r)
1197 return -EFAULT;
1198
1199 result += cur_size;
1200 buf += cur_size;
1201 *pos += cur_size;
1202 size -= cur_size;
1203 }
1204
1205 return result;
1206 }
1207
1208 static const struct file_operations amdgpu_ttm_gtt_fops = {
1209 .owner = THIS_MODULE,
1210 .read = amdgpu_ttm_gtt_read,
1211 .llseek = default_llseek
1212 };
1213
1214 #endif
1215
amdgpu_ttm_debugfs_init(struct amdgpu_device * adev)1216 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1217 {
1218 #if defined(CONFIG_DEBUG_FS)
1219 unsigned count;
1220
1221 struct drm_minor *minor = adev->ddev->primary;
1222 struct dentry *ent, *root = minor->debugfs_root;
1223
1224 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1225 adev, &amdgpu_ttm_vram_fops);
1226 if (IS_ERR(ent))
1227 return PTR_ERR(ent);
1228 i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1229 adev->mman.vram = ent;
1230
1231 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1232 adev, &amdgpu_ttm_gtt_fops);
1233 if (IS_ERR(ent))
1234 return PTR_ERR(ent);
1235 i_size_write(ent->d_inode, adev->mc.gtt_size);
1236 adev->mman.gtt = ent;
1237
1238 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1239
1240 #ifdef CONFIG_SWIOTLB
1241 if (!swiotlb_nr_tbl())
1242 --count;
1243 #endif
1244
1245 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1246 #else
1247
1248 return 0;
1249 #endif
1250 }
1251
amdgpu_ttm_debugfs_fini(struct amdgpu_device * adev)1252 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1253 {
1254 #if defined(CONFIG_DEBUG_FS)
1255
1256 debugfs_remove(adev->mman.vram);
1257 adev->mman.vram = NULL;
1258
1259 debugfs_remove(adev->mman.gtt);
1260 adev->mman.gtt = NULL;
1261 #endif
1262 }
1263