1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 * Authors: Christian König <christian.koenig@amd.com>
26 */
27
28 #include <linux/firmware.h>
29 #include <linux/module.h>
30 #include <drm/drmP.h>
31 #include <drm/drm.h>
32
33 #include "amdgpu.h"
34 #include "amdgpu_pm.h"
35 #include "amdgpu_vce.h"
36 #include "cikd.h"
37
38 /* 1 second timeout */
39 #define VCE_IDLE_TIMEOUT_MS 1000
40
41 /* Firmware Names */
42 #ifdef CONFIG_DRM_AMDGPU_CIK
43 #define FIRMWARE_BONAIRE "radeon/bonaire_vce.bin"
44 #define FIRMWARE_KABINI "radeon/kabini_vce.bin"
45 #define FIRMWARE_KAVERI "radeon/kaveri_vce.bin"
46 #define FIRMWARE_HAWAII "radeon/hawaii_vce.bin"
47 #define FIRMWARE_MULLINS "radeon/mullins_vce.bin"
48 #endif
49 #define FIRMWARE_TONGA "amdgpu/tonga_vce.bin"
50 #define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin"
51 #define FIRMWARE_FIJI "amdgpu/fiji_vce.bin"
52 #define FIRMWARE_STONEY "amdgpu/stoney_vce.bin"
53
54 #ifdef CONFIG_DRM_AMDGPU_CIK
55 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
56 MODULE_FIRMWARE(FIRMWARE_KABINI);
57 MODULE_FIRMWARE(FIRMWARE_KAVERI);
58 MODULE_FIRMWARE(FIRMWARE_HAWAII);
59 MODULE_FIRMWARE(FIRMWARE_MULLINS);
60 #endif
61 MODULE_FIRMWARE(FIRMWARE_TONGA);
62 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
63 MODULE_FIRMWARE(FIRMWARE_FIJI);
64 MODULE_FIRMWARE(FIRMWARE_STONEY);
65
66 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
67
68 /**
69 * amdgpu_vce_init - allocate memory, load vce firmware
70 *
71 * @adev: amdgpu_device pointer
72 *
73 * First step to get VCE online, allocate memory and load the firmware
74 */
amdgpu_vce_sw_init(struct amdgpu_device * adev,unsigned long size)75 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
76 {
77 const char *fw_name;
78 const struct common_firmware_header *hdr;
79 unsigned ucode_version, version_major, version_minor, binary_id;
80 int i, r;
81
82 INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
83
84 switch (adev->asic_type) {
85 #ifdef CONFIG_DRM_AMDGPU_CIK
86 case CHIP_BONAIRE:
87 fw_name = FIRMWARE_BONAIRE;
88 break;
89 case CHIP_KAVERI:
90 fw_name = FIRMWARE_KAVERI;
91 break;
92 case CHIP_KABINI:
93 fw_name = FIRMWARE_KABINI;
94 break;
95 case CHIP_HAWAII:
96 fw_name = FIRMWARE_HAWAII;
97 break;
98 case CHIP_MULLINS:
99 fw_name = FIRMWARE_MULLINS;
100 break;
101 #endif
102 case CHIP_TONGA:
103 fw_name = FIRMWARE_TONGA;
104 break;
105 case CHIP_CARRIZO:
106 fw_name = FIRMWARE_CARRIZO;
107 break;
108 case CHIP_FIJI:
109 fw_name = FIRMWARE_FIJI;
110 break;
111 case CHIP_STONEY:
112 fw_name = FIRMWARE_STONEY;
113 break;
114
115 default:
116 return -EINVAL;
117 }
118
119 r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
120 if (r) {
121 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
122 fw_name);
123 return r;
124 }
125
126 r = amdgpu_ucode_validate(adev->vce.fw);
127 if (r) {
128 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
129 fw_name);
130 release_firmware(adev->vce.fw);
131 adev->vce.fw = NULL;
132 return r;
133 }
134
135 hdr = (const struct common_firmware_header *)adev->vce.fw->data;
136
137 ucode_version = le32_to_cpu(hdr->ucode_version);
138 version_major = (ucode_version >> 20) & 0xfff;
139 version_minor = (ucode_version >> 8) & 0xfff;
140 binary_id = ucode_version & 0xff;
141 DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
142 version_major, version_minor, binary_id);
143 adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
144 (binary_id << 8));
145
146 /* allocate firmware, stack and heap BO */
147
148 r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
149 AMDGPU_GEM_DOMAIN_VRAM,
150 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
151 NULL, NULL, &adev->vce.vcpu_bo);
152 if (r) {
153 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
154 return r;
155 }
156
157 r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
158 if (r) {
159 amdgpu_bo_unref(&adev->vce.vcpu_bo);
160 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
161 return r;
162 }
163
164 r = amdgpu_bo_pin(adev->vce.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
165 &adev->vce.gpu_addr);
166 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
167 if (r) {
168 amdgpu_bo_unref(&adev->vce.vcpu_bo);
169 dev_err(adev->dev, "(%d) VCE bo pin failed\n", r);
170 return r;
171 }
172
173 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
174 atomic_set(&adev->vce.handles[i], 0);
175 adev->vce.filp[i] = NULL;
176 }
177
178 return 0;
179 }
180
181 /**
182 * amdgpu_vce_fini - free memory
183 *
184 * @adev: amdgpu_device pointer
185 *
186 * Last step on VCE teardown, free firmware memory
187 */
amdgpu_vce_sw_fini(struct amdgpu_device * adev)188 int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
189 {
190 if (adev->vce.vcpu_bo == NULL)
191 return 0;
192
193 amdgpu_bo_unref(&adev->vce.vcpu_bo);
194
195 amdgpu_ring_fini(&adev->vce.ring[0]);
196 amdgpu_ring_fini(&adev->vce.ring[1]);
197
198 release_firmware(adev->vce.fw);
199
200 return 0;
201 }
202
203 /**
204 * amdgpu_vce_suspend - unpin VCE fw memory
205 *
206 * @adev: amdgpu_device pointer
207 *
208 */
amdgpu_vce_suspend(struct amdgpu_device * adev)209 int amdgpu_vce_suspend(struct amdgpu_device *adev)
210 {
211 int i;
212
213 if (adev->vce.vcpu_bo == NULL)
214 return 0;
215
216 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
217 if (atomic_read(&adev->vce.handles[i]))
218 break;
219
220 if (i == AMDGPU_MAX_VCE_HANDLES)
221 return 0;
222
223 cancel_delayed_work_sync(&adev->vce.idle_work);
224 /* TODO: suspending running encoding sessions isn't supported */
225 return -EINVAL;
226 }
227
228 /**
229 * amdgpu_vce_resume - pin VCE fw memory
230 *
231 * @adev: amdgpu_device pointer
232 *
233 */
amdgpu_vce_resume(struct amdgpu_device * adev)234 int amdgpu_vce_resume(struct amdgpu_device *adev)
235 {
236 void *cpu_addr;
237 const struct common_firmware_header *hdr;
238 unsigned offset;
239 int r;
240
241 if (adev->vce.vcpu_bo == NULL)
242 return -EINVAL;
243
244 r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
245 if (r) {
246 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
247 return r;
248 }
249
250 r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
251 if (r) {
252 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
253 dev_err(adev->dev, "(%d) VCE map failed\n", r);
254 return r;
255 }
256
257 hdr = (const struct common_firmware_header *)adev->vce.fw->data;
258 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
259 memcpy(cpu_addr, (adev->vce.fw->data) + offset,
260 (adev->vce.fw->size) - offset);
261
262 amdgpu_bo_kunmap(adev->vce.vcpu_bo);
263
264 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
265
266 return 0;
267 }
268
269 /**
270 * amdgpu_vce_idle_work_handler - power off VCE
271 *
272 * @work: pointer to work structure
273 *
274 * power of VCE when it's not used any more
275 */
amdgpu_vce_idle_work_handler(struct work_struct * work)276 static void amdgpu_vce_idle_work_handler(struct work_struct *work)
277 {
278 struct amdgpu_device *adev =
279 container_of(work, struct amdgpu_device, vce.idle_work.work);
280
281 if ((amdgpu_fence_count_emitted(&adev->vce.ring[0]) == 0) &&
282 (amdgpu_fence_count_emitted(&adev->vce.ring[1]) == 0)) {
283 if (adev->pm.dpm_enabled) {
284 amdgpu_dpm_enable_vce(adev, false);
285 } else {
286 amdgpu_asic_set_vce_clocks(adev, 0, 0);
287 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
288 AMD_PG_STATE_GATE);
289 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
290 AMD_CG_STATE_GATE);
291 }
292 } else {
293 schedule_delayed_work(&adev->vce.idle_work,
294 msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
295 }
296 }
297
298 /**
299 * amdgpu_vce_note_usage - power up VCE
300 *
301 * @adev: amdgpu_device pointer
302 *
303 * Make sure VCE is powerd up when we want to use it
304 */
amdgpu_vce_note_usage(struct amdgpu_device * adev)305 static void amdgpu_vce_note_usage(struct amdgpu_device *adev)
306 {
307 bool streams_changed = false;
308 bool set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
309 set_clocks &= schedule_delayed_work(&adev->vce.idle_work,
310 msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
311
312 if (adev->pm.dpm_enabled) {
313 /* XXX figure out if the streams changed */
314 streams_changed = false;
315 }
316
317 if (set_clocks || streams_changed) {
318 if (adev->pm.dpm_enabled) {
319 amdgpu_dpm_enable_vce(adev, true);
320 } else {
321 amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
322 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
323 AMD_CG_STATE_UNGATE);
324 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
325 AMD_PG_STATE_UNGATE);
326
327 }
328 }
329 }
330
331 /**
332 * amdgpu_vce_free_handles - free still open VCE handles
333 *
334 * @adev: amdgpu_device pointer
335 * @filp: drm file pointer
336 *
337 * Close all VCE handles still open by this file pointer
338 */
amdgpu_vce_free_handles(struct amdgpu_device * adev,struct drm_file * filp)339 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
340 {
341 struct amdgpu_ring *ring = &adev->vce.ring[0];
342 int i, r;
343 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
344 uint32_t handle = atomic_read(&adev->vce.handles[i]);
345 if (!handle || adev->vce.filp[i] != filp)
346 continue;
347
348 amdgpu_vce_note_usage(adev);
349
350 r = amdgpu_vce_get_destroy_msg(ring, handle, NULL);
351 if (r)
352 DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
353
354 adev->vce.filp[i] = NULL;
355 atomic_set(&adev->vce.handles[i], 0);
356 }
357 }
358
amdgpu_vce_free_job(struct amdgpu_job * job)359 static int amdgpu_vce_free_job(
360 struct amdgpu_job *job)
361 {
362 amdgpu_ib_free(job->adev, job->ibs);
363 kfree(job->ibs);
364 return 0;
365 }
366
367 /**
368 * amdgpu_vce_get_create_msg - generate a VCE create msg
369 *
370 * @adev: amdgpu_device pointer
371 * @ring: ring we should submit the msg to
372 * @handle: VCE session handle to use
373 * @fence: optional fence to return
374 *
375 * Open up a stream for HW test
376 */
amdgpu_vce_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct fence ** fence)377 int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
378 struct fence **fence)
379 {
380 const unsigned ib_size_dw = 1024;
381 struct amdgpu_ib *ib = NULL;
382 struct fence *f = NULL;
383 struct amdgpu_device *adev = ring->adev;
384 uint64_t dummy;
385 int i, r;
386
387 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
388 if (!ib)
389 return -ENOMEM;
390 r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, ib);
391 if (r) {
392 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
393 kfree(ib);
394 return r;
395 }
396
397 dummy = ib->gpu_addr + 1024;
398
399 /* stitch together an VCE create msg */
400 ib->length_dw = 0;
401 ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
402 ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
403 ib->ptr[ib->length_dw++] = handle;
404
405 if ((ring->adev->vce.fw_version >> 24) >= 52)
406 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
407 else
408 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
409 ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
410 ib->ptr[ib->length_dw++] = 0x00000000;
411 ib->ptr[ib->length_dw++] = 0x00000042;
412 ib->ptr[ib->length_dw++] = 0x0000000a;
413 ib->ptr[ib->length_dw++] = 0x00000001;
414 ib->ptr[ib->length_dw++] = 0x00000080;
415 ib->ptr[ib->length_dw++] = 0x00000060;
416 ib->ptr[ib->length_dw++] = 0x00000100;
417 ib->ptr[ib->length_dw++] = 0x00000100;
418 ib->ptr[ib->length_dw++] = 0x0000000c;
419 ib->ptr[ib->length_dw++] = 0x00000000;
420 if ((ring->adev->vce.fw_version >> 24) >= 52) {
421 ib->ptr[ib->length_dw++] = 0x00000000;
422 ib->ptr[ib->length_dw++] = 0x00000000;
423 ib->ptr[ib->length_dw++] = 0x00000000;
424 ib->ptr[ib->length_dw++] = 0x00000000;
425 }
426
427 ib->ptr[ib->length_dw++] = 0x00000014; /* len */
428 ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
429 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
430 ib->ptr[ib->length_dw++] = dummy;
431 ib->ptr[ib->length_dw++] = 0x00000001;
432
433 for (i = ib->length_dw; i < ib_size_dw; ++i)
434 ib->ptr[i] = 0x0;
435
436 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
437 &amdgpu_vce_free_job,
438 AMDGPU_FENCE_OWNER_UNDEFINED,
439 &f);
440 if (r)
441 goto err;
442 if (fence)
443 *fence = fence_get(f);
444 fence_put(f);
445 if (amdgpu_enable_scheduler)
446 return 0;
447 err:
448 amdgpu_ib_free(adev, ib);
449 kfree(ib);
450 return r;
451 }
452
453 /**
454 * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
455 *
456 * @adev: amdgpu_device pointer
457 * @ring: ring we should submit the msg to
458 * @handle: VCE session handle to use
459 * @fence: optional fence to return
460 *
461 * Close up a stream for HW test or if userspace failed to do so
462 */
amdgpu_vce_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,struct fence ** fence)463 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
464 struct fence **fence)
465 {
466 const unsigned ib_size_dw = 1024;
467 struct amdgpu_ib *ib = NULL;
468 struct fence *f = NULL;
469 struct amdgpu_device *adev = ring->adev;
470 uint64_t dummy;
471 int i, r;
472
473 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
474 if (!ib)
475 return -ENOMEM;
476
477 r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, ib);
478 if (r) {
479 kfree(ib);
480 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
481 return r;
482 }
483
484 dummy = ib->gpu_addr + 1024;
485
486 /* stitch together an VCE destroy msg */
487 ib->length_dw = 0;
488 ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
489 ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
490 ib->ptr[ib->length_dw++] = handle;
491
492 ib->ptr[ib->length_dw++] = 0x00000014; /* len */
493 ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
494 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
495 ib->ptr[ib->length_dw++] = dummy;
496 ib->ptr[ib->length_dw++] = 0x00000001;
497
498 ib->ptr[ib->length_dw++] = 0x00000008; /* len */
499 ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
500
501 for (i = ib->length_dw; i < ib_size_dw; ++i)
502 ib->ptr[i] = 0x0;
503 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
504 &amdgpu_vce_free_job,
505 AMDGPU_FENCE_OWNER_UNDEFINED,
506 &f);
507 if (r)
508 goto err;
509 if (fence)
510 *fence = fence_get(f);
511 fence_put(f);
512 if (amdgpu_enable_scheduler)
513 return 0;
514 err:
515 amdgpu_ib_free(adev, ib);
516 kfree(ib);
517 return r;
518 }
519
520 /**
521 * amdgpu_vce_cs_reloc - command submission relocation
522 *
523 * @p: parser context
524 * @lo: address of lower dword
525 * @hi: address of higher dword
526 * @size: minimum size
527 *
528 * Patch relocation inside command stream with real buffer address
529 */
amdgpu_vce_cs_reloc(struct amdgpu_cs_parser * p,uint32_t ib_idx,int lo,int hi,unsigned size,uint32_t index)530 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
531 int lo, int hi, unsigned size, uint32_t index)
532 {
533 struct amdgpu_bo_va_mapping *mapping;
534 struct amdgpu_ib *ib = &p->ibs[ib_idx];
535 struct amdgpu_bo *bo;
536 uint64_t addr;
537
538 if (index == 0xffffffff)
539 index = 0;
540
541 addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
542 ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
543 addr += ((uint64_t)size) * ((uint64_t)index);
544
545 mapping = amdgpu_cs_find_mapping(p, addr, &bo);
546 if (mapping == NULL) {
547 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
548 addr, lo, hi, size, index);
549 return -EINVAL;
550 }
551
552 if ((addr + (uint64_t)size) >
553 ((uint64_t)mapping->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
554 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
555 addr, lo, hi);
556 return -EINVAL;
557 }
558
559 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
560 addr += amdgpu_bo_gpu_offset(bo);
561 addr -= ((uint64_t)size) * ((uint64_t)index);
562
563 ib->ptr[lo] = addr & 0xFFFFFFFF;
564 ib->ptr[hi] = addr >> 32;
565
566 return 0;
567 }
568
569 /**
570 * amdgpu_vce_validate_handle - validate stream handle
571 *
572 * @p: parser context
573 * @handle: handle to validate
574 * @allocated: allocated a new handle?
575 *
576 * Validates the handle and return the found session index or -EINVAL
577 * we we don't have another free session index.
578 */
amdgpu_vce_validate_handle(struct amdgpu_cs_parser * p,uint32_t handle,bool * allocated)579 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
580 uint32_t handle, bool *allocated)
581 {
582 unsigned i;
583
584 *allocated = false;
585
586 /* validate the handle */
587 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
588 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
589 if (p->adev->vce.filp[i] != p->filp) {
590 DRM_ERROR("VCE handle collision detected!\n");
591 return -EINVAL;
592 }
593 return i;
594 }
595 }
596
597 /* handle not found try to alloc a new one */
598 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
599 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
600 p->adev->vce.filp[i] = p->filp;
601 p->adev->vce.img_size[i] = 0;
602 *allocated = true;
603 return i;
604 }
605 }
606
607 DRM_ERROR("No more free VCE handles!\n");
608 return -EINVAL;
609 }
610
611 /**
612 * amdgpu_vce_cs_parse - parse and validate the command stream
613 *
614 * @p: parser context
615 *
616 */
amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser * p,uint32_t ib_idx)617 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
618 {
619 struct amdgpu_ib *ib = &p->ibs[ib_idx];
620 unsigned fb_idx = 0, bs_idx = 0;
621 int session_idx = -1;
622 bool destroyed = false;
623 bool created = false;
624 bool allocated = false;
625 uint32_t tmp, handle = 0;
626 uint32_t *size = &tmp;
627 int i, r = 0, idx = 0;
628
629 amdgpu_vce_note_usage(p->adev);
630
631 while (idx < ib->length_dw) {
632 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
633 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
634
635 if ((len < 8) || (len & 3)) {
636 DRM_ERROR("invalid VCE command length (%d)!\n", len);
637 r = -EINVAL;
638 goto out;
639 }
640
641 if (destroyed) {
642 DRM_ERROR("No other command allowed after destroy!\n");
643 r = -EINVAL;
644 goto out;
645 }
646
647 switch (cmd) {
648 case 0x00000001: // session
649 handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
650 session_idx = amdgpu_vce_validate_handle(p, handle,
651 &allocated);
652 if (session_idx < 0)
653 return session_idx;
654 size = &p->adev->vce.img_size[session_idx];
655 break;
656
657 case 0x00000002: // task info
658 fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
659 bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
660 break;
661
662 case 0x01000001: // create
663 created = true;
664 if (!allocated) {
665 DRM_ERROR("Handle already in use!\n");
666 r = -EINVAL;
667 goto out;
668 }
669
670 *size = amdgpu_get_ib_value(p, ib_idx, idx + 8) *
671 amdgpu_get_ib_value(p, ib_idx, idx + 10) *
672 8 * 3 / 2;
673 break;
674
675 case 0x04000001: // config extension
676 case 0x04000002: // pic control
677 case 0x04000005: // rate control
678 case 0x04000007: // motion estimation
679 case 0x04000008: // rdo
680 case 0x04000009: // vui
681 case 0x05000002: // auxiliary buffer
682 break;
683
684 case 0x03000001: // encode
685 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
686 *size, 0);
687 if (r)
688 goto out;
689
690 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11,
691 *size / 3, 0);
692 if (r)
693 goto out;
694 break;
695
696 case 0x02000001: // destroy
697 destroyed = true;
698 break;
699
700 case 0x05000001: // context buffer
701 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
702 *size * 2, 0);
703 if (r)
704 goto out;
705 break;
706
707 case 0x05000004: // video bitstream buffer
708 tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
709 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
710 tmp, bs_idx);
711 if (r)
712 goto out;
713 break;
714
715 case 0x05000005: // feedback buffer
716 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
717 4096, fb_idx);
718 if (r)
719 goto out;
720 break;
721
722 default:
723 DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
724 r = -EINVAL;
725 goto out;
726 }
727
728 if (session_idx == -1) {
729 DRM_ERROR("no session command at start of IB\n");
730 r = -EINVAL;
731 goto out;
732 }
733
734 idx += len / 4;
735 }
736
737 if (allocated && !created) {
738 DRM_ERROR("New session without create command!\n");
739 r = -ENOENT;
740 }
741
742 out:
743 if ((!r && destroyed) || (r && allocated)) {
744 /*
745 * IB contains a destroy msg or we have allocated an
746 * handle and got an error, anyway free the handle
747 */
748 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
749 atomic_cmpxchg(&p->adev->vce.handles[i], handle, 0);
750 }
751
752 return r;
753 }
754
755 /**
756 * amdgpu_vce_ring_emit_semaphore - emit a semaphore command
757 *
758 * @ring: engine to use
759 * @semaphore: address of semaphore
760 * @emit_wait: true=emit wait, false=emit signal
761 *
762 */
amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring * ring,struct amdgpu_semaphore * semaphore,bool emit_wait)763 bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring,
764 struct amdgpu_semaphore *semaphore,
765 bool emit_wait)
766 {
767 uint64_t addr = semaphore->gpu_addr;
768
769 amdgpu_ring_write(ring, VCE_CMD_SEMAPHORE);
770 amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
771 amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
772 amdgpu_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0));
773 if (!emit_wait)
774 amdgpu_ring_write(ring, VCE_CMD_END);
775
776 return true;
777 }
778
779 /**
780 * amdgpu_vce_ring_emit_ib - execute indirect buffer
781 *
782 * @ring: engine to use
783 * @ib: the IB to execute
784 *
785 */
amdgpu_vce_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)786 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
787 {
788 amdgpu_ring_write(ring, VCE_CMD_IB);
789 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
790 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
791 amdgpu_ring_write(ring, ib->length_dw);
792 }
793
794 /**
795 * amdgpu_vce_ring_emit_fence - add a fence command to the ring
796 *
797 * @ring: engine to use
798 * @fence: the fence
799 *
800 */
amdgpu_vce_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)801 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
802 unsigned flags)
803 {
804 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
805
806 amdgpu_ring_write(ring, VCE_CMD_FENCE);
807 amdgpu_ring_write(ring, addr);
808 amdgpu_ring_write(ring, upper_32_bits(addr));
809 amdgpu_ring_write(ring, seq);
810 amdgpu_ring_write(ring, VCE_CMD_TRAP);
811 amdgpu_ring_write(ring, VCE_CMD_END);
812 }
813
814 /**
815 * amdgpu_vce_ring_test_ring - test if VCE ring is working
816 *
817 * @ring: the engine to test on
818 *
819 */
amdgpu_vce_ring_test_ring(struct amdgpu_ring * ring)820 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
821 {
822 struct amdgpu_device *adev = ring->adev;
823 uint32_t rptr = amdgpu_ring_get_rptr(ring);
824 unsigned i;
825 int r;
826
827 r = amdgpu_ring_lock(ring, 16);
828 if (r) {
829 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
830 ring->idx, r);
831 return r;
832 }
833 amdgpu_ring_write(ring, VCE_CMD_END);
834 amdgpu_ring_unlock_commit(ring);
835
836 for (i = 0; i < adev->usec_timeout; i++) {
837 if (amdgpu_ring_get_rptr(ring) != rptr)
838 break;
839 DRM_UDELAY(1);
840 }
841
842 if (i < adev->usec_timeout) {
843 DRM_INFO("ring test on %d succeeded in %d usecs\n",
844 ring->idx, i);
845 } else {
846 DRM_ERROR("amdgpu: ring %d test failed\n",
847 ring->idx);
848 r = -ETIMEDOUT;
849 }
850
851 return r;
852 }
853
854 /**
855 * amdgpu_vce_ring_test_ib - test if VCE IBs are working
856 *
857 * @ring: the engine to test on
858 *
859 */
amdgpu_vce_ring_test_ib(struct amdgpu_ring * ring)860 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring)
861 {
862 struct fence *fence = NULL;
863 int r;
864
865 /* skip vce ring1 ib test for now, since it's not reliable */
866 if (ring == &ring->adev->vce.ring[1])
867 return 0;
868
869 r = amdgpu_vce_get_create_msg(ring, 1, NULL);
870 if (r) {
871 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
872 goto error;
873 }
874
875 r = amdgpu_vce_get_destroy_msg(ring, 1, &fence);
876 if (r) {
877 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
878 goto error;
879 }
880
881 r = fence_wait(fence, false);
882 if (r) {
883 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
884 } else {
885 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
886 }
887 error:
888 fence_put(fence);
889 return r;
890 }
891