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1 /*
2  * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
3  * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
4  * Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
19  */
20 
21 #include <linux/module.h>
22 #include <linux/gpio.h>
23 
24 #include <asm/mach-ar7/ar7.h>
25 
26 #define AR7_GPIO_MAX 32
27 #define TITAN_GPIO_MAX 51
28 
29 struct ar7_gpio_chip {
30 	void __iomem		*regs;
31 	struct gpio_chip	chip;
32 };
33 
ar7_gpio_get_value(struct gpio_chip * chip,unsigned gpio)34 static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
35 {
36 	struct ar7_gpio_chip *gpch =
37 				container_of(chip, struct ar7_gpio_chip, chip);
38 	void __iomem *gpio_in = gpch->regs + AR7_GPIO_INPUT;
39 
40 	return readl(gpio_in) & (1 << gpio);
41 }
42 
titan_gpio_get_value(struct gpio_chip * chip,unsigned gpio)43 static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
44 {
45 	struct ar7_gpio_chip *gpch =
46 				container_of(chip, struct ar7_gpio_chip, chip);
47 	void __iomem *gpio_in0 = gpch->regs + TITAN_GPIO_INPUT_0;
48 	void __iomem *gpio_in1 = gpch->regs + TITAN_GPIO_INPUT_1;
49 
50 	return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
51 }
52 
ar7_gpio_set_value(struct gpio_chip * chip,unsigned gpio,int value)53 static void ar7_gpio_set_value(struct gpio_chip *chip,
54 				unsigned gpio, int value)
55 {
56 	struct ar7_gpio_chip *gpch =
57 				container_of(chip, struct ar7_gpio_chip, chip);
58 	void __iomem *gpio_out = gpch->regs + AR7_GPIO_OUTPUT;
59 	unsigned tmp;
60 
61 	tmp = readl(gpio_out) & ~(1 << gpio);
62 	if (value)
63 		tmp |= 1 << gpio;
64 	writel(tmp, gpio_out);
65 }
66 
titan_gpio_set_value(struct gpio_chip * chip,unsigned gpio,int value)67 static void titan_gpio_set_value(struct gpio_chip *chip,
68 				unsigned gpio, int value)
69 {
70 	struct ar7_gpio_chip *gpch =
71 				container_of(chip, struct ar7_gpio_chip, chip);
72 	void __iomem *gpio_out0 = gpch->regs + TITAN_GPIO_OUTPUT_0;
73 	void __iomem *gpio_out1 = gpch->regs + TITAN_GPIO_OUTPUT_1;
74 	unsigned tmp;
75 
76 	tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
77 	if (value)
78 		tmp |= 1 << (gpio & 0x1f);
79 	writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
80 }
81 
ar7_gpio_direction_input(struct gpio_chip * chip,unsigned gpio)82 static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
83 {
84 	struct ar7_gpio_chip *gpch =
85 				container_of(chip, struct ar7_gpio_chip, chip);
86 	void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
87 
88 	writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
89 
90 	return 0;
91 }
92 
titan_gpio_direction_input(struct gpio_chip * chip,unsigned gpio)93 static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
94 {
95 	struct ar7_gpio_chip *gpch =
96 				container_of(chip, struct ar7_gpio_chip, chip);
97 	void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
98 	void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
99 
100 	if (gpio >= TITAN_GPIO_MAX)
101 		return -EINVAL;
102 
103 	writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
104 			gpio >> 5 ? gpio_dir1 : gpio_dir0);
105 	return 0;
106 }
107 
ar7_gpio_direction_output(struct gpio_chip * chip,unsigned gpio,int value)108 static int ar7_gpio_direction_output(struct gpio_chip *chip,
109 					unsigned gpio, int value)
110 {
111 	struct ar7_gpio_chip *gpch =
112 				container_of(chip, struct ar7_gpio_chip, chip);
113 	void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
114 
115 	ar7_gpio_set_value(chip, gpio, value);
116 	writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
117 
118 	return 0;
119 }
120 
titan_gpio_direction_output(struct gpio_chip * chip,unsigned gpio,int value)121 static int titan_gpio_direction_output(struct gpio_chip *chip,
122 					unsigned gpio, int value)
123 {
124 	struct ar7_gpio_chip *gpch =
125 				container_of(chip, struct ar7_gpio_chip, chip);
126 	void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
127 	void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
128 
129 	if (gpio >= TITAN_GPIO_MAX)
130 		return -EINVAL;
131 
132 	titan_gpio_set_value(chip, gpio, value);
133 	writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
134 		(gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
135 
136 	return 0;
137 }
138 
139 static struct ar7_gpio_chip ar7_gpio_chip = {
140 	.chip = {
141 		.label			= "ar7-gpio",
142 		.direction_input	= ar7_gpio_direction_input,
143 		.direction_output	= ar7_gpio_direction_output,
144 		.set			= ar7_gpio_set_value,
145 		.get			= ar7_gpio_get_value,
146 		.base			= 0,
147 		.ngpio			= AR7_GPIO_MAX,
148 	}
149 };
150 
151 static struct ar7_gpio_chip titan_gpio_chip = {
152 	.chip = {
153 		.label			= "titan-gpio",
154 		.direction_input	= titan_gpio_direction_input,
155 		.direction_output	= titan_gpio_direction_output,
156 		.set			= titan_gpio_set_value,
157 		.get			= titan_gpio_get_value,
158 		.base			= 0,
159 		.ngpio			= TITAN_GPIO_MAX,
160 	}
161 };
162 
ar7_gpio_enable_ar7(unsigned gpio)163 static inline int ar7_gpio_enable_ar7(unsigned gpio)
164 {
165 	void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
166 
167 	writel(readl(gpio_en) | (1 << gpio), gpio_en);
168 
169 	return 0;
170 }
171 
ar7_gpio_enable_titan(unsigned gpio)172 static inline int ar7_gpio_enable_titan(unsigned gpio)
173 {
174 	void __iomem *gpio_en0 = titan_gpio_chip.regs  + TITAN_GPIO_ENBL_0;
175 	void __iomem *gpio_en1 = titan_gpio_chip.regs  + TITAN_GPIO_ENBL_1;
176 
177 	writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
178 		gpio >> 5 ? gpio_en1 : gpio_en0);
179 
180 	return 0;
181 }
182 
ar7_gpio_enable(unsigned gpio)183 int ar7_gpio_enable(unsigned gpio)
184 {
185 	return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
186 				ar7_gpio_enable_ar7(gpio);
187 }
188 EXPORT_SYMBOL(ar7_gpio_enable);
189 
ar7_gpio_disable_ar7(unsigned gpio)190 static inline int ar7_gpio_disable_ar7(unsigned gpio)
191 {
192 	void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
193 
194 	writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
195 
196 	return 0;
197 }
198 
ar7_gpio_disable_titan(unsigned gpio)199 static inline int ar7_gpio_disable_titan(unsigned gpio)
200 {
201 	void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
202 	void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
203 
204 	writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
205 			gpio >> 5 ? gpio_en1 : gpio_en0);
206 
207 	return 0;
208 }
209 
ar7_gpio_disable(unsigned gpio)210 int ar7_gpio_disable(unsigned gpio)
211 {
212 	return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
213 				ar7_gpio_disable_ar7(gpio);
214 }
215 EXPORT_SYMBOL(ar7_gpio_disable);
216 
217 struct titan_gpio_cfg {
218 	u32 reg;
219 	u32 shift;
220 	u32 func;
221 };
222 
223 static const struct titan_gpio_cfg titan_gpio_table[] = {
224 	/* reg, start bit, mux value */
225 	{4, 24, 1},
226 	{4, 26, 1},
227 	{4, 28, 1},
228 	{4, 30, 1},
229 	{5, 6, 1},
230 	{5, 8, 1},
231 	{5, 10, 1},
232 	{5, 12, 1},
233 	{7, 14, 3},
234 	{7, 16, 3},
235 	{7, 18, 3},
236 	{7, 20, 3},
237 	{7, 22, 3},
238 	{7, 26, 3},
239 	{7, 28, 3},
240 	{7, 30, 3},
241 	{8, 0, 3},
242 	{8, 2, 3},
243 	{8, 4, 3},
244 	{8, 10, 3},
245 	{8, 14, 3},
246 	{8, 16, 3},
247 	{8, 18, 3},
248 	{8, 20, 3},
249 	{9, 8, 3},
250 	{9, 10, 3},
251 	{9, 12, 3},
252 	{9, 14, 3},
253 	{9, 18, 3},
254 	{9, 20, 3},
255 	{9, 24, 3},
256 	{9, 26, 3},
257 	{9, 28, 3},
258 	{9, 30, 3},
259 	{10, 0, 3},
260 	{10, 2, 3},
261 	{10, 8, 3},
262 	{10, 10, 3},
263 	{10, 12, 3},
264 	{10, 14, 3},
265 	{13, 12, 3},
266 	{13, 14, 3},
267 	{13, 16, 3},
268 	{13, 18, 3},
269 	{13, 24, 3},
270 	{13, 26, 3},
271 	{13, 28, 3},
272 	{13, 30, 3},
273 	{14, 2, 3},
274 	{14, 6, 3},
275 	{14, 8, 3},
276 	{14, 12, 3}
277 };
278 
titan_gpio_pinsel(unsigned gpio)279 static int titan_gpio_pinsel(unsigned gpio)
280 {
281 	struct titan_gpio_cfg gpio_cfg;
282 	u32 mux_status, pin_sel_reg, tmp;
283 	void __iomem *pin_sel = (void __iomem *)KSEG1ADDR(AR7_REGS_PINSEL);
284 
285 	if (gpio >= ARRAY_SIZE(titan_gpio_table))
286 		return -EINVAL;
287 
288 	gpio_cfg = titan_gpio_table[gpio];
289 	pin_sel_reg = gpio_cfg.reg - 1;
290 
291 	mux_status = (readl(pin_sel + pin_sel_reg) >> gpio_cfg.shift) & 0x3;
292 
293 	/* Check the mux status */
294 	if (!((mux_status == 0) || (mux_status == gpio_cfg.func)))
295 		return 0;
296 
297 	/* Set the pin sel value */
298 	tmp = readl(pin_sel + pin_sel_reg);
299 	tmp |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
300 	writel(tmp, pin_sel + pin_sel_reg);
301 
302 	return 0;
303 }
304 
305 /* Perform minimal Titan GPIO configuration */
titan_gpio_init(void)306 static void titan_gpio_init(void)
307 {
308 	unsigned i;
309 
310 	for (i = 44; i < 48; i++) {
311 		titan_gpio_pinsel(i);
312 		ar7_gpio_enable_titan(i);
313 		titan_gpio_direction_input(&titan_gpio_chip.chip, i);
314 	}
315 }
316 
ar7_gpio_init(void)317 int __init ar7_gpio_init(void)
318 {
319 	int ret;
320 	struct ar7_gpio_chip *gpch;
321 	unsigned size;
322 
323 	if (!ar7_is_titan()) {
324 		gpch = &ar7_gpio_chip;
325 		size = 0x10;
326 	} else {
327 		gpch = &titan_gpio_chip;
328 		size = 0x1f;
329 	}
330 
331 	gpch->regs = ioremap_nocache(AR7_REGS_GPIO, size);
332 	if (!gpch->regs) {
333 		printk(KERN_ERR "%s: failed to ioremap regs\n",
334 					gpch->chip.label);
335 		return -ENOMEM;
336 	}
337 
338 	ret = gpiochip_add(&gpch->chip);
339 	if (ret) {
340 		printk(KERN_ERR "%s: failed to add gpiochip\n",
341 					gpch->chip.label);
342 		return ret;
343 	}
344 	printk(KERN_INFO "%s: registered %d GPIOs\n",
345 				gpch->chip.label, gpch->chip.ngpio);
346 
347 	if (ar7_is_titan())
348 		titan_gpio_init();
349 
350 	return ret;
351 }
352