1 /*
2 * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2008 Atmel
6 *
7 * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
8 * ATMEL CORP.
9 *
10 * Based on at91-ssc.c by
11 * Frank Mandarino <fmandarino@endrelia.com>
12 * Based on pxa2xx Platform drivers by
13 * Liam Girdwood <lrg@slimlogic.co.uk>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 */
29
30 #include <linux/init.h>
31 #include <linux/module.h>
32 #include <linux/interrupt.h>
33 #include <linux/device.h>
34 #include <linux/delay.h>
35 #include <linux/clk.h>
36 #include <linux/atmel_pdc.h>
37
38 #include <linux/atmel-ssc.h>
39 #include <sound/core.h>
40 #include <sound/pcm.h>
41 #include <sound/pcm_params.h>
42 #include <sound/initval.h>
43 #include <sound/soc.h>
44
45 #include "atmel-pcm.h"
46 #include "atmel_ssc_dai.h"
47
48
49 #define NUM_SSC_DEVICES 3
50
51 /*
52 * SSC PDC registers required by the PCM DMA engine.
53 */
54 static struct atmel_pdc_regs pdc_tx_reg = {
55 .xpr = ATMEL_PDC_TPR,
56 .xcr = ATMEL_PDC_TCR,
57 .xnpr = ATMEL_PDC_TNPR,
58 .xncr = ATMEL_PDC_TNCR,
59 };
60
61 static struct atmel_pdc_regs pdc_rx_reg = {
62 .xpr = ATMEL_PDC_RPR,
63 .xcr = ATMEL_PDC_RCR,
64 .xnpr = ATMEL_PDC_RNPR,
65 .xncr = ATMEL_PDC_RNCR,
66 };
67
68 /*
69 * SSC & PDC status bits for transmit and receive.
70 */
71 static struct atmel_ssc_mask ssc_tx_mask = {
72 .ssc_enable = SSC_BIT(CR_TXEN),
73 .ssc_disable = SSC_BIT(CR_TXDIS),
74 .ssc_endx = SSC_BIT(SR_ENDTX),
75 .ssc_endbuf = SSC_BIT(SR_TXBUFE),
76 .ssc_error = SSC_BIT(SR_OVRUN),
77 .pdc_enable = ATMEL_PDC_TXTEN,
78 .pdc_disable = ATMEL_PDC_TXTDIS,
79 };
80
81 static struct atmel_ssc_mask ssc_rx_mask = {
82 .ssc_enable = SSC_BIT(CR_RXEN),
83 .ssc_disable = SSC_BIT(CR_RXDIS),
84 .ssc_endx = SSC_BIT(SR_ENDRX),
85 .ssc_endbuf = SSC_BIT(SR_RXBUFF),
86 .ssc_error = SSC_BIT(SR_OVRUN),
87 .pdc_enable = ATMEL_PDC_RXTEN,
88 .pdc_disable = ATMEL_PDC_RXTDIS,
89 };
90
91
92 /*
93 * DMA parameters.
94 */
95 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
96 {{
97 .name = "SSC0 PCM out",
98 .pdc = &pdc_tx_reg,
99 .mask = &ssc_tx_mask,
100 },
101 {
102 .name = "SSC0 PCM in",
103 .pdc = &pdc_rx_reg,
104 .mask = &ssc_rx_mask,
105 } },
106 {{
107 .name = "SSC1 PCM out",
108 .pdc = &pdc_tx_reg,
109 .mask = &ssc_tx_mask,
110 },
111 {
112 .name = "SSC1 PCM in",
113 .pdc = &pdc_rx_reg,
114 .mask = &ssc_rx_mask,
115 } },
116 {{
117 .name = "SSC2 PCM out",
118 .pdc = &pdc_tx_reg,
119 .mask = &ssc_tx_mask,
120 },
121 {
122 .name = "SSC2 PCM in",
123 .pdc = &pdc_rx_reg,
124 .mask = &ssc_rx_mask,
125 } },
126 };
127
128
129 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
130 {
131 .name = "ssc0",
132 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
133 .dir_mask = SSC_DIR_MASK_UNUSED,
134 .initialized = 0,
135 },
136 {
137 .name = "ssc1",
138 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
139 .dir_mask = SSC_DIR_MASK_UNUSED,
140 .initialized = 0,
141 },
142 {
143 .name = "ssc2",
144 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
145 .dir_mask = SSC_DIR_MASK_UNUSED,
146 .initialized = 0,
147 },
148 };
149
150
151 /*
152 * SSC interrupt handler. Passes PDC interrupts to the DMA
153 * interrupt handler in the PCM driver.
154 */
atmel_ssc_interrupt(int irq,void * dev_id)155 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
156 {
157 struct atmel_ssc_info *ssc_p = dev_id;
158 struct atmel_pcm_dma_params *dma_params;
159 u32 ssc_sr;
160 u32 ssc_substream_mask;
161 int i;
162
163 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
164 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
165
166 /*
167 * Loop through the substreams attached to this SSC. If
168 * a DMA-related interrupt occurred on that substream, call
169 * the DMA interrupt handler function, if one has been
170 * registered in the dma_params structure by the PCM driver.
171 */
172 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
173 dma_params = ssc_p->dma_params[i];
174
175 if ((dma_params != NULL) &&
176 (dma_params->dma_intr_handler != NULL)) {
177 ssc_substream_mask = (dma_params->mask->ssc_endx |
178 dma_params->mask->ssc_endbuf);
179 if (ssc_sr & ssc_substream_mask) {
180 dma_params->dma_intr_handler(ssc_sr,
181 dma_params->
182 substream);
183 }
184 }
185 }
186
187 return IRQ_HANDLED;
188 }
189
190 /*
191 * When the bit clock is input, limit the maximum rate according to the
192 * Serial Clock Ratio Considerations section from the SSC documentation:
193 *
194 * The Transmitter and the Receiver can be programmed to operate
195 * with the clock signals provided on either the TK or RK pins.
196 * This allows the SSC to support many slave-mode data transfers.
197 * In this case, the maximum clock speed allowed on the RK pin is:
198 * - Peripheral clock divided by 2 if Receiver Frame Synchro is input
199 * - Peripheral clock divided by 3 if Receiver Frame Synchro is output
200 * In addition, the maximum clock speed allowed on the TK pin is:
201 * - Peripheral clock divided by 6 if Transmit Frame Synchro is input
202 * - Peripheral clock divided by 2 if Transmit Frame Synchro is output
203 *
204 * When the bit clock is output, limit the rate according to the
205 * SSC divider restrictions.
206 */
atmel_ssc_hw_rule_rate(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)207 static int atmel_ssc_hw_rule_rate(struct snd_pcm_hw_params *params,
208 struct snd_pcm_hw_rule *rule)
209 {
210 struct atmel_ssc_info *ssc_p = rule->private;
211 struct ssc_device *ssc = ssc_p->ssc;
212 struct snd_interval *i = hw_param_interval(params, rule->var);
213 struct snd_interval t;
214 struct snd_ratnum r = {
215 .den_min = 1,
216 .den_max = 4095,
217 .den_step = 1,
218 };
219 unsigned int num = 0, den = 0;
220 int frame_size;
221 int mck_div = 2;
222 int ret;
223
224 frame_size = snd_soc_params_to_frame_size(params);
225 if (frame_size < 0)
226 return frame_size;
227
228 switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) {
229 case SND_SOC_DAIFMT_CBM_CFS:
230 if ((ssc_p->dir_mask & SSC_DIR_MASK_CAPTURE)
231 && ssc->clk_from_rk_pin)
232 /* Receiver Frame Synchro (i.e. capture)
233 * is output (format is _CFS) and the RK pin
234 * is used for input (format is _CBM_).
235 */
236 mck_div = 3;
237 break;
238
239 case SND_SOC_DAIFMT_CBM_CFM:
240 if ((ssc_p->dir_mask & SSC_DIR_MASK_PLAYBACK)
241 && !ssc->clk_from_rk_pin)
242 /* Transmit Frame Synchro (i.e. playback)
243 * is input (format is _CFM) and the TK pin
244 * is used for input (format _CBM_ but not
245 * using the RK pin).
246 */
247 mck_div = 6;
248 break;
249 }
250
251 switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) {
252 case SND_SOC_DAIFMT_CBS_CFS:
253 r.num = ssc_p->mck_rate / mck_div / frame_size;
254
255 ret = snd_interval_ratnum(i, 1, &r, &num, &den);
256 if (ret >= 0 && den && rule->var == SNDRV_PCM_HW_PARAM_RATE) {
257 params->rate_num = num;
258 params->rate_den = den;
259 }
260 break;
261
262 case SND_SOC_DAIFMT_CBM_CFS:
263 case SND_SOC_DAIFMT_CBM_CFM:
264 t.min = 8000;
265 t.max = ssc_p->mck_rate / mck_div / frame_size;
266 t.openmin = t.openmax = 0;
267 t.integer = 0;
268 ret = snd_interval_refine(i, &t);
269 break;
270
271 default:
272 ret = -EINVAL;
273 break;
274 }
275
276 return ret;
277 }
278
279 /*-------------------------------------------------------------------------*\
280 * DAI functions
281 \*-------------------------------------------------------------------------*/
282 /*
283 * Startup. Only that one substream allowed in each direction.
284 */
atmel_ssc_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)285 static int atmel_ssc_startup(struct snd_pcm_substream *substream,
286 struct snd_soc_dai *dai)
287 {
288 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
289 struct atmel_pcm_dma_params *dma_params;
290 int dir, dir_mask;
291 int ret;
292
293 pr_debug("atmel_ssc_startup: SSC_SR=0x%x\n",
294 ssc_readl(ssc_p->ssc->regs, SR));
295
296 /* Enable PMC peripheral clock for this SSC */
297 pr_debug("atmel_ssc_dai: Starting clock\n");
298 clk_enable(ssc_p->ssc->clk);
299 ssc_p->mck_rate = clk_get_rate(ssc_p->ssc->clk);
300
301 /* Reset the SSC unless initialized to keep it in a clean state */
302 if (!ssc_p->initialized)
303 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
304
305 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
306 dir = 0;
307 dir_mask = SSC_DIR_MASK_PLAYBACK;
308 } else {
309 dir = 1;
310 dir_mask = SSC_DIR_MASK_CAPTURE;
311 }
312
313 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
314 SNDRV_PCM_HW_PARAM_RATE,
315 atmel_ssc_hw_rule_rate,
316 ssc_p,
317 SNDRV_PCM_HW_PARAM_FRAME_BITS,
318 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
319 if (ret < 0) {
320 dev_err(dai->dev, "Failed to specify rate rule: %d\n", ret);
321 return ret;
322 }
323
324 dma_params = &ssc_dma_params[dai->id][dir];
325 dma_params->ssc = ssc_p->ssc;
326 dma_params->substream = substream;
327
328 ssc_p->dma_params[dir] = dma_params;
329
330 snd_soc_dai_set_dma_data(dai, substream, dma_params);
331
332 spin_lock_irq(&ssc_p->lock);
333 if (ssc_p->dir_mask & dir_mask) {
334 spin_unlock_irq(&ssc_p->lock);
335 return -EBUSY;
336 }
337 ssc_p->dir_mask |= dir_mask;
338 spin_unlock_irq(&ssc_p->lock);
339
340 return 0;
341 }
342
343 /*
344 * Shutdown. Clear DMA parameters and shutdown the SSC if there
345 * are no other substreams open.
346 */
atmel_ssc_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)347 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
348 struct snd_soc_dai *dai)
349 {
350 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
351 struct atmel_pcm_dma_params *dma_params;
352 int dir, dir_mask;
353
354 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
355 dir = 0;
356 else
357 dir = 1;
358
359 dma_params = ssc_p->dma_params[dir];
360
361 if (dma_params != NULL) {
362 dma_params->ssc = NULL;
363 dma_params->substream = NULL;
364 ssc_p->dma_params[dir] = NULL;
365 }
366
367 dir_mask = 1 << dir;
368
369 spin_lock_irq(&ssc_p->lock);
370 ssc_p->dir_mask &= ~dir_mask;
371 if (!ssc_p->dir_mask) {
372 if (ssc_p->initialized) {
373 free_irq(ssc_p->ssc->irq, ssc_p);
374 ssc_p->initialized = 0;
375 }
376
377 /* Reset the SSC */
378 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
379 /* Clear the SSC dividers */
380 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
381 }
382 spin_unlock_irq(&ssc_p->lock);
383
384 /* Shutdown the SSC clock. */
385 pr_debug("atmel_ssc_dai: Stopping clock\n");
386 clk_disable(ssc_p->ssc->clk);
387 }
388
389
390 /*
391 * Record the DAI format for use in hw_params().
392 */
atmel_ssc_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)393 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
394 unsigned int fmt)
395 {
396 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
397
398 ssc_p->daifmt = fmt;
399 return 0;
400 }
401
402 /*
403 * Record SSC clock dividers for use in hw_params().
404 */
atmel_ssc_set_dai_clkdiv(struct snd_soc_dai * cpu_dai,int div_id,int div)405 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
406 int div_id, int div)
407 {
408 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
409
410 switch (div_id) {
411 case ATMEL_SSC_CMR_DIV:
412 /*
413 * The same master clock divider is used for both
414 * transmit and receive, so if a value has already
415 * been set, it must match this value.
416 */
417 if (ssc_p->dir_mask !=
418 (SSC_DIR_MASK_PLAYBACK | SSC_DIR_MASK_CAPTURE))
419 ssc_p->cmr_div = div;
420 else if (ssc_p->cmr_div == 0)
421 ssc_p->cmr_div = div;
422 else
423 if (div != ssc_p->cmr_div)
424 return -EBUSY;
425 break;
426
427 case ATMEL_SSC_TCMR_PERIOD:
428 ssc_p->tcmr_period = div;
429 break;
430
431 case ATMEL_SSC_RCMR_PERIOD:
432 ssc_p->rcmr_period = div;
433 break;
434
435 default:
436 return -EINVAL;
437 }
438
439 return 0;
440 }
441
442 /*
443 * Configure the SSC.
444 */
atmel_ssc_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)445 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
446 struct snd_pcm_hw_params *params,
447 struct snd_soc_dai *dai)
448 {
449 int id = dai->id;
450 struct atmel_ssc_info *ssc_p = &ssc_info[id];
451 struct ssc_device *ssc = ssc_p->ssc;
452 struct atmel_pcm_dma_params *dma_params;
453 int dir, channels, bits;
454 u32 tfmr, rfmr, tcmr, rcmr;
455 int ret;
456 int fslen, fslen_ext;
457
458 /*
459 * Currently, there is only one set of dma params for
460 * each direction. If more are added, this code will
461 * have to be changed to select the proper set.
462 */
463 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
464 dir = 0;
465 else
466 dir = 1;
467
468 dma_params = ssc_p->dma_params[dir];
469
470 channels = params_channels(params);
471
472 /*
473 * Determine sample size in bits and the PDC increment.
474 */
475 switch (params_format(params)) {
476 case SNDRV_PCM_FORMAT_S8:
477 bits = 8;
478 dma_params->pdc_xfer_size = 1;
479 break;
480 case SNDRV_PCM_FORMAT_S16_LE:
481 bits = 16;
482 dma_params->pdc_xfer_size = 2;
483 break;
484 case SNDRV_PCM_FORMAT_S24_LE:
485 bits = 24;
486 dma_params->pdc_xfer_size = 4;
487 break;
488 case SNDRV_PCM_FORMAT_S32_LE:
489 bits = 32;
490 dma_params->pdc_xfer_size = 4;
491 break;
492 default:
493 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
494 return -EINVAL;
495 }
496
497 /*
498 * Compute SSC register settings.
499 */
500 switch (ssc_p->daifmt
501 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
502
503 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
504 /*
505 * I2S format, SSC provides BCLK and LRC clocks.
506 *
507 * The SSC transmit and receive clocks are generated
508 * from the MCK divider, and the BCLK signal
509 * is output on the SSC TK line.
510 */
511
512 if (bits > 16 && !ssc->pdata->has_fslen_ext) {
513 dev_err(dai->dev,
514 "sample size %d is too large for SSC device\n",
515 bits);
516 return -EINVAL;
517 }
518
519 fslen_ext = (bits - 1) / 16;
520 fslen = (bits - 1) % 16;
521
522 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
523 | SSC_BF(RCMR_STTDLY, START_DELAY)
524 | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
525 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
526 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
527 | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
528
529 rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
530 | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
531 | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
532 | SSC_BF(RFMR_FSLEN, fslen)
533 | SSC_BF(RFMR_DATNB, (channels - 1))
534 | SSC_BIT(RFMR_MSBF)
535 | SSC_BF(RFMR_LOOP, 0)
536 | SSC_BF(RFMR_DATLEN, (bits - 1));
537
538 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
539 | SSC_BF(TCMR_STTDLY, START_DELAY)
540 | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
541 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
542 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
543 | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
544
545 tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
546 | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
547 | SSC_BF(TFMR_FSDEN, 0)
548 | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
549 | SSC_BF(TFMR_FSLEN, fslen)
550 | SSC_BF(TFMR_DATNB, (channels - 1))
551 | SSC_BIT(TFMR_MSBF)
552 | SSC_BF(TFMR_DATDEF, 0)
553 | SSC_BF(TFMR_DATLEN, (bits - 1));
554 break;
555
556 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
557 /* I2S format, CODEC supplies BCLK and LRC clocks. */
558 rcmr = SSC_BF(RCMR_PERIOD, 0)
559 | SSC_BF(RCMR_STTDLY, START_DELAY)
560 | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
561 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
562 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
563 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
564 SSC_CKS_PIN : SSC_CKS_CLOCK);
565
566 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
567 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
568 | SSC_BF(RFMR_FSLEN, 0)
569 | SSC_BF(RFMR_DATNB, (channels - 1))
570 | SSC_BIT(RFMR_MSBF)
571 | SSC_BF(RFMR_LOOP, 0)
572 | SSC_BF(RFMR_DATLEN, (bits - 1));
573
574 tcmr = SSC_BF(TCMR_PERIOD, 0)
575 | SSC_BF(TCMR_STTDLY, START_DELAY)
576 | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
577 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
578 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
579 | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
580 SSC_CKS_CLOCK : SSC_CKS_PIN);
581
582 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
583 | SSC_BF(TFMR_FSDEN, 0)
584 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
585 | SSC_BF(TFMR_FSLEN, 0)
586 | SSC_BF(TFMR_DATNB, (channels - 1))
587 | SSC_BIT(TFMR_MSBF)
588 | SSC_BF(TFMR_DATDEF, 0)
589 | SSC_BF(TFMR_DATLEN, (bits - 1));
590 break;
591
592 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFS:
593 /* I2S format, CODEC supplies BCLK, SSC supplies LRCLK. */
594 if (bits > 16 && !ssc->pdata->has_fslen_ext) {
595 dev_err(dai->dev,
596 "sample size %d is too large for SSC device\n",
597 bits);
598 return -EINVAL;
599 }
600
601 fslen_ext = (bits - 1) / 16;
602 fslen = (bits - 1) % 16;
603
604 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
605 | SSC_BF(RCMR_STTDLY, START_DELAY)
606 | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
607 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
608 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
609 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
610 SSC_CKS_PIN : SSC_CKS_CLOCK);
611
612 rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
613 | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
614 | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
615 | SSC_BF(RFMR_FSLEN, fslen)
616 | SSC_BF(RFMR_DATNB, (channels - 1))
617 | SSC_BIT(RFMR_MSBF)
618 | SSC_BF(RFMR_LOOP, 0)
619 | SSC_BF(RFMR_DATLEN, (bits - 1));
620
621 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
622 | SSC_BF(TCMR_STTDLY, START_DELAY)
623 | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
624 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
625 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
626 | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
627 SSC_CKS_CLOCK : SSC_CKS_PIN);
628
629 tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
630 | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_NEGATIVE)
631 | SSC_BF(TFMR_FSDEN, 0)
632 | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
633 | SSC_BF(TFMR_FSLEN, fslen)
634 | SSC_BF(TFMR_DATNB, (channels - 1))
635 | SSC_BIT(TFMR_MSBF)
636 | SSC_BF(TFMR_DATDEF, 0)
637 | SSC_BF(TFMR_DATLEN, (bits - 1));
638 break;
639
640 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
641 /*
642 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
643 *
644 * The SSC transmit and receive clocks are generated from the
645 * MCK divider, and the BCLK signal is output
646 * on the SSC TK line.
647 */
648 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
649 | SSC_BF(RCMR_STTDLY, 1)
650 | SSC_BF(RCMR_START, SSC_START_RISING_RF)
651 | SSC_BF(RCMR_CKI, SSC_CKI_FALLING)
652 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
653 | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
654
655 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
656 | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
657 | SSC_BF(RFMR_FSLEN, 0)
658 | SSC_BF(RFMR_DATNB, (channels - 1))
659 | SSC_BIT(RFMR_MSBF)
660 | SSC_BF(RFMR_LOOP, 0)
661 | SSC_BF(RFMR_DATLEN, (bits - 1));
662
663 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
664 | SSC_BF(TCMR_STTDLY, 1)
665 | SSC_BF(TCMR_START, SSC_START_RISING_RF)
666 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
667 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
668 | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
669
670 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
671 | SSC_BF(TFMR_FSDEN, 0)
672 | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
673 | SSC_BF(TFMR_FSLEN, 0)
674 | SSC_BF(TFMR_DATNB, (channels - 1))
675 | SSC_BIT(TFMR_MSBF)
676 | SSC_BF(TFMR_DATDEF, 0)
677 | SSC_BF(TFMR_DATLEN, (bits - 1));
678 break;
679
680 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
681 /*
682 * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks.
683 *
684 * Data is transferred on first BCLK after LRC pulse rising
685 * edge.If stereo, the right channel data is contiguous with
686 * the left channel data.
687 */
688 rcmr = SSC_BF(RCMR_PERIOD, 0)
689 | SSC_BF(RCMR_STTDLY, START_DELAY)
690 | SSC_BF(RCMR_START, SSC_START_RISING_RF)
691 | SSC_BF(RCMR_CKI, SSC_CKI_FALLING)
692 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
693 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
694 SSC_CKS_PIN : SSC_CKS_CLOCK);
695
696 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
697 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
698 | SSC_BF(RFMR_FSLEN, 0)
699 | SSC_BF(RFMR_DATNB, (channels - 1))
700 | SSC_BIT(RFMR_MSBF)
701 | SSC_BF(RFMR_LOOP, 0)
702 | SSC_BF(RFMR_DATLEN, (bits - 1));
703
704 tcmr = SSC_BF(TCMR_PERIOD, 0)
705 | SSC_BF(TCMR_STTDLY, START_DELAY)
706 | SSC_BF(TCMR_START, SSC_START_RISING_RF)
707 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
708 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
709 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
710 SSC_CKS_CLOCK : SSC_CKS_PIN);
711
712 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
713 | SSC_BF(TFMR_FSDEN, 0)
714 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
715 | SSC_BF(TFMR_FSLEN, 0)
716 | SSC_BF(TFMR_DATNB, (channels - 1))
717 | SSC_BIT(TFMR_MSBF)
718 | SSC_BF(TFMR_DATDEF, 0)
719 | SSC_BF(TFMR_DATLEN, (bits - 1));
720 break;
721
722 default:
723 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n",
724 ssc_p->daifmt);
725 return -EINVAL;
726 }
727 pr_debug("atmel_ssc_hw_params: "
728 "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
729 rcmr, rfmr, tcmr, tfmr);
730
731 if (!ssc_p->initialized) {
732 if (!ssc_p->ssc->pdata->use_dma) {
733 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
734 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
735 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
736 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
737
738 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
739 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
740 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
741 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
742 }
743
744 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
745 ssc_p->name, ssc_p);
746 if (ret < 0) {
747 printk(KERN_WARNING
748 "atmel_ssc_dai: request_irq failure\n");
749 pr_debug("Atmel_ssc_dai: Stoping clock\n");
750 clk_disable(ssc_p->ssc->clk);
751 return ret;
752 }
753
754 ssc_p->initialized = 1;
755 }
756
757 /* set SSC clock mode register */
758 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div);
759
760 /* set receive clock mode and format */
761 ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
762 ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
763
764 /* set transmit clock mode and format */
765 ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
766 ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
767
768 pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n");
769 return 0;
770 }
771
772
atmel_ssc_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)773 static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
774 struct snd_soc_dai *dai)
775 {
776 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
777 struct atmel_pcm_dma_params *dma_params;
778 int dir;
779
780 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
781 dir = 0;
782 else
783 dir = 1;
784
785 dma_params = ssc_p->dma_params[dir];
786
787 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
788 ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error);
789
790 pr_debug("%s enabled SSC_SR=0x%08x\n",
791 dir ? "receive" : "transmit",
792 ssc_readl(ssc_p->ssc->regs, SR));
793 return 0;
794 }
795
atmel_ssc_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)796 static int atmel_ssc_trigger(struct snd_pcm_substream *substream,
797 int cmd, struct snd_soc_dai *dai)
798 {
799 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
800 struct atmel_pcm_dma_params *dma_params;
801 int dir;
802
803 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
804 dir = 0;
805 else
806 dir = 1;
807
808 dma_params = ssc_p->dma_params[dir];
809
810 switch (cmd) {
811 case SNDRV_PCM_TRIGGER_START:
812 case SNDRV_PCM_TRIGGER_RESUME:
813 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
814 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
815 break;
816 default:
817 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
818 break;
819 }
820
821 return 0;
822 }
823
824 #ifdef CONFIG_PM
atmel_ssc_suspend(struct snd_soc_dai * cpu_dai)825 static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
826 {
827 struct atmel_ssc_info *ssc_p;
828
829 if (!cpu_dai->active)
830 return 0;
831
832 ssc_p = &ssc_info[cpu_dai->id];
833
834 /* Save the status register before disabling transmit and receive */
835 ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
836 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
837
838 /* Save the current interrupt mask, then disable unmasked interrupts */
839 ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
840 ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
841
842 ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
843 ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
844 ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
845 ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
846 ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
847
848 return 0;
849 }
850
851
852
atmel_ssc_resume(struct snd_soc_dai * cpu_dai)853 static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
854 {
855 struct atmel_ssc_info *ssc_p;
856 u32 cr;
857
858 if (!cpu_dai->active)
859 return 0;
860
861 ssc_p = &ssc_info[cpu_dai->id];
862
863 /* restore SSC register settings */
864 ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
865 ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
866 ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
867 ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
868 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
869
870 /* re-enable interrupts */
871 ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
872
873 /* Re-enable receive and transmit as appropriate */
874 cr = 0;
875 cr |=
876 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
877 cr |=
878 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
879 ssc_writel(ssc_p->ssc->regs, CR, cr);
880
881 return 0;
882 }
883 #else /* CONFIG_PM */
884 # define atmel_ssc_suspend NULL
885 # define atmel_ssc_resume NULL
886 #endif /* CONFIG_PM */
887
888 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
889 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
890
891 static const struct snd_soc_dai_ops atmel_ssc_dai_ops = {
892 .startup = atmel_ssc_startup,
893 .shutdown = atmel_ssc_shutdown,
894 .prepare = atmel_ssc_prepare,
895 .trigger = atmel_ssc_trigger,
896 .hw_params = atmel_ssc_hw_params,
897 .set_fmt = atmel_ssc_set_dai_fmt,
898 .set_clkdiv = atmel_ssc_set_dai_clkdiv,
899 };
900
901 static struct snd_soc_dai_driver atmel_ssc_dai = {
902 .suspend = atmel_ssc_suspend,
903 .resume = atmel_ssc_resume,
904 .playback = {
905 .channels_min = 1,
906 .channels_max = 2,
907 .rates = SNDRV_PCM_RATE_CONTINUOUS,
908 .rate_min = 8000,
909 .rate_max = 384000,
910 .formats = ATMEL_SSC_FORMATS,},
911 .capture = {
912 .channels_min = 1,
913 .channels_max = 2,
914 .rates = SNDRV_PCM_RATE_CONTINUOUS,
915 .rate_min = 8000,
916 .rate_max = 384000,
917 .formats = ATMEL_SSC_FORMATS,},
918 .ops = &atmel_ssc_dai_ops,
919 };
920
921 static const struct snd_soc_component_driver atmel_ssc_component = {
922 .name = "atmel-ssc",
923 };
924
asoc_ssc_init(struct device * dev)925 static int asoc_ssc_init(struct device *dev)
926 {
927 struct platform_device *pdev = to_platform_device(dev);
928 struct ssc_device *ssc = platform_get_drvdata(pdev);
929 int ret;
930
931 ret = snd_soc_register_component(dev, &atmel_ssc_component,
932 &atmel_ssc_dai, 1);
933 if (ret) {
934 dev_err(dev, "Could not register DAI: %d\n", ret);
935 goto err;
936 }
937
938 if (ssc->pdata->use_dma)
939 ret = atmel_pcm_dma_platform_register(dev);
940 else
941 ret = atmel_pcm_pdc_platform_register(dev);
942
943 if (ret) {
944 dev_err(dev, "Could not register PCM: %d\n", ret);
945 goto err_unregister_dai;
946 }
947
948 return 0;
949
950 err_unregister_dai:
951 snd_soc_unregister_component(dev);
952 err:
953 return ret;
954 }
955
asoc_ssc_exit(struct device * dev)956 static void asoc_ssc_exit(struct device *dev)
957 {
958 struct platform_device *pdev = to_platform_device(dev);
959 struct ssc_device *ssc = platform_get_drvdata(pdev);
960
961 if (ssc->pdata->use_dma)
962 atmel_pcm_dma_platform_unregister(dev);
963 else
964 atmel_pcm_pdc_platform_unregister(dev);
965
966 snd_soc_unregister_component(dev);
967 }
968
969 /**
970 * atmel_ssc_set_audio - Allocate the specified SSC for audio use.
971 */
atmel_ssc_set_audio(int ssc_id)972 int atmel_ssc_set_audio(int ssc_id)
973 {
974 struct ssc_device *ssc;
975 int ret;
976
977 /* If we can grab the SSC briefly to parent the DAI device off it */
978 ssc = ssc_request(ssc_id);
979 if (IS_ERR(ssc)) {
980 pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n",
981 PTR_ERR(ssc));
982 return PTR_ERR(ssc);
983 } else {
984 ssc_info[ssc_id].ssc = ssc;
985 }
986
987 ret = asoc_ssc_init(&ssc->pdev->dev);
988
989 return ret;
990 }
991 EXPORT_SYMBOL_GPL(atmel_ssc_set_audio);
992
atmel_ssc_put_audio(int ssc_id)993 void atmel_ssc_put_audio(int ssc_id)
994 {
995 struct ssc_device *ssc = ssc_info[ssc_id].ssc;
996
997 asoc_ssc_exit(&ssc->pdev->dev);
998 ssc_free(ssc);
999 }
1000 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio);
1001
1002 /* Module information */
1003 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com");
1004 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface");
1005 MODULE_LICENSE("GPL");
1006