1 /* Intel Ethernet Switch Host Interface Driver 2 * Copyright(c) 2013 - 2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 19 */ 20 21 #ifndef _FM10K_TYPE_H_ 22 #define _FM10K_TYPE_H_ 23 24 /* forward declaration */ 25 struct fm10k_hw; 26 27 #include <linux/types.h> 28 #include <asm/byteorder.h> 29 #include <linux/etherdevice.h> 30 31 #include "fm10k_mbx.h" 32 33 #define FM10K_DEV_ID_PF 0x15A4 34 #define FM10K_DEV_ID_VF 0x15A5 35 36 #define FM10K_MAX_QUEUES 256 37 #define FM10K_MAX_QUEUES_PF 128 38 #define FM10K_MAX_QUEUES_POOL 16 39 40 #define FM10K_48_BIT_MASK 0x0000FFFFFFFFFFFFull 41 #define FM10K_STAT_VALID 0x80000000 42 43 /* PCI Bus Info */ 44 #define FM10K_PCIE_LINK_CAP 0x7C 45 #define FM10K_PCIE_LINK_STATUS 0x82 46 #define FM10K_PCIE_LINK_WIDTH 0x3F0 47 #define FM10K_PCIE_LINK_WIDTH_1 0x10 48 #define FM10K_PCIE_LINK_WIDTH_2 0x20 49 #define FM10K_PCIE_LINK_WIDTH_4 0x40 50 #define FM10K_PCIE_LINK_WIDTH_8 0x80 51 #define FM10K_PCIE_LINK_SPEED 0xF 52 #define FM10K_PCIE_LINK_SPEED_2500 0x1 53 #define FM10K_PCIE_LINK_SPEED_5000 0x2 54 #define FM10K_PCIE_LINK_SPEED_8000 0x3 55 56 /* PCIe payload size */ 57 #define FM10K_PCIE_DEV_CAP 0x74 58 #define FM10K_PCIE_DEV_CAP_PAYLOAD 0x07 59 #define FM10K_PCIE_DEV_CAP_PAYLOAD_128 0x00 60 #define FM10K_PCIE_DEV_CAP_PAYLOAD_256 0x01 61 #define FM10K_PCIE_DEV_CAP_PAYLOAD_512 0x02 62 #define FM10K_PCIE_DEV_CTRL 0x78 63 #define FM10K_PCIE_DEV_CTRL_PAYLOAD 0xE0 64 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_128 0x00 65 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_256 0x20 66 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_512 0x40 67 68 /* PCIe MSI-X Capability info */ 69 #define FM10K_PCI_MSIX_MSG_CTRL 0xB2 70 #define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK 0x7FF 71 #define FM10K_MAX_MSIX_VECTORS 256 72 #define FM10K_MAX_VECTORS_PF 256 73 #define FM10K_MAX_VECTORS_POOL 32 74 75 /* PCIe SR-IOV Info */ 76 #define FM10K_PCIE_SRIOV_CTRL 0x190 77 #define FM10K_PCIE_SRIOV_CTRL_VFARI 0x10 78 79 #define FM10K_ERR_PARAM -2 80 #define FM10K_ERR_NO_RESOURCES -3 81 #define FM10K_ERR_REQUESTS_PENDING -4 82 #define FM10K_ERR_RESET_REQUESTED -5 83 #define FM10K_ERR_DMA_PENDING -6 84 #define FM10K_ERR_RESET_FAILED -7 85 #define FM10K_ERR_INVALID_MAC_ADDR -8 86 #define FM10K_ERR_INVALID_VALUE -9 87 #define FM10K_NOT_IMPLEMENTED 0x7FFFFFFF 88 89 /* Start of PF registers */ 90 #define FM10K_CTRL 0x0000 91 #define FM10K_CTRL_BAR4_ALLOWED 0x00000004 92 93 #define FM10K_CTRL_EXT 0x0001 94 #define FM10K_GCR 0x0003 95 #define FM10K_GCR_EXT 0x0005 96 97 /* Interrupt control registers */ 98 #define FM10K_EICR 0x0006 99 #define FM10K_EICR_FAULT_MASK 0x0000003F 100 #define FM10K_EICR_MAILBOX 0x00000040 101 #define FM10K_EICR_SWITCHREADY 0x00000080 102 #define FM10K_EICR_SWITCHNOTREADY 0x00000100 103 #define FM10K_EICR_SWITCHINTERRUPT 0x00000200 104 #define FM10K_EICR_VFLR 0x00000800 105 #define FM10K_EICR_MAXHOLDTIME 0x00001000 106 #define FM10K_EIMR 0x0007 107 #define FM10K_EIMR_PCA_FAULT 0x00000001 108 #define FM10K_EIMR_THI_FAULT 0x00000010 109 #define FM10K_EIMR_FUM_FAULT 0x00000400 110 #define FM10K_EIMR_MAILBOX 0x00001000 111 #define FM10K_EIMR_SWITCHREADY 0x00004000 112 #define FM10K_EIMR_SWITCHNOTREADY 0x00010000 113 #define FM10K_EIMR_SWITCHINTERRUPT 0x00040000 114 #define FM10K_EIMR_SRAMERROR 0x00100000 115 #define FM10K_EIMR_VFLR 0x00400000 116 #define FM10K_EIMR_MAXHOLDTIME 0x01000000 117 #define FM10K_EIMR_ALL 0x55555555 118 #define FM10K_EIMR_DISABLE(NAME) ((FM10K_EIMR_ ## NAME) << 0) 119 #define FM10K_EIMR_ENABLE(NAME) ((FM10K_EIMR_ ## NAME) << 1) 120 #define FM10K_FAULT_ADDR_LO 0x0 121 #define FM10K_FAULT_ADDR_HI 0x1 122 #define FM10K_FAULT_SPECINFO 0x2 123 #define FM10K_FAULT_FUNC 0x3 124 #define FM10K_FAULT_SIZE 0x4 125 #define FM10K_FAULT_FUNC_VALID 0x00008000 126 #define FM10K_FAULT_FUNC_PF 0x00004000 127 #define FM10K_FAULT_FUNC_VF_MASK 0x00003F00 128 #define FM10K_FAULT_FUNC_VF_SHIFT 8 129 #define FM10K_FAULT_FUNC_TYPE_MASK 0x000000FF 130 131 #define FM10K_PCA_FAULT 0x0008 132 #define FM10K_THI_FAULT 0x0010 133 #define FM10K_FUM_FAULT 0x001C 134 135 /* Rx queue timeout indicator */ 136 #define FM10K_MAXHOLDQ(_n) ((_n) + 0x0020) 137 138 /* Switch Manager info */ 139 #define FM10K_SM_AREA(_n) ((_n) + 0x0028) 140 141 /* GLORT mapping registers */ 142 #define FM10K_DGLORTMAP(_n) ((_n) + 0x0030) 143 #define FM10K_DGLORT_COUNT 8 144 #define FM10K_DGLORTMAP_MASK_SHIFT 16 145 #define FM10K_DGLORTMAP_ANY 0x00000000 146 #define FM10K_DGLORTMAP_NONE 0x0000FFFF 147 #define FM10K_DGLORTMAP_ZERO 0xFFFF0000 148 #define FM10K_DGLORTDEC(_n) ((_n) + 0x0038) 149 #define FM10K_DGLORTDEC_VSILENGTH_SHIFT 4 150 #define FM10K_DGLORTDEC_VSIBASE_SHIFT 7 151 #define FM10K_DGLORTDEC_PCLENGTH_SHIFT 14 152 #define FM10K_DGLORTDEC_QBASE_SHIFT 16 153 #define FM10K_DGLORTDEC_RSSLENGTH_SHIFT 24 154 #define FM10K_DGLORTDEC_INNERRSS_ENABLE 0x08000000 155 #define FM10K_TUNNEL_CFG 0x0040 156 #define FM10K_TUNNEL_CFG_NVGRE_SHIFT 16 157 #define FM10K_SWPRI_MAP(_n) ((_n) + 0x0050) 158 #define FM10K_SWPRI_MAX 16 159 #define FM10K_RSSRK(_n, _m) (((_n) * 0x10) + (_m) + 0x0800) 160 #define FM10K_RSSRK_SIZE 10 161 #define FM10K_RSSRK_ENTRIES_PER_REG 4 162 #define FM10K_RETA(_n, _m) (((_n) * 0x20) + (_m) + 0x1000) 163 #define FM10K_RETA_SIZE 32 164 #define FM10K_RETA_ENTRIES_PER_REG 4 165 #define FM10K_MAX_RSS_INDICES 128 166 167 /* Rate limiting registers */ 168 #define FM10K_TC_CREDIT(_n) ((_n) + 0x2000) 169 #define FM10K_TC_CREDIT_CREDIT_MASK 0x001FFFFF 170 #define FM10K_TC_MAXCREDIT(_n) ((_n) + 0x2040) 171 #define FM10K_TC_MAXCREDIT_64K 0x00010000 172 #define FM10K_TC_RATE(_n) ((_n) + 0x2080) 173 #define FM10K_TC_RATE_QUANTA_MASK 0x0000FFFF 174 #define FM10K_TC_RATE_INTERVAL_4US_GEN1 0x00020000 175 #define FM10K_TC_RATE_INTERVAL_4US_GEN2 0x00040000 176 #define FM10K_TC_RATE_INTERVAL_4US_GEN3 0x00080000 177 178 /* DMA control registers */ 179 #define FM10K_DMA_CTRL 0x20C3 180 #define FM10K_DMA_CTRL_TX_ENABLE 0x00000001 181 #define FM10K_DMA_CTRL_TX_ACTIVE 0x00000008 182 #define FM10K_DMA_CTRL_RX_ENABLE 0x00000010 183 #define FM10K_DMA_CTRL_RX_ACTIVE 0x00000080 184 #define FM10K_DMA_CTRL_RX_DESC_SIZE 0x00000100 185 #define FM10K_DMA_CTRL_MINMSS_64 0x00008000 186 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 0x04800000 187 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 0x04000000 188 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1 0x03800000 189 #define FM10K_DMA_CTRL_DATAPATH_RESET 0x20000000 190 #define FM10K_DMA_CTRL_32_DESC 0x00000000 191 192 #define FM10K_DMA_CTRL2 0x20C4 193 #define FM10K_DMA_CTRL2_SWITCH_READY 0x00002000 194 195 /* TSO flags configuration 196 * First packet contains all flags except for fin and psh 197 * Middle packet contains only urg and ack 198 * Last packet contains urg, ack, fin, and psh 199 */ 200 #define FM10K_TSO_FLAGS_LOW 0x00300FF6 201 #define FM10K_TSO_FLAGS_HI 0x00000039 202 #define FM10K_DTXTCPFLGL 0x20C5 203 #define FM10K_DTXTCPFLGH 0x20C6 204 205 #define FM10K_TPH_CTRL 0x20C7 206 #define FM10K_MRQC(_n) ((_n) + 0x2100) 207 #define FM10K_MRQC_TCP_IPV4 0x00000001 208 #define FM10K_MRQC_IPV4 0x00000002 209 #define FM10K_MRQC_IPV6 0x00000010 210 #define FM10K_MRQC_TCP_IPV6 0x00000020 211 #define FM10K_MRQC_UDP_IPV4 0x00000040 212 #define FM10K_MRQC_UDP_IPV6 0x00000080 213 214 #define FM10K_TQMAP(_n) ((_n) + 0x2800) 215 #define FM10K_TQMAP_TABLE_SIZE 2048 216 #define FM10K_RQMAP(_n) ((_n) + 0x3000) 217 218 /* Hardware Statistics */ 219 #define FM10K_STATS_TIMEOUT 0x3800 220 #define FM10K_STATS_UR 0x3801 221 #define FM10K_STATS_CA 0x3802 222 #define FM10K_STATS_UM 0x3803 223 #define FM10K_STATS_XEC 0x3804 224 #define FM10K_STATS_VLAN_DROP 0x3805 225 #define FM10K_STATS_LOOPBACK_DROP 0x3806 226 #define FM10K_STATS_NODESC_DROP 0x3807 227 228 /* Timesync registers */ 229 #define FM10K_SYSTIME 0x3814 230 #define FM10K_SYSTIME_CFG 0x3818 231 #define FM10K_SYSTIME_CFG_STEP_MASK 0x0000000F 232 233 /* PCIe state registers */ 234 #define FM10K_PHYADDR 0x381C 235 236 /* Rx ring registers */ 237 #define FM10K_RDBAL(_n) ((0x40 * (_n)) + 0x4000) 238 #define FM10K_RDBAH(_n) ((0x40 * (_n)) + 0x4001) 239 #define FM10K_RDLEN(_n) ((0x40 * (_n)) + 0x4002) 240 #define FM10K_TPH_RXCTRL(_n) ((0x40 * (_n)) + 0x4003) 241 #define FM10K_TPH_RXCTRL_DESC_TPHEN 0x00000020 242 #define FM10K_TPH_RXCTRL_DESC_RROEN 0x00000200 243 #define FM10K_TPH_RXCTRL_DATA_WROEN 0x00002000 244 #define FM10K_TPH_RXCTRL_HDR_WROEN 0x00008000 245 #define FM10K_RDH(_n) ((0x40 * (_n)) + 0x4004) 246 #define FM10K_RDT(_n) ((0x40 * (_n)) + 0x4005) 247 #define FM10K_RXQCTL(_n) ((0x40 * (_n)) + 0x4006) 248 #define FM10K_RXQCTL_ENABLE 0x00000001 249 #define FM10K_RXQCTL_PF 0x000000FC 250 #define FM10K_RXQCTL_VF_SHIFT 2 251 #define FM10K_RXQCTL_VF 0x00000100 252 #define FM10K_RXQCTL_ID_MASK (FM10K_RXQCTL_PF | FM10K_RXQCTL_VF) 253 #define FM10K_RXDCTL(_n) ((0x40 * (_n)) + 0x4007) 254 #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY 0x00000001 255 #define FM10K_RXDCTL_DROP_ON_EMPTY 0x00000200 256 #define FM10K_RXINT(_n) ((0x40 * (_n)) + 0x4008) 257 #define FM10K_SRRCTL(_n) ((0x40 * (_n)) + 0x4009) 258 #define FM10K_SRRCTL_BSIZEPKT_SHIFT 8 /* shift _right_ */ 259 #define FM10K_SRRCTL_LOOPBACK_SUPPRESS 0x40000000 260 #define FM10K_SRRCTL_BUFFER_CHAINING_EN 0x80000000 261 262 /* Rx Statistics */ 263 #define FM10K_QPRC(_n) ((0x40 * (_n)) + 0x400A) 264 #define FM10K_QPRDC(_n) ((0x40 * (_n)) + 0x400B) 265 #define FM10K_QBRC_L(_n) ((0x40 * (_n)) + 0x400C) 266 #define FM10K_QBRC_H(_n) ((0x40 * (_n)) + 0x400D) 267 268 /* Rx GLORT register */ 269 #define FM10K_RX_SGLORT(_n) ((0x40 * (_n)) + 0x400E) 270 271 /* Tx ring registers */ 272 #define FM10K_TDBAL(_n) ((0x40 * (_n)) + 0x8000) 273 #define FM10K_TDBAH(_n) ((0x40 * (_n)) + 0x8001) 274 #define FM10K_TDLEN(_n) ((0x40 * (_n)) + 0x8002) 275 #define FM10K_TPH_TXCTRL(_n) ((0x40 * (_n)) + 0x8003) 276 #define FM10K_TPH_TXCTRL_DESC_TPHEN 0x00000020 277 #define FM10K_TPH_TXCTRL_DESC_RROEN 0x00000200 278 #define FM10K_TPH_TXCTRL_DESC_WROEN 0x00000800 279 #define FM10K_TPH_TXCTRL_DATA_RROEN 0x00002000 280 #define FM10K_TDH(_n) ((0x40 * (_n)) + 0x8004) 281 #define FM10K_TDT(_n) ((0x40 * (_n)) + 0x8005) 282 #define FM10K_TXDCTL(_n) ((0x40 * (_n)) + 0x8006) 283 #define FM10K_TXDCTL_ENABLE 0x00004000 284 #define FM10K_TXDCTL_MAX_TIME_SHIFT 16 285 #define FM10K_TXQCTL(_n) ((0x40 * (_n)) + 0x8007) 286 #define FM10K_TXQCTL_PF 0x0000003F 287 #define FM10K_TXQCTL_VF 0x00000040 288 #define FM10K_TXQCTL_ID_MASK (FM10K_TXQCTL_PF | FM10K_TXQCTL_VF) 289 #define FM10K_TXQCTL_PC_SHIFT 7 290 #define FM10K_TXQCTL_PC_MASK 0x00000380 291 #define FM10K_TXQCTL_TC_SHIFT 10 292 #define FM10K_TXQCTL_VID_SHIFT 16 293 #define FM10K_TXQCTL_VID_MASK 0x0FFF0000 294 #define FM10K_TXQCTL_UNLIMITED_BW 0x10000000 295 #define FM10K_TXINT(_n) ((0x40 * (_n)) + 0x8008) 296 297 /* Tx Statistics */ 298 #define FM10K_QPTC(_n) ((0x40 * (_n)) + 0x8009) 299 #define FM10K_QBTC_L(_n) ((0x40 * (_n)) + 0x800A) 300 #define FM10K_QBTC_H(_n) ((0x40 * (_n)) + 0x800B) 301 302 /* Tx Push registers */ 303 #define FM10K_TQDLOC(_n) ((0x40 * (_n)) + 0x800C) 304 #define FM10K_TQDLOC_BASE_32_DESC 0x08 305 #define FM10K_TQDLOC_SIZE_32_DESC 0x00050000 306 307 /* Tx GLORT registers */ 308 #define FM10K_TX_SGLORT(_n) ((0x40 * (_n)) + 0x800D) 309 #define FM10K_PFVTCTL(_n) ((0x40 * (_n)) + 0x800E) 310 #define FM10K_PFVTCTL_FTAG_DESC_ENABLE 0x00000001 311 312 /* Interrupt moderation and control registers */ 313 #define FM10K_INT_MAP(_n) ((_n) + 0x10080) 314 #define FM10K_INT_MAP_TIMER0 0x00000000 315 #define FM10K_INT_MAP_TIMER1 0x00000100 316 #define FM10K_INT_MAP_IMMEDIATE 0x00000200 317 #define FM10K_INT_MAP_DISABLE 0x00000300 318 #define FM10K_MSIX_VECTOR_MASK(_n) ((0x4 * (_n)) + 0x11003) 319 #define FM10K_INT_CTRL 0x12000 320 #define FM10K_INT_CTRL_ENABLEMODERATOR 0x00000400 321 #define FM10K_ITR(_n) ((_n) + 0x12400) 322 #define FM10K_ITR_INTERVAL1_SHIFT 12 323 #define FM10K_ITR_PENDING2 0x10000000 324 #define FM10K_ITR_AUTOMASK 0x20000000 325 #define FM10K_ITR_MASK_SET 0x40000000 326 #define FM10K_ITR_MASK_CLEAR 0x80000000 327 #define FM10K_ITR2(_n) ((0x2 * (_n)) + 0x12800) 328 #define FM10K_ITR_REG_COUNT 768 329 #define FM10K_ITR_REG_COUNT_PF 256 330 331 /* Switch manager interrupt registers */ 332 #define FM10K_IP 0x13000 333 #define FM10K_IP_NOTINRESET 0x00000100 334 335 /* VLAN registers */ 336 #define FM10K_VLAN_TABLE(_n, _m) ((0x80 * (_n)) + (_m) + 0x14000) 337 #define FM10K_VLAN_TABLE_SIZE 128 338 339 /* VLAN specific message offsets */ 340 #define FM10K_VLAN_TABLE_VID_MAX 4096 341 #define FM10K_VLAN_TABLE_VSI_MAX 64 342 #define FM10K_VLAN_LENGTH_SHIFT 16 343 #define FM10K_VLAN_CLEAR (1 << 15) 344 #define FM10K_VLAN_ALL \ 345 ((FM10K_VLAN_TABLE_VID_MAX - 1) << FM10K_VLAN_LENGTH_SHIFT) 346 347 /* VF FLR event notification registers */ 348 #define FM10K_PFVFLRE(_n) ((0x1 * (_n)) + 0x18844) 349 #define FM10K_PFVFLREC(_n) ((0x1 * (_n)) + 0x18846) 350 351 /* Defines for size of uncacheable memories */ 352 #define FM10K_UC_ADDR_START 0x000000 /* start of standard regs */ 353 #define FM10K_UC_ADDR_END 0x100000 /* end of standard regs */ 354 #define FM10K_UC_ADDR_SIZE (FM10K_UC_ADDR_END - FM10K_UC_ADDR_START) 355 356 /* Define timeouts for resets and disables */ 357 #define FM10K_QUEUE_DISABLE_TIMEOUT 100 358 #define FM10K_RESET_TIMEOUT 150 359 360 /* Maximum supported combined inner and outer header length for encapsulation */ 361 #define FM10K_TUNNEL_HEADER_LENGTH 184 362 363 /* VF registers */ 364 #define FM10K_VFCTRL 0x00000 365 #define FM10K_VFCTRL_RST 0x00000008 366 #define FM10K_VFINT_MAP 0x00030 367 #define FM10K_VFSYSTIME 0x00040 368 #define FM10K_VFITR(_n) ((_n) + 0x00060) 369 370 /* Registers contained in BAR 4 for Switch management */ 371 #define FM10K_SW_SYSTIME_ADJUST 0x0224D 372 #define FM10K_SW_SYSTIME_ADJUST_MASK 0x3FFFFFFF 373 #define FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE 0x80000000 374 #define FM10K_SW_SYSTIME_PULSE(_n) ((_n) + 0x02252) 375 376 enum fm10k_int_source { 377 fm10k_int_Mailbox = 0, 378 fm10k_int_PCIeFault = 1, 379 fm10k_int_SwitchUpDown = 2, 380 fm10k_int_SwitchEvent = 3, 381 fm10k_int_SRAM = 4, 382 fm10k_int_VFLR = 5, 383 fm10k_int_MaxHoldTime = 6, 384 fm10k_int_sources_max_pf 385 }; 386 387 /* PCIe bus speeds */ 388 enum fm10k_bus_speed { 389 fm10k_bus_speed_unknown = 0, 390 fm10k_bus_speed_2500 = 2500, 391 fm10k_bus_speed_5000 = 5000, 392 fm10k_bus_speed_8000 = 8000, 393 fm10k_bus_speed_reserved 394 }; 395 396 /* PCIe bus widths */ 397 enum fm10k_bus_width { 398 fm10k_bus_width_unknown = 0, 399 fm10k_bus_width_pcie_x1 = 1, 400 fm10k_bus_width_pcie_x2 = 2, 401 fm10k_bus_width_pcie_x4 = 4, 402 fm10k_bus_width_pcie_x8 = 8, 403 fm10k_bus_width_reserved 404 }; 405 406 /* PCIe payload sizes */ 407 enum fm10k_bus_payload { 408 fm10k_bus_payload_unknown = 0, 409 fm10k_bus_payload_128 = 1, 410 fm10k_bus_payload_256 = 2, 411 fm10k_bus_payload_512 = 3, 412 fm10k_bus_payload_reserved 413 }; 414 415 /* Bus parameters */ 416 struct fm10k_bus_info { 417 enum fm10k_bus_speed speed; 418 enum fm10k_bus_width width; 419 enum fm10k_bus_payload payload; 420 }; 421 422 /* Statistics related declarations */ 423 struct fm10k_hw_stat { 424 u64 count; 425 u32 base_l; 426 u32 base_h; 427 }; 428 429 struct fm10k_hw_stats_q { 430 struct fm10k_hw_stat tx_bytes; 431 struct fm10k_hw_stat tx_packets; 432 #define tx_stats_idx tx_packets.base_h 433 struct fm10k_hw_stat rx_bytes; 434 struct fm10k_hw_stat rx_packets; 435 #define rx_stats_idx rx_packets.base_h 436 struct fm10k_hw_stat rx_drops; 437 }; 438 439 struct fm10k_hw_stats { 440 struct fm10k_hw_stat timeout; 441 #define stats_idx timeout.base_h 442 struct fm10k_hw_stat ur; 443 struct fm10k_hw_stat ca; 444 struct fm10k_hw_stat um; 445 struct fm10k_hw_stat xec; 446 struct fm10k_hw_stat vlan_drop; 447 struct fm10k_hw_stat loopback_drop; 448 struct fm10k_hw_stat nodesc_drop; 449 struct fm10k_hw_stats_q q[FM10K_MAX_QUEUES_PF]; 450 }; 451 452 /* Establish DGLORT feature priority */ 453 enum fm10k_dglortdec_idx { 454 fm10k_dglort_default = 0, 455 fm10k_dglort_vf_rsvd0 = 1, 456 fm10k_dglort_vf_rss = 2, 457 fm10k_dglort_pf_rsvd0 = 3, 458 fm10k_dglort_pf_queue = 4, 459 fm10k_dglort_pf_vsi = 5, 460 fm10k_dglort_pf_rsvd1 = 6, 461 fm10k_dglort_pf_rss = 7 462 }; 463 464 struct fm10k_dglort_cfg { 465 u16 glort; /* GLORT base */ 466 u16 queue_b; /* Base value for queue */ 467 u8 vsi_b; /* Base value for VSI */ 468 u8 idx; /* index of DGLORTDEC entry */ 469 u8 rss_l; /* RSS indices */ 470 u8 pc_l; /* Priority Class indices */ 471 u8 vsi_l; /* Number of bits from GLORT used to determine VSI */ 472 u8 queue_l; /* Number of bits from GLORT used to determine queue */ 473 u8 shared_l; /* Ignored bits from GLORT resulting in shared VSI */ 474 u8 inner_rss; /* Boolean value if inner header is used for RSS */ 475 }; 476 477 enum fm10k_pca_fault { 478 PCA_NO_FAULT, 479 PCA_UNMAPPED_ADDR, 480 PCA_BAD_QACCESS_PF, 481 PCA_BAD_QACCESS_VF, 482 PCA_MALICIOUS_REQ, 483 PCA_POISONED_TLP, 484 PCA_TLP_ABORT, 485 __PCA_MAX 486 }; 487 488 enum fm10k_thi_fault { 489 THI_NO_FAULT, 490 THI_MAL_DIS_Q_FAULT, 491 __THI_MAX 492 }; 493 494 enum fm10k_fum_fault { 495 FUM_NO_FAULT, 496 FUM_UNMAPPED_ADDR, 497 FUM_POISONED_TLP, 498 FUM_BAD_VF_QACCESS, 499 FUM_ADD_DECODE_ERR, 500 FUM_RO_ERROR, 501 FUM_QPRC_CRC_ERROR, 502 FUM_CSR_TIMEOUT, 503 FUM_INVALID_TYPE, 504 FUM_INVALID_LENGTH, 505 FUM_INVALID_BE, 506 FUM_INVALID_ALIGN, 507 __FUM_MAX 508 }; 509 510 struct fm10k_fault { 511 u64 address; /* Address at the time fault was detected */ 512 u32 specinfo; /* Extra info on this fault (fault dependent) */ 513 u8 type; /* Fault value dependent on subunit */ 514 u8 func; /* Function number of the fault */ 515 }; 516 517 struct fm10k_mac_ops { 518 /* basic bring-up and tear-down */ 519 s32 (*reset_hw)(struct fm10k_hw *); 520 s32 (*init_hw)(struct fm10k_hw *); 521 s32 (*start_hw)(struct fm10k_hw *); 522 s32 (*stop_hw)(struct fm10k_hw *); 523 s32 (*get_bus_info)(struct fm10k_hw *); 524 s32 (*get_host_state)(struct fm10k_hw *, bool *); 525 s32 (*update_vlan)(struct fm10k_hw *, u32, u8, bool); 526 s32 (*read_mac_addr)(struct fm10k_hw *); 527 s32 (*update_uc_addr)(struct fm10k_hw *, u16, const u8 *, 528 u16, bool, u8); 529 s32 (*update_mc_addr)(struct fm10k_hw *, u16, const u8 *, u16, bool); 530 s32 (*update_xcast_mode)(struct fm10k_hw *, u16, u8); 531 void (*update_int_moderator)(struct fm10k_hw *); 532 s32 (*update_lport_state)(struct fm10k_hw *, u16, u16, bool); 533 void (*update_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *); 534 void (*rebind_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *); 535 s32 (*configure_dglort_map)(struct fm10k_hw *, 536 struct fm10k_dglort_cfg *); 537 void (*set_dma_mask)(struct fm10k_hw *, u64); 538 s32 (*get_fault)(struct fm10k_hw *, int, struct fm10k_fault *); 539 void (*request_lport_map)(struct fm10k_hw *); 540 s32 (*adjust_systime)(struct fm10k_hw *, s32 ppb); 541 u64 (*read_systime)(struct fm10k_hw *); 542 }; 543 544 enum fm10k_mac_type { 545 fm10k_mac_unknown = 0, 546 fm10k_mac_pf, 547 fm10k_mac_vf, 548 fm10k_num_macs 549 }; 550 551 struct fm10k_mac_info { 552 struct fm10k_mac_ops ops; 553 enum fm10k_mac_type type; 554 u8 addr[ETH_ALEN]; 555 u8 perm_addr[ETH_ALEN]; 556 u16 default_vid; 557 u16 max_msix_vectors; 558 u16 max_queues; 559 bool vlan_override; 560 bool get_host_state; 561 bool tx_ready; 562 u32 dglort_map; 563 }; 564 565 struct fm10k_swapi_table_info { 566 u32 used; 567 u32 avail; 568 }; 569 570 struct fm10k_swapi_info { 571 u32 status; 572 struct fm10k_swapi_table_info mac; 573 struct fm10k_swapi_table_info nexthop; 574 struct fm10k_swapi_table_info ffu; 575 }; 576 577 enum fm10k_xcast_modes { 578 FM10K_XCAST_MODE_ALLMULTI = 0, 579 FM10K_XCAST_MODE_MULTI = 1, 580 FM10K_XCAST_MODE_PROMISC = 2, 581 FM10K_XCAST_MODE_NONE = 3, 582 FM10K_XCAST_MODE_DISABLE = 4 583 }; 584 585 #define FM10K_VF_TC_MAX 100000 /* 100,000 Mb/s aka 100Gb/s */ 586 #define FM10K_VF_TC_MIN 1 /* 1 Mb/s is the slowest rate */ 587 588 struct fm10k_vf_info { 589 /* mbx must be first field in struct unless all default IOV message 590 * handlers are redone as the assumption is that vf_info starts 591 * at the same offset as the mailbox 592 */ 593 struct fm10k_mbx_info mbx; /* PF side of VF mailbox */ 594 int rate; /* Tx BW cap as defined by OS */ 595 u16 glort; /* resource tag for this VF */ 596 u16 sw_vid; /* Switch API assigned VLAN */ 597 u16 pf_vid; /* PF assigned Default VLAN */ 598 u8 mac[ETH_ALEN]; /* PF Default MAC address */ 599 u8 vsi; /* VSI identifier */ 600 u8 vf_idx; /* which VF this is */ 601 u8 vf_flags; /* flags indicating what modes 602 * are supported for the port 603 */ 604 }; 605 606 #define FM10K_VF_FLAG_ALLMULTI_CAPABLE ((u8)1 << FM10K_XCAST_MODE_ALLMULTI) 607 #define FM10K_VF_FLAG_MULTI_CAPABLE ((u8)1 << FM10K_XCAST_MODE_MULTI) 608 #define FM10K_VF_FLAG_PROMISC_CAPABLE ((u8)1 << FM10K_XCAST_MODE_PROMISC) 609 #define FM10K_VF_FLAG_NONE_CAPABLE ((u8)1 << FM10K_XCAST_MODE_NONE) 610 #define FM10K_VF_FLAG_CAPABLE(vf_info) ((vf_info)->vf_flags & (u8)0xF) 611 #define FM10K_VF_FLAG_ENABLED(vf_info) ((vf_info)->vf_flags >> 4) 612 #define FM10K_VF_FLAG_SET_MODE(mode) ((u8)0x10 << (mode)) 613 #define FM10K_VF_FLAG_SET_MODE_NONE \ 614 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE) 615 #define FM10K_VF_FLAG_MULTI_ENABLED \ 616 (FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_ALLMULTI) | \ 617 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_MULTI) | \ 618 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_PROMISC)) 619 620 struct fm10k_iov_ops { 621 /* IOV related bring-up and tear-down */ 622 s32 (*assign_resources)(struct fm10k_hw *, u16, u16); 623 s32 (*configure_tc)(struct fm10k_hw *, u16, int); 624 s32 (*assign_int_moderator)(struct fm10k_hw *, u16); 625 s32 (*assign_default_mac_vlan)(struct fm10k_hw *, 626 struct fm10k_vf_info *); 627 s32 (*reset_resources)(struct fm10k_hw *, 628 struct fm10k_vf_info *); 629 s32 (*set_lport)(struct fm10k_hw *, struct fm10k_vf_info *, u16, u8); 630 void (*reset_lport)(struct fm10k_hw *, struct fm10k_vf_info *); 631 void (*update_stats)(struct fm10k_hw *, struct fm10k_hw_stats_q *, u16); 632 s32 (*report_timestamp)(struct fm10k_hw *, struct fm10k_vf_info *, u64); 633 }; 634 635 struct fm10k_iov_info { 636 struct fm10k_iov_ops ops; 637 u16 total_vfs; 638 u16 num_vfs; 639 u16 num_pools; 640 }; 641 642 enum fm10k_devices { 643 fm10k_device_pf, 644 fm10k_device_vf, 645 }; 646 647 struct fm10k_info { 648 enum fm10k_mac_type mac; 649 s32 (*get_invariants)(struct fm10k_hw *); 650 struct fm10k_mac_ops *mac_ops; 651 struct fm10k_iov_ops *iov_ops; 652 }; 653 654 struct fm10k_hw { 655 u32 __iomem *hw_addr; 656 u32 __iomem *sw_addr; 657 void *back; 658 struct fm10k_mac_info mac; 659 struct fm10k_bus_info bus; 660 struct fm10k_bus_info bus_caps; 661 struct fm10k_iov_info iov; 662 struct fm10k_mbx_info mbx; 663 struct fm10k_swapi_info swapi; 664 u16 device_id; 665 u16 vendor_id; 666 u16 subsystem_device_id; 667 u16 subsystem_vendor_id; 668 u8 revision_id; 669 }; 670 671 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 672 #define FM10K_REQ_TX_DESCRIPTOR_MULTIPLE 8 673 #define FM10K_REQ_RX_DESCRIPTOR_MULTIPLE 8 674 675 /* Transmit Descriptor */ 676 struct fm10k_tx_desc { 677 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 678 __le16 buflen; /* Length of data to be DMAed */ 679 __le16 vlan; /* VLAN_ID and VPRI to be inserted in FTAG */ 680 __le16 mss; /* MSS for segmentation offload */ 681 u8 hdrlen; /* Header size for segmentation offload */ 682 u8 flags; /* Status and offload request flags */ 683 }; 684 685 /* Transmit Descriptor Cache Structure */ 686 struct fm10k_tx_desc_cache { 687 struct fm10k_tx_desc tx_desc[256]; 688 }; 689 690 #define FM10K_TXD_FLAG_INT 0x01 691 #define FM10K_TXD_FLAG_TIME 0x02 692 #define FM10K_TXD_FLAG_CSUM 0x04 693 #define FM10K_TXD_FLAG_FTAG 0x10 694 #define FM10K_TXD_FLAG_RS 0x20 695 #define FM10K_TXD_FLAG_LAST 0x40 696 #define FM10K_TXD_FLAG_DONE 0x80 697 698 /* These macros are meant to enable optimal placement of the RS and INT 699 * bits. It will point us to the last descriptor in the cache for either the 700 * start of the packet, or the end of the packet. If the index is actually 701 * at the start of the FIFO it will point to the offset for the last index 702 * in the FIFO to prevent an unnecessary write. 703 */ 704 #define FM10K_TXD_WB_FIFO_SIZE 4 705 706 /* Receive Descriptor - 32B */ 707 union fm10k_rx_desc { 708 struct { 709 __le64 pkt_addr; /* Packet buffer address */ 710 __le64 hdr_addr; /* Header buffer address */ 711 __le64 reserved; /* Empty space, RSS hash */ 712 __le64 timestamp; 713 } q; /* Read, Writeback, 64b quad-words */ 714 struct { 715 __le32 data; /* RSS and header data */ 716 __le32 rss; /* RSS Hash */ 717 __le32 staterr; 718 __le32 vlan_len; 719 __le32 glort; /* sglort/dglort */ 720 } d; /* Writeback, 32b double-words */ 721 struct { 722 __le16 pkt_info; /* RSS, Pkt type */ 723 __le16 hdr_info; /* Splithdr, hdrlen, xC */ 724 __le16 rss_lower; 725 __le16 rss_upper; 726 __le16 status; /* status/error */ 727 __le16 csum_err; /* checksum or extended error value */ 728 __le16 length; /* Packet length */ 729 __le16 vlan; /* VLAN tag */ 730 __le16 dglort; 731 __le16 sglort; 732 } w; /* Writeback, 16b words */ 733 }; 734 735 #define FM10K_RXD_RSSTYPE_MASK 0x000F 736 enum fm10k_rdesc_rss_type { 737 FM10K_RSSTYPE_NONE = 0x0, 738 FM10K_RSSTYPE_IPV4_TCP = 0x1, 739 FM10K_RSSTYPE_IPV4 = 0x2, 740 FM10K_RSSTYPE_IPV6_TCP = 0x3, 741 /* Reserved 0x4 */ 742 FM10K_RSSTYPE_IPV6 = 0x5, 743 /* Reserved 0x6 */ 744 FM10K_RSSTYPE_IPV4_UDP = 0x7, 745 FM10K_RSSTYPE_IPV6_UDP = 0x8 746 /* Reserved 0x9 - 0xF */ 747 }; 748 749 #define FM10K_RXD_HDR_INFO_XC_MASK 0x0006 750 enum fm10k_rxdesc_xc { 751 FM10K_XC_UNICAST = 0x0, 752 FM10K_XC_MULTICAST = 0x4, 753 FM10K_XC_BROADCAST = 0x6 754 }; 755 756 #define FM10K_RXD_STATUS_DD 0x0001 /* Descriptor done */ 757 #define FM10K_RXD_STATUS_EOP 0x0002 /* End of packet */ 758 #define FM10K_RXD_STATUS_L4CS 0x0010 /* Indicates an L4 csum */ 759 #define FM10K_RXD_STATUS_L4CS2 0x0040 /* Inner header L4 csum */ 760 #define FM10K_RXD_STATUS_L4E2 0x0800 /* Inner header L4 csum err */ 761 #define FM10K_RXD_STATUS_IPE2 0x1000 /* Inner header IPv4 csum err */ 762 #define FM10K_RXD_STATUS_RXE 0x2000 /* Generic Rx error */ 763 #define FM10K_RXD_STATUS_L4E 0x4000 /* L4 csum error */ 764 #define FM10K_RXD_STATUS_IPE 0x8000 /* IPv4 csum error */ 765 766 #define FM10K_RXD_ERR_SWITCH_ERROR 0x0001 /* Switch found bad packet */ 767 #define FM10K_RXD_ERR_NO_DESCRIPTOR 0x0002 /* No descriptor available */ 768 #define FM10K_RXD_ERR_PP_ERROR 0x0004 /* RAM error during processing */ 769 #define FM10K_RXD_ERR_SWITCH_READY 0x0008 /* Link transition mid-packet */ 770 #define FM10K_RXD_ERR_TOO_BIG 0x0010 /* Pkt too big for single buf */ 771 772 struct fm10k_ftag { 773 __be16 swpri_type_user; 774 __be16 vlan; 775 __be16 sglort; 776 __be16 dglort; 777 }; 778 779 #endif /* _FM10K_TYPE_H */ 780