1 /*
2 * Broadcom GENET MDIO routines
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11
12 #include <linux/types.h>
13 #include <linux/delay.h>
14 #include <linux/wait.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/bitops.h>
18 #include <linux/netdevice.h>
19 #include <linux/platform_device.h>
20 #include <linux/phy.h>
21 #include <linux/phy_fixed.h>
22 #include <linux/brcmphy.h>
23 #include <linux/of.h>
24 #include <linux/of_net.h>
25 #include <linux/of_mdio.h>
26 #include <linux/platform_data/bcmgenet.h>
27
28 #include "bcmgenet.h"
29
30 /* read a value from the MII */
bcmgenet_mii_read(struct mii_bus * bus,int phy_id,int location)31 static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
32 {
33 int ret;
34 struct net_device *dev = bus->priv;
35 struct bcmgenet_priv *priv = netdev_priv(dev);
36 u32 reg;
37
38 bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
39 (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
40 /* Start MDIO transaction*/
41 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
42 reg |= MDIO_START_BUSY;
43 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
44 wait_event_timeout(priv->wq,
45 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
46 & MDIO_START_BUSY),
47 HZ / 100);
48 ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
49
50 /* Some broken devices are known not to release the line during
51 * turn-around, e.g: Broadcom BCM53125 external switches, so check for
52 * that condition here and ignore the MDIO controller read failure
53 * indication.
54 */
55 if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (ret & MDIO_READ_FAIL))
56 return -EIO;
57
58 return ret & 0xffff;
59 }
60
61 /* write a value to the MII */
bcmgenet_mii_write(struct mii_bus * bus,int phy_id,int location,u16 val)62 static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
63 int location, u16 val)
64 {
65 struct net_device *dev = bus->priv;
66 struct bcmgenet_priv *priv = netdev_priv(dev);
67 u32 reg;
68
69 bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
70 (location << MDIO_REG_SHIFT) | (0xffff & val)),
71 UMAC_MDIO_CMD);
72 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
73 reg |= MDIO_START_BUSY;
74 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
75 wait_event_timeout(priv->wq,
76 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
77 MDIO_START_BUSY),
78 HZ / 100);
79
80 return 0;
81 }
82
83 /* setup netdev link state when PHY link status change and
84 * update UMAC and RGMII block when link up
85 */
bcmgenet_mii_setup(struct net_device * dev)86 void bcmgenet_mii_setup(struct net_device *dev)
87 {
88 struct bcmgenet_priv *priv = netdev_priv(dev);
89 struct phy_device *phydev = priv->phydev;
90 u32 reg, cmd_bits = 0;
91 bool status_changed = false;
92
93 if (priv->old_link != phydev->link) {
94 status_changed = true;
95 priv->old_link = phydev->link;
96 }
97
98 if (phydev->link) {
99 /* check speed/duplex/pause changes */
100 if (priv->old_speed != phydev->speed) {
101 status_changed = true;
102 priv->old_speed = phydev->speed;
103 }
104
105 if (priv->old_duplex != phydev->duplex) {
106 status_changed = true;
107 priv->old_duplex = phydev->duplex;
108 }
109
110 if (priv->old_pause != phydev->pause) {
111 status_changed = true;
112 priv->old_pause = phydev->pause;
113 }
114
115 /* done if nothing has changed */
116 if (!status_changed)
117 return;
118
119 /* speed */
120 if (phydev->speed == SPEED_1000)
121 cmd_bits = UMAC_SPEED_1000;
122 else if (phydev->speed == SPEED_100)
123 cmd_bits = UMAC_SPEED_100;
124 else
125 cmd_bits = UMAC_SPEED_10;
126 cmd_bits <<= CMD_SPEED_SHIFT;
127
128 /* duplex */
129 if (phydev->duplex != DUPLEX_FULL)
130 cmd_bits |= CMD_HD_EN;
131
132 /* pause capability */
133 if (!phydev->pause)
134 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
135
136 /*
137 * Program UMAC and RGMII block based on established
138 * link speed, duplex, and pause. The speed set in
139 * umac->cmd tell RGMII block which clock to use for
140 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
141 * Receive clock is provided by the PHY.
142 */
143 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
144 reg &= ~OOB_DISABLE;
145 reg |= RGMII_LINK;
146 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
147
148 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
149 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
150 CMD_HD_EN |
151 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
152 reg |= cmd_bits;
153 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
154 } else {
155 /* done if nothing has changed */
156 if (!status_changed)
157 return;
158
159 /* needed for MoCA fixed PHY to reflect correct link status */
160 netif_carrier_off(dev);
161 }
162
163 phy_print_status(phydev);
164 }
165
166
bcmgenet_fixed_phy_link_update(struct net_device * dev,struct fixed_phy_status * status)167 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
168 struct fixed_phy_status *status)
169 {
170 struct bcmgenet_priv *priv;
171 u32 reg;
172
173 if (dev && dev->phydev && status) {
174 priv = netdev_priv(dev);
175 reg = bcmgenet_umac_readl(priv, UMAC_MODE);
176 status->link = !!(reg & MODE_LINK_STATUS);
177 }
178
179 return 0;
180 }
181
182 /* Perform a voluntary PHY software reset, since the EPHY is very finicky about
183 * not doing it and will start corrupting packets
184 */
bcmgenet_mii_reset(struct net_device * dev)185 void bcmgenet_mii_reset(struct net_device *dev)
186 {
187 struct bcmgenet_priv *priv = netdev_priv(dev);
188
189 if (GENET_IS_V4(priv))
190 return;
191
192 if (priv->phydev) {
193 phy_init_hw(priv->phydev);
194 phy_start_aneg(priv->phydev);
195 }
196 }
197
bcmgenet_phy_power_set(struct net_device * dev,bool enable)198 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
199 {
200 struct bcmgenet_priv *priv = netdev_priv(dev);
201 u32 reg = 0;
202
203 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
204 if (!GENET_IS_V4(priv))
205 return;
206
207 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
208 if (enable) {
209 reg &= ~EXT_CK25_DIS;
210 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
211 mdelay(1);
212
213 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
214 reg |= EXT_GPHY_RESET;
215 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
216 mdelay(1);
217
218 reg &= ~EXT_GPHY_RESET;
219 } else {
220 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_GPHY_RESET;
221 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
222 mdelay(1);
223 reg |= EXT_CK25_DIS;
224 }
225 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
226 udelay(60);
227 }
228
bcmgenet_moca_phy_setup(struct bcmgenet_priv * priv)229 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
230 {
231 u32 reg;
232
233 /* Speed settings are set in bcmgenet_mii_setup() */
234 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
235 reg |= LED_ACT_SOURCE_MAC;
236 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
237
238 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
239 fixed_phy_set_link_update(priv->phydev,
240 bcmgenet_fixed_phy_link_update);
241 }
242
bcmgenet_mii_config(struct net_device * dev)243 int bcmgenet_mii_config(struct net_device *dev)
244 {
245 struct bcmgenet_priv *priv = netdev_priv(dev);
246 struct phy_device *phydev = priv->phydev;
247 struct device *kdev = &priv->pdev->dev;
248 const char *phy_name = NULL;
249 u32 id_mode_dis = 0;
250 u32 port_ctrl;
251 u32 reg;
252
253 priv->ext_phy = !priv->internal_phy &&
254 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
255
256 if (priv->internal_phy)
257 priv->phy_interface = PHY_INTERFACE_MODE_NA;
258
259 switch (priv->phy_interface) {
260 case PHY_INTERFACE_MODE_NA:
261 case PHY_INTERFACE_MODE_MOCA:
262 /* Irrespective of the actually configured PHY speed (100 or
263 * 1000) GENETv4 only has an internal GPHY so we will just end
264 * up masking the Gigabit features from what we support, not
265 * switching to the EPHY
266 */
267 if (GENET_IS_V4(priv))
268 port_ctrl = PORT_MODE_INT_GPHY;
269 else
270 port_ctrl = PORT_MODE_INT_EPHY;
271
272 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
273
274 if (priv->internal_phy) {
275 phy_name = "internal PHY";
276 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
277 phy_name = "MoCA";
278 bcmgenet_moca_phy_setup(priv);
279 }
280 break;
281
282 case PHY_INTERFACE_MODE_MII:
283 phy_name = "external MII";
284 phydev->supported &= PHY_BASIC_FEATURES;
285 bcmgenet_sys_writel(priv,
286 PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
287 break;
288
289 case PHY_INTERFACE_MODE_REVMII:
290 phy_name = "external RvMII";
291 /* of_mdiobus_register took care of reading the 'max-speed'
292 * PHY property for us, effectively limiting the PHY supported
293 * capabilities, use that knowledge to also configure the
294 * Reverse MII interface correctly.
295 */
296 if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
297 PHY_BASIC_FEATURES)
298 port_ctrl = PORT_MODE_EXT_RVMII_25;
299 else
300 port_ctrl = PORT_MODE_EXT_RVMII_50;
301 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
302 break;
303
304 case PHY_INTERFACE_MODE_RGMII:
305 /* RGMII_NO_ID: TXC transitions at the same time as TXD
306 * (requires PCB or receiver-side delay)
307 * RGMII: Add 2ns delay on TXC (90 degree shift)
308 *
309 * ID is implicitly disabled for 100Mbps (RG)MII operation.
310 */
311 id_mode_dis = BIT(16);
312 /* fall through */
313 case PHY_INTERFACE_MODE_RGMII_TXID:
314 if (id_mode_dis)
315 phy_name = "external RGMII (no delay)";
316 else
317 phy_name = "external RGMII (TX delay)";
318 bcmgenet_sys_writel(priv,
319 PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
320 break;
321 default:
322 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
323 return -EINVAL;
324 }
325
326 /* This is an external PHY (xMII), so we need to enable the RGMII
327 * block for the interface to work
328 */
329 if (priv->ext_phy) {
330 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
331 reg |= id_mode_dis;
332 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
333 reg |= RGMII_MODE_EN_V123;
334 else
335 reg |= RGMII_MODE_EN;
336 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
337 }
338
339 dev_info_once(kdev, "configuring instance for %s\n", phy_name);
340
341 return 0;
342 }
343
bcmgenet_mii_probe(struct net_device * dev)344 int bcmgenet_mii_probe(struct net_device *dev)
345 {
346 struct bcmgenet_priv *priv = netdev_priv(dev);
347 struct device_node *dn = priv->pdev->dev.of_node;
348 struct phy_device *phydev;
349 u32 phy_flags = 0;
350 int ret;
351
352 /* Communicate the integrated PHY revision */
353 if (priv->internal_phy)
354 phy_flags = priv->gphy_rev;
355
356 /* Initialize link state variables that bcmgenet_mii_setup() uses */
357 priv->old_link = -1;
358 priv->old_speed = -1;
359 priv->old_duplex = -1;
360 priv->old_pause = -1;
361
362 if (dn) {
363 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
364 phy_flags, priv->phy_interface);
365 if (!phydev) {
366 pr_err("could not attach to PHY\n");
367 return -ENODEV;
368 }
369 } else {
370 phydev = priv->phydev;
371 phydev->dev_flags = phy_flags;
372
373 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
374 priv->phy_interface);
375 if (ret) {
376 pr_err("could not attach to PHY\n");
377 return -ENODEV;
378 }
379 }
380
381 priv->phydev = phydev;
382
383 /* Configure port multiplexer based on what the probed PHY device since
384 * reading the 'max-speed' property determines the maximum supported
385 * PHY speed which is needed for bcmgenet_mii_config() to configure
386 * things appropriately.
387 */
388 ret = bcmgenet_mii_config(dev);
389 if (ret) {
390 phy_disconnect(priv->phydev);
391 return ret;
392 }
393
394 phydev->advertising = phydev->supported;
395
396 /* The internal PHY has its link interrupts routed to the
397 * Ethernet MAC ISRs
398 */
399 if (priv->internal_phy)
400 priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT;
401 else
402 priv->mii_bus->irq[phydev->addr] = PHY_POLL;
403
404 return 0;
405 }
406
407 /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
408 * their internal MDIO management controller making them fail to successfully
409 * be read from or written to for the first transaction. We insert a dummy
410 * BMSR read here to make sure that phy_get_device() and get_phy_id() can
411 * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
412 * PHY device for this peripheral.
413 *
414 * Once the PHY driver is registered, we can workaround subsequent reads from
415 * there (e.g: during system-wide power management).
416 *
417 * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
418 * therefore the right location to stick that workaround. Since we do not want
419 * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
420 * Device Tree scan to limit the search area.
421 */
bcmgenet_mii_bus_reset(struct mii_bus * bus)422 static int bcmgenet_mii_bus_reset(struct mii_bus *bus)
423 {
424 struct net_device *dev = bus->priv;
425 struct bcmgenet_priv *priv = netdev_priv(dev);
426 struct device_node *np = priv->mdio_dn;
427 struct device_node *child = NULL;
428 u32 read_mask = 0;
429 int addr = 0;
430
431 if (!np) {
432 read_mask = 1 << priv->phy_addr;
433 } else {
434 for_each_available_child_of_node(np, child) {
435 addr = of_mdio_parse_addr(&dev->dev, child);
436 if (addr < 0)
437 continue;
438
439 read_mask |= 1 << addr;
440 }
441 }
442
443 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
444 if (read_mask & 1 << addr) {
445 dev_dbg(&dev->dev, "Workaround for PHY @ %d\n", addr);
446 mdiobus_read(bus, addr, MII_BMSR);
447 }
448 }
449
450 return 0;
451 }
452
bcmgenet_mii_alloc(struct bcmgenet_priv * priv)453 static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
454 {
455 struct mii_bus *bus;
456
457 if (priv->mii_bus)
458 return 0;
459
460 priv->mii_bus = mdiobus_alloc();
461 if (!priv->mii_bus) {
462 pr_err("failed to allocate\n");
463 return -ENOMEM;
464 }
465
466 bus = priv->mii_bus;
467 bus->priv = priv->dev;
468 bus->name = "bcmgenet MII bus";
469 bus->parent = &priv->pdev->dev;
470 bus->read = bcmgenet_mii_read;
471 bus->write = bcmgenet_mii_write;
472 bus->reset = bcmgenet_mii_bus_reset;
473 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
474 priv->pdev->name, priv->pdev->id);
475
476 bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
477 if (!bus->irq) {
478 mdiobus_free(priv->mii_bus);
479 return -ENOMEM;
480 }
481
482 return 0;
483 }
484
bcmgenet_mii_of_init(struct bcmgenet_priv * priv)485 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
486 {
487 struct device_node *dn = priv->pdev->dev.of_node;
488 struct device *kdev = &priv->pdev->dev;
489 const char *phy_mode_str = NULL;
490 struct phy_device *phydev = NULL;
491 char *compat;
492 int phy_mode;
493 int ret;
494
495 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
496 if (!compat)
497 return -ENOMEM;
498
499 priv->mdio_dn = of_get_compatible_child(dn, compat);
500 kfree(compat);
501 if (!priv->mdio_dn) {
502 dev_err(kdev, "unable to find MDIO bus node\n");
503 return -ENODEV;
504 }
505
506 ret = of_mdiobus_register(priv->mii_bus, priv->mdio_dn);
507 if (ret) {
508 dev_err(kdev, "failed to register MDIO bus\n");
509 return ret;
510 }
511
512 /* Fetch the PHY phandle */
513 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
514
515 /* In the case of a fixed PHY, the DT node associated
516 * to the PHY is the Ethernet MAC DT node.
517 */
518 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
519 ret = of_phy_register_fixed_link(dn);
520 if (ret)
521 return ret;
522
523 priv->phy_dn = of_node_get(dn);
524 }
525
526 /* Get the link mode */
527 phy_mode = of_get_phy_mode(dn);
528 priv->phy_interface = phy_mode;
529
530 /* We need to specifically look up whether this PHY interface is internal
531 * or not *before* we even try to probe the PHY driver over MDIO as we
532 * may have shut down the internal PHY for power saving purposes.
533 */
534 if (phy_mode < 0) {
535 ret = of_property_read_string(dn, "phy-mode", &phy_mode_str);
536 if (ret < 0) {
537 dev_err(kdev, "invalid PHY mode property\n");
538 return ret;
539 }
540
541 priv->phy_interface = PHY_INTERFACE_MODE_NA;
542 if (!strcasecmp(phy_mode_str, "internal"))
543 priv->internal_phy = true;
544 }
545
546 /* Make sure we initialize MoCA PHYs with a link down */
547 if (phy_mode == PHY_INTERFACE_MODE_MOCA) {
548 phydev = of_phy_find_device(dn);
549 if (phydev)
550 phydev->link = 0;
551 }
552
553 return 0;
554 }
555
bcmgenet_mii_pd_init(struct bcmgenet_priv * priv)556 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
557 {
558 struct device *kdev = &priv->pdev->dev;
559 struct bcmgenet_platform_data *pd = kdev->platform_data;
560 struct mii_bus *mdio = priv->mii_bus;
561 struct phy_device *phydev;
562 int ret;
563
564 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
565 /*
566 * Internal or external PHY with MDIO access
567 */
568 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
569 mdio->phy_mask = ~(1 << pd->phy_address);
570 else
571 mdio->phy_mask = 0;
572
573 ret = mdiobus_register(mdio);
574 if (ret) {
575 dev_err(kdev, "failed to register MDIO bus\n");
576 return ret;
577 }
578
579 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
580 phydev = mdio->phy_map[pd->phy_address];
581 else
582 phydev = phy_find_first(mdio);
583
584 if (!phydev) {
585 dev_err(kdev, "failed to register PHY device\n");
586 mdiobus_unregister(mdio);
587 return -ENODEV;
588 }
589 } else {
590 /*
591 * MoCA port or no MDIO access.
592 * Use fixed PHY to represent the link layer.
593 */
594 struct fixed_phy_status fphy_status = {
595 .link = 1,
596 .speed = pd->phy_speed,
597 .duplex = pd->phy_duplex,
598 .pause = 0,
599 .asym_pause = 0,
600 };
601
602 phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
603 if (!phydev || IS_ERR(phydev)) {
604 dev_err(kdev, "failed to register fixed PHY device\n");
605 return -ENODEV;
606 }
607
608 /* Make sure we initialize MoCA PHYs with a link down */
609 phydev->link = 0;
610
611 }
612
613 priv->phydev = phydev;
614 priv->phy_interface = pd->phy_interface;
615
616 return 0;
617 }
618
bcmgenet_mii_bus_init(struct bcmgenet_priv * priv)619 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
620 {
621 struct device_node *dn = priv->pdev->dev.of_node;
622
623 if (dn)
624 return bcmgenet_mii_of_init(priv);
625 else
626 return bcmgenet_mii_pd_init(priv);
627 }
628
bcmgenet_mii_init(struct net_device * dev)629 int bcmgenet_mii_init(struct net_device *dev)
630 {
631 struct bcmgenet_priv *priv = netdev_priv(dev);
632 int ret;
633
634 ret = bcmgenet_mii_alloc(priv);
635 if (ret)
636 return ret;
637
638 ret = bcmgenet_mii_bus_init(priv);
639 if (ret)
640 goto out;
641
642 return 0;
643
644 out:
645 of_node_put(priv->phy_dn);
646 mdiobus_unregister(priv->mii_bus);
647 kfree(priv->mii_bus->irq);
648 mdiobus_free(priv->mii_bus);
649 return ret;
650 }
651
bcmgenet_mii_exit(struct net_device * dev)652 void bcmgenet_mii_exit(struct net_device *dev)
653 {
654 struct bcmgenet_priv *priv = netdev_priv(dev);
655
656 of_node_put(priv->phy_dn);
657 mdiobus_unregister(priv->mii_bus);
658 kfree(priv->mii_bus->irq);
659 mdiobus_free(priv->mii_bus);
660 }
661