1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <rdma/ib_umem.h>
36 #include <linux/atomic.h>
37
38 #include "iw_cxgb4.h"
39
40 int use_dsgl = 0;
41 module_param(use_dsgl, int, 0644);
42 MODULE_PARM_DESC(use_dsgl, "Use DSGL for PBL/FastReg (default=0)");
43
44 #define T4_ULPTX_MIN_IO 32
45 #define C4IW_MAX_INLINE_SIZE 96
46 #define T4_ULPTX_MAX_DMA 1024
47 #define C4IW_INLINE_THRESHOLD 128
48
49 static int inline_threshold = C4IW_INLINE_THRESHOLD;
50 module_param(inline_threshold, int, 0644);
51 MODULE_PARM_DESC(inline_threshold, "inline vs dsgl threshold (default=128)");
52
mr_exceeds_hw_limits(struct c4iw_dev * dev,u64 length)53 static int mr_exceeds_hw_limits(struct c4iw_dev *dev, u64 length)
54 {
55 return (is_t4(dev->rdev.lldi.adapter_type) ||
56 is_t5(dev->rdev.lldi.adapter_type)) &&
57 length >= 8*1024*1024*1024ULL;
58 }
59
_c4iw_write_mem_dma_aligned(struct c4iw_rdev * rdev,u32 addr,u32 len,dma_addr_t data,int wait)60 static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr,
61 u32 len, dma_addr_t data, int wait)
62 {
63 struct sk_buff *skb;
64 struct ulp_mem_io *req;
65 struct ulptx_sgl *sgl;
66 u8 wr_len;
67 int ret = 0;
68 struct c4iw_wr_wait wr_wait;
69
70 addr &= 0x7FFFFFF;
71
72 if (wait)
73 c4iw_init_wr_wait(&wr_wait);
74 wr_len = roundup(sizeof(*req) + sizeof(*sgl), 16);
75
76 skb = alloc_skb(wr_len, GFP_KERNEL);
77 if (!skb)
78 return -ENOMEM;
79 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
80
81 req = (struct ulp_mem_io *)__skb_put(skb, wr_len);
82 memset(req, 0, wr_len);
83 INIT_ULPTX_WR(req, wr_len, 0, 0);
84 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
85 (wait ? FW_WR_COMPL_F : 0));
86 req->wr.wr_lo = wait ? (__force __be64)(unsigned long) &wr_wait : 0L;
87 req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
88 req->cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE));
89 req->cmd |= cpu_to_be32(T5_ULP_MEMIO_ORDER_V(1));
90 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(len>>5));
91 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 16));
92 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr));
93
94 sgl = (struct ulptx_sgl *)(req + 1);
95 sgl->cmd_nsge = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_DSGL) |
96 ULPTX_NSGE_V(1));
97 sgl->len0 = cpu_to_be32(len);
98 sgl->addr0 = cpu_to_be64(data);
99
100 ret = c4iw_ofld_send(rdev, skb);
101 if (ret)
102 return ret;
103 if (wait)
104 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
105 return ret;
106 }
107
_c4iw_write_mem_inline(struct c4iw_rdev * rdev,u32 addr,u32 len,void * data)108 static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len,
109 void *data)
110 {
111 struct sk_buff *skb;
112 struct ulp_mem_io *req;
113 struct ulptx_idata *sc;
114 u8 wr_len, *to_dp, *from_dp;
115 int copy_len, num_wqe, i, ret = 0;
116 struct c4iw_wr_wait wr_wait;
117 __be32 cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE));
118
119 if (is_t4(rdev->lldi.adapter_type))
120 cmd |= cpu_to_be32(ULP_MEMIO_ORDER_F);
121 else
122 cmd |= cpu_to_be32(T5_ULP_MEMIO_IMM_F);
123
124 addr &= 0x7FFFFFF;
125 PDBG("%s addr 0x%x len %u\n", __func__, addr, len);
126 num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE);
127 c4iw_init_wr_wait(&wr_wait);
128 for (i = 0; i < num_wqe; i++) {
129
130 copy_len = len > C4IW_MAX_INLINE_SIZE ? C4IW_MAX_INLINE_SIZE :
131 len;
132 wr_len = roundup(sizeof *req + sizeof *sc +
133 roundup(copy_len, T4_ULPTX_MIN_IO), 16);
134
135 skb = alloc_skb(wr_len, GFP_KERNEL);
136 if (!skb)
137 return -ENOMEM;
138 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
139
140 req = (struct ulp_mem_io *)__skb_put(skb, wr_len);
141 memset(req, 0, wr_len);
142 INIT_ULPTX_WR(req, wr_len, 0, 0);
143
144 if (i == (num_wqe-1)) {
145 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
146 FW_WR_COMPL_F);
147 req->wr.wr_lo = (__force __be64)(unsigned long)&wr_wait;
148 } else
149 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR));
150 req->wr.wr_mid = cpu_to_be32(
151 FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
152
153 req->cmd = cmd;
154 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(
155 DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO)));
156 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr),
157 16));
158 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr + i * 3));
159
160 sc = (struct ulptx_idata *)(req + 1);
161 sc->cmd_more = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_IMM));
162 sc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO));
163
164 to_dp = (u8 *)(sc + 1);
165 from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE;
166 if (data)
167 memcpy(to_dp, from_dp, copy_len);
168 else
169 memset(to_dp, 0, copy_len);
170 if (copy_len % T4_ULPTX_MIN_IO)
171 memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO -
172 (copy_len % T4_ULPTX_MIN_IO));
173 ret = c4iw_ofld_send(rdev, skb);
174 if (ret)
175 return ret;
176 len -= C4IW_MAX_INLINE_SIZE;
177 }
178
179 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
180 return ret;
181 }
182
_c4iw_write_mem_dma(struct c4iw_rdev * rdev,u32 addr,u32 len,void * data)183 static int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len, void *data)
184 {
185 u32 remain = len;
186 u32 dmalen;
187 int ret = 0;
188 dma_addr_t daddr;
189 dma_addr_t save;
190
191 daddr = dma_map_single(&rdev->lldi.pdev->dev, data, len, DMA_TO_DEVICE);
192 if (dma_mapping_error(&rdev->lldi.pdev->dev, daddr))
193 return -1;
194 save = daddr;
195
196 while (remain > inline_threshold) {
197 if (remain < T4_ULPTX_MAX_DMA) {
198 if (remain & ~T4_ULPTX_MIN_IO)
199 dmalen = remain & ~(T4_ULPTX_MIN_IO-1);
200 else
201 dmalen = remain;
202 } else
203 dmalen = T4_ULPTX_MAX_DMA;
204 remain -= dmalen;
205 ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, daddr,
206 !remain);
207 if (ret)
208 goto out;
209 addr += dmalen >> 5;
210 data += dmalen;
211 daddr += dmalen;
212 }
213 if (remain)
214 ret = _c4iw_write_mem_inline(rdev, addr, remain, data);
215 out:
216 dma_unmap_single(&rdev->lldi.pdev->dev, save, len, DMA_TO_DEVICE);
217 return ret;
218 }
219
220 /*
221 * write len bytes of data into addr (32B aligned address)
222 * If data is NULL, clear len byte of memory to zero.
223 */
write_adapter_mem(struct c4iw_rdev * rdev,u32 addr,u32 len,void * data)224 static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len,
225 void *data)
226 {
227 if (is_t5(rdev->lldi.adapter_type) && use_dsgl) {
228 if (len > inline_threshold) {
229 if (_c4iw_write_mem_dma(rdev, addr, len, data)) {
230 printk_ratelimited(KERN_WARNING
231 "%s: dma map"
232 " failure (non fatal)\n",
233 pci_name(rdev->lldi.pdev));
234 return _c4iw_write_mem_inline(rdev, addr, len,
235 data);
236 } else
237 return 0;
238 } else
239 return _c4iw_write_mem_inline(rdev, addr, len, data);
240 } else
241 return _c4iw_write_mem_inline(rdev, addr, len, data);
242 }
243
244 /*
245 * Build and write a TPT entry.
246 * IN: stag key, pdid, perm, bind_enabled, zbva, to, len, page_size,
247 * pbl_size and pbl_addr
248 * OUT: stag index
249 */
write_tpt_entry(struct c4iw_rdev * rdev,u32 reset_tpt_entry,u32 * stag,u8 stag_state,u32 pdid,enum fw_ri_stag_type type,enum fw_ri_mem_perms perm,int bind_enabled,u32 zbva,u64 to,u64 len,u8 page_size,u32 pbl_size,u32 pbl_addr)250 static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry,
251 u32 *stag, u8 stag_state, u32 pdid,
252 enum fw_ri_stag_type type, enum fw_ri_mem_perms perm,
253 int bind_enabled, u32 zbva, u64 to,
254 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr)
255 {
256 int err;
257 struct fw_ri_tpte *tpt;
258 u32 stag_idx;
259 static atomic_t key;
260
261 if (c4iw_fatal_error(rdev))
262 return -EIO;
263
264 tpt = kmalloc(sizeof(*tpt), GFP_KERNEL);
265 if (!tpt)
266 return -ENOMEM;
267
268 stag_state = stag_state > 0;
269 stag_idx = (*stag) >> 8;
270
271 if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) {
272 stag_idx = c4iw_get_resource(&rdev->resource.tpt_table);
273 if (!stag_idx) {
274 mutex_lock(&rdev->stats.lock);
275 rdev->stats.stag.fail++;
276 mutex_unlock(&rdev->stats.lock);
277 kfree(tpt);
278 return -ENOMEM;
279 }
280 mutex_lock(&rdev->stats.lock);
281 rdev->stats.stag.cur += 32;
282 if (rdev->stats.stag.cur > rdev->stats.stag.max)
283 rdev->stats.stag.max = rdev->stats.stag.cur;
284 mutex_unlock(&rdev->stats.lock);
285 *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff);
286 }
287 PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
288 __func__, stag_state, type, pdid, stag_idx);
289
290 /* write TPT entry */
291 if (reset_tpt_entry)
292 memset(tpt, 0, sizeof(*tpt));
293 else {
294 tpt->valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F |
295 FW_RI_TPTE_STAGKEY_V((*stag & FW_RI_TPTE_STAGKEY_M)) |
296 FW_RI_TPTE_STAGSTATE_V(stag_state) |
297 FW_RI_TPTE_STAGTYPE_V(type) | FW_RI_TPTE_PDID_V(pdid));
298 tpt->locread_to_qpid = cpu_to_be32(FW_RI_TPTE_PERM_V(perm) |
299 (bind_enabled ? FW_RI_TPTE_MWBINDEN_F : 0) |
300 FW_RI_TPTE_ADDRTYPE_V((zbva ? FW_RI_ZERO_BASED_TO :
301 FW_RI_VA_BASED_TO))|
302 FW_RI_TPTE_PS_V(page_size));
303 tpt->nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32(
304 FW_RI_TPTE_PBLADDR_V(PBL_OFF(rdev, pbl_addr)>>3));
305 tpt->len_lo = cpu_to_be32((u32)(len & 0xffffffffUL));
306 tpt->va_hi = cpu_to_be32((u32)(to >> 32));
307 tpt->va_lo_fbo = cpu_to_be32((u32)(to & 0xffffffffUL));
308 tpt->dca_mwbcnt_pstag = cpu_to_be32(0);
309 tpt->len_hi = cpu_to_be32((u32)(len >> 32));
310 }
311 err = write_adapter_mem(rdev, stag_idx +
312 (rdev->lldi.vr->stag.start >> 5),
313 sizeof(*tpt), tpt);
314
315 if (reset_tpt_entry) {
316 c4iw_put_resource(&rdev->resource.tpt_table, stag_idx);
317 mutex_lock(&rdev->stats.lock);
318 rdev->stats.stag.cur -= 32;
319 mutex_unlock(&rdev->stats.lock);
320 }
321 kfree(tpt);
322 return err;
323 }
324
write_pbl(struct c4iw_rdev * rdev,__be64 * pbl,u32 pbl_addr,u32 pbl_size)325 static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl,
326 u32 pbl_addr, u32 pbl_size)
327 {
328 int err;
329
330 PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
331 __func__, pbl_addr, rdev->lldi.vr->pbl.start,
332 pbl_size);
333
334 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl);
335 return err;
336 }
337
dereg_mem(struct c4iw_rdev * rdev,u32 stag,u32 pbl_size,u32 pbl_addr)338 static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size,
339 u32 pbl_addr)
340 {
341 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0,
342 pbl_size, pbl_addr);
343 }
344
allocate_window(struct c4iw_rdev * rdev,u32 * stag,u32 pdid)345 static int allocate_window(struct c4iw_rdev *rdev, u32 * stag, u32 pdid)
346 {
347 *stag = T4_STAG_UNSET;
348 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0,
349 0UL, 0, 0, 0, 0);
350 }
351
deallocate_window(struct c4iw_rdev * rdev,u32 stag)352 static int deallocate_window(struct c4iw_rdev *rdev, u32 stag)
353 {
354 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0,
355 0);
356 }
357
allocate_stag(struct c4iw_rdev * rdev,u32 * stag,u32 pdid,u32 pbl_size,u32 pbl_addr)358 static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid,
359 u32 pbl_size, u32 pbl_addr)
360 {
361 *stag = T4_STAG_UNSET;
362 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0,
363 0UL, 0, 0, pbl_size, pbl_addr);
364 }
365
finish_mem_reg(struct c4iw_mr * mhp,u32 stag)366 static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag)
367 {
368 u32 mmid;
369
370 mhp->attr.state = 1;
371 mhp->attr.stag = stag;
372 mmid = stag >> 8;
373 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
374 PDBG("%s mmid 0x%x mhp %p\n", __func__, mmid, mhp);
375 return insert_handle(mhp->rhp, &mhp->rhp->mmidr, mhp, mmid);
376 }
377
register_mem(struct c4iw_dev * rhp,struct c4iw_pd * php,struct c4iw_mr * mhp,int shift)378 static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php,
379 struct c4iw_mr *mhp, int shift)
380 {
381 u32 stag = T4_STAG_UNSET;
382 int ret;
383
384 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid,
385 FW_RI_STAG_NSMR, mhp->attr.len ?
386 mhp->attr.perms : 0,
387 mhp->attr.mw_bind_enable, mhp->attr.zbva,
388 mhp->attr.va_fbo, mhp->attr.len ?
389 mhp->attr.len : -1, shift - 12,
390 mhp->attr.pbl_size, mhp->attr.pbl_addr);
391 if (ret)
392 return ret;
393
394 ret = finish_mem_reg(mhp, stag);
395 if (ret)
396 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
397 mhp->attr.pbl_addr);
398 return ret;
399 }
400
reregister_mem(struct c4iw_dev * rhp,struct c4iw_pd * php,struct c4iw_mr * mhp,int shift,int npages)401 static int reregister_mem(struct c4iw_dev *rhp, struct c4iw_pd *php,
402 struct c4iw_mr *mhp, int shift, int npages)
403 {
404 u32 stag;
405 int ret;
406
407 if (npages > mhp->attr.pbl_size)
408 return -ENOMEM;
409
410 stag = mhp->attr.stag;
411 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid,
412 FW_RI_STAG_NSMR, mhp->attr.perms,
413 mhp->attr.mw_bind_enable, mhp->attr.zbva,
414 mhp->attr.va_fbo, mhp->attr.len, shift - 12,
415 mhp->attr.pbl_size, mhp->attr.pbl_addr);
416 if (ret)
417 return ret;
418
419 ret = finish_mem_reg(mhp, stag);
420 if (ret)
421 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
422 mhp->attr.pbl_addr);
423
424 return ret;
425 }
426
alloc_pbl(struct c4iw_mr * mhp,int npages)427 static int alloc_pbl(struct c4iw_mr *mhp, int npages)
428 {
429 mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev,
430 npages << 3);
431
432 if (!mhp->attr.pbl_addr)
433 return -ENOMEM;
434
435 mhp->attr.pbl_size = npages;
436
437 return 0;
438 }
439
build_phys_page_list(struct ib_phys_buf * buffer_list,int num_phys_buf,u64 * iova_start,u64 * total_size,int * npages,int * shift,__be64 ** page_list)440 static int build_phys_page_list(struct ib_phys_buf *buffer_list,
441 int num_phys_buf, u64 *iova_start,
442 u64 *total_size, int *npages,
443 int *shift, __be64 **page_list)
444 {
445 u64 mask;
446 int i, j, n;
447
448 mask = 0;
449 *total_size = 0;
450 for (i = 0; i < num_phys_buf; ++i) {
451 if (i != 0 && buffer_list[i].addr & ~PAGE_MASK)
452 return -EINVAL;
453 if (i != 0 && i != num_phys_buf - 1 &&
454 (buffer_list[i].size & ~PAGE_MASK))
455 return -EINVAL;
456 *total_size += buffer_list[i].size;
457 if (i > 0)
458 mask |= buffer_list[i].addr;
459 else
460 mask |= buffer_list[i].addr & PAGE_MASK;
461 if (i != num_phys_buf - 1)
462 mask |= buffer_list[i].addr + buffer_list[i].size;
463 else
464 mask |= (buffer_list[i].addr + buffer_list[i].size +
465 PAGE_SIZE - 1) & PAGE_MASK;
466 }
467
468 if (*total_size > 0xFFFFFFFFULL)
469 return -ENOMEM;
470
471 /* Find largest page shift we can use to cover buffers */
472 for (*shift = PAGE_SHIFT; *shift < 27; ++(*shift))
473 if ((1ULL << *shift) & mask)
474 break;
475
476 buffer_list[0].size += buffer_list[0].addr & ((1ULL << *shift) - 1);
477 buffer_list[0].addr &= ~0ull << *shift;
478
479 *npages = 0;
480 for (i = 0; i < num_phys_buf; ++i)
481 *npages += (buffer_list[i].size +
482 (1ULL << *shift) - 1) >> *shift;
483
484 if (!*npages)
485 return -EINVAL;
486
487 *page_list = kmalloc(sizeof(u64) * *npages, GFP_KERNEL);
488 if (!*page_list)
489 return -ENOMEM;
490
491 n = 0;
492 for (i = 0; i < num_phys_buf; ++i)
493 for (j = 0;
494 j < (buffer_list[i].size + (1ULL << *shift) - 1) >> *shift;
495 ++j)
496 (*page_list)[n++] = cpu_to_be64(buffer_list[i].addr +
497 ((u64) j << *shift));
498
499 PDBG("%s va 0x%llx mask 0x%llx shift %d len %lld pbl_size %d\n",
500 __func__, (unsigned long long)*iova_start,
501 (unsigned long long)mask, *shift, (unsigned long long)*total_size,
502 *npages);
503
504 return 0;
505
506 }
507
c4iw_reregister_phys_mem(struct ib_mr * mr,int mr_rereg_mask,struct ib_pd * pd,struct ib_phys_buf * buffer_list,int num_phys_buf,int acc,u64 * iova_start)508 int c4iw_reregister_phys_mem(struct ib_mr *mr, int mr_rereg_mask,
509 struct ib_pd *pd, struct ib_phys_buf *buffer_list,
510 int num_phys_buf, int acc, u64 *iova_start)
511 {
512
513 struct c4iw_mr mh, *mhp;
514 struct c4iw_pd *php;
515 struct c4iw_dev *rhp;
516 __be64 *page_list = NULL;
517 int shift = 0;
518 u64 total_size;
519 int npages;
520 int ret;
521
522 PDBG("%s ib_mr %p ib_pd %p\n", __func__, mr, pd);
523
524 /* There can be no memory windows */
525 if (atomic_read(&mr->usecnt))
526 return -EINVAL;
527
528 mhp = to_c4iw_mr(mr);
529 rhp = mhp->rhp;
530 php = to_c4iw_pd(mr->pd);
531
532 /* make sure we are on the same adapter */
533 if (rhp != php->rhp)
534 return -EINVAL;
535
536 memcpy(&mh, mhp, sizeof *mhp);
537
538 if (mr_rereg_mask & IB_MR_REREG_PD)
539 php = to_c4iw_pd(pd);
540 if (mr_rereg_mask & IB_MR_REREG_ACCESS) {
541 mh.attr.perms = c4iw_ib_to_tpt_access(acc);
542 mh.attr.mw_bind_enable = (acc & IB_ACCESS_MW_BIND) ==
543 IB_ACCESS_MW_BIND;
544 }
545 if (mr_rereg_mask & IB_MR_REREG_TRANS) {
546 ret = build_phys_page_list(buffer_list, num_phys_buf,
547 iova_start,
548 &total_size, &npages,
549 &shift, &page_list);
550 if (ret)
551 return ret;
552 }
553
554 if (mr_exceeds_hw_limits(rhp, total_size)) {
555 kfree(page_list);
556 return -EINVAL;
557 }
558
559 ret = reregister_mem(rhp, php, &mh, shift, npages);
560 kfree(page_list);
561 if (ret)
562 return ret;
563 if (mr_rereg_mask & IB_MR_REREG_PD)
564 mhp->attr.pdid = php->pdid;
565 if (mr_rereg_mask & IB_MR_REREG_ACCESS)
566 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
567 if (mr_rereg_mask & IB_MR_REREG_TRANS) {
568 mhp->attr.zbva = 0;
569 mhp->attr.va_fbo = *iova_start;
570 mhp->attr.page_size = shift - 12;
571 mhp->attr.len = (u32) total_size;
572 mhp->attr.pbl_size = npages;
573 }
574
575 return 0;
576 }
577
c4iw_register_phys_mem(struct ib_pd * pd,struct ib_phys_buf * buffer_list,int num_phys_buf,int acc,u64 * iova_start)578 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
579 struct ib_phys_buf *buffer_list,
580 int num_phys_buf, int acc, u64 *iova_start)
581 {
582 __be64 *page_list;
583 int shift;
584 u64 total_size;
585 int npages;
586 struct c4iw_dev *rhp;
587 struct c4iw_pd *php;
588 struct c4iw_mr *mhp;
589 int ret;
590
591 PDBG("%s ib_pd %p\n", __func__, pd);
592 php = to_c4iw_pd(pd);
593 rhp = php->rhp;
594
595 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
596 if (!mhp)
597 return ERR_PTR(-ENOMEM);
598
599 mhp->rhp = rhp;
600
601 /* First check that we have enough alignment */
602 if ((*iova_start & ~PAGE_MASK) != (buffer_list[0].addr & ~PAGE_MASK)) {
603 ret = -EINVAL;
604 goto err;
605 }
606
607 if (num_phys_buf > 1 &&
608 ((buffer_list[0].addr + buffer_list[0].size) & ~PAGE_MASK)) {
609 ret = -EINVAL;
610 goto err;
611 }
612
613 ret = build_phys_page_list(buffer_list, num_phys_buf, iova_start,
614 &total_size, &npages, &shift,
615 &page_list);
616 if (ret)
617 goto err;
618
619 if (mr_exceeds_hw_limits(rhp, total_size)) {
620 kfree(page_list);
621 ret = -EINVAL;
622 goto err;
623 }
624
625 ret = alloc_pbl(mhp, npages);
626 if (ret) {
627 kfree(page_list);
628 goto err;
629 }
630
631 ret = write_pbl(&mhp->rhp->rdev, page_list, mhp->attr.pbl_addr,
632 npages);
633 kfree(page_list);
634 if (ret)
635 goto err_pbl;
636
637 mhp->attr.pdid = php->pdid;
638 mhp->attr.zbva = 0;
639
640 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
641 mhp->attr.va_fbo = *iova_start;
642 mhp->attr.page_size = shift - 12;
643
644 mhp->attr.len = (u32) total_size;
645 mhp->attr.pbl_size = npages;
646 ret = register_mem(rhp, php, mhp, shift);
647 if (ret)
648 goto err_pbl;
649
650 return &mhp->ibmr;
651
652 err_pbl:
653 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
654 mhp->attr.pbl_size << 3);
655
656 err:
657 kfree(mhp);
658 return ERR_PTR(ret);
659
660 }
661
c4iw_get_dma_mr(struct ib_pd * pd,int acc)662 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc)
663 {
664 struct c4iw_dev *rhp;
665 struct c4iw_pd *php;
666 struct c4iw_mr *mhp;
667 int ret;
668 u32 stag = T4_STAG_UNSET;
669
670 PDBG("%s ib_pd %p\n", __func__, pd);
671 php = to_c4iw_pd(pd);
672 rhp = php->rhp;
673
674 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
675 if (!mhp)
676 return ERR_PTR(-ENOMEM);
677
678 mhp->rhp = rhp;
679 mhp->attr.pdid = php->pdid;
680 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
681 mhp->attr.mw_bind_enable = (acc&IB_ACCESS_MW_BIND) == IB_ACCESS_MW_BIND;
682 mhp->attr.zbva = 0;
683 mhp->attr.va_fbo = 0;
684 mhp->attr.page_size = 0;
685 mhp->attr.len = ~0ULL;
686 mhp->attr.pbl_size = 0;
687
688 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid,
689 FW_RI_STAG_NSMR, mhp->attr.perms,
690 mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0);
691 if (ret)
692 goto err1;
693
694 ret = finish_mem_reg(mhp, stag);
695 if (ret)
696 goto err2;
697 return &mhp->ibmr;
698 err2:
699 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
700 mhp->attr.pbl_addr);
701 err1:
702 kfree(mhp);
703 return ERR_PTR(ret);
704 }
705
c4iw_reg_user_mr(struct ib_pd * pd,u64 start,u64 length,u64 virt,int acc,struct ib_udata * udata)706 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
707 u64 virt, int acc, struct ib_udata *udata)
708 {
709 __be64 *pages;
710 int shift, n, len;
711 int i, k, entry;
712 int err = 0;
713 struct scatterlist *sg;
714 struct c4iw_dev *rhp;
715 struct c4iw_pd *php;
716 struct c4iw_mr *mhp;
717
718 PDBG("%s ib_pd %p\n", __func__, pd);
719
720 if (length == ~0ULL)
721 return ERR_PTR(-EINVAL);
722
723 if ((length + start) < start)
724 return ERR_PTR(-EINVAL);
725
726 php = to_c4iw_pd(pd);
727 rhp = php->rhp;
728
729 if (mr_exceeds_hw_limits(rhp, length))
730 return ERR_PTR(-EINVAL);
731
732 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
733 if (!mhp)
734 return ERR_PTR(-ENOMEM);
735
736 mhp->rhp = rhp;
737
738 mhp->umem = ib_umem_get(pd->uobject->context, start, length, acc, 0);
739 if (IS_ERR(mhp->umem)) {
740 err = PTR_ERR(mhp->umem);
741 kfree(mhp);
742 return ERR_PTR(err);
743 }
744
745 shift = ffs(mhp->umem->page_size) - 1;
746
747 n = mhp->umem->nmap;
748 err = alloc_pbl(mhp, n);
749 if (err)
750 goto err;
751
752 pages = (__be64 *) __get_free_page(GFP_KERNEL);
753 if (!pages) {
754 err = -ENOMEM;
755 goto err_pbl;
756 }
757
758 i = n = 0;
759
760 for_each_sg(mhp->umem->sg_head.sgl, sg, mhp->umem->nmap, entry) {
761 len = sg_dma_len(sg) >> shift;
762 for (k = 0; k < len; ++k) {
763 pages[i++] = cpu_to_be64(sg_dma_address(sg) +
764 mhp->umem->page_size * k);
765 if (i == PAGE_SIZE / sizeof *pages) {
766 err = write_pbl(&mhp->rhp->rdev,
767 pages,
768 mhp->attr.pbl_addr + (n << 3), i);
769 if (err)
770 goto pbl_done;
771 n += i;
772 i = 0;
773 }
774 }
775 }
776
777 if (i)
778 err = write_pbl(&mhp->rhp->rdev, pages,
779 mhp->attr.pbl_addr + (n << 3), i);
780
781 pbl_done:
782 free_page((unsigned long) pages);
783 if (err)
784 goto err_pbl;
785
786 mhp->attr.pdid = php->pdid;
787 mhp->attr.zbva = 0;
788 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
789 mhp->attr.va_fbo = virt;
790 mhp->attr.page_size = shift - 12;
791 mhp->attr.len = length;
792
793 err = register_mem(rhp, php, mhp, shift);
794 if (err)
795 goto err_pbl;
796
797 return &mhp->ibmr;
798
799 err_pbl:
800 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
801 mhp->attr.pbl_size << 3);
802
803 err:
804 ib_umem_release(mhp->umem);
805 kfree(mhp);
806 return ERR_PTR(err);
807 }
808
c4iw_alloc_mw(struct ib_pd * pd,enum ib_mw_type type)809 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type)
810 {
811 struct c4iw_dev *rhp;
812 struct c4iw_pd *php;
813 struct c4iw_mw *mhp;
814 u32 mmid;
815 u32 stag = 0;
816 int ret;
817
818 if (type != IB_MW_TYPE_1)
819 return ERR_PTR(-EINVAL);
820
821 php = to_c4iw_pd(pd);
822 rhp = php->rhp;
823 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
824 if (!mhp)
825 return ERR_PTR(-ENOMEM);
826 ret = allocate_window(&rhp->rdev, &stag, php->pdid);
827 if (ret) {
828 kfree(mhp);
829 return ERR_PTR(ret);
830 }
831 mhp->rhp = rhp;
832 mhp->attr.pdid = php->pdid;
833 mhp->attr.type = FW_RI_STAG_MW;
834 mhp->attr.stag = stag;
835 mmid = (stag) >> 8;
836 mhp->ibmw.rkey = stag;
837 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) {
838 deallocate_window(&rhp->rdev, mhp->attr.stag);
839 kfree(mhp);
840 return ERR_PTR(-ENOMEM);
841 }
842 PDBG("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag);
843 return &(mhp->ibmw);
844 }
845
c4iw_dealloc_mw(struct ib_mw * mw)846 int c4iw_dealloc_mw(struct ib_mw *mw)
847 {
848 struct c4iw_dev *rhp;
849 struct c4iw_mw *mhp;
850 u32 mmid;
851
852 mhp = to_c4iw_mw(mw);
853 rhp = mhp->rhp;
854 mmid = (mw->rkey) >> 8;
855 remove_handle(rhp, &rhp->mmidr, mmid);
856 deallocate_window(&rhp->rdev, mhp->attr.stag);
857 kfree(mhp);
858 PDBG("%s ib_mw %p mmid 0x%x ptr %p\n", __func__, mw, mmid, mhp);
859 return 0;
860 }
861
c4iw_alloc_mr(struct ib_pd * pd,enum ib_mr_type mr_type,u32 max_num_sg)862 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
863 enum ib_mr_type mr_type,
864 u32 max_num_sg)
865 {
866 struct c4iw_dev *rhp;
867 struct c4iw_pd *php;
868 struct c4iw_mr *mhp;
869 u32 mmid;
870 u32 stag = 0;
871 int ret = 0;
872 int length = roundup(max_num_sg * sizeof(u64), 32);
873
874 if (mr_type != IB_MR_TYPE_MEM_REG ||
875 max_num_sg > t4_max_fr_depth(use_dsgl))
876 return ERR_PTR(-EINVAL);
877
878 php = to_c4iw_pd(pd);
879 rhp = php->rhp;
880 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
881 if (!mhp) {
882 ret = -ENOMEM;
883 goto err;
884 }
885
886 mhp->mpl = dma_alloc_coherent(&rhp->rdev.lldi.pdev->dev,
887 length, &mhp->mpl_addr, GFP_KERNEL);
888 if (!mhp->mpl) {
889 ret = -ENOMEM;
890 goto err_mpl;
891 }
892 mhp->max_mpl_len = length;
893
894 mhp->rhp = rhp;
895 ret = alloc_pbl(mhp, max_num_sg);
896 if (ret)
897 goto err1;
898 mhp->attr.pbl_size = max_num_sg;
899 ret = allocate_stag(&rhp->rdev, &stag, php->pdid,
900 mhp->attr.pbl_size, mhp->attr.pbl_addr);
901 if (ret)
902 goto err2;
903 mhp->attr.pdid = php->pdid;
904 mhp->attr.type = FW_RI_STAG_NSMR;
905 mhp->attr.stag = stag;
906 mhp->attr.state = 1;
907 mmid = (stag) >> 8;
908 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
909 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) {
910 ret = -ENOMEM;
911 goto err3;
912 }
913
914 PDBG("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag);
915 return &(mhp->ibmr);
916 err3:
917 dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size,
918 mhp->attr.pbl_addr);
919 err2:
920 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
921 mhp->attr.pbl_size << 3);
922 err1:
923 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
924 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
925 err_mpl:
926 kfree(mhp);
927 err:
928 return ERR_PTR(ret);
929 }
930
c4iw_set_page(struct ib_mr * ibmr,u64 addr)931 static int c4iw_set_page(struct ib_mr *ibmr, u64 addr)
932 {
933 struct c4iw_mr *mhp = to_c4iw_mr(ibmr);
934
935 if (unlikely(mhp->mpl_len == mhp->attr.pbl_size))
936 return -ENOMEM;
937
938 mhp->mpl[mhp->mpl_len++] = addr;
939
940 return 0;
941 }
942
c4iw_map_mr_sg(struct ib_mr * ibmr,struct scatterlist * sg,int sg_nents)943 int c4iw_map_mr_sg(struct ib_mr *ibmr,
944 struct scatterlist *sg,
945 int sg_nents)
946 {
947 struct c4iw_mr *mhp = to_c4iw_mr(ibmr);
948
949 mhp->mpl_len = 0;
950
951 return ib_sg_to_pages(ibmr, sg, sg_nents, c4iw_set_page);
952 }
953
c4iw_dereg_mr(struct ib_mr * ib_mr)954 int c4iw_dereg_mr(struct ib_mr *ib_mr)
955 {
956 struct c4iw_dev *rhp;
957 struct c4iw_mr *mhp;
958 u32 mmid;
959
960 PDBG("%s ib_mr %p\n", __func__, ib_mr);
961 /* There can be no memory windows */
962 if (atomic_read(&ib_mr->usecnt))
963 return -EINVAL;
964
965 mhp = to_c4iw_mr(ib_mr);
966 rhp = mhp->rhp;
967 mmid = mhp->attr.stag >> 8;
968 remove_handle(rhp, &rhp->mmidr, mmid);
969 if (mhp->mpl)
970 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
971 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
972 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
973 mhp->attr.pbl_addr);
974 if (mhp->attr.pbl_size)
975 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
976 mhp->attr.pbl_size << 3);
977 if (mhp->kva)
978 kfree((void *) (unsigned long) mhp->kva);
979 if (mhp->umem)
980 ib_umem_release(mhp->umem);
981 PDBG("%s mmid 0x%x ptr %p\n", __func__, mmid, mhp);
982 kfree(mhp);
983 return 0;
984 }
985